LMR70503 TI1 | Alldatasheet

Document overview

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Technical content

Features

  • Tiny 8-Bump Thin Micro SMD Package: 0.84 mm × 1.615 mm × 0.6 mm
  • 2.8 V to 5.5 V Input Voltage Range
  • Adjustable Output Voltage: -0.9 V to -5.5 V
  • 320 mA Switch Current Limit
  • 500 kHz Minimum Switching Frequency
  • Ground Referred Enable Input
  • Under Voltage Lock Out (UVLO)
  • No External Compensation
  • Internal Soft Start
  • 1 µA Shutdown Supply Current
  • Small Output Voltage Ripple
  • WEBENCH® Enabled Performance Benefits
  • Easy To Use
  • Tiny Overall Solution Size Reduces System Cost

Applications

  • General Purpose Negative Voltage Supply
  • Negative Rail / Bias Supply For Op-amp And Data Converters
  • LCD Biasing System Performance Efficiency, VOUT= -5.0 V 0 10 20 30 40 50 60 70 80 90 10030 80EFFICIENCY (%) LOAD (mA) 30184975 Efficiency, VOUT= -2.5 V 0 30 60 90 120 150 18030 80EFFICIENCY (%) LOAD (mA) 30184979 Typical Application Circuit 30184901 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

301849 SNVS850 Copyright © 1999-2012, Texas Instruments Incorporated

Ordering Information

Order Number Supplied As Package Type Package Drawing Package Marking LMR70503TM NOPB 250 Units on Tape and Reel Thin Micro SMD TMP08BAA S3LMR70503TMX NOPB 3000 Units on Tape and Reel Connection Diagrams 30184902 LMR70503 Bump Locations - Top View 30184903 (Diamond Denotes Bump A1) Pin Descriptions Pin Number Name Description A1 VREF Reference voltage output; connect to the bottom feedback resistor. B1 EN Active high enable input for the device. Enable voltage level is referred to GND. Device must be enabled only with the presence of valid VIN (2.8 V to 5.5 V). The peak of the Enable input voltage must always lower than VIN voltage. C1, C2 GND Analog ground for internal bias circuitry. D1 SW Switch node pin, connected to the internal high side MOSFET. The cathode of the external Schottky diode must be connected as close as possible to this pin, in order to reduce inductance in the discontinuous current path. A2 FB FB is connected to VOUT and VREF through two feedback resistors. It is compared to GND to regulate the output voltage. B2 VOUT Output voltage. The anode of the external Schottky diode and output filter capacitor(s) should be connected to this pin. D2 VIN Power supply input pin, connected to the internal high side MOSFET and powers the internal circuity. LMR70503

2 Copyright © 1999-2012, Texas Instruments Incorporated

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. VIN to GND -0.5 V to 6.0 V VOUT to GND -6.5 V to 0.5 V SW to GND -6.5 V to VIN +0.2 V EN to GND -0.5 V to VIN FB to GND -0.5V to 5.5V ESD Rating(Note 2) ±2 kV Junction Temperature 150 °C Storage Temperature Range -65 °C to 150 °C For Soldering Specs see: http://www.ti.com/lit/an/snoa549c/ snoa549c.pdf Operating Ratings Input Voltage Range (VIN) 2.8 V to 5.5 V Output Voltage Range (VOUT) -0.9 V to -5.5 V Junction Temperature Range (TJ) -40°C to 125°C Electrical Characteristics Specifications with standard typeface are for TJ = 25°C only; limits in bold face type apply over the operating junction temperature (TJ) range of -40 °C to +125 °C. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VIN = 3.3 V, VOUT = -5.0 V, VEN = 1.8 V, unless otherwise indicated in the conditions column. Symbol Parameter Conditions Min (Note 3) Typ (Note 4) Max (Note 3) Units VREF Reference Voltage RREF=100 kΩ to GND 1.166 1.19 1.214 V ISD Shutdown Current EN = 0 V VIN = 5.5 V 0.01 1 µA IQ Quiescent Current EN = 1.8 V, VIN = 5.5 V, No Switching 245 300 µA UVLORISE VIN Under Voltage Lock Out Threshold - Rising 2.55 2.7 V UVLOHYS VIN Under Voltage Lock Out Hysteresis Band 0.1 0.13 V VEN-RISE EN Input Voltage Rising Threshold VIN = 5.5 V 1.05 1.2 V VEN-HYS EN Input Voltage Threshold Hysteresis VIN = 5.5 V 0.1 0.15 V IEN Enable Current 30 nA IFB FB pin current 10 nA FSW-MIN Minimum Switching frequency 400 500 kHz TON-MIN Minimum High Side Switch On Time Load = 0 A 70 ns RDSON Switch On State Resistance VIN = 2.8V 1.1 2 Ω IPEAK-CL Switch Peak Current limit(Note 5) 270 320 370 mA TSDTH-HIGH Thermal Shutdown Threshold - Rising Junction Temperature 165 °C TSDHYS Thermal Shutdown Hysteresis Band Junction Temperature 10 °C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/ or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the recommended Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and should not be operated beyond such conditions. Note 2: ESD using the human body model which is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD22–A114. Note 3: Min and Max limits are 100% production tested at an ambient temperature (TA) of 25 °C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Note 4: Typical specifications represent the most likely parametric norm at 25°C operation. Note 5: The switch peak current limit is internally trimmed. The actual peak current limit observed on the applications are dependant on the input voltage VIN, inductance value L and junction temperature TJ. LMR70503 Copyright © 1999-2012, Texas Instruments Incorporated 3

Typical Performance Characteristics Unless otherwise specified, the following conditions apply: VIN = 6.8 µH (VLS2012ET-6R8M); TAMBIENT = 25 °C. Efficiency, VOUT = -5.0 V 0 10 20 30 40 50 60 70 80 90 100 80EFFICIENCY (%) LOAD (mA) 30184975 Output Regulation, VOUT = -5.0 V 0 10 20 30 40 50 60 70 80 90 100 4.90 4.92 4.95 4.96 4.99 5.00 5.02 5.04 5.06 5.08 5.10|VOUT| REGULATION (V) LOAD (mA) 30184976 Efficiency, VOUT = -3.3 V 0 20 40 60 80 100 120 140 80EFFICIENCY (%) LOAD (mA) 30184977 Output Regulation, VOUT = -3.3 V 0 20 40 60 80 100 120 1403.20 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40|VOUT| REGULATION (V) LOAD (mA) 30184978 Efficiency, VOUT = -2.5 V 0 30 60 90 120 150 180 80EFFICIENCY (%) LOAD (mA) 30184979 Output Regulation, VOUT = -2.5 V 0 30 60 90 120 150 180 2.40 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60|VOUT| REGULATION (V) LOAD (mA) 30184980 LMR70503

4 Copyright © 1999-2012, Texas Instruments Incorporated

Efficiency, VOUT = -1.5 V 0 30 60 90 120 150 180 210 80EFFICIENCY (%) LOAD (mA) 30184981 Output Regulation, VOUT = -1.5 V 0 30 60 90 120 150 180 2101.40 1.42 1.44 1.46 1.48 1.50 1.52 1.54 1.56 1.58 1.60|VOUT| REGULAITON (V) LOAD (mA) 30184982 Efficiency, VOUT = -0.9 V 0 50 100 150 200 250 80EFFICIENCY (%) LOAD (mA) 30184983 Output Regulation, VOUT = -0.9 V 0 50 100 150 200 2500.80 0.82 0.84 0.86 0.88 0.90 0.92 0.94 0.96 0.98 1.00|VOUT| REGULATION (V) LOAD (mA) 30184984 Maximum Load Current 100 150 200 250MAX LOADING (mA) VIN (V) VOUT = -5VVOUT = -3.3VVOUT = -2.5VVOUT = -1.5VVOUT = -0.9V 30184971 Minimum Switching Frequency 460 480 500 520 540 560 580 600MINIMUM SWITCHING FREQUENCY (kHz) VIN (V) Temp = -40°CTemp = 25°CTemp = 125°C 30184989 LMR70503 Copyright © 1999-2012, Texas Instruments Incorporated 5

0.0 0.5 1.0 1.5 2.0 2.5 3.0NO LOAD CURRENT (mA) VIN (V) 30184924 Rds-on -40 -20 0 20 40 60 80 100 120 140 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0RDS-ON (Ω) TEMPERATURE (°C) Vin = 2.8VVin = 4.0VVin = 5.5V 30184987 Enable Thresholds 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1EN THRESHOLDS (V) VIN (V) Rising TH -40°CFalling TH -40°CRising TH 25°CFalling TH 25°CRising TH 125°CFalling TH 125°C 30184988 Soft Start Time (No Load) 100 200 300 400 500 600 700 800SOFT START TIME (NO LOAD) (μs) VIN (V) 30184986 Soft Start Delay Time (From EN Rising Edge) 100 120 140 160SOFT START DELAY TIME (μs) VIN (V) Temp = -40°CTemp = 25°CTemp = 125°C 30184985 Soft Off Time, VOUT = -5.5 V (No Load, From EN Falling Edge) 0 10 20 30 40 50 60 70 80 90 300 400 500 600 700 800SOFT OFF TIME (EN TO 10% VOUT) (μs) TEMP (°C) VIN = 2.8 VVIN = 3.0 VVIN = 4.0 VVIN = 5.0 V 30184930 LMR70503

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Soft Start And Soft Off Waveform VIN = 5.0 V, VOUT = -5.0 V, No Load 30184951 Soft Start And Soft Off Waveform VIN = 5.0 V, VOUT = -5.0 V, Load = 50 Ω 30184952 Typical Switching Waveform VIN = 5.0 V, VOUT = -5.0 V, No Load 30184954 Typical Switching Waveform VIN = 5.0 V, VOUT = -5.0 V, IOUT = 70 mA 30184955 Load Transient, VIN = 4.0 V, VOUT = -5.5 V Load steps between 2 mA and 50 mA 30184912 Short Circuit Waveform VIN = 5.0 V, VOUT = -5.5 V 30184911 LMR70503 Copyright © 1999-2012, Texas Instruments Incorporated 7

instead of the lowest potential of the IC: the negative output voltage. The LMR70503 integrates an inverting buck-boost controller and a high-side MOSFET in one tiny 8-bump thin micro SMD package. A simplified buck-boost converter schematic is shown in Figure 1. FIGURE 1. Buck Boost Converter droops below a threshold. When the switch is off, the inductor current goes through the diode and charges the output capacitor(s). switch node voltage and the output voltage ripple (absolute value), are shown in Figure 2.

8 Copyright © 1999-2012, Texas Instruments Incorporated

the offset at the FB node, the higher the dummy load current, as shown in Figure 4. FIGURE 4. Dummy Load Current vs. FB Voltage transition load level between the constant frequency mode and the constant peak current mode varies with VIN, VOUT and L. the inductor current rising slope: V IN / L, approximately. For a typical inductor, the inductance will reduce at hot temperature. Therefore, IPEAK-MAX is the highest with 5.5 V input voltage at hot temperature. a higher inductance value and a diode with lower forward voltage drop VF.

10 Copyright © 1999-2012, Texas Instruments Incorporated

FIGURE 7. Enable Rising And Falling Thresholds vs. VIN It is important to ensure that a valid input voltage (2.8 V ≤ VIN≤ 5.5 V) is present on the VIN pin before the EN input is asserted. divider can be added from VIN to EN if an external enable signal is not available. to properly bias the internal circuitry. The typical UVLO rising threshold is 2.55 V and typical hysteresis band is 0.13 V. with the presence of valid EN voltage. The soft start action is inherent with the maximum peak current limit and minimum off time. µH and no load. Soft-start is reset any time the part is shut down or a thermal shutdown event occurs. FIGURE 8. Soft Start Time (No Load) vs. VIN The LMR70503 will shutdown when EN pin voltage goes below the falling threshold, or V IN goes below UVLO falling threshold. output capacitors. Typical soft off times (from EN falling edge to 10% of Vout ) over V IN and temperature are shown in Figure 9. Figure 10 shows the typical off time from 90% to 10% of Vout.

12 Copyright © 1999-2012, Texas Instruments Incorporated

Input Capacitor And Output Capacitor Selection The input capacitor selection is based on both input voltage ripple and RMS current. Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the regulator current during switch on-time. Low ESR ceramic capacitors are preferred. A minimum value of 10 μF at 6.3 V, is required at the input of the LMR70503. Larger values of input capacitance are desirable to reduce voltage ripple and noise on the input supply. The output capacitor is responsible for filtering the output voltage and suppling load current during transients and during the power diode off-time. Best performance is achieved with ceramic capacitors. For most applications, a minimum value of 22 μF, 6.3 V capacitor is required at the output of the LMR70503. The percentage of ripple coupled to the FB node can be found by RIPPLE PERCENTAGE = VREF / ( |VOUT| + VREF) where |VOUT| is the magnitude of the output voltage and V REF is the reference voltage. With lower magnitude V OUT, a higher percentage of output voltage ripple is coupled to the FB node. Output voltage ripple is also coupled to the FB node via the feed- forward capacitor CFF. Excessive ripple at the FB node may trigger peak current limit modulation causing unstable operation. Higher output capacitance is needed at lower magnitude output voltage. For VOUT = -0.9 V, a minimum of 44 μF, 6.3 V capacitor is required. Avoid using too much capacitance at CFF. A capacitor between VIN and VOUT also can be used to provide high frequency bypass. This capacitor is equivalent to the output capacitors in the small signal model. It also reduces the output voltage ripple if sufficiency capacitance is used. The voltage rating for this capacitor should be higher than VIN + |VOUT|. All ceramic capacitors have large voltage coefficients, in addition to normal tolerances and temperature coefficients. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum capacitance up to the desired value. This may also help with RMS current constraints by sharing the current among several capacitors. With the LMR70503, ceramic capacitors rated at 6.3 V, or higher, are suitable for all input and output voltage combinations. Many times it is desirable to use an electrolytic capacitor on the input, in parallel with the ceramics. The moderate ESR of this capacitor can help to damp any ringing on the input supply caused by long power leads. This method can also help to reduce voltage spikes that may exceed the maximum input voltage rating of the LMR70503. Power Inductor Selection The power inductor selection is critical to the operation of the LMR70503. It affects the efficiency, the operation mode transition point, the maximum loading capability and the size / cost of the solution. A 4.7 μH or 6.8 μH inductor is recommended for most LMR70503 applications. The maximum loading capability is reduced with smaller inductance value. The no load V OUT offset is higher at low V OUT with smaller inductance value, due to higher peak current with the same T ON-MIN. Higher inductance value usually comes with higher DCR with the same size and cost. Higher DCR will reduce the efficiency especially at heavy load. The inductor must be rated above the maximum peak current limit to prevent saturation. Good design practice requires that the inductor rating be adequate for the maximum I PEAK-MAX over VIN and temperature, plus some safety margin. If the inductor is not rated for the maximum expected current, saturation at high current may cause damage to the LMR70503 and/or the power diode. The DCR of the inductor should be as small as possible with given size / cost constrains to achieve optimal efficiency. Power Diode Selection A Schottky type power diode is required for all LMR70503 applications. The parameters of interests include the reverse voltage rating, the DC current rating, the repetitive peak current rating, the forward voltage drop, the reverse leakage current and the parasitic capacitance. In a buck-boost, this diode sees a reverse voltage of : VR-DIODE = |VOUT| + VIN The reverse breakdown voltage rating of the diode should be selected for this value, plus safety margin. A good rule of thumb is to select a diode with a reverse voltage rating of 1.3 times this maximum. Select a diode with a DC current rating at least equal to the maximum load current that will be seen in the application and the repetitive peak current rating higher than IPEAK-MAX over VIN and temperature. The forward voltage drop of the power diode is a big part of the power loss in a buck-boost converter. It is preferred to be as low as possible. The reverse leakage current and the parasitic capacitance are also part of the power losses in the converter, but usually less pronounced than the forward voltage drop loss. Pay attention to the temperature coefficients of all the parameters. Some of them may vary greatly over temperature and may adversely affect the efficiency over temperature. PC Board Layout Guidelines Board layout is critical for the proper operation of switching power converters. Switch mode converters are very fast switching devices. In such cases, the rapid increase of current combined with the parasitic trace inductance generates unwanted L·di/dt noise spikes. The magnitude of this noise tends to increase as the output current increases. This noise may turn into electromagnetic interference (EMI) and can also cause problems in device performance. Therefore, care must be taken in layout to minimize the effect of this switching noise. The most important layout rule is to keep the AC current loops as small as possible. Figure 1 shows the current flow in a buck-boost converter. The two dotted arrows indicate the current paths when the high side switch is on and when the power diode is on, respectively. The components and traces that contain discontinuous currents are critical in PCB layout design, since discontinuous currents contain high di/dt and high frequency noise. The components that carry critical discontinuous currents include the input capacitor(s), the high side switch, the power diode and the output capacitor(s). These components need to be placed as close as possible to each other and the traces between them must be made as short and wide as possible: place the input capacitor(s) as close as possible to the VIN pin of the LMR70503; place the cathode of the diode as close as possible to the SW pin; the anode of the diode should be as close as possible to the output capacitor(s); the GND end of the output capacitor(s) should be as close as possible to that of the input capacitor(s). Doing so will yield a small loop area, reducing the loop inductance and EMI. LMR70503

14 Copyright © 1999-2012, Texas Instruments Incorporated

feedback path will be shielded from switching noise. or heavier to help reducing the parasitic inductances of board traces. FIGURE 11. PCB Layout Example (top layer and top overlay)

TABLE 1. Bill of Materials

  • RB is represented by R1 in Figure 11.

16 Copyright © 1999-2012, Texas Instruments Incorporated

Physical Dimensions inches (millimeters) unless otherwise noted 8-Bump Thin Micro SMD Package LMR70503 Copyright © 1999-2012, Texas Instruments Incorporated 17

Copyright © 1999-2012, Texas Instruments Incorporated

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