ISL8225M_13 INTERSIL | Alldatasheet
Document overview
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- PDF pages: 28
Technical content
Features
- Fully-encapsulated dual step-down switching power supply
- Up to 100W output from a 17mm square PCB footprint
- Dual 15A or single 30A output
- Up to 95% conversion efficiency
- 4.5V to 20V input voltage range
- 0.6V to 6V output voltage range
- 1.5% output voltage accuracy with differential remote sensing
- Up to six modules may be paralleled to support 180A output current
- Output over-voltage, over-current and over-temperature protection
- Full power operation without heat sinks or fans
- QFN package with exposed leads permits easy probing and visual solder inspection
Applications
- Computing, networking an d telecom infrastructure equipment
- Industrial and medical equipment
- General purpose point-of-load (POL) power
FIGURE 1. COMPLETE 30A STEP-DOWN POWER SUPPLY FIGU RE 2. SMALL FOOTPRINT WITH HIGH POWER DENSITY NOTE: ALL PINS NOT SHOWN ARE FLOATING. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
2 FN7822.1 January 31, 2013 Pinout Internal Circuit VCC 2.2µF VIN1 EN/FF1 PGOOD CLKOUT ISHARE MODE SYNC SGND ISEN1B ISEN1A VOUT1 VSEN1+ PHASE1 COMP1 VMON1 VSEN1- PGND 10kΩ FILTER UGATE1 PGND13 LDO DIFF AMP1 ERROR AMP1 ZCOMP1 ZCOMP2 CURRENT SENSING/ SHARING GATE DRIVER LGATE1 SOFT-START AND FAULT LOGIC VIN2 EN/FF2 ISEN2B ISEN2A VOUT2 PHASE210 UGATE2 CURRENT SENSING/ SHARING GATE DRIVER LGATE2 SOFT-START AND FAULT LOGIC VSEN2+ COMP2 VMON2 VSEN2- DIFF AMP2 ZCOMP3 ZCOMP4 ERROR AMP2 INTERNAL REFERENCE INTERNAL REFERENCE 0.32µH 0.32µH 7.5kΩ MODE
3 FN7822.1 January 31, 2013
Ordering Information
(Notes 2, 3) PART MARKING TEMP. RANGE (°C) (Note 4) PACKAGE (Pb-Free) PKG. DWG. # ISL8225MIRZ ISL8225M -40 to +125 26 Ld QFN L26.17x17 ISL8225MIRZ-T (Note 1) ISL8225M -40 to +125 26 Ld QFN (Tape & Reel) L26.17x17 NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These products do contain Pb but they are RoHs compliant by EU exemption 5 (Pb in glass of cathode ray tubes, electronic components, and fluorescent tubes). 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8225M. For more information on MSL, please see tech brief TB363 4. The ISL8225M is guaranteed over the full -40°C to +125°C internal junction temperature range. Note that the allowed ambient temperature consistent with these specifications is determined by specific operating conditions, including board layout, cooling scheme and other environmental factors.
4 FN7822.1 January 31, 2013 Pin Configuration ISL8225M (26 LD QFN) TOP VIEW 23456789 13 14 15 16 17 18 19 20 COMP2 MODE VMON2 SYNC SGND VCC VIN2 PGND PHASE2 N/C PHASE1 PGND VIN1 EN/FF1 EN/FF2 CLKOUT VMON1 ISHARE COMP1 VSEN1- VSEN1+ VOUT1 PGOOD VOUT2 VSEN2+ VSEN2- PIN 1
5 FN7822.1 January 31, 2013 Pin Descriptions PIN NUMBER PIN NAME TYPE PIN DESCRIPTION 21, 1 VSEN1-, VSEN2- I Output voltage negative feedback. Negative input of the differential remote sense for the regulator. Connect to the negative rail or ground of the load/processor, as shown in Figure 19. The negative feedback pins can be used to program the module operation conditions. See Table 3 and Table 5 for details. 20, 2 COMP1, COMP2 I/O Error amplifier outputs. Typically floating for dual-output use. For parallel use, a 470pF~1nF capacitor is recommended on the COMP pins of each SLAVE phase to eliminate the coupling noise. All COMP pins of SLAVE phases need to tie to MASTER phase COMP1 pin (first phase). Internal compensation networks are implemented for working in the full range of I/O conditions. 3M O D E I Mode setting. Typically floating for dual-output use; tie to SGND for parallel use. See Table 3 and Table 5 for details. When VSEN2- is pulled within 700mV of VCC, the 2nd channel’s remote sensing amplifier is disabled. The MODE pin, as well as the VSEN2+ pin, determine relative phase-shift between the two channels and the CLKOUT signal output. 18, 4 VMON1, VMON2 I/O Remote sensing amplifier outputs. These pins are connected internally to OV/UV/PGOOD comparators, so they can’t be floated when the module works in multi-phase operation. When VSEN1-, VSEN2- are pulled within 700mV of VCC, the corresponding remote sensing amplifier is disabled; the output (VMON pin) is in high impedance. In this event, the VMON pins can be used as an additional monitor of the output voltage, with a resistor divider to protect the system against single point of failure. The default setting voltage is 0.6V. See Table 3 for details. 5S Y N C I Signal synchronization. An optional external resistor (RSYNC) connected from this pin to SGND increases oscillator switching frequency (Figure 31 and Table 1). The internal default frequency is 500kHz with this pin floating. Also, the internal oscillator can lock to an external frequency source or the CLKOUT signal from another ISL8225M. Input voltage range for external source: 3V to 5V square wave. No capacitor is recommended on this pin. 6S G N D P W R Control signal ground. Connect to PGND under the module in the quiet inner layer. Make sure to have the single location for the connection between SGND and PGND to avoid noise coupling. See “Layout Guide” on page 23. 7V C C P W R 5V internal linear regulator output. Voltage range: 3V to 5.6V. The decoupling ceramic capacitor for the VCC pin is recommended to be 4.7µF. 14, 8 VIN1, VIN2 PWR Power inputs. Input voltage range: 4.5V to 20V. Tie directly to the input rail. VIN1 provides power to the internal linear drive circuitry. When the input is 4.5V to 5.5V, VIN should be tied directly to VCC. 9, 13 PGND PWR Power ground. Power ground pins for both input and output returns. 12, 10 PHASE1, PHASE2 PWR Phase node. Use for monitoring switching frequency. Phase pins should be floating or used for snubber connections.To achieve better thermal performance, the phase planes can also be used for heat removal with thermal vias connected to large inner layers. See “Layout Guide” on page 23. 11 NC - Non-connection pin. This pin is floating with no connection inside. 15, 16 EN/FF1, EN/FF2 I/O Enable and feed-forward control. Tie a resistor divider to VIN or use the system enable signal for this pin. The voltage turn-on threshold is 0.8V. With a voltage lower than the threshold, the corresponding channel can be disabled independently. By connecting to VIN with a resistor divider, the input voltage can be monitored for UVLO (under-voltage lockout) function. The voltage on each EN/FF pin is also used to adjust the internal control loop gain independently to realize the feed-forward function. Please set the EN/FF between 1.25V to 5V. A 1nF capacitor is recommended on each EN/FF pin. Please see Table 1 to select resistor divider and application details in “EN/FF Turn ON/OFF” on page 19. 17 CLKOUT I/O Clock out. Provide the clock signal for the input synchronization signal of other ISL8225Ms. Typically tied to VCC for dual-output use with 180° phase-shift. See Table 3 and Table 5 when using more than one ISL8225M. When the module is in dual-output mode, the clock-out signal is disabled. By programming the voltage level of this CLKOUT pin, the module can work for DDR/tracking or as two independent outputs with selectable phase-shift. See Table 6. 19 ISHARE O Current sharing control. Tie all ISHARE pins together when multiple modules are configured for current sharing and share a common current output. The ISHARE voltage represents the average current of all active and connected channels. A 470pF capacitor is recommended for each ISHARE pin for multiple phase applications. Typically, the ISHARE pin should be floating for dual-output or single module application. 22, 26 VSEN1+, VSEN2+ I Output voltage positive feedback. Positive inputs of differential remote sense for the regulator. A resistor divider can be connected to this pin to program the output voltage. It is recommended to put the resistor divider close to the module and connect the kelvin sensing traces of VOUT and VSEN- to the sensing points of the load/processor; see Figure 19 . The VSEN2+ pin can be used to program the module operation conditions. See Table 3 and Table 5 for details. 23, 25 VOUT1, VOUT2 PWR Power Output. Apply output load between these pins and PGND pins. Output voltage range: 0.6V to 6V. 24 PGOOD O Power good. Provide open-drain power-good signal when the output is within 9% of the nominal output regulation point with 4% hysteresis (13%/9%) and soft-start complete. PGOOD monitors the outputs (VMON) of the internal differential amplifiers.
6 FN7822.1 January 31, 2013 Absolute Maximum Ratings Thermal Information ESD Rating Thermal Resistance (Typical) θ JA (°C/W) θJC (°C/W) Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. NOTES: 5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For θJC, the “case temp” location is the center of the phase exposed metal pad on the package underside. Electrical Specifications TA = +25°C, VIN = 12V, unless otherwise noted. Boldface limits apply over the internal junction temperature range, -40°C to +125°C (Note 4). PARAMETER SYMBOL TEST CONDITIONS MIN (Note 7) TYP (Note 8) MAX (Note 7) UNITS VCC SUPPLY CURRENT Nominal Supply VIN Current I Q_VIN VIN = 20V; No Load; EN1 = EN2 = high 131 mA VIN1 = 20V; No Load; EN1 = high, EN2 = low 72 mA VIN2 = 20V; No Load; EN1 = 0, EN2 = high 71 mA VIN1 = 12V; No Load; EN1 = high, EN2 = high 134 mA VIN = 4.5V; No Load; EN1 = EN2 = high 136 mA VIN1 = 4.5V; No Load; EN1 = high, EN2 = low 73 mA VIN2 = 4.5V; No Load; EN1 = 0, EN2 = high 70 mA INTERNAL LINEAR REGULATOR (Note 9) Maximum Current I PVCC VCC = 4V to 5.6V 250 mA Saturated Equivalent Impedance R LDO P-Channel MOSFET (VIN = 5V) 1 Ω VCC Voltage Level VCC I VCC = 0mA 5.15 5.4 5.95 V POWER-ON RESET (Note 9) Rising VCC Threshold 0°C to +75°C 2.85 2.97 V -40°C to +85°C 2.85 3.05 V Falling VCC Threshold 2.65 2.75 V System Soft-start Delay t SS_DLY After PLL and VCC PORs, and EN above their thresholds
384 Cycles
ENABLE (Note 9) Turn-On Threshold Voltage 0.75 0.8 0.86 V Hysteresis Sink Current I EN_HYS 23 30 35 µA Under-voltage Lockout Hysteresis V EN_HYS VEN_RTH = 10.6V; VEN_FTH = 9V, RUP = 53.6kΩ, RDOWN = 5.23kΩ 1.6 V Sink Current I EN_SINK VENFF = 1V 15.4 mA Sink Impedance R EN_SINK IEN_SINK = 5mA, VENFF = 1V 64 Ω OSCILLATOR Oscillator Frequency f OSC SYNC pin is open 510 kHz
7 FN7822.1 January 31, 2013 Total Variation (Note 9) V CC = 5V; -40°C < TA < +85°C -9 +9 % FREQUENCY SYNCHRONIZATION AND PHASE LOCK LOOP (Note 9) Synchronization Frequency V CC = 5V 150 1500 kHz PLL Locking Time V CC = 5.4V, fSW = 500kHz 130 µs Input Signal Duty Cycle Range 10 90 % PWM (Note 9) Minimum PWM OFF Time t MIN_OFF 310 345 410 ns Current Sampling Blanking Time t BLANKING 175 ns OUTPUT CHARACTERISTICS Output Continuous Current Range I OUT(DC) VIN = 12V, VOUT1 = 1.5V 01 5 A VIN = 12V, VOUT2 = 1.5V 01 5 A VIN = 12V, VOUT = 1.5V, in Parallel mode 03 0 A Line Regulation Accuracy ΔVOUT/ΔVIN VIN = 4.5V to 20V VOUT1 = 1.5V, IOUT1 = 0A 0.0065 % VOUT2 = 1.5V, IOUT2 = 0A 0.0065 % VIN = 4.5V to 20V VOUT1 = 1.5V, IOUT1 = 15A 0.01 % VOUT2 = 1.5V, IOUT2 = 15A 0.01 % Load Regulation Accuracy ΔVOUT/VOUT VIN = 12V, 5x22µF, 2x4.7µF ceramic capacitor and 1x330µF POSCAP IOUT1 = 0A to 15A, VOUT1 = 1.5V 1 % IOUT2 = 0A to 15A, VOUT2 = 1.5V 1 % Output Ripple Voltage ΔVOUT VIN = 12V, 3x100µF ceramic capacitor and 1x330µF POSCAP IOUT1 = 0A, VOUT1 = 1.5V 11 mV P-P IOUT2 = 0A, VOUT2 = 1.5V 11 mV P-P IOUT1 = 15A, VOUT1 = 1.5V 14 mV P-P IOUT2 = 15A, VOUT2 = 1.5V 14 mV P-P DYNAMIC CHARACTERISTICS Voltage Change for Positive Load Step ΔVOUT-DP Current slew rate = 2.5A/µs VIN = 12V, VOUT = 1.5V, 2x47µF ceramic capacitor and 1x330µF POSCAP IOUT1 = 0A to 7.5A 75 mV P-P IOUT2 = 0A to 7.5A 75 mV P-P Voltage Change for Negative Load Step ΔVOUT-DN Current slew rate = 2.5A/µs VIN = 12V, VOUT = 1.5V, 2x47µF ceramic capacitor and 1x330µF POSCAP IOUT1 = 7.5A to 0A 70 mV P-P IOUT2 = 7.5A to 0A 70 mV P-P REFERENCE (Note 9) Reference Voltage (Include Error and Differential Amplifier Offsets) VREF1 TA = -40°C to +85°C 0.6 V -0.7 0.7 % Electrical Specifications TA = +25°C, VIN = 12V, unless otherwise noted. Boldface limits apply over the internal junction temperature range, -40°C to +125°C (Note 4). (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 7) TYP (Note 8) MAX (Note 7) UNITS
8 FN7822.1 January 31, 2013 Reference Voltage (Include Error and Differential Amplifier Offsets) VREF2 TA = -40°C to +85°C 0.6 V -0.75 0.95 % DIFFERENTIAL AMPLIFIER (Note 9) DC Gain UG_DA Unity gain amplifier 0 dB Unity Gain Bandwidth UGBW_DA 5 MHz VSEN+ Pin Sourcing Current I VSEN+ 0.2 1 2.5 µA Maximum Source Current for Current Sharing IVSEN1- VSEN1- Source Current for Current Sharing when parallel multiple modules, each of which has its own voltage loop 350 µA Input Impedance R VSEN+_to _VSEN- VVSEN+/IVSEN+, VVSEN+ = 0.6V -600 k Ω Output Voltage Swing 0V CC - 1.8 V Input Common Mode Range -0.2 V CC - 1.8 V Disable Threshold V VSEN- VMON1,2 = tri-state V CC - 0.4 V OVER-CURRENT PROTECTION (Note 9) Channel Over-current Limit I limit1 VIN = 12V, VOUT1 = 1.5V, RSYNC = Open 20 A Ilimit2 VIN = 12V, VOUT2 = 1.5V, RSYNC = Open 20 A Share Pin OC Threshold V OC_SET VCC = 5V (comparator offset included) 1.16 1.20 1.22 V CURRENT SHARE Current Share Accuracy ΔI/IOUT V IN = 12V, VOUT = 1.5V IOUT = 30A, VSEN2- = high ±10 % POWER-GOOD MONITOR (Note 9) Under-voltage Falling Trip Point V UVF Percentage below reference point -15 -13 -11 % Under-voltage Rising Hysteresis V UVR_HYS Percentage above UV trip point 4 % Over-voltage Rising Trip Point V OVR Percentage above reference point 11 13 15 % Over-voltage Falling Hysteresis V OVF_HYS Percentage below OV trip point 4 % PGOOD Low Output Voltage I PGOOD = 2mA 0.35 V Sinking Impedance I PGOOD = 2mA 70 Ω Maximum Sinking Current V PGOOD < 0.8V 10 mA OVER-VOLTAGE PROTECTION (Note 9) OV Latching-up Trip Point EN/FF = UGATE = LATCH Low, LGATE = High 118 120 122 % OV Non-Latching-up Trip Point EN = Low, UGATE = Low, LGATE = High 113 % LGATE Release Trip Point EN = Low/HIGH, UGATE = Low, LGATE = Low 87 % OVER-TEMPERATURE PROTECTION (Note 9) Over-Temperature Trip (Controller Junction Temperature) 150 °C Over-Temperature Release Threshold (Controller Junction Temperature) 125 °C NOTES: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8. Parameters with TYP limits are not production tested, unless otherwise specified. 9. Parameters are 100% tested for internal IC prior to module assembly. Electrical Specifications TA = +25°C, VIN = 12V, unless otherwise noted. Boldface limits apply over the internal junction temperature range, -40°C to +125°C (Note 4). (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 7) TYP (Note 8) MAX (Note 7) UNITS
FIGURE 22. 4-PHASE PARALLELED AT 1.5V/60A WITH 90° INTERLEAVING
FIGURE 23. 3-PHASE PARALLELED AT 1.5V/40A AND 1- PHASE AT 5V/10A OUTPUT WITH 90° INTERLEAVING
FIGURE 24. SIX-PHASE 90A 1.2V OUTPUT CIRCUIT
TABLE 1. ISL8225M DESIGN GUIDE MATRIX (REFER TO FIGURE 18)
- CIN bulk capacitor is optional only for decoupling noise due to the long input cable. CIN2 and COUT1 ceramic capacitors are listed for one phase only.
Please double the capacitor quantity for dual-phase operations.
- EN/FF resistor divider is ti ed directly to VIN. The resistors listed here are for two channels' EN/FF pins tied together. If the separate resistor divider is
used for each channel, the resistor value needs to be doubled.
- MAX load current listed in the table is for conditions at +25°C and no air flow on a typical Intersil 4-layer evaluation board.
18 FN7822.1 January 31, 2013 TABLE 2. RECOMMENDED I/O CAPACITOR IN TABLE 1 TABLE 3. ISL8225M OPERATION MODES
DESCRIPTION
FOR DETAILS) OPERATION MODE OF 2ND MODULE OPERATION MODE OF 3RD MODULEMODE EN1/FF1 (I) EN2/FF2 (I) VSEN2- (I) MODE (I) VSEN2+ (I) CLKOUT/REFIN WRT 1ST (I OR O) VMON2 (Note 14) VMON1 OF 2ND MODULE (Note 14) 2ND CHANNEL WRT 1ST (O) (NOTE 13) 10 0 - - - -- - - - - D i s a b l e d 2A 0 1 Active Active Active - Active - VMON1 = VMON2 to Keep PGOOD Valid -- S i n g l e P h a s e VMON2 to Keep PGOOD Valid -- S i n g l e P h a s e 3A 1 1 <V CC -0.7V Active Active 29% to 45% of VCC (I) Active - 0° - - Dual Regulator 3B 1 1 <V CC -0.7V Active Active 45% to 62% of VCC (I) Active - 90° - - Dual Regulator 3C 1 1 <V CC -0.7V Active Active >62% of V CC (I) Active - 180° - - Dual Regulator 41 1 < V CC -0.7V Active Active <29% of V CC (I) Active - -60° - - DDR Mode 5A 1 1 V CC GND - 60° VMON1 or Divider - 180° - - 2-Phase 5B 1 1 V CC GND - 60° Divider Divider 180° 5B 5B 6-Phase 5C 1 1 V CC GND - 60° VMON1 or Divider Active 180° 5C 5C 3 Outputs 61 1 V CC VCC GND 120° 1k Ω Active 240° 2B - 3-Phase 7A 1 1 V CC VCC VCC 90° 1k Ω Divider 180° 7A - 4-Phase 7B 1 1 V CC VCC VCC 90° 1k Ω Active 180° 7B - 2 Outputs (1st module in Mode 7A) 7C 1 1 V CC VCC VCC 90° 1k Ω Active 180° 3, 4 - 3 Outputs (1st module in Mode 7A)
8 Cascaded Module Operation MODEs 5B+5B+7A+5B+5B +5B/7A, No External Clock Required 12-Phase
9 External Clock or External Logic Circuits Requir ed for Equal Phase Interval 5, 7, 8, 9, 10, 11,
(PHASE >12) NOTE: 13. “2 ND CHANNEL WRT 1ST” means “second channel with respect to first;” in other words, Channel 2 lags Channel 1 by the degrees specified in this column. For example, 90° means Channel 2 lags Channel 1 by 90°; -60° means Channel 2 leads Channel 1 by 60°. 14. “VMON1” means that the pin is tied to the VMON1 pin of the same module. “Divider” means that there is a resistor divider from VOUT to SGND; refer to Figure 24. “1kΩ” means that there is a 1kΩ resistor connecting the pin to SGND; refer to Figure 22.
thermal and electrical conductivity, low weight, and small size. mold compound to protect these devices. profile parameters. These guidelines are general design rules. Users can modify parameters according to specific applications. is shown in the L26.17x17 package outline drawing on page 28. should match 1:1 with the package exposed die pads. the thermal land size and as your board design rules allow. help prevent solder bridging between adjacent I/O lands. shown in the L26.17x17 package outline drawing on page 28. of the whole stencil pattern when designing the pads. recommended for this large-pitch (1.0mm) QFN. FIGURE 33. POWER LOSS CURVES OF 5V IN FIGURE 34. POWER LOSS CURVES OF 12V IN
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7822.1 January 31, 2013 For additional products, see www.intersil.com/en/products.html Reflow Parameters Due to the low mount height of the QFN, "No Clean" Type 3 solder paste, per ANSI/J-STD-005, is recommended. Nitrogen purge is also recommended during reflow. A system board reflow profile depends on the thermal mass of the entire populated board, so it is not practical to define a specific soldering profile just for the QFN. The profile given in Figure 41 is provided as a guideline to customize for varying manufacturing practices and applications. About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure, personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page. Also, please check the product information page to ensure that you have the most updated datasheet: ISL8225M To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php FIGURE 41. TYPICAL REFLOW PROFILE KEEP LESS THAN 30s WITHIN 5°C OF PEAK TEMP.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE January 4, 2013 FN7822.1 “Thermal Information” on page 6: Changed “Maximum Storage Temperature Range” from "-40°C to +150°C" to "-55°C to +150°C" “Selection of Input Capacitor” on page 19: Added "fSW" to Equation 2. Added "fSW is the switching frequency (Hz)" December 3, 2012 FN7822.0 Initial Release
27 FN7822.1 January 31, 2013 Package Outline Drawing L26.17x17
26 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN)
Rev 4, 10/12 BOTTOM VIEW SIDE VIEW TOP VIEW S 17.8±0.2 17.0±0.2 17.8±0.2 17.0±0.2 All Around of 10°(MAX) 0.25 7.5±0.2 R0.25 234567 13 14 1516 17181920 PIN-TO-PIN DISTANCE (BOTTOM VIEW)0.05 S AB
0.2 S AB
S 0.2 S0.03 AAAAAAAAAAAA AAAAAAAAAAAAA A A A A A A A A A A A A A A A A A A A A A A A A:1.0±0.1 234567 13 14 1516171819 20 PIN NO. DEFINITION (TOP VIEW) A B 52x 0.50 (ALL OF LEAD TIPS) 16x 1.75±0.05 (FULL LEAD) 16x 0.55 (FULL LEAD) 16X 0.70 (FULL LEAD) 3.50 3.50 3.50 2.37 2.775.33 4.93 3.66 8.95 0.38 0.80 4.00 3.353.35 14x 0.75 12x 1.07 2.97 0.10 0.25 4.93 8.95 0.10 0.25 5.33 0.100.10 0.100.10 3.50 0.70 0.38
28 FN7822.1 January 31, 2013 SOLDER STENCIL PATTERN WITH SQUARE PADS 1 OF 2 (TOP VIEW) SOLDER STENCIL PATTERN WITH SQUARE PADS 2 OF 2 (TOP VIEW) TYPICAL RECOMMENDED LAND PATTERN (TOP VIEW) 0.15 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 5.75 6.25 0.75 0.25 1.25 1.75 2.25 2.75 3.15 3.85 4.25 4.75 5.25 5.75 6.25 6.75 7.15 0.25 0.25 0.95 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 5.75 6.25 0.95 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 5.75 6.25 7.25 7.25 7.93 5.25 4.75 4.25 3.75 3.25 2.75 2.25 1.75 1.25 0.85 0.15 0.15 0.85 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 7.93 9.20 9.20 7.83 7.15 6.75 6.25 5.75 5.25 4.75 4.25 3.85 3.15 2.75 2.25 1.75 1.25 0.75 0.25 0.15 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 5.75 6.25 7.25 9.20 7.83 7.25 7.83 9.20 9.20 7.93 7.83 0.00 0.05 1.13 1.73 2.80 4.20 5.28 5.88 6.95 5.54 7.38 4.05 2.70 2.40 1.05 1.05 2.40 2.70 4.05 7.38 5.54 0.05 1.13 0.60 1.73 2.80 2.40 3.60 4.20 5.28 5.41 6.01 5.88 6.95 7.23 7.38 6.83 6.43 5.43 5.03 3.36 2.76 0.95 0.70 0.70 0.95 3.36 5.03 5.43 6.43 6.83 7.38 1.80 6.03 6.60 7.38 6.60 7.38 0.00 0.65 1.35 1.65 2.35 2.65 3.35 3.65 4.35 4.65 5.35 5.65 6.35 1.35 3.75 7.25 3.90 0.05 7.15 7.83 7.15 0.35 0.75 4.35 4.65 5.35 5.65 6.35 7.15 0.35 0.75 4.35 4.65 5.35 5.65 6.35 7.15 9.30 9.30 6.35 5.65 5.35 4.65 4.35 3.65 3.35 2.65 2.35 1.65 1.350.65 0.25 3.75 3.90 7.25 9.30 7.15 9.30 6.53 9.30 7.83 5.73 5.33 0.75 0.65 0.40 0.25 0.25 0.40 0.65 0.75 5.73 5.33 6.13 6.53 7.83 6.50 0.55 6.50 6.13 0.25 3.10 3.25 3.25 3.10 5.93 0.55 5.24 9.30 5.24 9.30 9.30 7.98 7.70 7.96 7.98 7.70 7.96