TMK325BJ106MM

TPS51123 TI | Alldatasheet

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(QFN-24) LL1 DRVL1 LL2 DRVL2 13 14 15 16 17 18 EN0 SKIPSEL GND VIN VREG5 ENC 6 5 4 3 2 1 TRIP2 VFB2 TONSEL VREF VFB1 TRIP1 PowerPAD 220 nF 20 k/c87 20 k/c87 30 k/c87 100 k/c87 VREG5 33 /c109F 5.1 /c87 0.1 /c109F 130 k/c87130 k/c87 3.3 /c109F 330 /c109F VO1 5 V VIN VREG5 ENC VIN 10 /c109F x 2 VIN 5.5 V to 28 V EN0 5.1 /c87 0.1 /c109F 3.3 /c109F 330 /c109F VO2 3.3 V 10 /c109F x 2 10 /c109F 13 k/c87 UDG-08167 VIN TPS51123 www.ti.com SLUS890 DECEMBER 2008 Dual-Synchronous, Step-Down Controller with Out-of-Audio Operation and 100-mA LDOs for Notebook System Power Notebook Computers Wide-Input Voltage Range: 5.5 V to V I/O Supplies Output Voltage Range: V to 5.5 V System Power Supplies Built-in 100-mA 5-V/3.3-V LDO with Switches Built-in 2-V Reference Output With/Without Out-of-Audio Mode Selectable The TPS51123 is a cost effective, dual-synchronous Light-Load and PWM only Operation buck controller targeted for notebook system power Internal 1.6-ms Voltage Servo Softstart supply solutions. It provides 5-V and 3.3-V LDOs and Adaptive On-Time Control Architecture with requires few external components. The TPS51123 Four Selectable Frequency Setting supports high efficiency, fast transient responses and provides a combined power-good signal. 4500 ppm/ C R DS(on) Current Sensing Out-of-Audio mode light-load operation enables low Built-In Output Discharge acoustic noise at much higher efficiency than Power Good Output conventional forced PWM operation. Adaptive on-time D-CAP control provides convenient and Built-in OVP/UVP/OCP efficient operation. The part operates with supply Thermal Shutdown (Non-latch) input voltages ranging from 5.5 V to V and 24-Pin QFN (RGE) Package supports output voltages from V to 5.5 The TPS51123 is available in a 24-pin QFN package and is specified from -40 C to C ambient temperature range. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. Out-of-Audio, D-CAP are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1) DISSIPATION RATINGS RECOMMENDED OPERATING CONDITIONS TPS51123 SLUS890 DECEMBER 2008 www.ti.com ORDERING INFORMATION (1) MINIMUM T A PACKAGE PART NUMBER PINS TRANSPORT MEDIA ECO PLAN QUANTITY TPS51123RGET 250 Green Plastic Quad Flat Pack -40 C to C Tape/Reel (RoHS and (QFN) TPS51123RGER 3000 no Sb/Br) (1) For the most current spcifications and package information, see the Package Option Addendum located at the end of this data sheet or refer to our web site at http://www.ti.com. over operating free-air temperature range (unless otherwise noted) PARAMETER VALUE UNIT VBST1, VBST2 -0.3 to VIN -0.3 to Input voltage range LL1, LL2 -2.0 to V (1) VBST1, VBST2 (2) -0.3 to EN0, ENC, TRIP1, TRIP2, VFB1, VFB2, VO1, VO2, TONSEL, SKIPSEL -0.3 to DRVH1, DRVH2 -1.0 to Output voltage range DRVH1, DRVH2 (2) -0.3 to V (1) PGOOD, VREG3, VREG5, VREF, DRVL1, DRVL2 -0.3 to T J Junction temperature range -40 to 125 C T stg Storage temperature -55 to 150 (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Voltage values are with respect to the corresponding LLx terminal. 2-oz. trace and copper pad with solder. DERATING FACTOR ABOVE T A PACKAGE T A C POWER RATING T A C POWER RATING C pin RGE (1) 1.85 W 18.5 mW/ C 0.74 W (1) Enhanced thermal conductance by x thermal vias beneath thermal pad. over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX UNIT Supply voltage VIN 5.5 Input voltage range VBST1, VBST2 -0.1 VBST1, VBST2 (wrt LLx) -0.1 5.5 EN0, ENC, TRIP1, TRIP2, VFB1, VFB2, VO1, VO2, -0.1 5.5 TONSEL, SKIPSEL V Output voltage range DRVH1, DRVH2 -0.8 DRVH1, DRVH2 (wrt LLx) -0.1 5.5 LL1, LL2 -1.8 VREF, VREG3, VREG5 -0.1 5.5 PGOOD, DRVL1, DRVL2 -0.1 5.5 T A Operating free-air temperature -40 C Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51123

www.ti.com SLUS890 DECEMBER 2008 over operating free-air temperature range, VIN V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VIN current, T A no load, VO1 I VIN1 VIN supply current1 VO2 EN0=open, ENC 0.55 mA TRIP1 TRIP2 VFB1 VFB2 2.05 V VIN current, T A no load, VO1 I VIN2 VIN supply current2 VO2 3.3 EN0=open, ENC 6.5 µ A TRIP1 TRIP2 VFB1 VFB2 2.05 V VO1 current, T A no load, VO1 I VO1 VO1 current VO2 3.3 EN0=open, ENC 0.8 1.5 mA TRIP1 TRIP2 VFB1 VFB2 2.05 V VO2 current, T A no load, VO1 I VO2 VO2 current VO2 3.3 EN0=open, ENC 100 TRIP1 TRIP2 VFB1 VFB2 2.05 V VIN current, T A no load, µ A I VINSTBY VIN standby current 250 EN0 1.2 ENC V VIN current, T A no load, I VINSDN VIN shutdown current EN0 ENC V VREF OUTPUT I VREF A 1.98 2.00 2.02 V VREF VREF output voltage V µ A I VREF 100 µ A 1.97 2.00 2.03 VREG5 OUTPUT VO1 I VREG5 100 mA, T A C 4.8 5.2 VO1 I VREG5 100 mA, V VREG5 VREG5 output voltage 4.75 5.25 V 6.5 V VIN V VO1 I VREG5 mA, 5.5 V VIN V 5.25 I VREG5 VREG5 output current VO1 VREG5 4.5 V 100 175 250 mA Turns on 4.55 4.7 4.85 V TH5VSW Switch over threshold V Hysteresis 0.15 0.25 0.3 R 5VSW V SW R ON VO1 I VREG5 100 mA Ω VREG3 OUTPUT VO2 I VREG3 100 mA, T A C 3.2 3.33 3.46 V VREG3 VREG3 output voltage VO2 I VREG3 100 mA, 6.5 V VIN V 3.13 3.33 3.5 V VO2 I VREG3 mA, 5.5 V VIN V 3.13 3.33 3.5 I VREG3 VREG3 output current VO2 VREG3 V 100 175 250 mA Turns on 3.05 3.15 3.25 V TH3VSW Switch over threshold V Hysteresis 0.1 0.2 0.25 R 3VSW V SW R ON VO2 3.3 I VREG3 100 mA 1.5 Ω INTERNAL REFERENCE VOLTAGE V IREF Internal reference voltage I VREF beginning of ON state 1.95 1.98 2.01 FB voltage, I VREF skip mode 1.98 2.01 2.04 V FB voltage, I VREF OOA mode (1) 2.00 2.035 2.07 V VFB VFB regulation voltage FB voltage, I VREF continuous conduction 2.00 mode (1) I VFB VFB input current VFBx 2.0 T A C -20 nA OUTPUT VOLTAGE, V OUT DISCHARGE I Dischg VOUT discharge current ENC VOx 0.5 V mA (1) Ensured by design. Not production tested. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS51123

www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VIN V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT OUTPUT DRIVERS Source, V BSTx DRVHx 100 mV R DRVH DRVH resistance Sink, V DRVHx LLx 100 mV 1.5 Ω Source, V VREG5 DRVLx 100 mV R DRVL DRVL resistance Sink, V DRVLx 100 mV 1.5 DRVHx-off to DRVLx-on T D Dead time ns DRVLx-off to DRVHx-on INTERNAL BST DIODE V FBST Forward voltage V VREG5-VBSTx I F mA, T A C 0.7 0.8 0.9 V I VBSTLK VBST leakage current VBSTx LLx T A C 0.1 µ A DUTY AND FREQUENCY CONTROL T ON11 CH1 on time V IN VO1 200 kHz setting 2080 T ON12 CH1 on time V IN VO1 245 kHz setting 1700 T ON13 CH1 on time V IN VO1 300 kHz setting 1390 T ON14 CH1 on time V IN VO1 365 kHz setting 1140 T ON21 CH2 on time V IN VO2 3.3 250 kHz setting 1100 ns T ON22 CH2 on time V IN VO2 3.3 305 kHz setting 900 T ON23 CH2 on time V IN VO2 3.3 375 kHz setting 730 T ON24 CH2 on time V IN VO2 3.3 460 kHz setting 600 T ON(min) Minimum on time T A C T OFF(min) Minimum off time T A C 300 SOFTSTART T SS Internal SS time Internal soft start 1.1 1.6 2.1 ms POWERGOOD PG in from lower 92.50% 95% 97.50% V THPG PG threshold PG in from higher 102.50% 105% 107.50% PG hysteresis 2.50% 7.50% I PGMAX PG sink current PGOOD 0.5 V mA T PGDEL PG delay Delay for PG in 350 510 670 µ s LOGIC THRESHOLD AND SETTING CONDITIONS Shutdown 0.4 V EN0 EN0 setting voltage V Enable 2.4 I EN0 EN0 current V EN0 0.2 V 3.5 µ A Shutdown 0.6 V ENC ENC threshold voltage V Enable 200 kHz/250 kHz 1.5 245 kHz/305 kHz 1.9 2.1 V TONSEL TONSEL setting voltage V 300 kHz/375 kHz 2.7 3.6 365 kHz/460 kHz 4.7 Auto skip 1.5 V SKIPSEL SKIPSEL setting voltage PWM only 1.9 2.1 V OOA auto skip 2.7 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51123

www.ti.com SLUS890 DECEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VIN V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT PROTECTION: CURRENT SENSE I TRIP TRIPx source current V TRIPx 920 mV, T A C 9.4 10.6 µ A TRIPx current temperature TC ITRIP On the basis of C 4500 ppm/ C coefficient ((V TRIPx-GND /9)-24 mV GND-LLx voltage, V OCLoff OCP comparator offset V TRIPx-GND 920 mV V OCL(max) Maximum OCL setting V TRIPx V 185 205 225 mV Zero cross detection V ZC V GND-LLx voltage comparator offset V TRIP Current limit threshold V TRIPx-GND voltage (2) 0.515 V PROTECTION: UNDERVOLTAGE AND OVERVOLTAGE PROTECTION V OVP OVP trip threshold OVP detect 110% 115% 120% T OVPDEL OVP prop delay µ s UVP detect 55% 60% 65% V UVP Output UVP trip threshold Hysteresis 10% T UVPDEL Output UVP prop delay µ s T UVPEN Output UVP enable delay 1.4 2.6 ms UNDERVOLTAGE LOCKOUT (UVLO) Wake up 4.1 4.2 4.3 V UVVREG5 VREG5 UVLO threshold Hysteresis 0.38 0.43 0.48 V V UVVREG3 VREG3 UVLO threshold Shutdown (2) VO2-1 THERMAL SHUTDOWN Shutdown temperature (2) 150 T SDN Thermal shutdown threshold C Hysteresis (2) (2) Ensured by design. Not production tested. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS51123

www.ti.com Table TERMINAL FUNCTIONS TABLE TERMINAL I/O NO. DRVH1 O High-side N-channel MOSFET driver outputs. LL referenced drivers. DRVH2 DRVL1 O Low-side N-channel MOSFET driver outputs. GND referenced drivers. DRVL2 Master enable input. EN0 I/O Open LDOs on, and ready to turn both switcher channels. GND disable all circuit Channel and Channel enable input. Pull up to the voltage ranging 3.3-V to 5-V to turn on both ENC I switcher channels. Short to ground to shutdown them. GND Ground. LL1 I Switch node connections for high-side drivers, current limit and control circuitry. LL2 PGOOD O Powergood window comparator output for channel and (Logical AND) Selection pin for operation mode: OOA auto skip Connect to VREG3 or VREG5 SKIPSEL I PWM only: Connect to VREF Auto skip: Connect to GND TRIP1 I/O OCL trip setting pins. Connect resistor from this pin to GND to set threshold for synchronous R DS(on) sense. TRIP2 On-time adjustment pin. 365 kHz/460 kHz setting: connect to VREG5 TONSEL I 300 kHz/375 kHz setting: connect to VREG3 245 kHz/305 kHz setting: connect to VREF 200 kHz/250 kHz setting: connect to GND VBST1 I Supply input for high-side N-channel MOSFET driver (boost terminal). VBST2 VFB1 I SMPS feedback inputs. Connect with feedback resistor divider. VFB2 VIN I High voltage power supply input for 5-V/3.3-V LDO. VO1 Output connection to SMPS. These terminals work as fixed voltage inputs and output discharge I/O inputs. VO1 and VO2 also work as 5-V and 3.3-V switch over return power input respectively. VO2 2-V reference voltage output. Connect 220-nF to µ F ceramic capacitor to Signal GND near the VREF O device. 3.3-V power supply output. Connect a 10- µ F ceramic capacitor to Power GND near the device. A VREG3 O µ F ceramic capacitor is acceptable when not loaded. VREG5 O 5-V power supply output. Connect a 33- µ F ceramic capacitor to Power GND near the device. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51123

(QFN-24) VO1 PGOOD VO2 VREG3 VBST1 DRVL1 LL1 DRVH1 VBST2 DRVH2 LL2 DRVL2 EN0TRIP2 VFB2 VREF TONSEL VFB1 TRIP1 SKIPSEL GND VIN ENC VREG52 7 8 9 10 11 24 23 22 21 20 19 TPS51123 www.ti.com SLUS890 DECEMBER 2008 QFN PACKAGE (TOP VIEW) Functional Block Diagram Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS51123

www.ti.com Switcher Controller Block Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51123

-50 0 50 100 150 TJ - Junction Temperature - /c176C IVIN1 - VIN Supply Current1 - /c109A VIN SUPPLY CURRENT1 vs INPUT VOLTAGE 100 200 300 400 500 600 700 800 5 10 15 20 25 VIN - Input Voltage - V IVIN1 - VIN Supply Current1 - /c109A VIN SUPPLY CURRENT2 vs JUNCTION TEMPERATURE -50 0 50 100 150 TJ - Junction Temperature - °C IVI N2 - VIN Supply Current2 - /c109A VIN SUPPLY CURRENT2 vs INPUT VOLTAGE 5 10 15 20 25 VIN - Input Voltage - V IVIN2 - VIN Supply Current2 - /c109A TPS51123 www.ti.com SLUS890 DECEMBER 2008 Figure Figure Figure Figure Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS51123

VIN□STANDBY CURRENT vs INPUT□VOLTAGE 100 150 200 250 5 10 15 20 25 VIN -□Input□Voltage□-□V IVINSTBY - VIN Standby Current - nA VIN STANDBY CURRENT vs JUNCTION TEMPERATURE 100 150 200 250 -50 0 50 100 150 TJ - Junction Temperature - °C IVINSTBY - VIN Standby Current - /c109A VIN SHUTDOWN CURRENT vs JUNCTION TEMPERATURE -50 0 50 100 150 TJ - Junction Temperature - °C IVI NSDN - VIN Shutdown Current - /c109A VIN SHUTDOWN CURRENT vs INPUT VOLTAGE 5 10 15 20 25 VIN - Input Voltage - V IVINSDN - VIN Shutdown Current - /c109A TPS51123 SLUS890 DECEMBER 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure Figure Figure Figure Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51123

SWITCHING□FREQUENCY vs INPUT□VOLTAGE 100 200 300 400 500 6 8 10 12 14 16 18 20 22 24 26 VIN -□Input□Voltage□-□V fSW - Swithching Frequency - kHz TONSEL =□GND CH1 CH2 CURRENT SENSE CURRENT vs JUNCTION TEMPERATURE 50 0 50 100 150 TJ - Junction Temperature - °C - Current Sense Current - /c109AITRIP SWITCHING□FREQUENCY vs INPUT□VOLTAGE 100 200 300 400 500 6 8 10 12 14 16 18 20 22 24 26 VIN -□Input□Voltage□-□V fSW - Swithching Frequency - kHz TONSEL =□3.3V CH1 CH2 SWITCHING□FREQUENCY vs INPUT□VOLTAGE 100 200 300 400 500 6 8 10 12 14 16 18 20 22 24 26 VIN -□Input□Voltage□-□V fSW - Swithching Frequency - kHz TONSEL =□2V CH1 CH2 TPS51123 www.ti.com SLUS890 DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) Figure Figure 10. Figure 11. Figure 12. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS51123

SWITCHING□FREQUENCY vs OUTPUT□CURRENT 100 200 300 400 500 0.001 0.01 0.1 1 10 IOUT -□Output□Current□- A fSW - Swithching Frequency - kHz TONSEL =□GND CH2 Auto-skip CH2□OOA CH2□PWM□Only CH1□PWM□Only CH1 Auto-skip CH1□OOA SWITCHING□FREQUENCY vs INPUT□VOLTAGE 100 200 300 400 500 6 8 10 12 14 16 18 20 22 24 26 VIN -□Input□Voltage□-□V fSW - Swithching Frequency - kHz TONSEL =□5V CH1 CH2 SWITCHING□FREQUENCY vs OUTPUT□CURRENT 100 200 300 400 500 0.001 0.01 0.1 1 10 IOUT -□Output□Current□- A fSW - Swithching Frequency - kHz TONSEL =□3.3V CH2 Auto-skip CH2□OOA CH2□PWM□Only CH1□PWM□Only CH1 Auto-skip CH1□OOA SWITCHING□FREQUENCY vs OUTPUT□CURRENT 100 200 300 400 500 0.001 0.01 0.1 1 10 IOUT -□Output□Current□- A fSW - Swithching Frequency - kHz TONSEL =□2V CH2 Auto-skip CH2□OOA CH2□PWM□Only CH1□PWM□Only CH1 Auto-skip CH1□OOA TPS51123 SLUS890 DECEMBER 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure 13. Figure 14. Figure 15. Figure 16. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51123

SWITCHING□FREQUENCY vs OUTPUT□CURRENT 100 200 300 400 500 0.001 0.01 0.1 1 10 IOUT -□Output□Current□- A fSW - Swithching Frequency - kHz TONSEL =□5V CH2 Auto-skip CH2□OOA CH2□PWM□Only CH1□PWM□Only CH1 Auto-skip CH1□OOA OVP/UVP THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 100 110 120 130 140 150 -50 0 50 100 150 TJ - Junction Temperature - °C V OVP/VUVP - OVP/UVP Threshold - % VR E G5 OU TPU T VOLTAGE vs OU TPU T CU R R E N T 4.90 4.95 5.00 5.05 0 20 40 60 80 100 IVREG5 - VR E G5 Output Curre nt - m A VVREG5 - VREG5 Output Voltage - V VR E G3 OU TPU T VOLTAGE vs OU TPU T CU R R E N T 3.2 3.25 3.3 3.35 0 20 40 60 80 100 IVREG3 - VR E G3 Output Curre nt - m A VVREG3 - VREG3 Output Voltage - V TPS51123 www.ti.com SLUS890 DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) Figure 17. Figure 18. Figure 19. Figure 20. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS51123

4.950 4.975 5.000 5.025 5.050 5.075 0.001 0.01 0.1 1 10 IOUT1 - 5-V Output Current - A VO UT1- 5-V Output Voltage - V PWM Only Auto-skip OOA VREF OUTPUT VOLTAGE vs OUTPUT CURRENT 1.980 1.985 1.990 1.995 2.000 2.005 2.010 2.015 2.020 0 20 40 60 80 100 IVREF - VREF Output Current - /c109A VVREF - VREF Output Voltage - V 5-V□OUTPUT□VOLTAGE vs INPUT□VOLTAGE 4.950 4.975 5.000 5.025 5.050 5.075 6 8 10 12 14 16 18 20 22 24 26 VIN -□Input□Voltage□-□V VOUT1 - 5-V Output Voltage - V IO =□0A IO =□6A 3.3-V□OUTPUT□VOLTAGE vs OUTPUT□CURRENT 3.240 3.270 3.300 3.330 3.360 0.001 0.01 0.1 1 10 IOUT2 -□3.3-V□Output□Current□- A VOUT2 - 3.3-V Output Voltage - V PWM□Only Auto-skip OOA TPS51123 SLUS890 DECEMBER 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure 21. Figure 22. Figure 23. Figure 24. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51123

0.001 0.01 0.1 1 10 /c104– Efficiency – % VIN = 20 V VIN = 12 V VIN = 8 V OOA Auto-Skip PWM Only IOUT1 – 5-V Output Current – A 5-V EFFICIENCY vs OUTPUT CURRENT 3.3-V□OUTPUT□VOLTAGE vs INPUT□VOLTAGE 3.240 3.270 3.300 3.330 3.360 6 8 10 12 14 16 18 20 22 24 26 VIN -□Input□Voltage□-□V VOUT2 - 3.3-V Output Voltage - V IO =□0A IO =□6A 3.3-V EFFICIENCY vs OUTPUT CURRENT 100 0.001 0.01 0.1 1 10 IOUT2 - 3.3-V Output Current - A /c104- Efficiency - % Auto-skip PWM Only OOA 5-V Switcher ON VIN=8V VIN=12V VIN=20V TPS51123 www.ti.com SLUS890 DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) Figure 25. Figure 26. Figure 27. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS51123

VOUT1 (100mV/div) IIND (5A/div) IOUT1 (5A/div) VOUT2 (100mV/div) IIND (5A/div) IOUT2 (5A/div) ENC (5 V/div) VOUT2 (2 V/div) PGOOD (5 V/div) ENC (5 V/div) VOUT1 (2 V/div) PGOOD (5 V/div) TPS51123 SLUS890 DECEMBER 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) 5-V Load Transient Response 3.3-V Load Transient Response Figure 28. Figure 29. 5-V Startup Waveforms 3.3-V Startup Waveforms Figure 30. Figure 31. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51123

VOUT1 (200mV/div) VREG5 (200mV/div) VOUT2 (200mV/div) VREG3 (200mV/div) ENC (10 V/div) VOUT2 (2 V/div) PGOOD (5 V/div) DRVL2 (5 V/div) ENC (10 V/div) VOUT1 (2 V/div) PGOOD (5 V/div) DRVL1 (5 V/div) TPS51123 www.ti.com SLUS890 DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) 5-V Switchover Waveforms 3.3-V Switchover Waveforms Figure 32. Figure 33. 5-V Soft-stop Waveforms 3.3-V Soft-stop Waveforms Figure 34. Figure 35. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS51123

www.ti.com The main control loop of the switch mode power supply (SMPS) is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports a proprietary D-CAP mode. D-CAP mode does not require external compensation circuit and is suitable for low external component count configuration when used with appropriate amount of ESR at the output capacitor(s). At the beginning of each cycle, the synchronous top MOSFET is turned on, or becomes ON state. This MOSFET is turned off, or becomes OFF state, after internal one shot timer expires. This one shot is determined by V IN and V OUT to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time control. The MOSFET is turned on again when the feedback point voltage, VFB, decreased to match with internal 2-V reference. The inductor current information is also monitored and should be below the over current threshold to initiate this new cycle. Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom or the rectifying MOSFET is turned on at the beginning of each OFF state to keep the conduction loss minimum.The rectifying MOSFET is turned off before the top MOSFET turns on at next switching cycle or when inductor current information detects zero level. In the auto-skip mode or the OOA skip mode, this enables seamless transition to the reduced frequency operation at light load condition so that high efficiency is kept over broad range of load current. TPS51123 does not have a dedicated oscillator on board. However, the part runs with pseudo-constant frequency by feed-forwarding the input and output voltage into the on-time, one-shot timer. The on-time is controlled inverse proportional to the input voltage and proportional to the output voltage so that the duty ratio will be kept as VOUT/VIN technically with the same cycle time. The frequencies are set by TONSEL terminal connection as Table Table TONSEL Connection and Switching Frequency SWITCHING FREQUENCY (kHz) TONSEL CONNECTION CH1 CH2 GND 200 250 VREF 245 305 VREG3 300 375 VREG5 365 460 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51123

Switching ModulatorVoltage Divider IoIcIL Vc Output Capacitor fSW O 1f 2 ESR C 4/c61 /c163/c112 /c180 /c180 (1) Ramp Signal TPS51123 www.ti.com SLUS890 DECEMBER 2008 From small-signal loop analysis, a buck converter using D-CAP TM mode can be simplified as below. Figure 36. Simplifying the Modulator The output voltage is compared with internal reference voltage after divider resistors, and R2. The PWM comparator determines the timing to turn on high-side MOSFET. The gain and speed of the comparator is high enough to keep the voltage at the beginning of each on cycle substantially constant. For the loop stability, the 0dB frequency, f defined below need to be lower than of the switching frequency. As f is determined solely by the output capacitor's characteristics, loop stability of D-CAP TM mode is determined by the capacitor's chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of several 100 µ F and ESR in range of m Ω These make f on the order of 100 kHz or less and the loop will be stable. However, ceramic capacitors have f at more than 700 kHz, which is not suitable for this operational mode. The TPS51123 adds a ramp signal to the 2-V reference in order to improve its jitter performance. As described in the previous section, the feedback voltage is compared with the reference information to keep the output voltage in regulation. By adding a small ramp signal to the reference, the S/N ratio at the onset of a new switching cycle is improved. Therefore the operation becomes less jitter and stable. The ramp signal is controlled to start with -20mV at the beginning of ON-cycle and to become mV at the end of OFF-cycle in steady state. By using this scheme, the TPS51123 improve jitter performance without sacrificing the reference accuracy. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS51123

/c40 /c41 f IN OUT OUT OUT(LL) IN 2 L V V V V /c180 /c180 /c180 /c45 /c180/c61 (2) Out-of-Audio Light-Load Operation Enable and Soft Start VREG5/VREG3 Linear Regulators TPS51123 SLUS890 DECEMBER 2008 www.ti.com The TPS51123 automatically reduces switching frequency at light load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly and without increase of V OUT ripple. Detail operation is described as follows. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor current is detected. As the load current further decreased, the converter runs in discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next ON cycle. The ON time is kept the same as that in the heavy load condition. In reverse, when the output current increase from light load to heavy load, switching frequency increases to the preset value as the inductor current reaches to the continuous conduction. The transition load point to the light load operation I OUT(LL) (i.e. the threshold between continuous and discontinuous conduction mode) can be calculated as follows; where f is the PWM switching frequency. Switching frequency versus output current in the light load condition is a function of V IN and V OUT but it decreases almost proportional to the output current from the I OUT(LL) shown in Equation For example, it ise kHz at I OUT(LL) if the frequency setting is 300 kHz. Out-of-Audio (OOA) light-load mode is a unique control feature that keeps the switching frequency above acoustic audible frequencies toward virtually no load condition while maintaining best of the art high conversion efficiency. When the Out-of-Audio operation is selected, OOA control circuit monitors the states of both MOSFET and force to change into the ON state if both of MOSFETs are off for more than µ This means that the top MOSFET is turned on even if the output voltage is higher than the target value so that the output capacitor is tends to be overcharged. The OOA control circuit detects the over-voltage condition and begins to modulate the on time to keep the output voltage regulated. As a result, the output voltage becomes 0.5% higher than normal light-load operation. EN0 is the control pin of VREG5, VREG3 and VREF regulators. Bring this node down to GND disables those three regulators and minimize the shutdown supply current to µ Pulling this node up to 3.3 V or V will turn the three regulators on to standby mode. The two switch mode power supplies (channel-1, channel-2) become ready to enable at this standby mode. The TPS51123 has an internal, 1.6 ms, voltage servo softstart for each channel. When the ENC pin becomes higher than the enable threshold voltage, which is typically 1.26 an internal DAC begins ramping up the reference voltage to both of the PWM comparators at the same time. Smooth control of the output voltage is maintained during start up. Table Enabling State EN0 ENC VREF VREG5 VREG3 CH1 CH2 GND Don t Care Off Off Off Off Off Open Off On On On Off Off Open On On On On On On There are two sets of 100-mA standby linear regulators which outputs V and 3.3 respectively. The VREG5 serves as the main power supply for the analog circuitry of the device and provides the current for gate drivers. The VREG3 is intended mainly for auxiliary 3.3-V supply for the notebook system during standby mode. Add a ceramic capacitor with a value of at least µ F and place it close to the VREG5 pin, and add at most µ F to the VREG3 pin. Total capacitance connected to the VREG3 pin should not exceed µ F Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51123

www.ti.com SLUS890 DECEMBER 2008 When the VO1 voltage becomes higher than 4.7 V AND channel-1 internal powergood flag is generated, internal 5-V LDO regulator is shut off and the VREG5 output is connected to VO1 by internal switch over MOSFET. The 510- µ s powergood delay helps a switch over without glitch. When the VO2 voltage becomes higher than 3.15 V AND channel-2 internal powergood flag is generated, internal 3.3-V LDO regulator is shut off and the VREG3 output is connected to VO2 by internal switch over MOSFET. The 510- µ s powergood delay helps a switch over without glitch. The TPS51123 has one powergood output that indicates 'high' when both switcher outputs are within the targets (AND gated). The powergood function is activated with 2-ms internal delay after ENC goes high. If the output voltage becomes within of the target value, internal comparators detect power good state and the powergood signal becomes high after 510- µ s internal delay. Therefore PGOOD goes high around 2.5 ms after ENC goes high. If the output voltage goes outside of 10% of the target value, the powergood signal becomes low after µ s internal delay. The powergood output is an open drain output and is needed to be pulled up outside. Also note that, in the case of Auto-skip or Out-of-Audio mode, if the output voltage goes +10% above the target value and the power-good signal flags low, then the loop attempts to correct the output by turning on the low-side driver (forced PWM mode). After the feedback voltage returns to be within +5% of the target value and the power-good signal goes high, the controller returns back to auto-skip mode or Out-of-Audio mode. When ENC is low, the TPS51123 discharges outputs using internal MOSFET which is connected to VOx and GND. The current capability of these MOSFETs is limited to discharge slowly. The low-side driver is designed to drive high current low R DS(on) N-channel MOSFET(s). The drive capability is represented by its internal resistance, which are Ω for VREG5 to DRVLx and 1.5 Ω for DRVLx to GND. A dead time to prevent shoot through is internally generated between top MOSFET off to bottom MOSFET on, and bottom MOSFET off to top MOSFET on. 5-V bias voltage is delivered from VREG5 supply. The instantaneous drive current is supplied by an input capacitor connected between VREG5 and GND. The average drive current is equal to the gate charge at Vgs V times switching frequency. This gate drive current as well as the high-side gate drive current times V makes the driving power which need to be dissipated from TPS51123 package. The high-side driver is designed to drive high current, low R DS(on) N-channel MOSFET(s). When configured as a floating driver, 5-V bias voltage is delivered from VREG5 supply. The average drive current is also calculated by the gate charge at Vgs V times switching frequency. The instantaneous drive current is supplied by the flying capacitor between VBSTx and LLx pins. The drive capability is represented by its internal resistance, which are Ω for VBSTx to DRVHx and 1.5 Ω for DRVHx to LLx. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS51123

/c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41TRIP TRIP TRIP R k I AV mV 24 mV 9 /c87 /c180 /c109/c61 /c45 (3) /c40 /c41 /c40 /c41 /c40 /c41 f IN OUT OUTTRIP RIPPLE TRIP OCP INDS on DS on V V VV I V 1I R 2 R 2 L V /c45 /c180/c61 /c43 /c61 /c43 /c180 /c180 /c180 (4) Overvoltage and Undervoltage Protection TPS51123 SLUS890 DECEMBER 2008 www.ti.com TPS51123 has cycle-by-cycle over current limiting control. The inductor current is monitored during the OFF state and the controller keeps the OFF state during the inductor current is larger than the over current trip level. In order to provide both good accuracy and cost effective solution, TPS51123 supports temperature compensated MOSFET R DS(on) sensing. The TRIPx pin should be connected to GND through the trip voltage setting resistor, R TRIP TRIPx terminal sources I TRIP current, which is µ A typically at room temperature, and the trip level is set to the OCL trip voltage V TRIP as below. Note that the V TRIP is limited up to about 205 mV internally. Note that when TRIPx voltage is under a certain thershould (typically 0.4V), the switcher channel concerned is shut down. The inductor current is monitored by the voltage between GND pin and LLx pin so that LLx pin should be connected to the drain terminal of the bottom MOSFET properly. Itrip has 4500 ppm/ C temperature slope to compensate the temperature dependency of the R DS(on) GND is used as the positive current sensing node so that GND should be connected to the proper current sensing device, i.e. the source terminal of the bottom MOSFET. As the comparison is done during the OFF state, V TRIP sets valley level of the inductor current. Thus, the load current at over current threshold, I OCP can be calculated as follows; In an over current condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall down. Eventually, it ends up with crossing the under voltage protection threshold and shutdown both channels. TPS51123 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuit latches as the top MOSFET driver OFF and the bottom MOSFET driver ON. Also, TPS51123 monitors VOx voltage directly and if it becomes greater than 5.75 V the TPS51123 turns off the top MOSFET driver. When the feedback voltage becomes lower than 60% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After µ TPS51123 latches OFF both top and bottom MOSFETs drivers, and shut off both drivers of another channel. This function is enabled after ms following ENC has become high. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51123

/c40 /c41 OUTV 2.0R1 R2 2.0 /c45/c61 /c180 (5) Choose the Inductor /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41f f OUT OUT OUT OUTIN max IN max IND ripple IN max OUT max IN max 1 3 I I V V V V V V L V V /c180 /c180 /c180 /c45 /c180 /c45 /c180 /c61 /c61 /c180 (6) /c40 /c41 /c40 /c41 /c40 /c41/c40 /c41 /c40 /c41f OUT OUTIN m axTRIP IND peak DS on IN m ax V 1 R L V V V I V/c180 /c45 /c180 /c61 /c43 /c180 (7) Choose the Output Capacitor(s) /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 fOUT RIPPLE V 20 mV 1 D 20 mV LESR 2 V I 2 V /c180 /c180 /c45 /c180 /c180/c61 /c45 /c180 (8) TPS51123 www.ti.com SLUS890 DECEMBER 2008 TPS51123 has VREG5 under voltage lock out protection (UVLO). When the VREG5 voltage is lower than UVLO threshold voltage both switch mode power supplies are shut off. This is non-latch protection. When the VREG3 voltage is lower than (VO2 V), both switch mode power supplies are also shut off TPS51123 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 150 C), TPS51123 is shut off including LDOs. This is non-latch protection. The external components selection is much simple in D-CAP Mode. The output voltage is programmed by the voltage-divider resistor, and R2, as shown in Figure is connected between VFBx pin and the output, and is connected betwen the VFBx pin and GND. Recommended value is from k Ω to k Ω Determine using equation as below. The inductance value should be determined to give the ripple current of approximately to of maximum output current. Larger ripple current increases output ripple voltage and improves S/N ratio and helps stable operation. The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated as follows. Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to meet required ripple voltage. A quick approximation is as shown in Equation This equation is based on that required output ripple slope is approximately mV per T SW (switching period) in terms of VFB terminal voltage. where D is the duty cycle Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS51123

www.ti.com Certain points must be considered before starting a layout work using the TPS51123. TPS51123 has only one GND pin and special care of GND trace design makes operation stable, especially when both channels operate. Group GND terminals of output voltage divider of both channels and the VREF capacitor as close as possible, and connect them to an inner GND plane with PowerPad and the overcurrent setting resistor, as shown in the thin GND line of Figure This trace is named Signal Ground (SGND). Group ground terminals of VIN capacitor(s), VOUT capacitor(s) and source of low-side MOSFETs as close as possible, and connect them to another inner GND plane with GND pin of the device and the GND terminal of VREG3 and VREG5 capacitors, as shown in the bold GND line of Figure This trace is named Power Ground (PGND). SGND should be connected to PGND at the middle point between ground terminal of VOUT capacitors. Inductor, VOUT capacitor(s), VIN capacitor(s) and MOSFETs are the power components and should be placed on one side of the PCB (solder side). Power components of each channel should be at the same distance from the TPS51123. Other small signal parts should be placed on another side (component side). Inner GND planes should shield and isolate the small signal traces from noisy power lines. PCB trace defined as LLx node, which connects to source of high-side MOSFET, drain of low-side MOSFET and high-voltage side of the inductor, should be as short and wide as possible. VREG5 requires capacitance of at least 33- µ F and VREG3 requires capacitance of at most 10- µ VREF requires a 220-nF ceramic bypass capacitor which should be placed close to the device and traces should be no longer than mm. Connect the overcurrent setting resistors from TRIPx to SGND and close to the device, right next to the device if possible. The discharge path (VOx) should have a dedicated trace to the output capacitor; separate from the output voltage sensing trace. When LDO5 is switched over Vo1 trace should be 1.5 mm with no loops. When LDO3 is switched over and loaded Vo2 trace should also be 1.5 mm with no loops. There is no restriction for just monitoring Vox. Make the feedback current setting resistor (the resistor between VFBx to SGND) close to the device. Place on the component side and avoid vias between this resistor and the device. Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0.65-mm (25 mils) or wider trace and via(s) of at least 0.5 mm (20 mils) diameter along this trace. All sensitive analog traces and components such as VOx, VFBx, VREF, GND, EN0, TRIPx, PGOOD, TONSEL and SKIPSEL should be placed away from high-voltage switching nodes such as LLx, DRVLx, and DRVHx nodes to avoid coupling. Traces for VFB1 and VFB2 should be short and laid apart each other to avoid channel to channel interference. In order to effectively remove heat from the package, prepare thermal land and solder to the package s thermal pad. Three by three or more vias with a 0.33-mm (13 mils) diameter connected from the thermal land to the internal ground plane should be used to help dissipation. This thermal land underneath the package should be connected to SGND, and should NOT be connected to PGND. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51123

(QFN24) 13 14 15 16 VBST1 DRVL1 LL1 DRVH1 VBST2 DRVH2 LL2 DRVL2 EN0 TRIP2 VFB2 VREF TONSEL VFB1 2 1 TRIP1 SKIPSEL 19 GND VIN ENC VO1 5V/8A 3.3/c109H IRF7821 VO1_GND PGND 10 /c109F 0.1/c109F VIN VO2 3.3V/8A 3.3 /c109H IRF7821 VO2_GND 0.1 /c109F VIN PowerPAD C11 33 /c109F VREG5 C10 POSCAP 330/c109F PGND 5.1/c87 VIN 5.5 ~ 28V 5.1/c87 10 /c109F 10 /c109F PGND POSCAP 330 /c109F 5V/100mA PGND 30k/c87 20k/c87 13k/c87 SGND VREG5 VREG5 100k/c87 PGND 20k/c87 0.22/c109F PGND SGND 130k/c87 SGND 130k/c87 ENC 10 /c109F PGND 3.3V/100mA 10 /c109F EN0 PGNDPGND SGND FDS6690AS FDS6690AS UDG-08165 SGND TPS51123 www.ti.com SLUS890 DECEMBER 2008 Figure 37. GND system of DC/DC converter using the TPS51123 Figure 38. 5-V/8-A, 3.3-V/8-A Application Circuit (245-kHz/305-kHz Setting) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS51123

www.ti.com List of Materials for 5-V/8-A, 3.3-V/8-A Application Circuit REFERENCE SPECIFICATION MANUFACTURER PART NUMBER DESIGNATOR C1, C2, C8, µ F/25 V Taiyo Yuden TMK325BJ106MM µ F/6.3 V TDK C2012X5R0J106K C11 µ F/6.3V TDK C3216X5RBJ336M C5, C10 330 µ F/6.3 V/25 m Ω Sanyo 6TPE330ML L1, 3.3 µ 15.6 5.92 m Ω TOKO FDA1055-3R3M Q1, 9.5 m Ω IR IRF7821 Q2, (1) m Ω Fairchild FDS6690AS (1) Use a MOSFET with an integrated Schottky barrier diode (SBD) for the low-side, or add an SBD in parallel with a normal MOSFET. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51123

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPS51123RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS51123RGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 23-Dec-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 22-Dec-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51123RGER VQFN RGE 24 3000 346.0 346.0 29.0 TPS51123RGET VQFN RGE 24 250 190.5 212.7 31.8 PACKAGE MATERIALS INFORMATION www.ti.com 22-Dec-2008 Pack Materials-Page 2

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