TMK325B7106MM-T

SIC414 VISHAY | Alldatasheet

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SiC414, SiC424 Document Number: 63388 S13-0248-Rev. B, 04-Feb-13 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com

6 A, microBUCK® SiC414, SiC424

Integrated Buck Regulator with 5 V LDO

DESCRIPTION

The Vishay Siliconix SiC414 and SiC424 are an advanced stand-alone synchronous buck regulator featuring integrated power MOSFETs, bootstrap switch, and an internal 5 V LDO in a space-saving PowerPAK MLP44-28L package. The SiC414 and SiC424 are capable of operating with all ceramic solutions and switching frequencies up to 1 MHz. The programmable frequency, synchronous operation and selectable power-save allow operation at high efficiency across the full range of load current. The internal LDO may be used to supply 5 V for the gate drive circuits or it may be bypassed with an external 5 V for optimum efficiency and used to drive external n-channel MOSFETs or other loads. Additional feat ures include cycle-by-cycle current limit, voltage soft-start, under-voltage protection, programmable over-current protection, soft shutdown and selectable power-save. The Vishay Siliconix SiC414 and SiC424 also provides an enable input and a power good output.

FEATURES

• High efficiency > 95 %  6 A continuous output current capability  Integrated bootstrap switch  Integrated 5 V/200 mA LDO with bypass logic  Temperature compensated current limit  Pseudo fixed-frequency adaptive on-time control  All ceramic solution enabled  Programmable input UVLO threshold  Independent enable pin for switcher and LDO  Selectable ultrasonic power-save mode (SiC414)  Selectable power-save mode (SiC424)  Internal soft-sta rt and soft-shutdown  1 % internal reference voltage  Power good output and over voltage protection  Material categorization: For definitions of compliance please see www.vishay.com/doc?99912

APPLICATIONS

 Notebook, desktop, and server computers  Digital HDTV and digital consumer applications  Networking and telecommunication equipment  Printers, DSL, and STB applications  Embedded applications  Point of load power supplies TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTION PRODUCT SUMMARY Input Voltage Range 3 V to 28 V Output Voltage Range 0.75 V to 5.5 V Operating Frequency 200 kHz to 1 MHz Continuous Output Current 6 A Peak Efficiency 95 % PAD1 AGND PGOOD BST VLDO VIN VOUT AGND V5V FB PAD3 LX PAD2 VIN LX PGND PGND PGND PGND LX LX VIN VIN VIN VIN LX PGND PGND ENL TON AGND EN/PSV LX ILIM1 8 9 10 11 12 13 14 28 27 26 25 24 23 22 VOUT VIN VOUT LDO_EN PGOOD EN/PSV (Tri-State) 3.3 V

www.vishay.com Document Number: 63388 S13-0248-Rev. B, 04-Feb-13 Vishay Siliconix SiC414, SiC424 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com PIN CONFIGURATION (top view) PAD1 AGND PGOOD BST VLDO VIN VOUT AGND V5V FB PAD3 LX PAD2 VIN LX P GND PGND PGND PGND LX LX VIN VIN VIN VIN LX PGND PGND 28 27 26 25 24 23 22 ENL TON AGND EN/PSV LX ILIM PIN DESCRIPTION Pin Number Symbol Description 1F B Feedback input for switching regulator used to program the output voltage - connect to an external resistor divider from VOUT to AGND. 2V 5 V Bias input for internal analog circuits and gate drives - connect to external 3 V or 5 V supply or bias connection to VLDO. 3, 26, PAD 1 A GND Analog ground. 4V OUT Switcher output voltage sense pin, and also the input to the internal switch-over between VOUT and VLDO. 5, 8 to 11, PAD 2 V IN Input supply voltage. 6V LDO 5 V LDO output. 7B S T Bootstrap pin - connect a capacitor from BST to LXBST to develop the floating supply for the high-side gate drive. 12 LXBST LX Boost - connect to the BST capacitor. 15, 20, 21, PAD 3 LX Switching (Phase) node. 13, 14, 16 to 19 P GND Power ground.

22 P GOOD

Open-drain power good indicator. High impedance indicates power is good. An external pull-up resistor is required. 23 I LIM Current limit sense pin - used to program the current limit by connecting a resistor from ILIM to LXS. 24 LXS LX sense - connect to R ILIM resistor.

25 EN/PSV

Enable/power save input for the switching regulator - connect to AGND to disable the switching regulator. Float to operate in forced continuous mode (power save disabled). For SiC414, connect to V5V to operate with ultrasonic power save mode enabled. For SiC424, connect to V5V to operate with power save mode enabled with no minimum frequency. 27 t ON On-time programming input - set the on-time by connecting through a resistor to AGND. 28 ENL Enable input for the LDO - connect ENL to AGND to disable the LDO. Drive with logic to + 3 V for logic control, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.

ORDERING INFORMATION

SiC414CD-T1-GE3 PowerPAK MLP44-28 SiC424CD-T1-GE3 PowerPAK MLP44-28 SiC414DB Reference board

Document Number: 63388 S13-0248-Rev. B, 04-Feb-13 www.vishay.com Vishay Siliconix SiC414, SiC424 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com FUNCTIONAL BLOCK DIAGRAM Stresses beyond those listed under "Absolute Maximum Ratings" may c ause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Electrical Parameter Conditions Limits Unit V IN to PGND - 0.3 to + 30 V LX to P GND - 0.3 to + 30 LX (transient < 100 ns) to P GND - 2 to + 30 EN/PSV, PGOOD, ILIM to GND - 0.3 to + (V5V + 0.3) VOUT, VLDO, FB to GND - 0.3 to + (V5V + 0.3) V5V to P GND - 0.3 to + 6 tON to PGND - 0.3 to + (V5V - 1.5) BST to LX - 0.3 to + 6 to PGND - 0.3 to + 35 ENL - 0.3 to VIN AGND to PGND - 0.3 to + 0.3 Temperature Maximum Junction Temperature 150 Storage Temperature - 65 to 150 Power Dissipation Junction to Ambient Thermal Impedance (R thJA)b IC Section 43 °C/W Maximum Power Dissipation Ambient Temperature = 25 °C 3.4 W Ambient Temperature = 100 °C 1.3 ESD Protection HBM 2 kV Gate Drive Control On-Time Generator Zero Cross Detector FB Comparator Soft Start Reference V5V 2 22 25 AGND 3, 26, PAD1 PGOODV5V Control and Status EN/PSV FB TON VOUT Valley1-LimitBypass Comparator A B Y LDO ENL VINVLDO MUX V5V DL BST LX ILIM PGND VINVIN V5V 13, 14, 16 to 19 12, 15, 20, 21,

24 PAD3

5, 8 to 11, PAD2

www.vishay.com Document Number: 63388 S13-0248-Rev. B, 04-Feb-13 Vishay Siliconix SiC414, SiC424 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com Note: For proper operation, the device should be used within the recommended conditions. RECOMMENDED OPERATING RANGE (all voltages referenced to GND = 0 V) Parameter Min. Typ. Max. Unit V IN 32 8 VV5V to PGND 35 . 5 VOUT to PGND 0.75 5.5 Temperature Recommended Ambient Temperature - 40 to 85 °C ELECTRICAL SPECIFICATIONS Parameter Symbol Test Conditions Unless Specified VIN = 12 V, V5V = 5 V, TA = + 25 °C for typ., - 40 °C to + 85 °C for min. and max., TJ = < 125 °C Min. Typ. Max. Unit Input Supplies V IN UVLO Threshold Voltagea (not available for V5V < 4.5 V) VUVLO Sensed at ENL pin, rising edge 2.4 2.6 2.95 V Sensed at ENL pin, falling edge 2.23 2.4 2.57 VIN UVLO Hysteresis V UVLO_HYS 0.2 V5V UVLO Threshold Voltage V UVLO Measured at VDD pin, rising edge 2.5 2.9 3.0 Measured at VDD pin, falling edge 2.4 2.7 2.9 VDD UVLO Hysteresis V UVLO_HYS 0.2 VIN Supply Current I IN EN/PSV, ENL = 0 V, VIN = 28 V 8.5 20 µA Standby mode: ENL = V5V, EN/PSV = 0 V 130 V5V Supply Current I DD EN/PSV, ENL = 0 V, V5V = 5 V 3 7 EN/PSV, ENL = 0 V, V5V = 3 V 2 SiC414, EN/PSV = V5V, no load, sw = 25 kHz), VFB > 0.75 Vb 1 mA SiC424, EN/PSV = V5V, no load, VFB > 0.75 Vb 0.4 V5V = 5 V, fsw = 250 kHz, EN/PSV = floating, no loadb 4 V5V = 5 V, fsw = 250 kHz, EN/PSV = floating, no loadb 2.5 Controller FB Comparator Threshold V FB Static VIN and load, - 40 °C to + 85 °C, V5V = 3 V or 5 V 0.7425 0.750 0.7575 V Frequency Rangeb fsw Continuous mode 200 1000 kHzMinimum fSW, (SiC414 only), EN/PSV= V5V, no load 25 Bootstrap Switch Resistance 10  Timing On-Time t ON Continuous mode operation VIN = 15 V, VOUT = 3 V, fSW = 300 kHz, Rton = 133 k 1350 1500 1650 nsMinimum On-Timeb tON, min. 80 Minimum Off-Timeb tOFF , min. V5V = 5 V 320 V5V = 3 V 390 Soft Start Soft Start Time b tSS 1.7 ms Analog Inputs/Outputs V OUT Input Resistance R O-IN 500 k  Current Sense Zero-Crossing Detector Threshold Voltage V Sense-th LX-PGND - 3 0 + 3 mV

Document Number: 63388 S13-0248-Rev. B, 04-Feb-13 www.vishay.com Vishay Siliconix SiC414, SiC424 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com Notes: a. V IN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference. b. Guaranteed by design. c. The switch-over threshold is the maximum voltage differential between the V LDO and V OUT pins which ensures that V LDO will internally switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures that VLDO will not switch-over to VOUT. d. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point. Power Good Power Good Threshold Voltage PG_V TH_UPPER Upper limit, VFB > internal reference 750 mV + 20 %Lower limit, VFB < internal reference 750 mV - 10 Start-Up Delay Time (between PWM enable and P GOOD high) PG_Td V5V = 5 V 4 msV5V = 3 V 2 Fault (noise-immunity) Delay Timeb PG_ICC 5µ s Power Good Leakage Current PG_I LK 1µ A Power Good On-Resistance PG_R DS-ON 10  Fault Protection Valley Current Limit V5V = 5 V, R ILIM = 5 k 345 A ILIM Source Current I LIM 8µ A ILIM Comparator Offset Voltage V ILM-LK With respect to AGND - 8 0 + 8 mV Output Under-Voltage Fault V OUV_Fault VFB with respect to Internal 750 mV reference, 8 consecutive clocks - 25 %Smart Power-Save Protection Threshold Voltage b PSAVE_VTH VFB with respect to internal 750 mV reference + 10 Over-Voltage Protection Threshold VFB with respect to internal 750 mV reference + 20 Over-Voltage Fault Delayb tOV-Delay 5µ s Over Temperature Shutdownb TShut 10 °C hysteresis 150 °C Logic Inputs/Outputs Logic Input High Voltage V IH ENL 1 VLogic Input Low Voltage V IL 0.4 EN/PSV Input for PSAVE Operation b % of V5V 45 100 %EN/PSV Input for Forced Continuous Operation b 1V 42 EN/PSV Input for Disabling Switcher 00 . 4 V EN/PSV Input Bias Current I EN EN/PSV = V5V or AGND - 10 + 10 µAENL Input Bias Current V IN = 28 V 11 18 FB Input Bias Current FBL_I LK FB = V5V or AGND - 1 + 1 Linear Dropout Regulator V LDO Accuracy V LDO_ACC VLDO load = 10 mA 4.9 5 5.1 V LDO Current Limit LDO_I LIM Start-up and foldback, VIN = 12 V 115 mAOperating current limit, VIN = 12 V 135 200 VLDO to VOUT Switch-Over Thresholdc VLDO-BPS - 140 + 140 mVVLDO to VOUT Non-Switch-Over Thresholdc VLDO-NBPS - 450 + 450 VLDO to VOUT Switch-Over Resistance R LDO VOUT = 5 V 2  LDO Drop Out Voltaged From VIN to VVLDO , VVLDO = 5 V, IVLDO = 100 mA 1.2 V ELECTRICAL SPECIFICATIONS Parameter Symbol Test Conditions Unless Specified VIN = 12 V, V5V = 5 V, TA = + 25 °C for typ., - 40 °C to + 85 °C for min. and max., TJ = < 125 °C Min. Typ. Max. Unit

www.vishay.com Document Number: 63388 S13-0248-Rev. B, 04-Feb-13 Vishay Siliconix SiC414, SiC424 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com

ELECTRICAL CHARACTERISTICS

Efficiency vs. IOUT (in Continuous Conduction Mode) VOUT vs. IOUT (in Continuous Conduction Mode) VOUT vs. VIN at IOUT = 0 A (in Continuous Conduction Mode, FSW = 500 kHz) 01234567 Efficiency (%) IOUT (A) VIN = 12 V, VOUT = 1 V, FSW = 500 kHz VOUT (V) IOUT (A) 0.95 0.96 0.97 0.98 0.99 1.01 1.02 1.03 1.04 1.05 01234567 VIN = 12 V, VOUT = 1 V, FSW = 500 kHz VOUT (V) VIN (V) 0.95 0.96 0.97 0.98 0.99 1.01 1.02 1.03 1.04 1.05 369 1 2 1 5 1 8 2 1 2 4 VOUT = 1 V, IOUT = 0 A Efficiency vs. IOUT (in Power-Save-Mode) VOUT vs. IOUT (in Power-Save-Mode) VOUT vs. VIN at IOUT = 6 A (in Continuous Conduction Mode, FSW = 500 kHz) Efficiency (%) IOUT (A) 01234567 VIN = 12 V, VOUT = 1 V, FSW = 500 kHz (at 6 A) VOUT (V) IOUT (A) 0.95 0.96 0.97 0.98 0.99 1.01 1.02 1.03 1.04 1.05 01234567 VIN = 12 V, VOUT = 1 V, FSW = 500 kHz (at 6 A) VOUT (V) VIN (V) 0.95 0.96 0.97 0.98 0.99 1.01 1.02 1.03 1.04 1.05 369 1 2 1 5 1 8 2 1 2 4 VOUT = 1 V, IOUT = 6 A

SiC414, SiC424 Document Number: 63388 S13-0248-Rev. B, 04-Feb-13 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com VOUT vs. VIN (IOUT = 0 A in Power-Save-Mode) VOUT Ripple vs. VIN (IOUT = 0 A in Continuous Conduction Mode) FSW vs. IOUT (in Continuous Conduction Mode) VOUT (V) VIN (V) 0.95 0.96 0.97 0.98 0.99 1.01 1.02 1.03 1.04 1.05 369 1 2 1 5 1 8 2 1 2 4 VOUT = 1 V, IOUT = 0 A VOUT Ripple (mV) VIN (V) 0 5 10 15 20 25 VOUT = 1 V, IOUT = 0 A, FSW = 500 kHz FSW (kHz) IOUT (A) 350 375 400 425 450 475 500 525 550 01234567 VIN = 12 V, VOUT = 1 V, FSW = 500 kHz (at 6 A) VOUT Ripple vs. VIN (IOUT = 6 A in Continuous Conduction Mode) VOUT Ripple vs. VIN (IOUT = 0 A in Power-Save-Mode) FSW vs. IOUT (in Power-Save-Mode) VOUT Ripple (mV) VIN (V) 0 5 10 15 20 25 VOUT = 1 V, IOUT = 6 A, FSW = 500 kHz VOUT Ripple (mV) VIN (V) 0 5 10 15 20 25 VOUT = 1 V, IOUT = 0 A, PSV Mode FSW (kHz) IOUT (A) 120 170 220 270 320 370 420 470 520 01234567 VIN = 12 V, VOUT = 1 V, FSW = 500 kHz (at 6 A)

www.vishay.com Document Number: 63388 S13-0248-Rev. B, 04-Feb-13 Vishay Siliconix SiC414, SiC424 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com VOUT Ripple in Continuous Conduction Mode (No Load) (VIN = 12 V, VOUT = 1 V, FSW = 500 kHz) Transient Response in Continuous Conduction Mode (0.2 A - 6 A) (VIN = 12 V, VOUT = 1 V, FSW = 500 kHz) Transient Response in Power Save Mode (0.2 A - 6 A) (VIN = 12 V, VOUT = 1 V, FSW = 500 kHz at 6A) OutputC urrent 2 A/div. 5 µs/div. Output Voltage 50 mV/div. 5 µs/div. AC Coupling OutputC urrent 2 A/div. 5 µs/div. Output Voltage 50 mV/div. 5 µs/div. AC Coupling VOUT Ripple in Power Save Mode (No Load) (VIN = 12 V, VOUT = 1 V) Transient Response in Continuous Conduction Mode (6 A - 0.2 A) (VIN = 12 V, VOUT = 1 V, FSW = 500 kHz) Transient Response in Power Save Mode (6 A - 0.2 A) (VIN = 12 V, VOUT = 1 V, FSW = 500 kHz at 6 A) LX Switching Node 2V/div. 2ms/div Output Ripple Voltage 20 mV/div. 2 ms/div OutputC urrent 2 A/div. 5 µs/div. Output Voltage 50 mV/div. 5 µs/div. AC Coupling OutputC urrent 2 A/div. 5 µs/div. Output Voltage 50 mV/div. 5 µs/div. AC Coupling

SiC414, SiC424 Document Number: 63388 S13-0248-Rev. B, 04-Feb-13 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com Using the On-chip LDO to Bias the SIC414/SIC424 The following steps must be followed when using the onchip LDO to bias the device.  Connect V5V to V LDO before enabling the LDO.  Any external load on V LDO should not exceed 40 mA until the LDO voltage has reached 90 % of final value.  Do not connect the EN pin directly to the V5V or any other supply voltage if VOUT is greater than or equal to 4.5 V. Many applications connect the EN pin to V5V and control the on/off of the LDO and PWM simultaneously with the ENL pin. This allows one signal to control both the bias and power output of the SiC414 and SiC424. When V OUT > 4.5 V this configuration can cause problems due to the parasitic diodes in the LDO switchover circuitry. After the VOUT > 4.5 V PWM output is up and running the switchover diodes can hold up V5V > UVLO even if the ENL pin is grounded, turning off the LDO. Operating in this way can potentially damage the part. Design Procedure When designing a switch mode power supply, the input voltage range, load current, switching frequency, and inductor ripple current must be specified. The maximum input voltage (V INMAX) is the highest specified input voltage. The minimum input voltage (V INMIN) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and PCB traces. The following parameters define the design:  Nominal output voltage (V OUT)  Static or DC output tolerance  Transient response  Maximum load current (I OUT) There are two values of load current to evaluate - continuous load current and peak load current. Continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. Peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. The following values are used in this design:  V IN = 12 V ± 10 %  VOUT = 1.5 V ± 4 %  fSW = 250 kHz  Load = 6 A maximum Frequency Selection Selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. The desired switching frequency is 250 kHz which results from using component selected for optimum size and cost. A resistor (R tON) is used to program the on-time (indirectly setting the frequency) using the following equation. To select RtON, use the maximum value for VIN, and for tON use the value associated with maximum VIN. tON = 303 ns at 13.2 VIN, 1 VOUT, 250 kHz Substituting for RtON results in the following solution RtON = 130.9 k, use RtON = 130 k. Inductor Selection In order to determine the inductance, the ripple current must first be defined. Low inductor values result in smaller size but create higher ripple current which can reduce efficiency. Higher inductor values will reduce the ripple current/voltage and for a given DC resistance are more efficient. However, larger inductance translates directly into larger packages and higher cost. Cost, size, output ripple, and efficiency are all used in the selection process. The ripple current will also set the boundary for power-save operation. The switching w ill typically enter power-save mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 4 A then Power-save operation will typically start for loads less than 2 A. If ripple current is set at 40 % of maximum load current, then power- save will start for loads less than 20 % of maximum current. The inductor value is typically selected to provide a ripple current that is between 25 % to 50 % of the maximum load current. This provides an optim al trade-off between cost, efficiency, and transient performance. During the DH on-time, voltage across the inductor is IN - V OUT). The equation for determining inductance is shown next. Example In this example, the inductor ripple current is set equal to 50 % of the maximum load current. Therefore ripple current will be 50 % x 6 A or 3 A. To find the minimum inductance needed, use the V IN and t ON values that correspond to VINMAX. A slightly larger value of 1.5 µH is selected. This will decrease the maximum I RIPPLE to 2.53 A. Note that the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current. The ripple current under minimum V IN conditions is also checked using the following equations. RtON = 1 25 pF x fsw - 400 Ω x VIN VOUT tON = VOUT VINMAX. x fSW L = (VIN - VOUT) x tON IRIPPLE L = (13.2 V - 1 V) x 318 ns 3 A = 1.26 µH

www.vishay.com Document Number: 63388 S13-0248-Rev. B, 04-Feb-13 Vishay Siliconix SiC414, SiC424 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com Capacitor Selection The output capacitors are chosen based on required ESR and capacitance. The maximum ESR requirement is controlled by the output ripple requirement and the DC tolerance. The output voltage has a DC value that is equal to the valley of the output ripple plus 1/2 of the peak-to-peak ripple. Change in the output ripple voltage will lead to a change in DC voltage at the output. The design goal is for the output voltage regulation to be ± 4 % under static conditions. The internal 750 mV reference tolerance is 1 %. Assuming a 1 % tolerance from the FB resistor divider, this allows 2 % tolerance due to V OUT ripple. Since this 2 % error comes from 1/2 of the ripple voltage, the allowable ripple is 4 %, or 40 mV for a 1 V output. The maximum ripple current of 2.53 A creates a ripple voltage across the ESR. The maximum ESR value allowed is shown by the following equations. The output capacitance is chosen to meet transient requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. If the load release is instantaneous (load changes from maximum to zero in < 1 µs), the output capacitor must absorb all the inductor's stored energy. This will cause a peak voltage on the capacitor according to the following equation. Assuming a peak voltage V PEAK of 1.150 (100 mV rise upon load release), and a 6 A load release, the required capacitance is shown by the next equation. If the load release is relatively slow, the output capacitance can be reduced. At heavy loads during normal switching, when the FB pin is above the 750 mV reference, the DL output is high and the low-si de MOSFET is on. During this time, the voltage across the inductor is approximately - V OUT. This causes a down-slope or falling dI/dt in the inductor. If the load dI/dt is not much faster than the - dI/dt in the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. The following can be used to calculate the needed capacitance for a given dI LOAD/dt: Peak inductor current is shown by the next equation. I LPK = IMAX + 1/2 x IRIPPLEMAX ILPK = 10 + 1/2 x 2.53 = 7.26 A Rate of change of load current = dILOAD/dt IMAX = maximum load release = 6 A Example This causes the output current to move from 6 A to 0 A in 4.8 µs, giving the minimum ou tput capacitance requirement shown in the following equation. Note that C OUT is much smaller in this example, 443 µF compared to 772 µF based on a worst-case load release. To meet the two design criteria of minimum 443 µF and maximum 15 m ESR, select two capacitors rated at 220 µF and 15 m ESR or less. It is recommended that an additional small capacitor be placed in parallel with C OUT in order to filter high frequency switching noise. Stability Considerations Unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or ESR loop instability. Double-pulsing occurs due to switching noise seen at the FB input or because the FB ripple voltage is too low. This causes the FB comparator to trigger prematurely after the minimum off-time has expired. In extreme cases the noise can cause three or more successive on-times. Double-pulsing will result in higher ripple voltage at the output, but in most applications it will not affect operation. This form of instability can usually be avoided by providing the FB pin with a smooth, clean ripple signal that is at least 10 mV p-p, which may dictate the need to increase the ESR of the output capacitors. It is also imperative to provide a prope r PCB layout as discussed in the Layout Guidelines section. tON_VINMIN = 25 pF x RtON x VOUT VINMIN IRIPPLE = (VIN - VOUT) x tON L IRIPPLE_VINMIN = (10.8 - 1 V) x 311 ns 1.5µH = 2.03 A + 10 ns = 311 ns ESRMAX = VRIPPLE IRIPPLEMAX ESRMAX = 15.8 mΩ = 40 mV 2.53 A COUT_MIN = L (IOUT + x IRIPPLEMAX)2 (VPEAK)2 - (VOUT)2 COUT_MIN = 1.5 µH (6 A + x 2.53)2 (1.05)2 - (1 V)2 COUT_MIN = 772 µF COUT = ILPK x L x - x dt 2 (VPK - VOUT) ILPK VOUT IMAX dlLOAD Load dlLOAD dt =1.25 A 1 µs COUT = 7.26 x 1.5 µH x - x 1 µs 2 (1.05 V - 1 V) 7.26 1 V 6 A 1.25 A COUT = 443 µF

www.vishay.com Document Number: 63388 S13-0248-Rev. B, 04-Feb-13 Vishay Siliconix SiC414, SiC424 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced as seen at the load. The use of 1 % feedback resistors may result in up to an additional 1 % error. If tighter DC accuracy is required, resistors with lower tolerances should be used. The output inductor value may change with current. This will change the output ripple and therefore will have a minor effect on the DC output voltage. The output ESR also affects the output ripple and thus has a minor effect on the DC output voltage. Switching Frequency Variations The switching frequency will vary depending on line and load conditions. The line variations are a result of fixed propagation delays in the on-time one-shot, as well as unavoidable delays in the external MOSFET switching. As V IN increases, these factors make the actual DH on-time slightly longer than the ideal on-time. The net effect is that frequency tends to falls slightly with increasing input voltage inductor. An adaptive on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from V IN as losses increase). The on-time is essentially constant for a given VOUT/VIN combination, to offset the losses the off-time will tend to reduce slightly as load increases. The net effect is that switching frequency increases slightly with increasing load. BILL OF MATERIALS Qty. Ref. Designator Description Value Voltage Footprint Part Number Manufacturer 1U 1 SiC424 COT Buck Converter MLPQ-28 4 x 4 mm SiC424 Vishay

4 C16, C18, C17, C23 220 µF , 10 V D 220 µF 10 V SM593D 593D227X0010E2TE3 Vishay

4 C15, C20, C21, C22 10 µF , 16 V, X7R.B, 1206 10 µF 16 V SM1206 GRM31CR71C106KAC7L Murata

1 L1 1 µH 1 µH IHLP2525 IHLP2525EZER1R0M01 Vishay

1 Q1 Si4812BDY -E3 SO-8 Si4812BDY Vishay

5 C1, C2, C3, C4,

C29 CAP . 22 µF , 16 V, 1210 22 µF 16 V SM1210 GRM32ER71C226ME18L Murata 3 C8, C9, C10 CAP . 10 µF , 25 V, 1210 10 µF 25 V SM1210 TMK325B7106MM-T Taiyo Yuden 1 C26 4.7 µF , 10 V, 0805 4.7 µF 10 V SM0805 LMK212B7475KG-T Taiyo Yuden 1 C12 CAP . Radial 150 µF , 35 V 150 µF 35 V Radial EU-FM1V151 Panasonic 1R 4 1 , 2512 1  200 V SM2512 CRCW25121R00FKEG Vishay 2 R7, R11 Res. 0  0  50 V SM0603 CRCW0603 0000ZOEA Vishay

1 R39 0R, 50 V, 0402 0  50 V SM0402 CRCW04020000ZOED Vishay

1 R3 Res. 1K, 50 V, 0402 1K 50 V SM0402 CRCW04021K00FKED Vishay 2 R5, R6 Res. 100K, 0603 100K 50 V SM0603 CRCW0603 100K FKEA Vishay 3 R8, R10, R15 Res. 10K, 50 V, 0603 10K 50 V SM0603 CRCW060310KFKED Vishay 1C 6 CAP . CER 1 µF , 35 V, X7R 0805 1 µF 35 V SM0805 GMK212B7105KG-T Murata 1R 2 3 Res. 16.5 k 1/10 W, 1%, 0603 SMD 16.5K 50 V SM0603 CRCW060316K5FKEA Vishay 1 R13 Res. 1K, 50 V, 0402 1K 50 V SM0402 CRCW04021K00FKED Vishay 1 C30 CAP . 180 pF , 0402 180 pF 50 V SM0402 VJ0402A181JXACW1BC Vishay 1R 3 0 Res. 78.7 k 1/10 W, 1 %, 0603 SMD 78.7k 50 V SM0603 CRCW060378K7FKEA Vishay 4 C7, C11, C14, C28 CAP . 0.1 µF , 50 V, 0603 0.1 µF 50 V SM0603 VJ0603Y104KXACW1BC Vishay 1 C5 CAP . 0.1 µF , 10 V, 0402 0.1 µF 10 V SM0402 VJ0402Y104MXQCW1BC Vishay

4 B1, B2, B3, B4 Solder Banana 575-6 Keystone

1 C13 CAP . 0.01 µF , 50 V, 0402 0.01 µF 50 V SM0402 VJ0402Y103KXACW1BC Vishay P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12 Probe Hook Terminal 0 Keystone

4 M1, M2, M3, M4 Nylon on Stand off 8834 Keystone

www.vishay.com Document Number: 63388 S13-0248-Rev. B, 04-Feb-13 Vishay Siliconix SiC414, SiC424 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com PACKAGE DIMENSIONS AND MARKING INFO Dimensions Millimeters Inches A1 0.00 - 0.05 0.000 - 0.002 A2 0.20 Ref. 0.008 Ref. D 4.00 BSC 0.157 BSC e 0.45 BSC 0.018 BSC E 4.00 BSC 0.157 BSC N(3) 28 28 Nd(3) 77 Ne(3) 77 K1 0.46 BSC 0.018 BSC K2 0.40 BSC 0.016 BSC 2x A B C Bottom View Side View Marking PIN 1 Dot by Top View 28L T/SLP (4.0 mm x 4.0 mm) 0.2030 Ref.0.000-0.0500 A E D (Nd-1)X e Ref. b e E2-1 D2-3 D2-1 D2-2 E2-2 E2-3 L (Ne-1)X e Ref.

0.10 C B

0.10 C A

0.10 C A B

0.08 C K20.4000 PIN 1 Identification Notes: 1. Use millimeters as the primary measurement. 2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994. 3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction. 4. Dimensions b applies to plated terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. 5. The pin #1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body. 6. Exact shape and size of this feature is optional. 7. Package warpage max. 0.08 mm. 8. Applied only for terminals.

SiC414, SiC424 Document Number: 63388 S13-0248-Rev. B, 04-Feb-13 www.vishay.com This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 For technical questions, contact: powerictechsupport@vishay.com RECOMMENDED LAND PATTERN Notes: a. Controlling dimensions are in millimeters (angles in degrees). b. This land pattern is for reference purposes only. Consult y our manufacturing group to ensure your company’s manufacturing gui delines are met. c. Square package-dimensions apply in both X and Y directions. Vishay Siliconix maintains worldwide manufacturing capability. Pr oducts may be manufactured at one of several qualified locatio ns. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?63388. 2.58 X K P 1.29 K G H2 1.29 H Y (C) Z Dimensions Millimeters C (3.95) G 3.20 H 2.58 H1 0.73 H2 1.45 K 1.06 P 0.45 X 0.30 Y 0.75 Z 4.70

Document Number: 65739 www.vishay.com Revision: 22-Feb-10 1

Package Information

PowerPAK® MLP44-28L CASE OUTLINE DIM. MILLIMETERS INCHES A1 0.00 - 0.05 0.000 - 0.002 A2 0.20 REF 0.008 REF b D 4.00 BSC 0.157 BSC e 0.45 BSC 0.018 BSC E 4.00 BSC 0.157 BSC N (3) 28 28 Nd (3) 77 Ne (3) 77 K1 0.46 BSC 0.018 BSC K2 0.40 BSC 0.016 BSC ECN: T10-0056-Rev. A, 22-Feb-10 DWG: 5996 2x A B C Bottom View Side View Marking PIN 1 Dot by Top View 28L T/SLP (4.0 mm x 4.0 mm) 0.2030 Ref.0.000-0.0500 A E D (Nd-1)X e Ref. b e E2-1 D2-3 D2-1 D2-2 E2-2 E2-3 L (Ne-1)X e Ref. 0.08 C K20.4000 PIN#1 Identification R0.20 Notes: 1. Use millimeters as the primary measurement. 2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994. 3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction. 4. Dimensions b applies to plated terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. 5. The pin #1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body. 6. Exact shape and size of this feature is optional. 7. Package warpage max. 0.08 mm. 8. Applied only for terminals.

Document Number: 70567 www.vishay.com Revision: 17-May-10 1 PAD Pattern Vishay Siliconix PowerPAK® MLP44-28L Land Pattern Recommended Land Pattern Recommended Land Pattern vs. Case Outline 0.30 0.060.06 0.06 3 0.75 0.400 2.58 1.06 0.45 0.30 1.29 1.06 3.95 1.450.73 0.75 1.29 2.58 3.20 4.70

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