TPS6211X TI | Alldatasheet
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Technical content
Efficiency□vs□Output□Current 100 0.0001 0.001 0.01 0.1 10 1 I -□Output□Current- AO Efficiency□-□% 5□V 4.2□V 12□V 8.4□V V =□3.3□V T PFM□Mode O A =□25 C o SYNC GND PGND SW VO = 3.3 V
6.8 H/c109
C = 22 FO /c109 6.3 V VIN LBI C = 10 FI /c109 25 V
1 F/c109
V = 3.8 V to 17 VI VIN EN VINA PGNDGND PwPD AGND TPS62111 SW LBO PG
1 M/c87
Sample & Buy T echnical Documents Tools & Software Support & Community TPS62110,TPS62111,TPS62112,TPS62113 SLVS585E –JULY 2005–REVISED JUNE 2015 TPS6211x17-V,1.5-A,SynchronousStep-DownConverter
1 Features 3 Description
The TPS6211x devices are a family of low-noise 1• High-Efficiency Synchronous Step-Down synchronous step-down DC-DC converters that areConverter With up to 95% Efficiency ideally suited for systems powered from a 2- to 4-cell• 3.1-V to 17-V Operating Input Voltage Range Li-ion battery or from a 12-V or 15-V rail.
- Adjustable Output Voltage Range: 1.2 V to 16 V The TPS6211x devices are synchronous pulse width• Fixed Output Voltage Options Available in modulation (PWM) converters with integrated N- and 3.3 V and 5 V P-channel power MOSFET switches. Synchronous rectification is used to increase efficiency and to• Synchronizable to External Clock: Up to 1.4 MHz reduce external component count. To achieve highest• Up to 1.5-A Output Current efficiency over a wide load-current range, the• High Efficiency Over a Wide Load-Current converter enters a power-saving, pulse frequency Range Due to PFM/PWM Operation Mode modulation (PFM) mode at light load currents. Operating frequency is typically 1 MHz, allowing the• 100% Maximum Duty Cycle for Lowest Dropout use of small inductor and capacitor values. The• 20-µA Quiescent Current (Typical) device can be synchronized to an external clock• Overtemperature and Overcurrent Protected signal in the range of 0.8 MHz to 1.4 MHz. For low-
- Available in 16-Pin VQFN Package noise operation, the converter can be operated in PWM-only mode. In shutdown mode, the current consumption is reduced to less than 2 µA. The2 Applications TPS6211x family of devices are available in the 16-• Point-of-Load Regulation From 12-V Buses pin (RSA) VQFN package, and operate over a free-
- Organizers, PDAs, and Handheld PCs air temperature range of –40°C to 85°C.
- Handheld Scanners Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS62110 TPS62111 VQFN (16) 4.00 mm × 4.00 mm TPS62112 TPS62113 (1) For all available packages, see the orderable addendum at the end of the data sheet.
4 Typical Application Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62110,TPS62111,TPS62112,TPS62113 SLVS585E –JULY 2005–REVISED JUNE 2015 www.ti.com Table of Contents
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (January 2014) to Revision E Page
- Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device Changes from Revision C (October 2012) to Revision D Page Changes from Revision B (October 2012) to Revision C Page Changes from Revision A (February 2009) to Revision B Page
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Product Folder Links: TPS62110 TPS62111 TPS62112 TPS62113
TPS62110,TPS62111,TPS62112,TPS62113 www.ti.com SLVS585E –JULY 2005–REVISED JUNE 2015 Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS62110 TPS62111 TPS62112 TPS62113
TPS62110,TPS62111,TPS62112,TPS62113 SLVS585E –JULY 2005–REVISED JUNE 2015 www.ti.com
6 Device Comparison Table
PACKAGED DEVICES LBI/LBOOUTPUT VOLTAGEPLASTIC VQFN 16 PIN(1) (RSA) FUNCTIONALITY TPS62110 Adjustable 1.2 V to 16 V Standard TPS62111 Fixed 3.3 V Standard TPS62112 Fixed 5 V Standard TPS62113 Adjustable 1.2 V to 16 V Enhanced (1) The RSA package is available in tape and reel. Add R suffix (TPS62110RSAR) to order quantities of 3000 parts per reel. Add T suffix (TPS62110RSAT) to order quantities of 250 parts per reel.
7 Pin Configuration and Functions
NAME NO. AGND 9 I Analog ground, connect to GND and PGND. Enable. A logic high enables the converter; logic low forces the device into shutdown mode reducing theEN 4 I supply current to less than 2 µA. Do not leave floating. Feedback pin for the fixed output voltage versions. Connect to VOUT for these devices. For the FB 10 I adjustable versions, an external resistive divider is connected to this pin. The internal voltage divider is disabled for the adjustable versions. GND 11, 12 I Ground LBI 7 I Low-battery input. Do not leave floating. Open-drain, low-battery output. This pin is pulled low if LBI is below its threshold. If not used, the pinLBO 6 O may be left floating or connected to GND. Power good comparator output. This is an open-drain output. A pullup resistor should be connected PG 13 O between PG and VOUT. The output goes high when the output voltage is greater than 98.4% of the nominal value. If not used, the pin may be left floating or connected to GND. PGND 1, 16 I Power ground. Connect all power grounds to this pin. Connect the inductor to this pin. This pin is the switch pin and connected to the drain of the internalSW 14, 15 O power MOSFETS. Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an external clock signal with CMOS level. Also controls power save mode by being tied high or low. SYNC 5 I SYNC = HIGH: Low-noise mode enabled, fixed-frequency PWM operation is forced SYNC = LOW (GND): Power save mode enabled, PFM/PWM mode enabled VIN 2, 3 I Supply voltage input (power stage)
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Product Folder Links: TPS62110 TPS62111 TPS62112 TPS62113
TPS62110,TPS62111,TPS62112,TPS62113 www.ti.com SLVS585E –JULY 2005–REVISED JUNE 2015 Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. VINA 8 I Supply voltage input (support circuits) Exposed Connect to AGND. Must be soldered to achieve appropriate power dissipation and mechanical– –Thermal Pad reliability.
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Supply voltage at VIN, VINA –0.3 20 V Voltage at SW –1 20 VI Voltage at EN, SYNC, LBO, PG –0.3 20 V Voltage at LBI, FB –0.3 7 IO Output current at SW 2400 mA TJ Maximum junction temperature 150 °C TA Operating free-air temperature –40 85 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±500C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
VCC Supply voltage at VIN, VINA 3.1 17 V Maximum voltage at PG, LBO, EN, SYNC 17 V TJ Operating junction temperature –40 125 °C
8.4 Thermal Information
THERMAL METRIC(1) RSA (VQFN) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 48.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 45.4 °C/W RθJB Junction-to-board thermal resistance 16.3 °C/W ψJT Junction-to-top characterization parameter 0.5 °C/W ψJB Junction-to-board characterization parameter 16.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS62110 TPS62111 TPS62112 TPS62113
TPS62110,TPS62111,TPS62112,TPS62113 SLVS585E –JULY 2005–REVISED JUNE 2015 www.ti.com
8.5 Electrical Characteristics
VI = 12 V, VO = 3.3 V, IO = 600 mA, EN = VI, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VI Input voltage 3.1 17 V IO = 0 mA, SYNC = GND, VI = 7.2 V, 20TA = 25°C (1) I(Q) Operating quiescent current µA IO = 0 mA, SYNC = GND, VI = 17 V (1) 23 26 Quiescent current with enhanced LBIIQ(LBI) EN = VI , LBI = GND 10 µAcomparator version (TPS62113 only). EN = GND 1.5 5 I(SD) Shutdown current µA EN = GND, TA = 25°C, VI = 7.2 V 1.5 3 ENABLE VIH EN high-level input voltage 1.3 V VIL EN low-level input voltage 0.3 V EN trip-point hysteresis 170 mV Ilkg EN input leakage current EN = GND or VI, VI = 12 V 0.01 0.2 µA I(EN) EN input current 0.6 V ≤ V(EN) ≤ 4 V 10 20 µA V(UVLO) Undervoltage lockout threshold Input voltage falling 2.8 3 3.1 V Undervoltage lockout hysteresis 250 300 mV POWER SWITCH VI ≥ 5.4 V; IO = 350 mA 165 250 RDS(ON) P-channel MOSFET ON-resistance VI = 3.5 V; IO = 200 mA 340 mΩ VI = 3 V; IO = 100 mA 490 Ilkg P-channel MOSFET leakage current VDS = 17 V 0.1 1 µA ILIMF P-channel MOSFET current limit VI = 7.2 V, VO = 3.3 V 2100 2400 2600 mA VI ≥ 5.4 V; IO = 350 mA 145 200 RDS(ON) N-channel MOSFET ON-resistance VI = 3.5 V; IO = 200 mA 170 mΩ VI = 3 V; IO = 100 mA 200 Ilkg N-channel MOSFET leakage current VDS = 17 V 0.1 2 µA PG OUTPUT, LBI, LBO V(PG) Power good trip voltage VO – 1.6% V VO ramping positive 50 Power good delay time µs VO ramping negative 200 VOL PG, LBO output-low voltage V(FB) = 0.8 × VO nominal, IOL = 1 mA 0.3 V IOL PG, LBO sink current 1 mA Ilkg PG, LBO output leakage current V(FB) = VO nominal, V(LBI) = VI 0.01 0.25 µA Minimum supply voltage for valid power 3 Vgood, LBI, LBO signal VLBI LBI input trip voltage Input voltage falling 1.256 V Ilkg LBI input leakage current 10 100 nA LBI input trip-point 1.5%accuracy VLBI,HYS Low-battery input hysteresis 25 mV (1) Device is not switching.
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Product Folder Links: TPS62110 TPS62111 TPS62112 TPS62113
TPS62110,TPS62111,TPS62112,TPS62113 www.ti.com SLVS585E –JULY 2005–REVISED JUNE 2015 Electrical Characteristics (continued) VI = 12 V, VO = 3.3 V, IO = 600 mA, EN = VI, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OSCILLATOR fS Oscillator frequency 900 1000 1100 kHz f(SYNC) Synchronization range CMOS-logic clock signal on SYNC pin 800 1400 kHz VIH SYNC high-level input voltage 1.5 V VIL SYNC low-level input voltage 0.3 V Ilkg SYNC input leakage current SYNC = GND or VIN 0.01 0.2 µA SYNC trip-point hysteresis 170 mV Ilkg SYNC input leakage current 0.6 V ≤ V(SYNC) ≤ 4 V 10 20 µA Duty cycle of external clock signal 30% 90% OUTPUT TPS62110VO Adjustable output voltage range 1.153 16 VTPS62113 TPS62110VFB Feedback voltage 1.153 VTPS62113 TPS62110Ilkg FB input leakage current 10 100 nATPS62113 TPS62110 VI = 3.1 V to 17 V;Feedback voltage tolerance –2% 2%TPS62113 0 mA < IO < 1500 mA(2) VI = 3.8 V to 17 V;TPS62111 –3% 3%0 mA < IO < 1500 mA(2) Fixed output voltage tolerance(3) VI = 5.5 V to 17 V;TPS62112 –3% 3%0 mA < IO < 1500 mA(2) VI ≥ 3 V (once undervoltage lockout 100voltage exceeded) VI ≥ 3.5 V 500IO Maximum output current mA VI ≥ 4.3 V 1200 VI ≥ 6 V 1500 Current into internal voltage divider for 5 µAfixed voltage versions VI = 7.2 V; VO = 3.3 V; IO = 600 mA η Efficiency 92% VI = 12 V, Vo = 5 V, Io = 600 mA Duty-cycle range for main switches at 1 MHz 10% 100% Minimum ton time for main switch 100 ns TSD Shutdown temperature 145 °C Start-up time IO = 800 mA, VI = 12 V, Vo = 3.3 V 1 ms (2) The maximum output current depends on the input voltage. See the maximum output current for further restrictions on the minimum input voltage. (3) The output voltage accuracy includes line and load regulation over the full temperature range TA = –40°C to 85°C. See No-Load Operation. Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS62110 TPS62111 TPS62112 TPS62113
8.6 Typical Characteristics
Figure 2. Switching Frequency vs Input VoltageFigure 1. TPS62111 Maximum Output Current vs Input Figure 3. Quiescent Current vs Input Voltage
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9 Detailed Description
9.1 Overview
The TPS6211x family of devices are synchronous step-down converters that operate with a 1-MHz fixed- frequency pulse-width modulation (PWM) at moderate-to-heavy load currents, and enters the power-save mode at light load current. During PWM operation, the converter uses a unique fast-response voltage-mode control scheme with input- voltage feedforward. Good line and load regulation is achieved with the use of small input and output ceramic capacitors. At the beginning of each clock cycle initiated by the clock signal (S), the P-channel MOSFET switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns the switch off. The switch is turned off by the current limit comparator if the current limit of the P-channel switch is exceeded. After the dead time prevents current shoot through, the N-channel MOSFET rectifier is turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal turning off the N-channel rectifier, and turning on the P-channel switch. The error amplifier as well as the input voltage determines the rise time of the sawtooth generator. Therefore, any change in input voltage or output voltage directly controls the duty cycle of the converter, giving a very good line- and load-transient regulation. Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPS62110 TPS62111 TPS62112 TPS62113
R N-Channel Power MOSFETComparator High Comparator Low Comparator High 2 V(COMP) Sawtooth Generator V I Undervoltage Lockout Bias Supply Comparator High Comparator Low Compensation V = 1.153 VREF (See Note A) EN SW FB PGND Gm Thermal Shutdown VINA +SKIP Comparator PG LBO LBI GND 1.256 V SYNC VIN TPS62110,TPS62111,TPS62112,TPS62113 SLVS585E –JULY 2005–REVISED JUNE 2015 www.ti.com
9.2 Functional Block Diagram
For the adjustable version (TPS62110 and TPS62113), the internal feedback divider is disabled and the FB pin is directly connected to the internal compensation block.
9.3 Feature Description
9.3.1 Enable
A logic low on EN forces the TPS6211x devices into shutdown. In shutdown, the power switch, drivers, voltage reference, oscillator, and all other functions are turned off. The LBO pin is high impedance, while PG is held low. The supply current is reduced to less than 2 µA in the shutdown mode. When the device is in thermal shutdown, the band gap is forced to be switched on even if the device is set into shutdown by pulling EN to GND.
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Product Folder Links: TPS62110 TPS62111 TPS62112 TPS62113
SYNC Pins (SLVA295) for details.
9.3.2 Low-Battery Detector (Standard Version)
external pullup resistor can be connected to VO, or any other voltage rail in the voltage range of 0 V to 17 V. disabled when the device is disabled. implemented. See Adding Hysteresis to Low-Battery Input on the TPS62113 (SLVA373) for details. Figure 4. LBI With Increased Hysteresis
9.3.3 Enable/Low-Battery Detector - Enhanced Version (TPS62113 Only)
the LBI trip point of 1.256 V, the device is completely enabled and starts switching. This functionality is the only difference between the TPS62110 and TPS62113 devices.
9.3.4 Power Good Comparator
than the undervoltage lockout V(UVLO). the PG pin floating or grounded when not used.
TPS62110,TPS62111,TPS62112,TPS62113 SLVS585E –JULY 2005–REVISED JUNE 2015 www.ti.com Feature Description (continued)
9.3.5 Undervoltage Lockout
The undervoltage lockout (UVLO) circuit prevents the device from misoperation at low-input voltages. It prevents the converter from turning on the switch or rectifier MOSFET under undefined conditions. The minimum input voltage to start up the TPS6211x devices is 3.4 V (worst case). The device shuts down at 2.8 V minimum.
9.3.6 Synchronization
If no clock signal is applied, the converter operates with a typical switching frequency of 1 MHz. It is possible to synchronize the converter to an external clock within a frequency range from 0.8 MHz to 1.4 MHz only. The device automatically detects the rising edge of the first clock and synchronizes immediately to the external clock. If the clock signal is stopped, the converter automatically switches back to the internal clock and continues operation. The switch over is initiated if no rising edge on the SYNC pin is detected for a duration of four clock cycles. Therefore, the maximum delay time can be 6.25 µs if the internal clock has its minimum frequency of 800 kHz. If the device is synchronized to an external clock, the power save mode is disabled, and the devices stay in forced PWM mode. Connecting the SYNC pin to the GND pin enables the power save mode. The converter operates in the PWM mode at moderate-to-heavy loads, and in the PFM mode during light loads, which maintains high efficiency over a wide load current range.
9.3.7 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 145°C typical, the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG goes high impedance. When TJ decreases by typically 10°C, the converter resumes normal operation.
9.4 Device Functional Modes
9.4.1 Soft Start
The TPS6211x has an internal soft-start circuit that limits the inrush current during start-up. This prevents possible voltage drops of the input voltage when a battery or a high-impedance power source is connected to the input of the TPS6211x devices. The soft start is implemented as a digital circuit increasing the switch current in steps of 300 mA, 600 mA, and 1200 mA for 250 µs each. Then, the switch current limit is set to 2.4 A typical. Therefore, the start-up time depends on the output capacitor and load current. Typical start-up time with a 22-µF output capacitor and 800- mA load current is 1 ms. The TPS6211x devices can start into a prebiased output. During monotonic prebiased start-up, the N-channel MOSFET is not allowed to turn on until the internal ramp of the device sets an output voltage greater than the prebias voltage.
9.4.2 Constant-Frequency Mode of Operation (Sync = High)
In constant-frequency mode, the output voltage is regulated by varying the duty cycle of the PWM signal in the range of 100% to 10%. Connecting the SYNC pin to a voltage greater than 1.5 V forces the converter to operate permanently in the PWM mode even at light- or no-load currents. The advantage is that the converter operates with a fixed switching frequency that allows simple filtering of the switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save mode during light loads. The N- MOSFET of the devices stays on even when the current into the output drops to zero. This prevents the device from going into discontinuous mode, and the device transfers unused energy back to the input. Therefore, there is no ringing at the output, which usually occurs in discontinuous mode. The duty cycle range in constant- frequency mode is 100% to 10%.
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Product Folder Links: TPS62110 TPS62111 TPS62112 TPS62113
9.4.3 Power Save Mode of Operation (Sync = Low)
Figure 5. Power Save Mode Output-Voltage Thresholds Use Equation 1 the typical PFM (SKIP) current threshold for the TPS6211x devices. operation with the use of the 100% duty-cycle mode. In this mode, the P-channel switch is constantly turned on. load current and output voltage, and is calculated using Equation 2.
TPS62110,TPS62111,TPS62112,TPS62113 SLVS585E –JULY 2005–REVISED JUNE 2015 www.ti.com Device Functional Modes (continued)
9.4.5 No-Load Operation
When the converter operates in the forced PWM mode and there is no load connected to the output, the converter regulates the output voltage by allowing the inductor current to reverse for a short time.
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Product Folder Links: TPS62110 TPS62111 TPS62112 TPS62113
1 M/c87 1 M/c87
validate and test their design implementation to confirm system functionality.
10.1 Application Information
suited for systems powered from a 2- to 4-cell Li-ion battery or from a 12-V or 15-V rail.
10.2 Typical Applications
10.2.1 Standard Connection for Adjustable Version
Figure 6. Standard Connection for Adjustable Version
10.2.1.1 Design Requirements
Table 1. Bill of Materials for the Adjustable Version
Table 1. Bill of Materials for the Adjustable Version (continued)
10.2.1.2 Detailed Design Procedure
dividers adjusted according Table 2. Table 2. Recommended Resistors
10.2.1.2.1 External Component Selection
inductor and output capacitor. Table 3. Advantages and Disadvantages When Designing the Inductor and Output Capacitor
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Table 3. Advantages and Disadvantages When Designing the Inductor and Output Capacitor (continued)
10.2.1.2.2 Inductor Selection
voltages greater than 12 V, it makes sense to increase the inductor value to keep the inductor-current ripple low. be avoided to keep the voltage overshoot during load transient in an acceptable range.
- Current rating of the inductor
- DC resistance The DC resistance of the inductance directly influences the efficiency of the converter. Therefore, an inductor with lowest DC resistance should be selected for highest efficiency. To avoid saturation of the inductor, the inductor should be rated at least for the maximum output current plus the inductor ripple current which is calculated using Equation 4. where
- f = Switching frequency (1000 kHz typical)
- L = Inductor value
- ΔIL = Peak-to-peak inductor ripple current
- IL(max) = Maximum inductor current (4) The highest inductor current occurs at maximum VI. A more conservative approach is to select the inductor current rating just for the maximum switch current of the TPS6211x, which is 2.4 A (typically). See Table 4 for recommended inductors.
Table 4. List of Inductors
10.2.1.2.3 Output Capacitor Selection
The RMS ripple current is calculated using Equation 5.
- the highest output voltage ripple occurs at the highest input voltage VI. (6)
10.2.1.2.4 Input Capacitor Selection
calculated using Equation 7. same source. TI does not recommend an RC filter from VIN to VINA.
10.2.1.2.5 Feedforward Capacitor Selection
The feedforward capacitor (Cff) is needed to compensate for parasitic capacitance from the feedback pin to GND. output voltage ripple in PFM mode.
10.2.1.2.6 Recommended Capacitors
capacitors listed in Table 5 have been tested with the TPS6211x devices with good performance. Table 5. List of Capacitors
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10.2.1.3 Application Curves
Figure 8. TPS62110 Efficiency vs Output CurrentFigure 7. TPS62110 Efficiency vs Output Current Figure 10. TPS62110 Efficiency vs Output CurrentFigure 9. TPS62110 Efficiency vs Output Current
10.2.2 Standard Connection for Fixed-Voltage Version
Figure 11. Standard Connection for Fixed-Voltage Version
10.2.2.1 Design Requirements
Table 6. Bill of Materials for the Fixed Voltage Versions
10.2.2.2 Detailed Design Procedure
10.2.2.3 Application Curves
Figure 12. TPS62112 Efficiency vs Output Current Figure 13. TPS62112 Efficiency vs Output Current Figure 14. TPS62111 Efficiency vs Output Current Figure 15. TPS62111 Efficiency vs Output Current
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5 V/div
Figure 17. TPS62111 Line TransientFigure 16. TPS62111 Efficiency vs Output Current Figure 19. TPS62111 Output RippleFigure 18. TPS62111 Load Transient Figure 20. TPS62111 Start-up Timing
10.3 System Examples
shows and application example with 9-V output. A. For an output voltage greater than 5 V, an output capacitor of 33 μF minimum is required for stability. Figure 21. Application With 9-V Output
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11 Power Supply Recommendations
The TPS6211x family of devices has no special requirements for its input power supply. The output current of the input power supply must be rated according to the supply voltage, output voltage, and output current of the TPS6211x devices.
12 Layout
12.1 Layout Guidelines
A proper layout is critical for the operation of a switched-mode power supply (SMPS), even more at high switching frequencies. Therefore, the PCB layout of the TPS6211x devices demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity. Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load current should be as short and wide as possible. The input and output capacitance should be placed as close as possible to the IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Provide low capacitive paths (with respect to all other nodes) for wires with high dv/dt. Therefore, keep the SW node small. Loops which conduct an alternating current should outline an area as small as possible, as this area is proportional to the energy radiated. Sensitive nodes like FB and LBI need to be connected with short wires and not nearby high dv/dt signals (that is, SW). The FB resistors, R1 and R2, and LBI resistors, R5 and R6, should be kept close to the IC and connect directly to those pins and AGND. The 1-µF capacitor on VINA should connect directly from VINA to AGND. All grounds (GND, AGND, and PGND) are directly connected to the exposed thermal pad. The exposed thermal pad must be soldered to the circuit board for mechanical reliability and to achieve appropriate power dissipation. See Figure 22 for the recommended layout of the TPS6211x. Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: TPS62110 TPS62111 TPS62112 TPS62113
12.2 Layout Example
Figure 22. Recommended Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Related Links
tools and software, and quick access to sample or buy. Table 7. Related Links
13.3 Community Resources
solve problems with fellow engineers. contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
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www.ti.com 11-Jul-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS62110RSAR ACTIVE QFN RSA 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TPS 62110 Samples TPS62110RSARG4 ACTIVE QFN RSA 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TPS 62110 Samples TPS62110RSAT ACTIVE QFN RSA 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 62110 Samples TPS62110RSATG4 ACTIVE QFN RSA 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 62110 Samples TPS62111RSAR ACTIVE QFN RSA 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TPS 62111 Samples TPS62111RSARG4 ACTIVE QFN RSA 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TPS 62111 Samples TPS62111RSAT ACTIVE QFN RSA 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 62111 Samples TPS62112RSAR ACTIVE QFN RSA 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 62112 Samples TPS62112RSARG4 ACTIVE QFN RSA 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 62112 Samples TPS62112RSAT ACTIVE QFN RSA 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 62112 Samples TPS62113RSAR ACTIVE QFN RSA 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 62113 Samples TPS62113RSAT ACTIVE QFN RSA 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 62113 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". Addendum-Page 1
www.ti.com 11-Jul-2024 RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS62110, TPS62111, TPS62112 :
- Automotive : TPS62110-Q1
- Enhanced Product : TPS62110-EP , TPS62111-EP , TPS62112-EP NOTE: Qualified Version Definitions:
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
- Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 20-Apr-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 20-Apr-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62110RSAR QFN RSA 16 3000 346.0 346.0 33.0 TPS62110RSAT QFN RSA 16 250 210.0 185.0 35.0 TPS62111RSAR QFN RSA 16 3000 346.0 346.0 33.0 TPS62111RSAT QFN RSA 16 250 210.0 185.0 35.0 TPS62112RSAR QFN RSA 16 3000 346.0 346.0 33.0 TPS62112RSAT QFN RSA 16 250 210.0 185.0 35.0 TPS62113RSAR QFN RSA 16 3000 346.0 346.0 33.0 TPS62113RSAT QFN RSA 16 250 210.0 185.0 35.0 Pack Materials-Page 2
www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRSA 16 PLASTIC QUAD FLATPACK - NO LEAD4 x 4, 0.65 mm pitch 4230969/A
www.ti.com PACKAGE OUTLINE C 16X 0.38 0.23 2.7 0.1 16X 0.5 0.3 1.0 0.8 (0.2) TYP 0.05 0.00 12X 0.65 1.95 A 4.1 3.9 B 4.1 3.9 VQFN - 1 mm max heightRSA0016B PLASTIC QUAD FLATPACK - NO LEAD 4219093/A 08/2021 PIN 1 INDEX AREA 0.08 SEATING PLANE 5 8 16 13 X 0.3)(45 PIN 1 ID 0.1 C A B 0.05 C EXPOSED THERMAL PAD SYMM
17 SYMM
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 4. Reference JEDEC registration MO-220. SCALE 3.300
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MIN
0.07 MAX
16X (0.31) 16X (0.6) ( 0.2) TYP VIA 12X (0.65) (3.8) (3.8) (1.1) ( 2.7) (R0.05) TYP (1.1) VQFN - 1 mm max heightRSA0016B PLASTIC QUAD FLATPACK - NO LEAD 4219093/A 08/2021 SYMM 5 8 1316 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)
www.ti.com EXAMPLE STENCIL DESIGN 16X (0.6) 16X (0.31) 12X (0.65) (3.8) (3.8) 4X ( 1.19) (0.695) TYP (0.695) TYP (R0.05) TYP VQFN - 1 mm max heightRSA0016B PLASTIC QUAD FLATPACK - NO LEAD 4219093/A 08/2021 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP EXPOSED SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 77% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 5 8 1316
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