TMDS461PZT

TMDS461 TI1 | Alldatasheet

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www.ti.com SLLS915 JANUARY 2009 1080p Deep Color 4-to-1 HDMI/DVI Switch with Adaptive Equalization Temperature Range: C to C 4:1 Switch Supporting DVI Above 1920 1200 Automatic Port Select Feature and HDMI HDTV Resolutions up to 1080p With Robust TMDS Receive Stage That Can Work 16-bit Color Depth With Non-Compliant Input Common-Mode Designed for Signaling Rates up to Gbps HDMI Signals HDMI1.3a Spec Compliant Adaptive Equalization to Support up to 20-m High-Definition Digital TV HDMI Cable LCD TMDS Input Clock-Detect Circuit Plasma DDC Repeater Function DLP mW Low-Power Mode Local I C or GPIO Configurable Enhanced ESD. HBM: kV on All Input TMDS, DDC I C pins 3.3-Volt Power Supply The TMDS461 is a 4-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to four DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to Gbps to allow 1080p resolution in 16-bit color depth. The TMDS461 provides an analog adaptive equalizer for different ranges of cable lengths. The equalizer automatically compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to dB at Gbps (see Figure Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. DLP is a registered trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(CONTINUED) TMDS461 SLLS915 JANUARY 2009 www.ti.com When any input port is selected, the integrated terminations (50- Ω termination resistors pulled up to VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state. The TMDS461 is designed to be controlled via a local I C interface or GPIO interface based on the status of the I2C_SEL pin. The local I C interface in TMDS461 is a slave-only I C interface. (See the I2C INTERFACE NOTES section.) I C Mode When the I2C_SEL pin is set high, the device is in I C mode. Refer to Table to Table for I C register description. With local I the interface port status can be read and the advanced configurations of the device such as TMDS output edge rate control, DDC I C buffer output-voltage-select (OVS) settings (See the DDC I2C Function I C buffer description), device power management, TMDS clock-detect feature, Automatic Port Selection and TMDS input-port selection can be set. In I C mode when any system level change such as change in 5V_PWR on the source side, a change in the selected port, or a change in the selected port s valid clock detect is detected, TMDS461 can issue an Interrupt Request via IRQ pin (refer IRQ Section A micro-controller connected to TMDS461 can read I C register address 0X01, (See Table to obtain the current status of 5V_PWR, the selected port, and clock-detect status. Once the micro-controller has read I C register 0x01, the IRQ pin returns to low. GPIO mode: When the I2C_SEL pin is set low, the device is in GPIO control mode. The port selection is controlled with source selectors, and S2. The power-saving mode is controlled through the LP pin. In GPIO mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set. The DDC I C buffer OVS setting can be changed through OVS GPIO pin, see Table In GPIO mode, IRQ pin reflects the status of the selected port s clock detect. If a valid clock is detected by the clock detect circuit, IRQ goes high. If no valid clock is detected, IRQ is driven low. Following are some of the key (advantages) that TMDS461 provides to the overall sink-side system (HDTV). 4:1 switch that supports TMDS data rates up to Gbps on all four input ports. ESD: Built-in support for high ESD protection (up to kV on the TMDS and DDC I C pins The HDMI source-side pins on the TMDS461 are connected via the HDMI/DVI exterior connectors and cable to the HDMI/DVI sources (e.g., DVD player). In TV applications, it can be expected that the source side may be subjected to higher ESD stresses compared to the sink side that is connected internally to the HDMI receiver. Adaptive equalization: The built-in analog adaptive equalization support compensates for intersymbol interference [ISI] loss of up to dB, which represents a typical 20-m HDMI/DVI cable at Gbps. Analog Adaptive equalization adjusts the equalization gain automatically based on the cable length and the incoming TMDS data rate. TMDS clock-detect circuitry: This feature provides an automatic power-management feature and also ensures that the TMDS output port is turned on only if there is a valid TMDS input signal. TMDS clock-detect feature can be by-passed in I C Mode, (See Table It is recommended to enable TMDS clock-detect circuitry during normal operation. However, for HDMI compliance testing (TMDS Termination Voltage Test), the clock detect feature should be disabled by using the I C mode control. To comply with the TMDS Termination Voltage Test in the GPIO mode (default TMDS clock-detect circuitry enabled), a valid TMDS clock will need to be provided. With the clock present, the internal terminations are present providing the correct termination voltage. DDC I C buffer: This feature provides isolation on the source side and sink side DDC I C capacitance, thus helping the sink system to pass system-level compliance. Robust TMDS receive stage: This feature ensures that the TMDS461 can work with TMDS input signals which have common-mode voltage levels that can be either compliant or non-compliant with HDMI/DVI specifications VSadj: This feature adjusts the TMDS output swing and can help the sink system to tune the output TMDS swing of the TMDS461 (if needed) based on the system requirements. GPIO or local I C interface to control the device 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

HPD_SINK 4-to-1 MUX Local□I2C Control□Logic Vcc RINT TMDS□Rx w/ AEQ Clock□Detect RINT Vcc RINT TMDS□Rx RINT Vcc RINT TMDS□Rx w/ AEQ Clock□Detect RINT Vcc RINT TMDS□Rx RINT Dx+_1 Dx-_1 CLK+_1 CLK-_1 Dx+_4 Dx-_4 CLK+_4 CLK-_4 xx2 xx3 Rx Tx Rx Tx SCL1 SDA1 Rx Tx Rx Tx SCL4 SDA4 5V_PWR1 HPD1 1kΩ 5V_PWR2 HPD2 1kΩ 5V_PWR3 HPD3 1kΩ 5V_PWR4 HPD4 1kΩ VSadj Dx+_SINK Dx-_SINK CLK+_SINK CLK-_SINK TMDS Tx TMDS Tx Tx Rx Tx Rx SDA_SINK SCL_SINK IRQ 5V_Ind LP I2C_SEL Local_SDA Local_SCL Clock□Detect OVS TMDS461 www.ti.com SLLS915 JANUARY 2009 TMDS output edge-rate control: This feature adjusts the TMDS461 TMDS output rise and fall times. There are four settings that can be chosen. The default setting is the fastest rise and fall time; the other three settings are slower. Slower edge transitions can potentially help the sink system (HDTV) in passing regulatory EMI compliance. Automatic Port Select Feature available in I C mode 5V_PWR detect for each port connected, Hot Plug Detect (HPD) of non selected port follows 5V_PWR, whereas HPD of selected port follows HPD_SINK. Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CLK-_1 CLK+_1 D0-_1 D0+_1 D1-_1 D1+_1 D2-_1 D2+_1 SCL1 SDA1 5V_PWR1 CLK-_2 CLK+_2 D0-_2 D0+_2 D1-_2 D1+_2 D2-_2 D2+_2 CLK-_SINK CLK+_SINKD0-_SINK D0+_SINKD1-_SINK D1+_SINKD2-_SINK D2+_SINK SCL_SINK SDA_SINK 5V_Ind SCL2 SDA2 HPD2 SCL4 SDA4 HPD4 SCL3 SDA3 HPD3 VCC VCC VCC VCC VCC GND GND GND GND HPD1 5V_PWR2 5V_PWR4 5V_PWR3 VCC GND VCC GNDGND VCC GND VCC GND VCC VCC VCCGND GND CLK-_3CLK+_3 D0-_3D0+_3 D1-_3D1+_3 D2-_3D2+_3 CLK-_4CLK+_4 VSadj Local_SCL Local_SDA Local_AddrIRQ S1 S2LPI2C_SELGND OVSVCC GND NC HPD_SINK GND VCC GND TMDS461 SLLS915 JANUARY 2009 www.ti.com TERMINAL FUNCTIONS TERMINAL I/O NO. TMDS INPUT PINS CLK+_1 I Port-1 TMDS differential clock CLK-_1 D[0:2]+_1 I Port-1 TMDS differential data inputs D[0:2]-_1 CLK+_2 I Port-2 TMDS differential clock CLK-_2 D[0:2]+_2 18, 21, 24, I Port-2 TMDS differential data inputs D[0:2]-_2 17, 20, CLK+_3 I Port-3 TMDS differential clock CLK-_3 D[0:2]+_3 31, 34, I Port-3 TMDS differential data inputs D[0:2]-_3 30, 33, CLK+_4 I Port-4 TMDS differential clock CLK-_4 Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

www.ti.com SLLS915 JANUARY 2009 TERMINAL FUNCTIONS (continued) TERMINAL I/O NO. D[0:2]+_4 43, 46, I Port-4 TMDS differential data inputs D[0:2]-_4 42, 45, TMDS OUTPUT PINS CLK+_SINK O TMDS sink differential clock CLK-_SINK D[0:2]+_SINK 95, 92, O TMDS sink differential data outputs D[0:2]-_SINK 96, 93, HOT-PLUG-DETECT STATUS PINS HPD[1:4] 70, 65, 60, O Source port hot-plug-detect output HPD_SINK I Sink hot plug detect input DDC PINS SCL[1:4] 67, 62, 57, I/O TMDS port bidirectional DDC clock SDA[1:4] 68, 63, 58, I/O TMDS port bidirectional DDC data SCL_SINK I/O TMDS sink side bidirectional DDC clock SDA_SINK I/O TMDS sink side bidirectional DDC data STATUS PINS IRQ O Interrupt Request 5V_PWR[1:4] 69, 64, 59, I Source Port Signal Input 5V_Ind O Selected Port Power Indicator CONTROL PINS LP I Low-power select bar S[1:2] 83,82 I Source Selection GPIO I2C_SEL I Local I C control select Local_SCL I Local I C clock Local_SDA I/O Local I C data Local_Addr I Local I C address VSadj I TMDS compliant voltage swing control OVS I DDC offset selector NC No Connect SUPPLY AND GROUND PINS VCC 10, 16, 22, 26, 32, 3.3 V supply 38, 44, 50, 56, 80, 88, 94, 100 GND 13, 19, 25, 29, Ground 35, 41, 47, 51, 61, 71, 84, 91, Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

www.ti.com Table Source Selection Lookup (1) CONTROL I/O SELECTED HOT-PLUG DETECT STATUS Power Mode PINS SCL_SINK Port Selected HPD1 HPD2 HPD3 HPD4 SDA_SINK Port SCL1 L L Terminations of port HPD_SINK 5V_PWR2 5V_PWR3 5V_PWR4 Normal mode SDA1 and are disconnected. Port SCL2 L H Terminations of port 5V_PWR1 HPD_SINK 5V_PWR3 5V_PWR4 Normal mode SDA2 and are disconnected. Port SCL3 H L Terminations of port 5V_PWR1 5V_PWR2 HPD_SINK 5V_PWR4 Normal mode SDA3 and are disconnected. Port SCL4 H H Terminations of port SDA4 5V_PWR1 5V_PWR2 5V_PWR3 HPD_SINK Normal mode and are disconnected. (1) Logic high; Logic low Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

DDC□Buffer Buffer TMDS□Input□Stage A B VCC 50 /c87 50 /c87 VCC TMDS□Output□Stage Z Y 10□mA VCC HPD□[x] HPD_SINK 5□V_PWR□[x] HPD□Output□Stage IRQ,□5V_Ind VCC 1kΩ Output□StageStatus□and□Source□Selector HPD_SINK VCC 5□V_PWR□[x] TMDS461 www.ti.com SLLS915 JANUARY 2009 Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

www.ti.com Table Control Pin Lookup Table (1) SIGNAL LEVEL STATE H Normal Mode Normal operational mode for device. LP Low-power Device is forced into a low power state, causing the inputs and outputs to go to a L mode high-impedance state. All other inputs are ignored. L L Port Port is selected as the active port; all other ports are disabled. S[2:1] L H Port Port is selected as the active port; all other ports are disabled. GPIO Mode H L Port Port is selected as the active port; all other ports are disabled. H H Port Port is selected as the active port; all other ports are disabled. H I C Device is configured by I C logic. I2C_SEL L GPIO Device is configured by GPIO. H 0101101 The 7-bit address for the local I C logic is 0101101 Local_Addr L 0101100 The 7-bit address for the local I C logic is 0101100 H Offset DDC sink side VOL and VIL offset range V IL1 (max) 0.4V, V OL1 (max) 0.7V OVS L Offset DDC sink side VOL and VIL offset range V IL2 (max) 0.4V, V OL2 (max) 0.6V Hi-Z Offset DDC sink side VOL and VIL offset range V IL3 (max) 0.3V, V OL3 (max) 0.5V Driver output voltage swing precision control to aid with system compliance. VSadj resistor Compliant VSadj 4.02 k Ω value could be selected to be Voltage Swing 4.02 k Ω 10% based on the system requirement to pass HDMI compliance. (1) (H) Logic high; (L) Logic low ORDERING INFORMATION (1) PART NUMBER PART MARKING PACKAGE TMDS461PZTR TMDS461 100-pin TQFP reel TMDS461PZT TMDS461 100-pin TQFP tray (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT Supply voltage range (2) VCC 0.3 to 3.6 V Voltage range TMDS I/O 0.3 to HPD and DDC I/O 0.3 to 5.5 V Control and status I/O 0.3 to 5.5 Electrostatic discharge Human body model (3) on SCL[1:4], SDA[1:4], D[0:2]+_[1:4], D[0:2] _[1:4], 10,000 CLK+_[1:4], CLK _[1:4] pins Human body model (3) on all other pins 6,000 V Charged-device model (4) 1500 Machine model (5) 200 Continuous power dissipation See Dissipation Ratings table (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-B (4) Tested in accordance with JEDEC Standard 22, Test Method C101-A (5) Tested in accordance with JEDEC Standard 22, Test Method A115-A Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

www.ti.com SLLS915 JANUARY 2009 PCB JEDEC STANDARD T A C DERATING FACTOR (1) T A C PACKAGE ABOVE T A C POWER RATING 100-pin TQFP (PZT) Low-K 1329 mW 13.2 mW/ C 731 mW High-K 1631 mW 16.3 mW/ C 897 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX (1) UNIT R θ JB Junction-to-board thermal resistance 37.13 C/W R θ JC Junction-to-case thermal resistance 15.3 C/W Device power dissipation in normal mode LP HIGH TMDS: V ID(pp) 1200 mV, Gbps 666 P D(1) TMDS data pattern; HPD_SINK HIGH, S1/S2 792 mW LOW/LOW, LOW/HIGH, HIGH/HIGH, HIGH/LOW. Device power dissipation in standby LP HIGH, TMDS: V ID(pp) 1200 mV, Gbps mode TMDS data pattern; HPD_SINK HIGH, (See P D(2) Table Register 0x02[7:6] =[0:1]. Note that mW standby power mode is only available when TMDS461 is configured in I C mode. Device power dissipation in low-power P SD LP LOW. mW mode Device power dissipation in normal mode LP HIGH, No TMDS input clock, HPD_SINK 61.2 with no active TMDS input clock =HIGH, P NCLK mW S1/S2 LOW/LOW, LOW/HIGH, HIGH/HIGH, HIGH/LOW. (1) The maximum rating is simulated under 3.6V VCC across worse case temperature and process variation, Typical conditions are simulated at 3.3V VCC, C with nominal process material. MIN NOM MAX UNIT VCC Supply voltage 3.3 3.6 V T A Operating free-air temperature C TMDS DIFFERENTIAL OUTPUT PINS V ID(pp) Peak-to-peak input differential voltage 0.15 1.56 V V IC Input common mode voltage V CC V CC 0.01 V 0.4 AV CC TMDS output termination voltage 3.3 3.6 V d R Data rate Gbps R VSADJ Resistor for TMDS compliant voltage swing range 3.66 4.02 4.47 K Ω R t Termination resistance Ω DDC PINS V I Input voltage 5.5 V d R(I2C) I C data rate 100 Kbps HPD_SINK, 5V_PWR[x], S1, S2, OVS V IH High-level input voltage: HPD_SINK, 5V_PWR[x], S1, 5.5 V V IL Low-level input voltage: HPD_SINK, 5V_PWR[x], S1, 0.8 V V IHOVS High-level input voltage: OVS 5.5 V V ILOVS Low-level input voltage: OVS 0.5 V Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

www.ti.com The TMDS461 is designed to operate from a single 3.3-V supply voltage. The TMDS461 has three power modes of operation. These three modes are referred to as normal mode, standby mode, and low-power mode. Normal mode is designed to be used during typical operating conditions. In normal mode, the device is fully functional and consumes the greatest amount of power. Standby mode is designed to be used when reduced power is desired, but DDC and HPD communication must be maintained. Standby mode can be enabled via the I C interface (See Table only. In standby mode, the high-speed TMDS data and clock channels are disabled to reduce power consumption. The internal I C logic and DDC function normally. HPD[1:4] of the selected port follows HPD_SINK. HPD[1:4] of the non-selected port follows 5V_PWR[1:4]. Low-power mode is designed to consume the least possible amount of power while still applying 3.3 V to the device. Low-power mode can be enabled by either the LP pin or by local I C (See Table In low-power mode, all of the inputs and outputs are disabled with the exception of the internal I C logic and LP pin. The clock-detect feature in the TMDS461 provides an automatic power-management feature in normal mode. if no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected, and the TMDS outputs are high-Z. As soon as a valid TMDS clock is detected, the terminations on the TMDS data lines are connected, the TMDS outputs come out of high-Z, and the device is fully functional and consumes the greatest amount of power. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I CC Normal-mode supply current LP HIGH TMDS: V ID(pp) 1200 mV, Gbps TMDS data pattern; 185 220 mA HPD_SINK HIGH, S1/S2 LOW/LOW, LOW/HIGH, HIGH/HIGH, HIGH/LOW. I STBY Standby supply current LP HIGH, TMDS: V ID(pp) 1200 mV, Gbps TMDS data pattern; 5.5 mA HPD_SINK HIGH, (See Table Register 0x02[7:6] =[0:1]. Note that standby power mode is only available when TMDS461 is configured in I C mode. I SD Shutdown current LP LOW. 300 555 µ A Normal-mode supply current, LP HIGH, No TMDS input clock, HPD_SINK =HIGH, S1/S2 I NCLK with no active TMDS input LOW/LOW, mA clock LOW/HIGH, HIGH/HIGH, HIGH/LOW. DETECT TMDS461 incorporates detect logic on each input port. 5V_PWR is the that an HDMI/DVI source provides to an HDMI/DVI sink. As soon as TMDS461 detects a high on any of the 5V_PWR[1:4] signals, the 5V_Ind pin which is Power detect indicator goes high. In I C mode, a micro controller connected to TMDS461 can read the status of 5V_PWR[x] signals by reading (See Table I C register 0x01. Hot Plug Detect: The TMDS461 is designed to support the Hot Plug indication to the input ports. For the selected port, the state of the Hot Plug output (HPD[1:4]) follows the state of the Hot Plug input (HPD_SINK). For the non selected ports, the state of the Hot Plug outputs follows logic state of 5V_PWR. (See Table HPD[x] are internally connected to 5V_PWR[x] via Ω resistor as shown in Figure (b). Thus even if the TMDS461 is powered off, HPD[x] will still follow 5V_PWR[x]. When the HDMI transmitter does not have the capability of detecting the TMDS receiver termination, using the HPD signal as a reference for sensing port selections is the only possible method. Thus it is recommended that HPD_SINK can be held low before port selection is done and then forced high after port selection, this ensures that HPD[x] of the selected port is pulsed High-to-Low at port selection before HPD[x] follows HPD_SINK. In Standby power savings mode, HPD functions similar to normal mode. In low LP) power savings mode, the HPD[x] follows 5V_PWR[x]. Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

5□pF 5□pF 5□V 1□k/c87 HPD□[x] HPD_SINK 5□pF 5□V_PWR□[x] 5□pF (a) (b) TMDS461 www.ti.com SLLS915 JANUARY 2009 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OH(HPD[x]) High-level output voltage 5V_PWR =4.5-5.5V 5V_PW V R V OL(HPD[x]) Low-level output voltage 5V_PWR =4.5-5.5V 0.4 V I H(HPD_SINK) High-level input current V IH 2V, V CC 3.6 V µ A I L(HPD_SINK) Low-level input current V IL 0.8V, V CC 3.6 V µ A I H(5V_PWR[x]) High-level input current V IH 5.5V, V CC 3.6 V µ A V OH(5V_Ind) High-level output voltage I OH 100 µ A 2.4 VCC V V OL(5V_Ind) Low-level output voltage I OL 100 µ A 0.4 V R L(HPD[x]) Output source impedance R L(HPD[x]) is connected between 800 1000 1200 k Ω 5V_PWR[x] and HPD[x]. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t PD1(HPD) HPD_SINK propagation delay HPD_SINK to HPD[1:4] ns t PD2(HPD) 5V_PWR to HPD propagation delay 5V_PWR[1:4] to HPD[1:4]. ns t S1(HPD) Selecting port HPD switch time S[1:2] to HPD[1:4] ns t S2(HPD) De-selecting port HPD switch time S[1:2] to HPD[1:4] ns t z(HPD) LP to HPD[x] switch time LP to HPD[x] ns t PD3(5v) 5V_PWR to 5V_Ind propagation delay PWR to 5V_Ind propagation Delay ns (Load on 5V_Ind: pF) Figure 5V_PWR and HPD Test Circuit Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

5 V_PWR[x]

5 V_Ind

2.5 V VCC tpd3(5□V) LP HPD_SINK HPD[x]: selected□port tz(HPD) 5V_PWR[x] 5 V 5 V 2.5 V 2.5 V (5V_PWR[x])/2

5 VHPD_SINK

HPD_ [x]: Selected□Port

5 V_PWR

tpd 1(HPD) 2.5 V

5 V_ PWR/2

5 V5 V _ PWR[x]

HPD_ [x]: Non□Selected Port 5 V_PWR tpd2(HPD ) 2.5 V

5 V_PWR/2

tz(HPD) VCC/2 (5V_PWR[x])/2 TMDS461 SLLS915 JANUARY 2009 www.ti.com Figure HPD Timing Diagram Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

HPD_SINK HPD[3] 5 V_PWR3 PORT3 is□non□selected port PORT3 is□selected□port PORT3 is□non□selected port tS 1(HPD) tpd1(HPD) tS2□(HPD) 2.5V 2.5V (5V_PWR3)/2(5V_PWR3)/2 5 V 5 V 2.5V (5V_PWR3)/2 IRQ ELECTRICAL CHARACTERISTICS TMDS461 www.ti.com SLLS915 JANUARY 2009 Figure HPD Timing Diagram I C mode: When TMDS461 is configured in I C mode, the IRQ pin in TMDS461 functions as a system level interrupt indicator pin. The TMDS461 issues Interrupt Requests by raising the IRQ pin from low to high, which can be detected by the sink micro-controller. An Interrupt Request occurs when any system level change is detected by TMDS461, which is a change in 5V_PWR on the source side, a change in the selected port, or a change in the selected port s valid clock detect. The micro-controller can read I C register address 0x01 to obtain the current status of 5V_PWR, the selected port, and clock detect status. Once the micro-controller has read 0x01, the IRQ pin returns to low. It is desired that as soon as the sink micro-controller gets an Interrupt Request, it reads I C register address 0x01 GPIO mode: When TMDS461 is configured in GPIO mode, the IRQ pin in TMDS461 functions as a clock-detect indicator pin for the selected port. If a valid clock is detected by the clock detect circuit, IRQ goes high. If no valid clock is detected, IRQ is driven low. Refer to TMDS Main Link Switching Characteristics t CLK1 for valid clock enable time and TMDS Main Link Switching Characteristics t CLK2 for valid clock disable time. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OH(IRQ) High-level output voltage I OH 100 µ A 2.4 V CC V V OL(IRQ) Low-level output voltage I OL 100 µ A 0.4 V R L(IRQ) Output source impedance 800 1000 1200 k Ω Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

Port 1 is□selected Port 2 is□selected Port 3 is□selected Port 4 is□selected [5V_PWR1 = LOW & 5V_PWR2 = LOW & 5V_PWR3 = LOW & 5V_PWR4 = HIGH ] [5V_PWR1 = LOW & 5V_PWR2 = LOW & 5V_PWR3 = HIGH & 5V_PWR4 = X ] [5V_PWR1 = LOW & 5V_PWR2 = HIGH & 5V_PWR3 = X & 5V_PWR4 = X ] [5V_PWR1 = LOW & 5V_PWR2 = LOW & 5V_PWR3 = HIGH & 5V_PWR4 = X ] [5V_PWR1 = LOW & 5V_PWR2 = HIGH & 5V_PWR3 = X & 5V_PWR4 = X ][5V_PWR1 = HIGH & 5V_PWR2 = X & 5V_PWR3 = X & 5V_PWR4 = X ] [5V_PWR1 = LOW & 5V_PWR2 = HIGH & 5V_PWR3 = X & 5V_PWR4 = X ] TMDS461 configured□in Automatic Port□Selection□Mode□with Port 1 as□Priority□Port [5V_PWR1 =High & 5V_PWR2 = X & 5V_PWR3 = X & 5V_PWR4 = X ] TMDS461 SLLS915 JANUARY 2009 www.ti.com TMDS461 incorporates an AutoSelect Feature that is available in I C mode only. Refer to Table bits If the TMDS461 is configured in AutoSelect Mode, then the port selection is done based on the priority bit (Refer to Table bit and 5V_PWR[x] (See Table bit as indicated in Figure Figure Figure and Figure Figure TMDS461 Configured in AutoSelect Mode, with Port as Priority Port Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

Port 2 is□selected Port 1 is□selected Port 3 is□selected Port 4 is□selected [5V_PWR2 = LOW & 5V_PWR1 = LOW & 5V_PWR3 = LOW & 5V_PWR4 = HIGH ] [5V_PWR2 = LOW & 5V_PWR1 = LOW & 5V_PWR3 = HIGH & 5V_PWR4 = X ] [5V_PWR2 = LOW & 5V_PWR1 = HIGH & 5V_PWR3 = X & 5V_PWR4 = X ] [5V_PWR2 = LOW & 5V_PWR1 = LOW & 5V_PWR3 = HIGH & 5V_PWR4 = X ] [5V_PWR2 = LOW & 5V_PWR1 = HIGH & 5V_PWR3 = X & 5V_PWR4 = X ][5V_PWR2 = HIGH & 5V_PWR1 = X & 5V_PWR3 = X & 5V_PWR4 = X ] [5V_PWR2 = LOW & 5V_PWR1 = HIGH & 5V_PWR3 = X & 5V_PWR4 = X ] TMDS461 configured□in Automatic Port□Selection□Mode□with Port 2 as□Priority□Port [5V_PWR2 =High & 5V_PWR1 = X & 5V_PWR3 = X & 5V_PWR4 = X ] TMDS461 www.ti.com SLLS915 JANUARY 2009 Figure TMDS461 Configured in AutoSelect Mode, with Port as Priority Port Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

Port 3 is□selected Port 1 is□selected Port 2 is□selected Port 4 is□selected [5V_PWR3 = LOW & 5V_PWR1 = LOW & 5V_PWR2 = LOW & 5V_PWR4 = HIGH ] [5V_PWR3 = LOW & 5V_PWR1 = LOW & 5V_PWR2 = HIGH & 5V_PWR4 = X ] [5V_PWR3 = LOW & 5V_PWR1 = HIGH & 5V_PWR2 = X & 5V_PWR4 = X ] [5V_PWR3 = LOW & 5V_PWR1 = LOW & 5V_PWR2 = HIGH & 5V_PWR4 = X ] [5V_PWR3 = LOW & 5V_PWR1 = HIGH & 5V_PWR2 = X & 5V_PWR4 = X ][5V_PWR3 = HIGH & 5V_PWR1 = X & 5V_PWR2 = X & 5V_PWR4 = X ] [5V_PWR3 = LOW & 5V_PWR1 = HIGH & 5V_PWR2 = X & 5V_PWR4 = X ] TMDS461 configured□in Automatic Port□Selection□Mode□with Port 3 as□Priority□Port [5V_PWR3 =High & 5V_PWR1 = X & 5V_PWR2 = X & 5V_PWR4 = X ] TMDS461 SLLS915 JANUARY 2009 www.ti.com Figure TMDS461 Configured in AutoSelect Mode, with Port as Priority Port Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

Port 4 is□selected Port 1 is□selected Port 2 is□selected Port 3 is□selected [5V_PWR4 = LOW & 5V_PWR1 = LOW & 5V_PWR2 = LOW & 5V_PWR3 = HIGH ] [5V_PWR4 = LOW & 5V_PWR1 = LOW & 5V_PWR2 = HIGH & 5V_PWR3 = X ] [5V_PWR4 = LOW & 5V_PWR1 = HIGH & 5V_PWR2 = X & 5V_PWR3 = X ] [5V_PWR4 = LOW & 5V_PWR1 = LOW & 5V_PWR2 = HIGH & 5V_PWR3 = X ] [5V_PWR4 = LOW & 5V_PWR1 = HIGH & 5V_PWR2 = X & 5V_PWR3 = X ][5V_PWR4 = HIGH & 5V_PWR1 = X & 5V_PWR2 = X & 5V_PWR3 = X ] [5V_PWR4 = LOW & 5V_PWR1 = HIGH & 5V_PWR2 = X & 5V_PWR3 = X ] TMDS461 configured□in Automatic Port□Selection□Mode□with Port 4 as□Priority□Port [5V_PWR4 =High & 5V_PWR1 = X & 5V_PWR2 = X & 5V_PWR3 = X ] TMDS DDC and Local I C Pins TMDS461 www.ti.com SLLS915 JANUARY 2009 Figure TMDS461 Configured in AutoSelect Mode, with Port as Priority Port DDC I C Buffer or Repeater: The TMDS461 provides buffering on the DDC I C interface for each of the input ports connected. This feature isolates the capacitance on the source side from the sink side and thus helps in passing system-level compliance. See the DDC I2C Function a detailed I C buffer operates. Note that a key requirement on the sink side is that the V IL(Sink) (input to TMDS461) should be less than 0.4 This requirement should be met for the DDC I C buffer to function properly. There are three settings of V IL(Sink) and V OL(Sink) that can be chosen based on OVS settings (See Table Local I C Interface: The TMDS461 includes a slave I C interface to control device selection, TMDS output edge-rate control, power management, DDC buffer OVS settings, etc. See Table through Table The TMDS461 is designed to be controlled via a local I C interface or GPIO interface, based on the status of the I2C_SEL pin. The local I C interface in the TMDS461 is only a slave I C interface. See the I2C INTERFACE NOTES section for a detailed I C functionality. Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

GENERATOR D.U.T. VCC 5□V RT VIN VOUT R =□2□kL /c87 C =□100□pFL TMDS461 SLLS915 JANUARY 2009 www.ti.com over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I L Low-level input current VCC 3.6 V I V µ A I lkg(Sink) Input leakage current Sink pins VCC 3.6 V I 4.95 V µ A C IO(Sink) Input/output capacitance Sink pins DC bias 2.5 AC 3.5 Vp-p, f 100 kHz pF V IH(Sink) High-level input voltage Sink pins 2.1 5.5 V V IL1(Sink) Low-level input voltage Sink pins OVS 0.2 0.4 V V OL1(Sink) Low-level output voltage Sink pins I O mA, OVS HIGH 0.6 0.7 V V IL2(Sink) Low-level input voltage Sink pins OVS 0.2 0.4 V V OL2(Sink) Low-level output voltage Sink pins I O mA, OVS LOW 0.5 0.6 V V IL3(Sink) Low-level input voltage Sink pins OVS 0.2 0.3 V V OL3(Sink) Low-level output voltage Sink pins I O mA, OVS high-Z 0.4 0.5 V I lkg(I2C) Input leakage current Port[1:4] pins VCC 3.6 V I 4.95 V µ A C IO(I2C) Input/output capacitance Port[1:4] pins DC bias 2.5 AC 3.5 Vp-p, f 100 kHz pF V IH(I2C) High-level input voltage Port[1:4] pins 2.1 5.5 V V IL(I2C) Low-level input voltage Port[1:4] pins 0.2 1.5 V V OL(I2C) Low-level output voltage Port[1:4] pins I O mA 0.2 V over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t PLH2 Propagation delay time, low to high Source to sink 251 ns t PHL2 Propagation delay time, high to low Source to sink 200 ns t PLH1 Propagation delay time, low to high Sink to source 204 459 ns t PHL1 Propagation delay time, high to low Sink to source 200 ns t Output signal fall time Sink side ns t Output-signal fall time Source side ns f SCL SCL clock frequency for internal register Local I C 100 kHz t W(L) Clock LOW period for I C register Local I C 4.7 µ s t W(H) Clock HIGH period for internal register Local I C µ s t SU1 Internal register setup time, SDA to SCL Local I C 250 ns t h(1) Internal register hold time, SCL to SDA Local I C µ s t (buf) Internal register bus free time between STOP and START Local I C 4.7 µ s t su(2) Internal register setup time, SCL to START Local I C 4.7 µ s t h(2) Internal register hold time, START to SCL Local I C µ s t su(3) Internal register hold time, SCL to STOP Local I C µ s Figure Sink-Side Test Circuit Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

GENERATOR D.U.T. VCC 5□V RT VIN VOUT R =□2□kL /c87 C =□400□pFL SCL[x] SDA[x] Input SCL SDA_SINK Output _SINK 80% 20% tPHL2 tPLH2 5□V 1.6□V 0.1□V 5□V 1.6□V VOL T0388-01 tf2 SCL SDA_SINK Input _SINK SCL[x] SDA[x] Output 80% 20% tPHL1 5□V 1.6□V 0.1□V 5□V 1.6□V VOL tf1 T0389-01 SCL SDA_SINK Input _SINK SCL[x] SDA[x] Output tPLH1 5□V VOL 5□V 1.6□V T0390-01 TMDS461 www.ti.com SLLS915 JANUARY 2009 Figure Source-Side Test Circuit Figure 10. Sink-Side Output AC Measurements Figure 11. Source-Side Output AC Measurements Figure 12. Source-Side Output AC Measurements Cont. Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

www.ti.com The TMDS port of the TMDS461 is designed to be compliant with the Digital Video Interface (DVI) 1.0 and High Definition Multimedia Interface (HDMI) 1.3a specifications. The differential output voltage swing can be fine-tuned with the VSadj resistor. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OH Single-ended HIGH-level output voltage AVCC 3.3 R T Ω See Figure AVCC AVCC mV V OL Single-ended LOW-level output voltage AVCC AVCC mV 600 400 V SWING Single-ended output voltage swing 400 600 mV Change in steady-state common-mode output voltage V OC(SS) mV between logic states V OD(pp) Peak-to-peak output differential voltage 800 1200 mV V (O)SBY Single-ended standby output voltage AVCC AVCC mV V VCC 1.5 AVCC 3.3 I (O)OFF Single-ended power-down output current µ A R T Ω I OS Short-circuit output current See Figure mA V CD(pp) Minimum valid clock differential voltage (peak-to-peak) Input TMDS clock frequency 300 MHz 100 mV over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT t PLH Propagation delay time 250 800 ps t PHL Propagation delay time 250 800 ps t Rise time, fastest mode (default setting): Fastest 110 140 ps Setting t Fall time, fastest mode (default setting): Fastest 110 140 ps Setting t Rise time, fastest mode ps (approximately) 142 160 190 ps AVCC 3.3 R T Ω See Figure and t Fall time, fastest mode ps (approximately) 142 160 190 ps Figure t Rise time, fastest mode 100 ps (approximately) 187 210 230 ps t Fall time, fastest mode 100 ps (approximately) 187 210 230 ps t Rise time, fastest mode 120 ps 216 230 260 ps (approximately): Slowest Setting t Fall time, fastest mode 120 ps (approximately): 216 230 260 ps Slowest Setting t SK(P) Pulse skew (see (2) ps t SK(D) Intra-pair skew AVCC 3.3 R T Ω See Figure ps t SK(O) Inter-pair skew (see (3) 100 ps t JITD(PP) Peak-to-peak output residual data jitter AVCC 3.3 R T Ω dR 2.25 Gbps. ps See Figure for measurement setup; residual jitter is the total jitter measured at TTP4 minus the jitter measured at TTP1. See Figure for the loss profile of the cable used for t JITD(PP) measurement. Also see Typical Characteristics for t JITD(PP) across cable length and input TMDS data rate. (1) All typical values are at C and with a 3.3-V supply. (2) t sk(p) is the magnitude of the time difference between t PLH and t PHL of a specified terminal. (3) t sk(o) is the magnitude of the difference in propagation delay times between any specified terminals of a sink-port bank when inputs of the active source port are tied together. Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

Y Z VY VZ 50 /c87 VD- V =□V -□V V =□(V +□V ) ID D+ D- ICM D+ D- V =□V -□V V =□(V +□V ) OD Y Z OC Y Z 0.5□pF 50 /c87 50 /c87 AVCC TMDS461 www.ti.com SLLS915 JANUARY 2009 SWITCHING CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT t JITC(PP) Peak-to-peak output residual clock jitter AVCC 3.3 R T Ω input TMDS clock ps frequency 225 MHz. See Figure for measurement setup; residual jitter is the total jitter measured at TTP4 minus the jitter measured at TTP1. See Figure for the loss profile of the cable used for t JITC(PP) measurement. t CLK1 Valid clock-detect enable time AVCC 3.3 R T Ω input TMDS clock 300 500 ns frequency 300 MHz. See Figure t CLK2 Invalid clock-detect disable time AVCC 3.3 R T Ω input TMDS clock 500 800 ns frequency MHz. See Figure t SEL1 Port selection time (see (4) AVCC 3.3 R T Ω 300 500 ns t SEL2 Port deselection time (see (5) AVCC 3.3 R T Ω ns f CD Clock-detect frequency AVCC 3.3 R T Ω See Figure 300 MHz (4) t SEL1 includes the time for the valid clock detect enable time and t S1(HPD) because the t S1(HPD) event happens in parallel with t SEL1 thus, the t SEL1 time is primarily the t CLK1 time. (5) t SEL2 is primarily the t S2(HPD) time. Figure 13. TMDS Main Link Test Circuit Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

0□V tPHL tf tPLH 80% 80% VID VID(PP) VOD(PP) VOD 20% 20% tr 3.3□V 2.8□V VID- 50% VOLtsk(D) VY VZ VOH VOC ΔV OC(SS) T0424-01 tclk1 tclk2 VCD(PP) VOD(PP) TMDS□outputs Hi□Z□during□this□duration Valid□Input TMDS clock that□meets□the□min Frequency Threshold□and Amplitude TMDS□output□clock□with peak□to□peak□swing compliant□to□the□HDMI spec□and□same□frequency as□the□Input TMDS□clock frequency TMDS outputs Hi□Z TMDS461 SLLS915 JANUARY 2009 www.ti.com Figure 14. TMDS Main Link Timing Measurements Figure 15. Definition of Intra-Pair Differential Skew Figure 16. TMDS Main Link Common Mode Measurements Figure 17. Clock-Detect Timing Diagram Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

Data– Clk+ Clk– Coax TMDS461 SMA A VCC (4) RT A VCC RT TTP4TTP2TTP1 HDMI Cable (1) RX +EQ OUT RX +EQ OUT SMA SMA SMA SMA TTP3 Coax SMA Coax SMA Coax SMA Coax Coax Coax Coax Video Patterm Generator 1000-mVpp Differential RT (5) RT Jitter T est Instrument (2, 3) Jitter T est Instrument (2, 3) <2-Inch 50- Transmission Line (6) /c87 <2-Inch 50- Transmission Line (6) /c87 <2-Inch 50- Transmission Line (6) /c87 <2-Inch 50- Transmission Line (6) /c87 f − Frequency − GHz −35 −30 −25 −20 −15 −10 Amplitude − dB G001 HDMI Cable 20 m Driver 50 /c87 50 /c87 IOS 0□V□or□3.6□V TMDS461 www.ti.com SLLS915 JANUARY 2009 (1) The HDMI cable between TTP1 and TTP2 is See Figure for the loss profile of the cable. (2) All jitter is measured at a BER of (3) Residual jitter is the total jitter measured at TTP4 minus the jitter measured at TTP1. (4) AVCC 3.3 (5) R T Ω (6) inches 5.08 cm. Figure 18. TMDS Jitter Measurements Figure 19. Loss Profile of 20-m Cable Figure 20. TMDS Main Link Short Circuit Output Circuit Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

TA − Ambient Temperature − °C 490 500 510 520 530 540 550 560 570 580 590 0 10 20 30 40 50 60 70 Power − mW G002 VCC = 3.3 V, Input TMDS Data Rate = 2.25 Gbps Fastest (Default) TMDS Output Edge Rate Slowest TMDS Output Edge Rate VSadj = 4.02 KW Input TMDS Data Rate − Gbps 490 500 510 520 530 540 550 560 570 580 590 Power − mW G003 TA = 25°C, VCC = 3.3 V, VSadj = 4.02 KW Fastest (Default) TMDS Output Edge Rate Slowest TMDS Output Edge Rate Input TMDS Data Rate − Gbps 100 Peak-to-Peak Residual Data Jitter − ps G005 VSadj = 4.02 kW, TA =25°C, VCC = 3.3 V 10 m, 28 AWG HDMI Cable 20 m, 24 AWG HDMI Cable 15 m, 26 AWG HDMI Cable 3 m, 28 AWG HDMI Cable HDMI Cable Length 100 120 140 Peak-to-Peak Residual Data Jitter − ps G007 TA = 25°C VCC = 3.3 V VSadj = 4.02 kW 20 m

28 AWG

24 AWG

26 AWG

30 AWG

www.ti.com AVCC 3.3 R T Ω POWER POWER vs vs AMBIENT TEMPERATURE INPUT TMDS DATA RATE Figure 21. Figure 22. PEAK-PEAK RESIDUAL DATA JITTER PEAK-PEAK RESIDUAL DATA JITTER vs vs INPUT TMDS DATA RATE HDMI CABLE LENGTH Figure 23. Figure 24. Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

VSadj Resistance − kW 200 400 600 800 1000 1200 1400 1600 3 4 5 6 7 VOD(pp) − Differential Output Voltage − mV G008 TA = 25°C VCC = 3 V VCC = 3.6 V VCC = 3.3 V Video Format Generator TMDS461 T est□Board TMDS 461 TP1 TP2 TP3 HDMI□Cable TMDS461 www.ti.com SLLS915 JANUARY 2009 TYPICAL CHARACTERISTICS (continued) V OD(pp) vs VSadj Figure 25. Figure 26. HDMI Cable Test-Point Configuration Figure 27. Eye at TP3 (output of TMDS461) with Figure 28. Eye at TP3 (output of TMDS461) with AWG HDMI cable, 2.25 Gbps Input TMDS data Rate, AWG HDMI cable, Gbps Input TMDS data Rate, Fastest Fastest Rise and Fall Time Setting on TMDS outputs Rise and Fall Time Setting on TMDS outputs Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

www.ti.com TYPICAL CHARACTERISTICS (continued) Figure 29. Eye at TP3 (output of TMDS461) with Figure 30. Eye at TP3 (output of TMDS461) with AWG HDMI cable, Gbps Input TMDS data Rate, Fastest AWG HDMI cable, Gbps Input TMDS data Rate, Slowest Rise and Fall Time Setting on TMDS outputs Rise and Fall Time Setting on TMDS outputs Figure 31. Eye at TP3 (output of TMDS461) with AWG HDMI cable, 2.25 Gbps Input TMDS data Rate, Slowest Rise and Fall Time Setting on TMDS outputs Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

I C Function T B0344-01 TMDS461 www.ti.com SLLS915 JANUARY 2009 The TMDS461 is powered up with a single power source that is 3.3-V VCC for the TMDS circuitry for HPD, DDC, and most of the control logic. The TMDS461 incorporates clock-detect circuitry. If there is no valid TMDS clock from the connected HDMI/DVI source, the TMDS461 does not switch on the terminations on the source-side data channels. Additionally, the TMDS outputs are placed in the high-impedance state. This prevents the TMDS461 from turning on its outputs if there is no valid incoming HDMI/DVI data. A 10% precision resistor, 4.02-k Ω is recommended to control the output swing to the HDMI-compliant 800-mV to 1200-mV range V OD(pp) (1000 mV typical). The TMDS461 provides buffers on the DDC I C lines on all four input ports. This section explains the operation of the buffer. For representation, the source side of the TMDS461 is represented by RSCL/RSDA, and the sink side is represented by TSCL/TSDA. The buffers on the RSCL/RSDA and TSCL/TSDA pins are 5-V tolerant when the device is powered off and high-impedance under low supply voltage, 1.5 V or below. If the device is powered up, the driver T (see Figure is turned on or off depending on the corresponding R-side voltage level. When the R side is pulled low below 1.5 the corresponding T-side driver turns on and pulls the T side down to a low level output voltage, V OL The value of V OL and V IL on the T side or the sink side of the TMDS461 switch depends on the output-voltage select (OVS) control settings. OVS control can be changed by the slave I see Table When the OVS1 setting is selected, V OL is typically 0.7 V and V IL is typically 0.4 When the OVS2 setting is selected, V OL is typically 0.6 V and V IL is typically 0.4 When OVS3 setting (default) is selected, V OL is typically 0.5 V and V IL is typically 0.3 V OL is always higher than the driver-R input threshold, V IL on the T side or the sink side, preventing lockup of the repeater loop. The TMDS461 is targeted primarily as a switch in the HDTV market and is expected to be a companion chip to an HDMI receiver; thus, the OVS control has been provided on the sink side, so that the requirement of V IL to be less than 0.4 V can be met. The V OL value can be selected to improve or optimize noise margins between V OL and V IL of the repeater itself or V IL of some external device connected on the T side. When the R side is pulled up, above 1.5 the T-side driver turns off and the T-side pin is high-impedance. Figure 32. I C Drivers in the TMDS461 Side Is the HDMI Source Side, T Side Is the HDMI Sink Side) When the T side is pulled below 0.4 V by an external I C driver, both drivers R and T are turned on. Driver R pulls the R side to near and driver T is on, but is overridden by the external I C driver. If driver T is already on, due to a low on the R side, driver R just turns on. When the T side is released by the external I C driver, driver T is still on, so the T side is only able to rise to the V OL of driver Driver R turns off, because V OL is above its 0.4-V V IL threshold, releasing the R side. If no external I C driver is keeping the R side low, the R side rises, and driver T turns off once the R side rises above 1.5 see Figure Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

0.5V 5V + 10% Vcc/2 tPLH DDC I C Behavior Master Slave Driver□R Driver T VRdd RRup CCABLE CSOURCE CI CO Cslave VTdd RTup Cmedium RSCL RSDA 9th□Clock□Pulse□- Acknowledge□From□Slave TMDS461 SLLS915 JANUARY 2009 www.ti.com Figure 33. Waveform of Driver T Turning Off It is important that any external I C driver on the T side is able to pull the bus below 0.4 V to achieve full operation. If the T side cannot be pulled below 0.4 driver R may not recognize and transmit the low value to the R side. The typical application of the TMDS461 is as a 4:1 switch in a TV connecting up to four HDMI input sources to an HDMI receiver. The I C repeater is 5-V tolerant, and no additional circuitry is required to translate between 3.3-V and 5-V bus voltages. In the following example, the system master is running on an R-side I C-bus while the slave is connected to a T-side bus. Both buses run at 100 kHz, supporting standard-mode I C operation. Master devices can be placed on either bus. Figure 34. Typical Application Figure illustrates the waveforms seen on the R-side I C-bus when the master writes to the slave through the I C repeater circuit of the TMDS461. This looks like a normal I C transmission, and the turnon and turnoff of the acknowledge signals are slightly delayed. Figure 35. Bus-R Waveform Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

9th□Clock□Pulse□- Acknowledge□From□Slave VOL Of□Slave VOL Of□Driver T I C Pullup Resistors TMDS461 www.ti.com SLLS915 JANUARY 2009 Figure illustrates the waveforms seen on the T-side I C-bus under the same operation as in Figure On the T-side of the I C repeater, the clock and data lines would have a positive offset from ground equal to the V OL of the driver After the 8th clock pulse, the data line is pulled to the V OL of the slave device, which is very close to ground in this example. At the end of the acknowledge, the slave device releases and the bus level rises back to the V OL set by the driver until the R-side rises above VCC/2, after which it continues to be high. It is important to note that any arbitration or clock-stretching events require that the low level on the T-side bus at the input of the TMDS461 I C repeater is below 0.4 V to be recognized by the device and then transmitted to the R-side I C bus. Figure 36. Bus T Waveform The pullup resistor value is determined by two requirements: The maximum sink current of the I C buffer is mA or slightly higher for an I C driver supporting standard-mode I C operation. R up(min) V DD /Isink (1) The maximum transition time, of an I C on the bus is set by an RC time constant, where R is the pullup resistor value and C is the total load capacitance. The parameter, can be calculated from Equation by solving for the times at which certain voltage thresholds are reached. Different input threshold combinations introduce different values of Table summarizes the possible values of k under different threshold combinations. T k RC (2) V(t) V DD e t/RC (3) Table Value of k for Different Input Threshold Voltages V th th+ 0.7 V DD 0.65 V DD 0.6 V DD 0.55 V DD 0.5 V DD 0.45 V DD 0.4 V DD 0.35 V DD 0.3 V DD 0.1 V DD 1.0986 0.9445 0.8109 0.6931 0.5878 0.4925 0.4055 0.3254 0.2513 0.15 V DD 1.0415 0.8873 0.7538 0.6360 0.5306 0.4353 0.3483 0.2683 0.1942 0.2 V DD 0.9808 0.8267 0.6931 0.5754 0.4700 0.3747 0.2877 0.2076 0.1335 0.25 V DD 0.9163 0.7621 0.6286 0.5108 0.4055 0.3102 0.2231 0.1431 0.0690 0.3 V DD 0.8473 0.6931 0.5596 0.4418 0.3365 0.2412 0.1542 0.0741 From Equation R up(min) 5.5 V/3 mA 1.83 k Ω to operate the bus under a 5-V pullup voltage and provide less than mA when the I C device is driving the bus to a low state. If a higher sink current, for example mA, is allowed, R up(min) can be as low as 1.375 k Ω Given a 5-V I C device with input low and high threshold voltages at 0.3 V dd and 0.7 V dd respectively, the value of k is 0.8473 from Table Taking into account the 1.83-k Ω pullup resistor, the maximum total load capacitance is C (total-5V) 645 pF. C cable(max) should be restricted to be less than 545 pF if C source and C I can be as high as pF. Here the C I is treated as C sink the load capacitance of a sink device. Fixing the maximum transition time from Table T µ and using the k values from Table the recommended maximum total resistance of the pullup resistors on an I C bus can be calculated for different system setups. To support the maximum load capacitance specified in the HDMI spec, C cable(max) 700 pF/C source pF/C I pF, R (max) can be calculated as shown in Table Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

www.ti.com Table Pullup Resistor for Different Threshold Voltages and 800-pF Load V th th+ 0.7 V DD 0.65 V DD 0.6 V DD 0.55 V DD 0.5 V DD 0.45 V DD 0.4 V DD 0.35 V DD 0.3 V DD UNIT 0.1 V DD 1.14 1.32 1.54 1.80 2.13 2.54 3.08 3.84 4.97 k Ω 0.15 V DD 1.20 1.41 1.66 1.97 2.36 2.87 3.59 4.66 6.44 k Ω 0.2 V DD 1.27 1.51 1.80 2.17 2.66 3.34 4.35 6.02 9.36 k Ω 0.25 V DD 1.36 1.64 1.99 2.45 3.08 4.03 5.60 8.74 18.12 k Ω 0.3 V DD 1.48 1.80 2.23 2.83 3.72 5.18 8.11 16.87 k Ω Or, limiting the maximum load capacitance of each cable to 400 pF to accommodate with I C spec version 2.1. C cable(max) 400 pF/C source pF/C I pF, the maximum values of R (max) are calculated as shown in Table Table Pullup Resistor Upon Different Threshold Voltages and 500-pF Loads V th th+ 0.7 V DD 0.65 V DD 0.6 V DD 0.55 V DD 0.5 V DD 0.45 V DD 0.4 V DD 0.35 V DD 0.3 V DD UNIT 0.1 V DD 1.82 2.12 2.47 2.89 3.40 4.06 4.93 6.15 7.96 k Ω 0.15 V DD 1.92 2.25 2.65 3.14 3.77 4.59 5.74 7.46 10.30 k Ω 0.2 V DD 2.04 2.42 2.89 3.48 4.26 5.34 6.95 9.63 14.98 k Ω 0.25 V DD 2.18 2.62 3.18 3.92 4.93 6.45 8.96 13.98 28.99 k Ω 0.3 V DD 2.36 2.89 3.57 4.53 5.94 8.29 12.97 26.99 k Ω Obviously, to accommodate the 3-mA drive current specification, a narrower threshold voltage range is required to support a maximum 800-pF load capacitance for a standard-mode I C bus. When the input low- and high-level threshold voltages, V th and V th+ are 0.7 V and 1.9 respectively, which is 0.15 V DD and 0.4 V DD approximately. With V DD V from Table the maximum pullup resistor is 3.59 k Ω The allowable pullup resistor is in the range of 1.83 k Ω and 3.59 k Ω The high-speed differential TMDS inputs are the most critical paths for the TMDS461. There are several considerations to minimize discontinuities on these transmission lines between the connectors and the device: Maintain 100- Ω differential transmission line impedance into and out of the TMDS461. Keep an uninterrupted ground plane beneath the high-speed I/Os. Keep the ground-path vias to the device as close as possible to allow the shortest return current path. Keep the trace lengths of the TMDS signals between connector and device as short as possible. The TMDS461 supports a DTV with up to four HDMI inputs when used in conjunction with a signal-port HDMI receiver. The CEC is an optional feature of the HDMI interface for centralizing and simplifying user control instructions from multiple audio/video products in an interconnected system, even when all the audio/video products are from different manufacturers. This feature minimizes the number of remote controls in a system, as well as reducing the number of times buttons must be pressed. In TMDS461, the HPD[x] of non-selected port follows the 5V_PWR[x] in normal operation. In Low Power mode LP mode) or if the TMDS461 is powered off, the HPD[x] will still follow 5V_PWR[x] from source, thus if it is desired for the source to read the E-EDID memory in LP mode, a possible configuration in Figure is recommended. Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

A DTV Supporting an Active CEC Link SINK HDMI□RX DDC_SDA DDC_SCL 5 V 5 V 5 V 47k/c87 47k/c87 47k/c87 3.3V 4.7k/c87 4.7k/c87 CEC CEC CEC 4.02 k/c87/c32/c32/c49/c48/c37 E-EDID E-EDID E-EDID /c109Controller HPD1 SDA1 SCL1 HPD2 SDA2 SCL2 HPD3 SDA3 SCL3 Local_SCL Local_SDA 5V_Ind SDA_SINK SCL_SINK Y1/Z1 Y2/Z2 Y3/Z3 Y4/Z4 VSADJ GND CEC PHY 1k /c87 HPD SDA SCL CEC CLK HPD SDA SCL CEC CLK HPD SDA SCL CEC CLK HPD SDA SCL CEC CLK HPD SDA SCL CEC CLK HPD SDA SCL CEC CLK SOURCE□1 SOURCE□2 SOURCE□3 A11/B11 A12/B12 A13/B13 A14/B14 A21/B21 A22/B22 A23/B23 A24/B24 A31/B31 A32/B32 A33/B33 A34/B34 VCC (3.3□V) Y1/Z1 Y2/Z2 Y3/Z3 Y4/Z4 5V_PWR[1] 5V_PWR[2] 5V_PWR[3] 5 V 47k/c87 CEC E-EDID HPD4 SDA4 SCL4 HPD SDA SCL CEC CLK HPD SDA SCL CEC CLK SOURCE□4 A41/B41 A42/B42 A43/B43 A44/B44 5V_PWR[4] HPD_SINK CEC LOGIC I C INTERFACE NOTES TMDS461 www.ti.com SLLS915 JANUARY 2009 In Figure the CEC PHY and CEC LOGIC functions are included. The DTV can initiate and/or react to CEC signals from its remote control or other audio/video products on the same CEC bus. All sources must have their own CEC physical address to support the full functionality of the CEC link. A source reads its CEC physical address stored its E-EDID memory after receiving a logic-high from the HPD feedback. When HPD is high, the sink-assigned CEC physical address should be maintained. Otherwise, when HPD is low, the source sets CEC physical address value to (F.F.F.F). Figure 37. Four-Port HDMI-Enabled DTV With TMDS461 CEC Commands Active The I C interface is used to access the internal registers of the TMDS461. I C is a two-wire serial interface developed by Philips Semiconductor (see I C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I C-compatible devices connect to the I C bus through open-drain I/O pins, SDA and SCL. A master device, usually a micro controller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addressing information. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The TMDS461 works as a slave and supports standard-mode transfer (100 kbps). Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

S Start Condition Stop Condition P SDA SCL SDA SCL T0393-01 GENERAL I C PROTOCOL SDA SCL Data□Line Stable; Data□Valid Change□of□Data Allowed T0394-01 TMDS461 SLLS915 JANUARY 2009 www.ti.com The basic I C start and stop access cycles are shown in Figure The basic access cycle consists of the following: A start condition A slave address cycle Any number of data cycles A stop condition Figure 38. I C Start and Stop Conditions The master initiates data transfer by generating a start condition The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure All I C-compatible devices should recognize a start condition The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure by pulling the SDA line low during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a communication link with a slave has been established. The master generates further SCL cycles to either transmit data to the slave (R/W bit or receive data from the slave (R/W bit 1). In either case, the receiver must acknowledge the data sent by the transmitter So an acknowledge signal can be generated either by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary (See Figure through Figure To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure This releases the bus and stops the communication link with the addressed slave. All I C compatible devices must recognize the stop condition. Upon the receipt of a stop condition all devices know that the bus is released, and they wait for a start condition followed by a matching address. Figure 39. I C Bit Transfer Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

Data□Output by Transmitter Data□Output by□Receiver SCL From Master START Condition S 1 2 8 9 Clock□Pulse□for Acknowledgement Acknowledge Not Acknowledge T0395-01 SCL SDA MSB Slave Address Acknowledge Data Acknowledge Stop T0396-01 S Slave Address W A Data A Data A P From□Receiver From Transmitter A =□No Acknowledge□(SDA High) A = Acknowledge S□=□Start□Condition P =□Stop□Condition W□=□Write R0007-01 TMDS461 www.ti.com SLLS915 JANUARY 2009 Figure 40. I C Acknowledge Figure 41. I C Address, Data Cycle(s), and Stop During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle so that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting device after the last byte is transferred. An example of a write cycle can be found in Figure and Figure Note that the TMDS461 allows multiple write transfers to occur. See the Example Writing to the TMDS461 section for more information. During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its address. Following this initial acknowledge by the slave, the master device becomes a receiver and acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from the slave, the not-acknowledge A condition is initiated by the master by keeping the SDA signal high just before it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure and Figure See the Example Reading from the TMDS461 section for more information. Figure 42. I C Write Cycle Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

(From□Receiver) Start Condition Acknowledge (Receiver) Acknowledge (Receiver) SDA Stop Condition I C□Device Address□and Read/Write□Bit First□Data□Byte Other Data□Bytes Last□Data□Byte A6 ACKA5 A1 A0 R/W D7 D6 D1 D0 ACK D7 D6 D1 D0 ACK T0397-01 S Slave Address W A Data A Data A P Receiver Transmitter A =□No Acknowledge□(SDA High) A = Acknowledge S□=□Start□Condition P =□Stop□Condition W□=□Write R□=□Read R0008-01 Start Condition SDA Acknowledge (From□Receiver) Acknowledge (From Transmitter) Not Acknowledge (Transmitter) Stop Condition Last□Data□ByteI C□Device Address□and Read/Write□Bit First□Data Byte Other Data□Bytes A6 A0 ACKR/W D7 D0 ACK D7 D6 D1 D0 ACK T0398-01 Slave Address EXAMPLE WRITING TO THE TMDS461 TMDS461 SLLS915 JANUARY 2009 www.ti.com Figure 43. Multiple-Byte Write Transfer Figure 44. I C Read Cycle Figure 45. Multiple-Byte Read Transfer Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. These resistors should comply with the I C specification that ranges from k Ω to k Ω When the bus is free, both lines are high. The address byte is the first byte received following the START condition from the master device. The 7-bit address is factory preset to 0101100 or 0101101 based on the status of the Local_Addr pin Table lists the calls to which the TMDS461 responds. Table TMDS461 Slave Address FIXED ADDRESS READ/WRITE BIT Bit Bit Bit Bit Bit Bit Bit Bit (R/W) (MSB) (Local_Addr pin =LOW) (Local_Addr pin HIGH) The proper way to write to the TMDS461 is illustrated as follows: An I C master initiates a write operation to the TMDS461 by generating a start condition (S) followed by the TMDS461 I C address (as shown following, in MSB-first bit order, followed by a to indicate a write cycle. After receiving an acknowledge from the TMDS461, the master presents the subaddress (sink port) to be written, consisting of one byte of data, MSB-first. The TMDS461 acknowledges the byte after completion of the transfer. Finally, the master presents the data to be written to the register (sink port), and the TMDS461 acknowledges the byte. The master can continue presenting data to be written after TMDS461 acknowledges the previous byte (steps 7). After the last byte to be written has been acknowledged by TMDS461, the I C master then terminates the write operation by generating a stop condition (P). Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

www.ti.com SLLS915 JANUARY 2009 Step I C start (master) S Step I C general address (master) (Local_Addr pin =LOW) (Local_Addr pin HIGH) Step I C acknowledge (slave) A Step I C write sink logic address (master) Addr Addr Addr Addr Step I C acknowledge (slave) A Step I C write data (master) Data Data Data Data Data Data Data Data Data is the register address or register data to be written Step I C acknowledge (slave) A Step I C stop (master) P An example of the proper bit control for selecting port is: Step 0000 0011 Step 00101000 The read operation consists of two phases. The first phase is the address phase. In this phase, an I C master initiates a write operation to the TMDS461 by generating a start condition (S) followed by the TMDS461 I C address, in MSB-first bit order, followed by a to indicate a write cycle. After receiving acknowledges from the TMDS461, the master presents the subaddress of the register to be read. After the cycle is acknowledged (A), the master may optionally terminate the cycle by generating a stop condition (P). The second phase is the data phase. In this phase, an I C master initiates a read operation to the TMDS461 by generating a start condition followed by the TMDS461 I C address (as shown following for a read operation), in MSB first bit order, followed by a to indicate a read cycle. After an acknowledge from the TMDS461, the I C master receives one byte of data from the TMDS461. The master can continue receiving data byes by issuing an acknowledge after each byte read (steps 10, 11). After the last data byte has been transferred from the TMDS461 to the master, the master generates a not-acknowledge followed by a stop. Step I C start (master) S Step I C general address (master) (Local_Addr pin =LOW) (Local_Addr pin HIGH) Step I C acknowledge (slave) A Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

www.ti.com Step I C write sink logic address (master) Addr Addr Addr Addr Where Addr is determined by the values shown in Table Step I C acknowledge (slave) A Step I C stop (master) P Step is optional. Step I C start (master) S Step I C general address (master) (Local_Addr pin =LOW) (Local_Addr pin HIGH) Step I C acknowledge (slave) A Step I C read data (slave) Data Data Data Data Data Data Data Data Where data is determined by the logic values contained in the internal registers. Step 11A I C acknowledge (master) A If Step 11A is executed, go to step 10. If Step 11B is executed, go to Step 12. Step 11B I C not acknowledge (master) A Step I C stop (master) P Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

www.ti.com SLLS915 JANUARY 2009 Table I C Register 0x01 Lookup Table (1) BIT VALUE STATE DEFAULT X Reserved 6:5 Bit Bit Port Select Status Indicator X Indicates Port is selected as the active port, all other ports are disabled Indicates Port is selected as the active port, all other ports are disabled Indicates Port is selected as the active port, all other ports are disabled Indicates Port is selected as the active port, all other ports are disabled Valid TMDS A valid TMDS clock signal is detected on the selected input port. If clock-detect circuit is Clock Detected disabled in I C register 0x03, then bit of I C register 0x01 will always be No Valid TMDS X The selected port does not have a valid TMDS clock signal Clock Detected Port 5V_PWR is detected as HIGH on Port 5V_PWR Detected Port X 5V_PWR is detected as LOW on Port 5V_PWR not Detected Port 5V_PWR is detected as HIGH on Port 5V_PWR Detected Port X 5V_PWR is detected as LOW on Port 5V_PWR not Detected Port 5V_PWR is detected as HIGH on Port 5V_PWR Detected Port X 5V_PWR is detected as LOW on Port 5V_PWR not Detected Port 5V_PWR is detected as HIGH on Port 5V_PWR Detected Port X 5V_PWR is detected as LOW on Port 5V_PWR not Detected (1) I C register 0x01 is Read Only. This register is supposed to be read by the sink micro-controller on IRQ interrupt (IRQ goes high). The register values get updated in real time. IRQ will be reset (IRQ goes low) once the sink micro controller has completed reading this register. Table I C Register 0x02 Lookup Table (1) BIT VALUE STATE DEFAULT 7:6 Bit Bit Power Mode Device enters low power mode LP mode) Device enters low power mode LP mode) Device is in Standby mode X Device is in normal power mode Automatic Port Port Selection will be automatic based on state of 5V_PWR[1:4] as indicated by I C Select On register 0x01:bits[3:0] and priority bit which is I C register 0x02:bits [4:3] Automatic Port X Port Selection based on I C register 0x03:bits [6:5] Select Off (1) During switching of modes between Auto-select on/off, it is required that the sink micro controller reads the register 0x01 to determine which port is selected. Register 0x02 is Read/Write. Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

www.ti.com Table I C Register 0x02 Lookup Table (continued) BIT VALUE STATE DEFAULT 4:3 Bit Bit Priority Select X Port is the priority port Port is the priority port Port is the priority port Port is the priority port Reserved X Reserved (Do not write a to this bit) 1:0 Bit Bit Output Edge Rate Control Fastest TMDS output rise and fall time setting 120 ps approximately (slowest rise and fall time setting) Fastest TMDS output rise and fall time setting 100 ps approximately Fastest TMDS output rise and fall time setting ps approximately X Fastest TMDS output rise and fall time setting Table I C Register 0x03 Lookup Table (1) BIT VALUE STATE DEFAULT X Clock Detect Circuit Enabled. It is recommended that TMDS461 is used in this default mode in Detect the normal operation, where clock-detect circuit is enabled. The terminations on the TMDS input Enabled data lines are connected only when valid TMDS clock is detected on the selected port. Clock Clock Detect Circuit Disabled. For HDMI compliance testing (TMDS Termination Voltage Test), Detect clock-detect feature should be disabled. In this mode the terminations on the TMDS input data Disabled lines are always connected when the port is selected. 6:5 Bit Bit Port select I C mode X Port is selected as the active port, all other ports disabled. Port is selected as the active port, all other ports disabled. Port is selected as the active port, all other ports disabled. Port is selected as the active port, all other ports disabled. 4:3 Bit Bit OVS Control DDC sink side VOL and VIL offset range V IL2 (max) 0.4V, V OL2 (max) 0.6V X DDC sink side VOL and VIL offset range V IL3 (max) 0.3V, V OL3 (max) 0.5V DDC sink side VOL and VIL offset range V IL1 (max) 0.4V, V OL1 (max) 0.7V 2:0 RSVD X Reserved (1) Register 0x03 is Read/Write. Table 10. I C Register 0x04 Lookup Table (1) BIT VALUE STATE DEFAULT 7:0 RSVD X Reserved. Read-only, value is indeterministic. (1) Register x04 is TI internal usage only. Table 11. I C Register 0x05 Lookup Table (1) BIT VALUE STATE DEFAULT 7:0 RSVD X Reserved. Read-only, value is indeterministic. (1) Register x05 is TI internal usage only. Table 12. I C Register 0x06 Lookup Table (1) BIT VALUE STATE DEFAULT 7:0 RSVD X Reserved. Read-only, value is indeterministic. (1) Register x06 is TI internal usage only. Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated Product Folder Link(s) TMDS461

www.ti.com SLLS915 JANUARY 2009 Table 13. I C Register 0x07 Lookup Table (1) BIT VALUE STATE DEFAULT 7:6 RSVD X Reserved Port Select The selected port has changed since reading 0x01 Changed Port Select X The selected port has not changed since reading 0x01 Unchanged Clock-Detect The selected port s clock detect status has changed since reading 0x01 Changed Clock-Detect X The selected port s clock detect status has not changed since reading 0x01 Unchanged Port 5V_PWR on Port has changed since reading 0x01 5V_PWR Changed Port X 5V_PWR on Port has not changed since reading 0x01 5V_PWR Unchanged Port 5V_PWR on Port has changed since reading 0x01 5V_PWR Changed Port X 5V_PWR on Port has not changed since reading 0x01 5V_PWR Unchanged Port 5V_PWR on Port has changed since reading 0x01 5V_PWR Changed Port X 5V_PWR on Port has not changed since reading 0x01 5V_PWR Unchanged Port 5V_PWR on Port has changed since reading 0x01 5V_PWR Changed Port X 5V_PWR on Port has not changed since reading 0x01 5V_PWR Unchanged (1) I C register 0x07 is Read Only. The register values get latched whenever a system-level interrupt occurs (IRQ goes high); and, the register values are cleared when the IRQ gets cleared upon reading register 0x01. This I C register can be used for debug purposes, if needed. If register 0x01 is not read, then the latched values in register x07, will keep on updating based on any system level event. Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) TMDS461

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMDS461PZTR TQFP PZT 100 1000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

MTQF012B – OCTOBER 1994 – REVISED DECEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PZT (S-PQFP-G100) PLASTIC QUAD FLATPACK 4073179/B 11/96 0,13 NOM 0,75 0,45 0,25 0,05 MIN Seating Plane Gage Plane 0,27 0,17 100 SQ SQ 15,80 16,20 14,20 13,80 12,00 TYP 1,20 MAX 1,05 0,95 0,50 M0,08 0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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