TMDS341APFC

TMDS341A_07 TI | Alldatasheet

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1.3a 3.3-V Supply Operation Supports 2.25 Gbps Signaling Rate for 480i/p, 80-Pin TQFP Package 720i/p, and 1080i/p Resolutions up to 12-Bit ROHS Compatible and 260 C Reflow Rated Color Depth Each Port Supports HDMI or DVI Inputs Switching From Three Digital-Video (DVI) or Isolated Digital Display Control (DDC) Bus for Digital-Audio Visual (HDMI) Sources Unused Ports Digital TV 5-V Tolerance to all DDC and HPD_SINK Digital Projector Inputs Audio Video Receiver Integrated Receiver Termination Inter-Pair Output Skew 100 ps Intra-Pair Skew ps 8-dB Receiver Equalization to Compensate for 5-m DVI Cable Losses High Impedance Outputs When Disabled TMDS Inputs HBM ESD Protection The TMDS341A is a 3-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug detector, and an I C interface are supported on each port. Each TMDS channel allows signaling rates up to 2.25 Gbps. The active source is selected by configuring source selectors, S1, S2, and S3. The selected TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I C interface of the selected input port is linked to the I C interface of the output port, and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the unused ports, the I C interfaces are isolated, and the HPD pins are kept low. Termination resistors (50- Ω pulled up to V CC are integrated at each receiver input pin. External terminations are not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the differential output voltage to be compliant with the TMDS standard. When the output is connected to a standard TMDS termination and OE is high, the output is high impedance. The TMDS341A provides fixed 8-dB input equalization and selectable 3-dB output de-emphasis to optimize system performance through 5-meter or longer DVI compliant cables. The device is characterized for operation from C to Typical Application Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2006 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com PRE VSADJ HPD_SINK SCL_SINK SDA_SINK SDA3 SCL3 SDA2 SCL2 SDA1 SCL1 HPD3 HPD2 HPD1 B31 A31 B32 A32 B33 A33 B34 A34 B21 A21 B22 A22 B23 A23 B24 A24 Rx w/ EQ Rx w/ EQ Rx w/ EQ Rx w/ EQ Rx w/ EQ Rx w/ EQ Rx w/ EQ Rx w/ EQ Control Logic 3−to−1 MUX TMDS Drive TMDS Drive TMDS Drive TMDS Drive Rx w/ EQ Rx w/ EQ Rx w/ EQ Rx w/ EQ VCC (3.3 V) VCC VCC VCC VCC VCC VCC VCC (3.3 V) VCC (3.3 V) A11 B11 A12 B12 A13 B13 A14 B14 R INT R INT R INT R INT R INT R INT R INT RINT RINT RINT RINT R INT OE TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM Submit Documentation Feedback

www.ti.com HPD2 SDA2 SCL2 GND GND B21 A21 B22 A22 GND B23 A23 V B24 A24 GND HPD1 NC O E HP D3 SDA 3 S CL3 GND B 31 A 31 B 32 A 32 GND B 33 A 33 B 34 A 34 GND N C HPD_SINK SDA_SINK SCL_SINK GND GND GND GND N C P R E V G N D A 1 4 B 1 4 A 1 3 B1 3 A 1 2 B1 2 A1 1 B1 1 G N D S C L 1 S D A 1 CC VCC VCC VCC V CC V CC C C V C C VC C V C C VSADJ 2 3 4 5 6 7 8 9 10 11 12 131 14 15 16 17 18 19 20 59 58 57 56 5560 54 52 51 50 53 49 48 47 46 45 44 43 42 41 V C C V C C N C G N D TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 PFC PACKAGE (TOP VIEW) Submit Documentation Feedback

www.ti.com TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 TERMINAL FUNCTIONS TERMINAL I/O NO. A11, A12, A13, A14 12, I Port TMDS positive inputs A21, A22, A23, A24 68, 71, 74, I Port TMDS positive inputs A31, A32, A33, A34 49, 52, 55, I Port TMDS positive inputs B11, B12, B13, B14 11, I Port TMDS negative inputs B21, B22, B23, B24 67, 70, 73, I Port TMDS negative inputs B31, B32, B33, B34 48, 51, 54, I Port TMDS negative inputs 10, 24, 30, GND 36, 37, 47, 53, Ground 59, 65, 66, 72, HPD1 O Port hot plug detector output HPD2 O Port hot plug detector output HPD3 O Port hot plug detector output Sink side hot plug detector input HPD_SINK I High: 5-V power signal asserted from source to sink and EDID is ready Low: No 5-V power signal asserted from source to sink, or EDID is not ready NC 20, 41,60 No connect OE I Output enable, active low Output de-emphasis adjustment PRE I High: dB Low: dB SCL1 I/O Port DDC bus clock line SCL2 I/O Port DDC bus clock line SCL3 I/O Port DDC bus clock line SCL_SINK I/O Sink side DDC bus clock line SDA1 I/O Port DDC bus data line SDA2 I/O Port DDC bus data line SDA3 I/O Port DDC bus data line SDA_SINK I/O Sink side DDC bus data line S1, S2, 21, 22, I Source selector input 13, 27, 33, V CC 43, 50, 61, 69, Power supply 75, VSADJ I TMDS compliant voltage swing control Y1, Y2, Y3, 34, 31, 28, O TMDS positive outputs Z1, Z2, Z3, 35, 32, 29, O TMDS negative outputs Submit Documentation Feedback

www.ti.com TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 Table Source Selection Lookup (1) CONTROL PINS I/O SELECTED HOT PLUG DETECT STATUS SCL_SINK Y/Z HPD1 HPD2 HPD3 SDA_SINK SCL1 H x x A1/B1 HPD_SINK L L SDA1 SCL2 L H x A2/B2 L HPD_SINK L SDA2 SCL3 L L H A3/B3 L L HPD_SINK SDA3 L L L None (Z) None (Z) L L L (1) Logic high; Logic low; Don't care; High impedance Submit Documentation Feedback

www.ti.com EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS Z TMDS Output Stage Y HPD output stageControl Input Stage OE HPD_SINK PRE S1, S2, S3 Vcc HPD1 HPD2 HPD3 Vcc TMDS Input Stage 25 Ω A B Vcc 50Ω 50Ω 25 Ω 10 mA 400Ω Vcc SCL/SCA Source SCL/SCA Sink DDC pass gate 8V 8V TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 ORDERING INFORMATION (1) PART NUMBER PART MARKING PACKAGE TMDS341APFC TMDS341A 80-PIN TQFP TMDS341APFCR TMDS341A 80-PIN TQFP Tape/Reel (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Submit Documentation Feedback

www.ti.com ABSOLUTE MAXIMUM RATINGS DISSIPATION RATINGS RECOMMENDED OPERATING CONDITIONS TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range, V CC (2) 0.5 V to V Anm (3) Bnm 2.5 V to V Voltage range Ym, Zm, VSADJ, PRE, Sn, OE HPDn 0.5V to V SCLn, SCL_SINK, SDAn, SDA_SINK, HPD_SINK 0.5 V to V Anm, Bnm kV Human body model (4) All pins kV Electrostatic discharge Charged-device model (5) (all pins) 1000 V Machine model (6) (all pins) 250 V See Dissipation Rating Continuous power dissipation Table (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) n m (4) Tested in accordance with JEDEC Standard 22, Test Method A114-B (5) Tested in accordance with JEDEC Standard 22, Test Method C101-A (6) Tested in accordance with JEDEC Standard 22, Test Method A115-A DERATING FACTOR (1) T A C PACKAGE T A C ABOVE T A C POWER RATING 80-TQFP 1342 mW 13.42 mW/ C 738 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. MIN NOM MAX UNIT V CC Supply voltage 3.3 3.6 V T A Operating free-air temperature C TMDS DIFFERENTIAL PINS (A/B) V ID Receiver peak-to-peak differential input voltage 150 1560 mVp-p V IC Input common mode voltage V CC 0.4 V CC +0.01 V R VSADJ Resistor for TMDS compliant voltage swing range 4.6 4.64 4.68 k Ω AV CC TMDS output termination voltage, see Figure 3.3 3.6 V R T Termination resistance, see Figure Ω Signaling rate 2.25 Gbps CONTROL PINS (PRE; OE V IH LVTTL High-level input voltage V CC V V IL LVTTL Low-level input voltage GND 0.8 V DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK) V I(DDC) Input voltage GND 5.5 V STATUS PINS (HPD_SINK) V IH LVTTL High-level input voltage 5.3 V V IL LVTTL Low-level input voltage GND 0.8 V Submit Documentation Feedback

www.ti.com ELECTRICAL CHARACTERISTICS TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT V IH V CC V IL V CC 0.4 R VSADJ 4.64 k Ω R T Ω AV CC 3.3 V I CC Supply current 190 230 mA Am/Bm 1.65 Gbps HDMI data pattern, m A1/B1 165 MHz clock V IH V CC V IL V CC 0.4 R VSADJ 4.64 k Ω R T Ω AV CC 3.3 V P D Power dissipation 394 657 mW Am/Bm 1.65 Gbps HDMI data pattern, m A1/B1 165 MHz clock TMDS DIFFERENTIAL PINS (A/B; Y/Z) V OH Single-ended high-level output voltage AV CC AV CC +10 mV V OL Single-ended low-level output voltage AV CC 600 AV CC 400 mV V swing Single-ended output swing voltage 400 600 mV See Figure AV CC 3.3 V OD(O) Overshoot of output differential voltage 15% V swing R T Ω PRE V V OD(U) Undershoot of output differential voltage 12% 25% V swing Change in steady-state common-mode Δ V OC(SS) 0.5 mV output voltage between logic states V V CC 1.5 I (O)OFF Single-ended standby output current µ A AV CC 3.3 R T Ω (OS) Short circuit output current See Figure mA Steady state output differential voltage with See Figure PRE V CC V ODE(SS) 560 840 mVp-p de-emphasis Am/Bm 250 Mbps HDMI data pattern, m A1/B1 MHz clock V ODE(pp) Peak-to-peak output differential voltage 800 1200 mVp-p Single-ended input voltage under high V I(open) I I µ A V CC V CC +10 mV impedance input or open input R INT Input termination resistance V IN 2.9 V Ω DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK) lkg Input leakage current V I 0.1 V CC to 0.9 V CC to isolated DDC ports 0.1 µ A C IO Input/output capacitance V I V 7.5 pF R ON Switch resistance I O mA, V O 0.4 V Ω V PASS Switch output voltage V I 3.3 I O 100 µ A 1.5 (2) 2.0 2.5 (3) V STATUS PINS (HPD) V OH(TTL) TTL High-level output voltage I OH mA 2.4 V V OL(TTL) TTL Low-level output voltage I OL mA 0.4 V CONTROL PINS (PRE, OE IH High-level digital input current V IH V or V CC 0.1 µ A IL Low-level digital input current V IL GND or 0.8 V 0.1 µ A STATUS PINS (HPD_SINK) V IH 5.3 V 100 IH High-level digital input current µ A V IH V or V CC 0.1 IL Low-level digital input current V IL GND or 0.8 V 0.1 µ A (1) All typical values are at C and with a 3.3-V supply. (2) The value is tested in full temperature range at 3.0 (3) The value is tested in full temperature range at 3.6 Submit Documentation Feedback

www.ti.com SWITCHING CHARACTERISTICS TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT TMDS DIFFERENTIAL PINS (Y/Z) t PLH Propagation delay time, low-to-high-level output 250 800 ps t PHL Propagation delay time, high-to-low-level output 250 800 ps t r Differential output signal rise time (20% 80%) 240 ps t f Differential output signal fall time (20% 80%) 240 ps See Figure AV CC 3.3 R T Ω PRE V t sk(p) Pulse skew (|t PHL t PLH ps t sk(D) Intra-pair differential skew, see Figure ps t sk(o) Inter-pair channel-to-channel output skew (2) 100 ps t sk(pp) Part-to-part skew (3) 200 ps t jit(pp) Peak-to-peak output jitter from Y/Z(1) residual jitter See Figure PRE V ps Am/Bm 1.65 Gbps HDMI data pattern, m t jit(pp) Peak-to-peak output jitter from Y/Z(2:4) residual jitter ps A1/B1 165 MHz clock t jit(pp) Peak-to-peak output jitter from Y/Z(1) residual jitter See Figure PRE V ps Am/Bm 2.25 Gbps HDMI data pattern, m t jit(pp) Peak-to-peak output jitter from Y/Z(2:4) residual jitter ps A1/B1 225 MHz clock See Figure PRE V CC Am/Bm 250 Mbps HDMI data pattern, t PRE De-emphasis duration 240 (4) ps m A1/B1 MHz clock t SX Select to switch output ns t en Enable time See Figure ns t dis Disable time ns DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK) Propagation delay from SCLn to SCL_SINK or SDAn to t pd(DDC) See Figure C L pF 0.4 2.5 ns SDA_SINK or SDA_SINK to SDAn CONTROL AND STATUS PINS (S, HPD_SINK, HPD) t pd(HPD) Propagation delay (from HPD_SINK to the active port of HPD) 6.0 ns See Figure C L pF t sx(HPD) Switch time (from port select to the latest valid status of HPD) 6.5 ns (1) All typical values are at C and with a 3.3-V supply. (2) t sk(o) is the magnitude of the difference in propagation delay times between any specified terminals of channel to of a device when inputs are tied together. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of channel to of two devices, or between channel of two devices, when both devices operate with the same source, the same supply voltages, at the same temperature, and have identical packages and test circuits. (4) The typical value is ensured by simulation. Submit Documentation Feedback

www.ti.com PARAMETER MEASUREMENT INFORMATION TMDS Driver AVcc R T R T TMDS Receiver ZO = RT ZO = RT VOC(SS) V OC tPHL tPLH 100% 0V Differential 80% 20% tf tr VID 0.4 V 0 V −0.4 V V OD(O) VOD(U) VOD(pp) V IDVID(pp) Vcc R INT R INT TMDS Receiver TMDS Driver Y Z A B AVcc R T R TVID VB V A V Y VZ C L 0.5 pF VA VB Vcc Vcc−0.4 V VY V Zswing = −VV ID= −V V BA /C0110 DC Coupled Vcc+0.2 V Vcc−0.2 V AC Coupled TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 Figure Termination for TMDS Output Driver NOTE: All input pulses are supplied by a generator having the following characteristics: t r or t f 100 ps, 100 MHz from Agilent 81250. C L includes instrumentation and fixture capacitance within 0.06 m of the D.U.T. Measurement equipment provides a bandwidth of GHz minimum. Figure Timing Test Circuit and Definitions Submit Documentation Feedback

www.ti.com TMDS Driver 0 V or 3.6 V 50 /C0087 50 /C0087 IOS VOD(pp) VODE(SS) 20% 80% tPRE 1 bit 1 to N bit 50% VOLtsk(D) VY VZ VOH TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure Short Circuit Output Current Test Circuit Figure De-Emphasis Output Voltage Waveforms and Duration Measurement Definitions Figure Definition of Intra-Pair Differential Skew Submit Documentation Feedback

www.ti.com Input−1 Kept High Input−2/Input−3 Kept Low A B A B S1 Clocking S2 or S3 Kept High Y Z Output OE tsx tdis ten tsx Hi−Z75 mV −75 mV 75 mV −75 mV 3.3 V 0 V VCC 0 V VCC 3.3 V tpd(HPD) tpd(HPD) tsx(HPD) tpd(DDC) tpd(DDC) 0 V VCC VCC VCC 0 V 2.4 V 0.4 V VCC VCC 2HPD_SINK HPD1 HPD2 HPD3 SDA_SINK SDA1 SDA2 SDA3 TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure TMDS Outputs Control Timing Definitions Figure HPD Timing Definitions Submit Documentation Feedback

www.ti.com Data + Data − Clk+ Clk− Video Patterm Generator 1000 mVpp Differential Coax Coax Coax Coax Coax Coax Coax Coax <2” 50Ω Transmission Line 5m 28AWG HDMI Cable TMDS341A RX EQ M U X OUT 0dB RX EQ M U X OUT 0dB <2” 50Ω Transmission Line <2” 50Ω Transmission Line <2” 50Ω Transmission Line SMA SMA SMA SMA SMA SMA SMA SMA AVcc R T R T AVcc R T R T Jitter Test Instrument Jitter Test Instrument TP3TP2TP1 TMDS341 input equalization gain vs. 5m DVI/HDMI cable response −18 −16 −14 −12 −10 0 200 400 600 800 1000 1200 1400 1600 1800 2000 f − Frequency − MHz Gain − dB Inversed TMDS341 EQ Gain

28 AWG 5m HDMI Cable

28 AWG 5m DVI Cable

(continued) All jitters are measured in BER of -12 The residual jitter reflects the total jitter measured at the TMDS341A output, TP3, subtract the total jitter from the signal generator, TP1 Figure Jitter Test Circuit Figure shows the frequency loss response from a 28AWG HDMI cable and a 28AWG DVI cable. The TMDS341A built-in passive input equalizer compensates for ISI. For an 8-dB loss HDMI cable, the TMDS341A typically reduces jitter by ps from the device input to the device output. Figure S-Parameter Plots of 5-m DVI and HDMI Cables Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS 185 187 189 191 193 195 0 10 20 30 40 50 60 70 I -□Supply□Current□-□mACC T -□Free-Air□Temperature□-□CA V = AV =□3.3□V, Input□(2:4)□2.2 HDMI□Data□Pattern Input□(1)□165□MHz CC CC ID(PP) VSADJ /c87 5□Gbps Clock 160 170 180 190 200 210 220 230 25 45 65 75 85 105 145 165 f□-□Frequency□-□MHz I -□Supply□Current□-□mACC PRE□= =□Low Input□(2:4)□HDMI□Data□Pattern,□250□Mbps□-□2.25□Gbps CC CC ID(PP) p-p VSADJ A /c87 OE 200 250 450 650 750 850 1050 1250 1450 1650 Data□Rate□-□Mbps Residual□Deterministic□Jitter□-□%□Unit□Interval 1□m□HDMI□Cable 3□m□HDMI□Cable 5□m□HDMI□Cable PRE□= =□Low,□Source□jitter□=□180□ps CC CC ID(PP) VSADJ A /c87 OE 20 25 45 65 75 85 105 125 145 165 Clock□Frequency□-□MHz Residual□Peak-Peak□Jitter□-□%□Unit□Interval 5□m□HDMI□Cable 1□m□HDMI□Cable 3□m□HDMI□Cable PRE□= =□Low,□Source□jitter□=□150□ps CC CC ID(PP) p-p VSADJ A /c87 OE TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 SUPPLY CURRENT SUPPLY CURRENT vs vs FREQUENCY FREE-AIR TEMPERATURE Figure 10. Figure 11. RESIDUAL DETERMINISTIC JITTER RESIDUAL PEAK-TO-PEAK JITTER vs vs DATA RATE CLOCK FREQUENCY Figure 12. Figure 13. Submit Documentation Feedback

www.ti.com -11 -10 Peak-to-Peak□Differential□Input□Voltage□-□mVp-p Residual□Peak-Peak□Jitter□-□%□Unit□Interval 74.25□MHz 148.5□MHz 150 350 550 750 950 1150 1550 1350 27□MHz R =□4.64□K PRE□= =□Low CC CC VSADJ A /c87/c44 OE 150 350 550 750 950 1150 1350 1550 Peak-to-Peak□Differential□Input□Voltage□-□mVp-p Residual□Deterministic□Jitter□-□%□Unit□Interval 1485□Mbps 742.5□Mbps 270□Mbps R =□4.64□K PRE□= =□Low CC CC VSADJ A /c87/c44 OE Residual□Deterministic□Jitter□-□%□Unit□Interval1 5 7 11 15 19 FR4□PCB□Trace□-□Inch 270□Mbps 742.5□Mbps 1485□Mbps PRE□=□High, =□Low, 5-m□28 AWG□HDMI□Cable CC CC ID(PP) VSADJ A /c87 OE Residual□Peak-Peak□Jitter□-□%□Unit□Interval 0.5 2.0 2.5 3.5 5 7 11 15 19 FR4□PCB□Trace□-□Inch 27□MHz 74.25□MHz 148.5□MHz PRE□=□High, =□Low,□5-m□28 AWG□HDMI□Cable CC CC ID(PP) VSADJ A /c87 OE TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 TYPICAL CHARACTERISTICS (continued) RESIDUAL DETERMINISTIC JITTER RESIDUAL PEAK-TO-PEAK JITTER vs vs DIFFERENTIAL INPUT VOLTAGE DIFFERENTIAL INPUT VOLTAGE Figure 14. Figure 15. RESIDUAL DETERMINISTIC JITTER RESIDUAL PEAK-TO-PEAK JITTER vs vs FR4 PCB TRACE (at 3dB Pre-Emphasis) FR4 PCB TRACE (at 3dB Pre-Emphasis) Figure 16. Figure 17. Submit Documentation Feedback

www.ti.com 750 950 1150 1485 1650 1850 2250 Clock Frequency - MHz Residual□Peak-Peak□Jitter□-□%□Unit□Interval 3□m□30 AWG 5□m□28 AWG Channels□2,□3,□4, Tp1□V =□1000□mV , 720p/1080i□8-Bit□=□742.5□Mbps, 720p/1080i□12-Bit□=□1113.75□Mbps, 1080p□8-Bit□=□1485□Mbps, 1080p□12-Bit□=□2227.5□Mbps CC CC ID(PP) p-p A R =□4.64□K PRE□= =□Low, VSADJ /c87/c44 OE 75 95 115 148.5 165 185 225 Clock Frequency - MHz Residual□Peak-Peak□Jitter□□-□%□Unit□Interval 5□m□28 AWG 3□m□30 AWG Channel□1, Tp1□V =□1000□mV CC CC ID(PP) p-p A R =□4.64□K PRE□= =□Low, VSADJ /c87/c44 OE TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 TYPICAL CHARACTERISTICS (continued) RESIDUAL PEAK-TO-PEAK JITTER RESIDUAL PEAK-TO-PEAK JITTER (Data Channels) (Clock Channel) vs vs CLOCK FREQUENCY CLOCK FREQUENCY Figure 18. Figure 19. Submit Documentation Feedback

www.ti.com HDMI Cables Running at 165-MHz Pixel Clock Video Format Generator TMDS341ATest□Board TMDS 341A TP1 TP2 TP3

28 AWG□HDMI□Cable

(continued) Figure 20. 1-m and 5-m HDMI Cable Test Point Configuration Figure 21. Clock at TP1 Figure 22. Clock at TP2 Figure 23. Clock at TP3 Figure 24. Data at TP1 Figure 25. Data at TP2 Figure 26. Data at TP3 Submit Documentation Feedback

www.ti.com 5-m Cable Length Eye Patterns TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 TYPICAL CHARACTERISTICS (continued) Figure 27. Clock at TP1 Figure 28. Clock at TP2 Figure 29. Clock at TP3 Figure 30. Data at TP1 Figure 31. Data at TP2 Figure 32. Data at TP3 (DC-Coupled Input) Figure 33. Data at TP3 (AC-Coupled Input) Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION Supply Voltage TMDS Inputs TMDS Input Fail-Safe VCC R INTR INT TMDS Receiver TMDS Driver R T R T Y Z A B AV CC TMDS341A TMDS Outputs TMDS341A VCC GND TMDS Driver AV CC ZO = RT ZO = RT R TR T TMDS Receiver TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 All V CC pins can be tied to a single 3.3-V power source. A 0.01- µ F capacitor is connected from each V CC pin directly to ground to filter supply noise. Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Each input channel contains an 8-dB equalization circuit to compensate for cable losses. The voltage at the TMDS input pins must be limited per the absolute maximum ratings. An unused input should not be connected to ground as this would result in excessive current flow damaging the device. TMDS input pins do not incorporate fail-safe circuits. An unused input channel can be externally biased to prevent output oscillation. One pin can be left open with the other grounded through a 1-k Ω resistor as shown in Figure Figure 34. TMDS Input Fail-Safe Recommendation A precision resister, 4.64-k Ω connected from VSADJ to ground is recommended to allow the differential output swing to comply with TMDS signal levels. The differential output driver provides a typical 10-mA current sink capability, which provides a typical 500-mV voltage drop across a 50- Ω termination resistor. Figure 35. TMDS Driver and Termination Circuit As shown in Figure if V CC (TMDS341A supply) and AV CC (sink termination supply) are powered, the TMDS output signals are high impedance when OE is high. Normal operation is with both supplies active. Also shown in Figure if V CC is on and AV CC is off, the TMDS outputs source a typical 5-mA current through each termination resistor to ground. The terminations consume a total of mW of power independent of the OE logical selection. When AV CC is powered on, normal operation OE controls output impedance) is resumed. Submit Documentation Feedback

www.ti.com HPD Pins DDC Channels Configuring the TMDS341A as a 2:1 Switch Layout Considerations Connecting Cables Longer Than m TMDS Signal Path TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 APPLICATION INFORMATION (continued) When the power source of the device, V CC is off and the power source to termination, AV CC is on, the output leakage current o(off) specification ensures leakage current is limited to 10- µ A or less. The PRE pin provides 3-dB de-emphasis, allowing output signal pre-conditioning to offset interconnect losses from the TMDS341A outputs to a TMDS receiver. PRE is recommended to be low to the circuit design of a stand-alone switch box. The input of the HPD_SINK is 5-V tolerant, allowing direct connection to 5-V signals. The HPD pin output resistance is 35- Ω typically. A 1-k Ω 10% resistor is recommended to be connected from an HPD pin at the TMDS341A to the HPD pin of the HDMI connector. The DDC channels are designed with a bi-directional pass gate, providing 5-V signal tolerance. The 5-V tolerance allows direct connection to a standard I C bus. The level shifter between 3.3 V and V I C interface can be eliminated. The TMDS341A can be configured as a 2-to-1 switch by pulling the source selector pin (S1, S2, S3) of the non-active port low and leaving the corresponding TMDS inputs, SCL, SDA, and HPD pins open. The high-speed TMDS inputs are the most critical paths for the TMDS341A. There are several considerations to minimize discontinuities on these transmission lines between the connectors and the device: Maintain 100- Ω differential transmission line impedance into and out of the TMDS341A Keep an uninterrupted ground plane beneath the high-speed I/Os Keep the ground-path vias to the device as close as possible to allow the shortest return current path Layout of the TMDS differential inputs should be with the shortest stubs from the connectors When using the TMDS341A with cables longer than the impact to the TMDS signal path as well as the DDC signal path must be considered. The TMDS341A receiver equalization circuit provides the capability of compensating inter-symbol interference (ISI) losses in a 5-m 28-AWG DVI cable. Typical cable measurements indicate that the TMDS341A can drive a 5-m 28-AWG HDMI cable and pass the eye mask at the output of a HDMI source (TP1) and a 10-m 28-AWG HDMI cable and pass the eye mask at the input of a HDMI sink (TP2). Figure through Figure show the eye mask measurement results. Figure 36. Eye Diagram at Output 5-m 28-AWG Cable vs Figure 37. Eye Diagram Recovered by TMDS341A vs TP1 TP1 Eye Mask Eye Mask Submit Documentation Feedback

www.ti.com DDC Signal Path TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 APPLICATION INFORMATION (continued) Figure 38. Eye Diagram at Output 10-m 28-AWG Cable Figure 39. Eye Diagram Recovered by TMDS341A vs TP2 vs TP2 Eye Mask Eye Mask Observed I C bus voltage is dependent on bus resistance, capacitance, and time. The transient bus voltage, when charging from a low state to a high state, can be calculated using equation (1). V(t) V DD e t/RC (1) Where: t is the time since the charging started V DD is the pull-up termination voltage R is the total resistance on the I C link C is the total capacitance on the I C link In the I C bus specification, version 2.1, the high-level threshold voltage is V IH 0.7 V DD and the low-level threshold voltage is V IL 0.3 V DD From equation (1), the times to charge from a bus voltage of V to the V IH and V IL levels are: t IH 1.204 RC t IL 0.357 RC The bus rise time (from 0.3 V DD to 0.7 V DD is then given by equation (2): t r(30-70) t IH t IL 0.847 RC (2) The TMDS341A can be easily applied in stand-alone switch boxes and digital displays. The following sections show the bus lengths that can be supported in each case. Maximum Bus Lengths for Switch a stand-alone switch. Both pull-up resistors are decided by the source and sink equipment. A 1.5-k Ω resistor at the source and a 47-k Ω resistor at the sink are recommended. Submit Documentation Feedback

www.ti.com SDAn Switch Box TMDS341A SDA_Sink VDDsink R upsink C sinkC cable2C OC IC cable1C source VDDsource R upsource Source Sink C source Sink TMDS341A SDA_SinkSDAn Source C cable C sink DVI/HDMI RX VDDsource R upsource VDDsink R upsink TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 APPLICATION INFORMATION (continued) Figure 40. DDC Link from Source to Sink With External Switch Box R upsource 1.5-k Ω pull-up to V R upsink 47-k Ω pull-up to V R total R upsource R upsink 1.45 k Ω C total C source C cable1 C i C o C cable2 C sink For standard mode I the frequency is at 100 kHz, and the transition time must be less than µ The total allowable capacitance, C total is then 814-pF. C source and C sink are limited by the HDMI specification to pF. C i/o for the TMDS341A is pF max. The total capacitance from DVI or HDMI cables, C cable1 and C cable2 should then be less than 704 pF. Typical capacitance is 200 pF for a 28-AWG 5-m HDMI cable and 300 pF for a 28-AWG 5-m DVI cable. The recommended total cable length is the length of cable Lcable1, plus the length of cable Lcable2. For a 28-AWG DVI cable, the total cable length is and for a 28-AWG HDMI cable, the total cable length is This calculation is applicable to V IH V pass Maximum Bus Lengths for DTV a switch in a DTV and being placed on the same PCB board as the DVI/HDMI receiver. Unlike Figure the output connector of the TMDS341A stand-alone switch and the input connector of the sink are removed, which results in a lower capacitance in the DDC link and eliminates the impedance discontinuity. However, the capacitance of the removed connectors is relatively small, relative to the total allowable capacitance. The results from the previous section Maximum Bus Lengths for Switch values. The recommended total cable length is the length from source to sink. Figure 41. DDC Link From Source to Sink Without External Switch Box Submit Documentation Feedback

www.ti.com TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 APPLICATION INFORMATION (continued) Table summarizes the recommended cable lengths based on threshold voltages V IH 0.7 V DD and V IL 0.3 V DD Table Recommended Cable Lengths Under General Threshold Voltages, 0.7 V DD and 0.3 V DD of a DDC Interface DDC THRESHOLD VOLTAGE, V IH 0.7 V DD V IL 0.3 V DD TOTAL CABLE LENGTH (m) SUGGESTED PULL-UP RESISTANCE Ω CABLE TYPE SWITCH BOX Lcable1 Lcable2 DIGITAL DISPLAY Lcable 28-AWG DVI R upsource 1.5 k Ω R upsink k Ω 28-AWG HDMI Applying the same methodology to the case of V IH 1.9 V and V IL 0.7 Table summarizes the recommended cable lengths to meet the timing requirement of the DDC interface. Table Recommended Cable Lengths Under General Threshold Voltages, 1.9 V and 0.7 of a DDC Interface DDC THRESHOLD VOLTAGE, V IH 1.9 V V IL 0.7 V TOTAL CABLE LENGTH (m) SUGGESTED PULL-UP RESISTANCE Ω CABLE TYPE SWITCH BOX Lcable1 Lcable2 DIGITAL DISPLAY Lcable 28-AWG DVI R upsource 1.5 k Ω R upsink k Ω 28-AWG HDMI Submit Documentation Feedback

www.ti.com TMDS341A SLLS702B MAY 2006 REVISED MARCH 2007 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from A Revision (November 2006) to B Revision Page Changed signaling rate from 1.65 Gbps to 2.25 Gbps and color depth from 8-bit to 12-bit Changed 1.65 Gbps to 2.25 Gbps Changed from 1.65 Gbps to 2.25 Gbps Added data channels residual peak-to-peak jitter curves Added clock channel residual peak-to-peak jitter curves Added A to the device on test board Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TMDS341APFC ACTIVE TQFP PFC 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMDS341APFCG4 ACTIVE TQFP PFC 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMDS341APFCR ACTIVE TQFP PFC 80 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMDS341APFCRG4 ACTIVE TQFP PFC 80 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 23-Feb-2007 Addendum-Page 1

MTQF009A – OCTOBER 1994 – REVISED DECEMBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PFC (S-PQFP-G80) PLASTIC QUAD FLATPACK 4073177/B 11/96 0,13 NOM 0,25 0,75 0,45 Seating Plane 0,05 MIN Gage Plane 0,27 0,17 SQ SQ 12,20 13,80 14,20 11,80 9,50 TYP 1,05 1,20 MAX 0,95 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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