TMDS3242260-08

SM320C26B TI1 | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 42

Technical content

www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 DIGITALSIGNALPROCESSOR

1 DigitalSignalProcessor

• Block Moves forData or Program Management1.1 Features
• Repeat InstructionsforEfficientUse of 1• 100-nsInstructionCycle Time Program Space• 1568 Words ofConfigurableOn-Chip Data and • EightAuxiliaryRegistersand DedicatedProgram RAM ArithmeticUnitforIndirectAddressing• 256 Words ofOn-Chip Program ROM • SerialPortforDirectCode Interface• 128K Words ofData/Program Space • SynchronizationInputforSynchronous• Pin-for-PinCompatible withtheSMJ320C25 MultiprocessorConfigurations
• 16 Inputand 16 Output Channels • Wait StatesforCommunication to
• 16-BitParallelInterface Slow-Off-ChipMemories or Peripherals
• DirectlyAccessibleExternalData Memory • On-Chip Timer forControlOperations Space • Three ExternalMaskable User Interrupts
• GlobalData Memory Interface • InputPin Polledby SoftwareBranch
• 16-BitInstructionand Data Words Instruction
• 32-BitALU and Accumulator • Programmable Output Pin forSignaling ExternalDevices• Single-CycleMultiplyor Accumulate Instructions • 1.6-μm CMOS Technology
• 0 to16-BitScalingShifter • Single5-V Supply
• BitManipulationand LogicalInstructions • 68-PinLeaded Ceramic Chip Carrier(FJSuffix)
• InstructionSet Support forFloating-Point Operations,AdaptiveFiltering,and Extended- PrecisionArithmetic

1.2 Description

The SM320C26B DigitalSignalProcessor is a VLSI digitalsignalprocessorand peripheral.The SM320C26B supportsa wide rangeofdigitalsignalprocessingapplications,such as telecommunications, modems, image processing,speech processing,spectrum analysis,audio processing,digitalfiltering, high-speedcontrol,graphics,and othercomputationintensiveapplications. With a 100-nsinstructioncycletimeand an innovativememory configuration,theSM320C26B performs operationsnecessaryformany realtime digitalsignalprocessingalgorithms.Since most instructions requireonlyone cycle,theSM320C26B iscapableofexecutingtenmillioninstructionsper second.On- chipprogrammable data/programRAM of 1568 words of 16 bits,on-chipprogram ROM of 256-words, directaddressingof up to 64K-words of externalprogram and 64K-words of data memory space,and multiprocessorinterfacefeaturesforsharingglobalmemory minimizeunnecessarydatatransferstotake fulladvantageofthecapabilitiesoftheprocessor. The SM320C26B scalingshifterhas a 16-bitinputconnected to the data bus and a 32-bitoutput connectedto the ALU. The scalingshifterproduces a leftshiftof 0 to 16 bitson the inputdata,as programmed intheinstruction.The LSBs oftheoutputarefilledwithzeroes,and theMSBs may be either filledwithzeroesorsign-extended,dependingupon thestatusprogrammed intotheSXM (sign-extension mode) bitofstatusregisterST1. NOTE The SM320C26B isintendedtosupportexistingdesigns,and isnotrecommended fornew designs.The datasheethas referencestodesignsoftwareand hardwaretoolsthatmay no longerbe available. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate.Productsconformto Copyright© 2012,Texas InstrumentsIncorporatedspecificationsper the terms of the Texas Instrumentsstandardwarranty.Production processingdoes notnecessarilyincludetestingofallparameters.

D15 RSMP/MC BIO HOLD READYCLKRCLKX VCCVCC 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 VSS IACK MSC CLKOUT1 CLKOUT2 XF HOLDA DX FSX A8 A9 A10 A11 A12 A13 A14 A15A6 A7VCC X2/CLKIN BR STRB R/W PS IS DS VSS SYNC INT0 INT1 INT2 VCC DR FSR SM320C26B SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com

2 Device Information

2.1 OrderingInformation(1)

TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING -55°C to125°C FJ SM320C26BFJM SM320C26BFJM (1) Forthemost currentpackage and orderinginformationsee thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com.

2.2 Pin Assignments

(TOP VIEW)

2 DeviceInformation Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012

2.2.1 TerminalFunctions

Table2-1.TerminalFunctions TERMINAL TYPE (1) DESCRIPTION NAME PIN A0 26 A1 28 A2 29 A3 30 A4 31 A5 32 A6 33 A7 34 O/Z 16-bitaddressbus A15 (MSB) throughA0 (LSB) A8 36 A9 37 A10 38 A11 39 A12 40 A13 41 A14 42 A15 43 BI0 68 I Branchcontrolinput.Polledby BIOZ instruction. Bus requestsignal.Assertedwhen theSM320C26B requiresaccesstoan externalglobalBR 50 O datamemory space. CLKOUT1 58 O Masterclockoutput(crystalorCLKIN frequency/4) CLKOUT2 57 O A second clockoutputsignal CLKR 64 I Clockinputforserialportreceiver CLKX 63 I Clockinputforserialporttransmitter D0 18 D1 17 D2 16 D3 15 D4 14 D5 13 D6 12 D7 11 16-bitdatabus D15 (MSB) throughD0 (LSB).Multiplexedbetween program,data,andI/O/Z I/Ospaces.D8 9 D9 8 D10 7 D11 6 D12 5 D13 4 D14 3 D15 2 DR 24 I Serialdatareceiveinput DX 54 O/Z Serialdatatransmitoutput FSR 25 I Frame synchronizationpulseforreceiveinput FSX 53 I/O/Z Frame synchronizationpulsefortransmit.Configurableas eitheran inputoran output. (1) I= input,O = output,Z = highimpedance Copyright© 2012,Texas InstrumentsIncorporated DeviceInformation 3 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com Table2-1.TerminalFunctions(continued) TERMINAL TYPE (1) DESCRIPTION NAME PIN Holdinput.When asserted,SM320C26B goes intoan idlemode and placesthedata,HOLD 67 I address,and controllinesinthehigh-impedancestate. HOLDA 55 O Holdacknowledgesignal IACK 60 O Interruptacknowledgesignal INT0 20 INT1 21 I Externaluserinterruptinputs INT2 22 DS 45 IS 46 O/Z Program,data,and I/Ospace selectsignals PS 47 MP/MC 1 I Microprocessor/microcomputermode selectpin MSC 59 O Microstatecompletesignal Data readyinput.Assertedby externallogicwhen usingslowerdevicestoindicatethatREADY 66 I thecurrentbus transactioniscomplete. RS 65 I Resetinput R/W 48 O/Z Read/writesignal STRB 49 O/Z Strobesignal SYNC 19 I Synchronizationinput VCC I 5-V supplypins VSS I Ground pins XF 56 O Externalflagoutput(latchedsoftware-programmablesignal) X1 51 O Outputfrominternaloscillatorforcrystal X2/CLKIN 52 I Inputtointernaloscillatorfromcrystalorexternalclock

4 DeviceInformation Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

RSR(16) XSR(16) DRR(16) DXR(16) TIM(16) PRD(16) IMR(6) GREG(8) QIR(16) IR(16) ST0(16) ST1(16) RPTC(8) IFR(6) MUX MUX MUX MUX MUX MUXMUXMUX MUX MUX MUX PROGRAM BUS DR CLKR FSR DX CLKX FSX 161616 16 16 1616 32 32 1616 16161616 16 16 16 16

7 LSB

PC(16) STACK (8 - 16)ADDRESS PROGRAM ROM (256 x 16) INSTRUCTION PFC(16) MCS(16) ARP(3) ARS(3) DAT A RAM (32 x 16) BLOCK B2 DAT A/PROG RAM (512 x 16) BLOCK B3 DAT A/PROG RAM (512 x 16) BLOCK B1 DAT A/PROG RAM (512 x 16) BLOCK B0 SHIFTERS (0–7) C ACCH(16) ACCL(16) ALU(32) SHIFTER (6.0.1.4) TR(16) MULTIPLIER PR(32) SHIFTER(0–16) DP(9) AR0(16) AR1(16) AR2(16) AR3(16) AR4(16) AR5(16) AR6(16) AR7(16) ARAU(16) MUX MUX CONTROLLER DAT A BUS R/W STRB READY BR XF HOLD HOLDA MSC BIO RS IACK MP/MC INT(2-0) A15–A0 D15–D0 PSDSIS SYNC X1 X2/CLKINCLKOUT1 CLKOUT2 PROGRAM BUS DATA BUS LEGEND: ACCH = Accumulator high ACCL = Accumulator low ALU = Arithmetic logic unit ARAU = Auxiliary register arithmetic unit ARS = Auxiliary register pointer buffer ARP = Auxiliary register pointer DP = Data memory page pointer DRR = Serial port data receive register DXR = Serial port data trademark register IFR = Interrupt flag register IMR = Interrupt mask register IR = Instruction register MCS = Microcall stack QIR = Queue instruction register PR = Product register PRD = Product register for timer TIM = Timer TR = Temporary register PC = Program counter PFC = Prefetch counter RPTC = Repeat instruction counter GREG = Global memory allocation register RSR = Serial port receive shift register XSR = Serial port to transmit shift register AR0–AR7 = Auxiliary registers ST0, ST1 = Status regi sters C = Carry bit SM320C26B www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012

3 FunctionalOverview

Figure3-1.FunctionalBlock Diagram Copyright© 2012,Texas InstrumentsIncorporated FunctionalOverview 5 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com

3.1 ArchitecturalOverview

The SM320C26B architectureis based on the SMJ320C25 witha differentinternalRAM and ROM configuration.The SM320C26B integrates256 words of on-chipROM and 1568 words of on-chipRAM compared to 4K words of on-chipROM and 544 words of on-chipRAM forthe SMJ320C25. The SM320C26B ispinforpincompatiblewiththeSMJ320C25. Increasedthroughputon theSM320C26B formany DSP applicationsisaccomplishedby means ofsingle cyclemultiply/accumulateinstructionswitha datamove option,eightauxiliaryregisterswitha dedicated arithmeticunit,and fasterI/Onecessaryfordataintensivesignalprocessing. The architecturaldesignoftheSM320C26B emphasizes overallspeed,communication,and flexibilityin theprocessorconfiguration.Controlsignalsand instructionsprovidefloatingpointsupport,blockmemory transfers,communicationtosloweroff-chipdevices,and multiprocessingimplementations. Three largeon-chipRAM blocks,configurableeitheras separateprogram and data spaces or as three contiguousdatablocks,provideincreasedflexibilityinsystem design.Programs ofup to256 words can be masked intothe internalprogram ROM. The remainderof the 64K-word program memory space is locatedexternally.Largeprogramscan executeatfullspeed fromthismemory space.Programs can also be downloaded fromslowexternalmemory tohighspeed on-chipRAM. A datamemory addressspace of 64K words isincludedto facilitateimplementationof DSP algorithms.The VLSI implementationof the SM320C26B incorporatesallofthesefeaturesas wellas many others,includinga hardwaretimer,serial port,and blockdatatransfercapabilities. 3.2 32-BitALU and Accumulator The SM320C26B 32-bitarithmeticlogicunit(ALU) and accumulatorperforma wide range of arithmetic and logicalinstructions,themajorityofwhichexecuteina singleclockcycle.The ALU executesa variety of branch instructionsdependent on the statusof the ALU or a singlebitina word.These instruction providethefollowingcapabilities:

• Branchtoan addressspecifiedby theaccumulator
• Normalizefixed-pointnumbers containedintheaccumulator
• Testa specifiedbitofa word indatamemory. One inputtotheALU isalwaysprovidedfromtheaccumulator,and theotherinputcan be providedfrom theproductregister(PA)ofthemultiplierortheinputscalingshifterwhichhas fetcheddatafromtheRAM on thedatabus.AftertheALU has performedthearithmeticor logicaloperations,theresultisstoredin theaccumulator. The 32-bitaccumulatorissplitintotwo 16-bitsegments forstorageindatamemory. Additionalshiftersat theoutputoftheaccumulatorperformshiftswhilethedataisbeingtransferredtothedatabus forstorage. The contentsoftheaccumulatorremainunchanged.

6 FunctionalOverview Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012

3.3 ScalingShifter

The SM320C26B scalingshifterhas a 16-bitinputconnected to the data bus and a 32-bitoutput connectedto the ALU. The scalingshifterproduces a leftshiftof 0 to 16 bitson the inputdata,as programmed intheinstruction.The LSBs oftheoutputarefilledwithzeroes,and theMSBs can be either filledwithzeroesorsign-extended,dependingupon thestatusprogrammed intotheSXM (sign-extension mode) bitofstatusregisterSTO. 3.4 16 x 16-BitParallelMultiplier The SM320C26B has a 16 x 16-bithardware multiplier,which is capable of computing a signed or unsigned 32-bitproductin a singlemachine cycle.The multiplierhas the followingtwo associated registers:

• A 16-bittemporaryregister(TR)thatholdsone oftheoperandsforthemultiplier,and
• A 32-bitproductregister(PR)thatholdstheproduct. IncorporatedintotheSM320C26B instructionsetare single-cyclemultiplyor accumulateinstructionsthat allowbothoperandstobe processedsimultaneously.The datafortheseoperationscan resideanywhere ininternalor externalmemory and can be transferredto the multipliereach cycleviathe program and databuses. Four productshiftmodes areavailableattheproductregister(PR) outputthatareusefulwhen performing multiplyoraccumulateoperations,fractionalarithmetic,orjustifyingfractionalproducts.

3.5 Timer

The SM320C26B providesa memory mapped 16-bittimerforcontroloperations.The on-chiptimer(TIM) registerisa down counterthatiscontinuouslyclockedby CLKOUT1. A timerinterrupt(TINT)isgenerated everytimethetimerdecrementstozero,providedthetimerinterruptisenabled.The timerisreloadedwith the value containedin the period(PRD) registerwithinthe next cycleafteritreaches zero so that interruptsmay be programmed tooccuratregularintervalsofPRD + 1 cyclesofCLKOUT1.

3.6 Memory Control

The SM320C26B providesa totalof1568 16-bitwords ofon-chipdataRAM, dividedintothreeseparate blocks(B0,B1, and B2).Of the1568 words,32 words (blockB2) arealwaysdatamemory, and allother blocksare programmable as eitherdataor program memory. A datamemory sizeof1568 words allows the SMJ320C26 to handlea data arrayof 1536 words,whilestillleaving32 locationsforintermediate storage.When usingB0, B1, or B3 as program memory, instructionscan be downloaded from external memory intoon-chipRAM, and thenexecuted. When usingon-chipprogram RAM, ROM, orhigh-speedexternalprogram memory, theSM320C26B runs atfullspeed withoutwaitstates.However, theREADY linecan be used tointerfacetheSM320C26B to slower,less-expensiveexternalmemory. Downloadingprograms from slow off-chipmemory to on-chip programRAM speeds processingwhilecuttingsystemcosts. The SM320C26B providesthreeseparateaddressspaces forprogram memory, datamemory, and I/O. The on-chipmemory ismapped intoeitherthedatamemory orprogram memory space,dependingupon thechoiceofmemory configuration. The instructionconfiguration(parameter)isused as followsto configurethe blocksB0, B1, and B3 as programoras datamemory. Copyright© 2012,Texas InstrumentsIncorporated FunctionalOverview 7 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com Table3-1.InstructionConfiguration CONFIGURATION B0 B1 B3

0 Data Data Data

1 Program Data Data

2 Program Program Data

3 Program Program Program

Regardlessoftheconfiguration,theusermay stillexecutefromexternalprogrammemory. The SM320C26B providesa ROM of 256 words.The ROM issufficientto allowthe programming of a bootstrapprogramand interrupthandler,ortoimplementselftestroutines. The SM320C26B has sixregisterswhich are mapped intothe data memory space:a serialportdata receiveregister,serialportdatatransmitregister,timerregister,periodregister,interruptmask register, and globalmemory allocationregister.

8 FunctionalOverview Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

(EXTERNAL) EXTERNAL ON-CHIP MMRs RESERVED ON-CHIP BLOCK B2 RESERVED ON-CHIP BLOCK B0 ON-CHIP BLOCK B1 EXTERNAL ON-CHIP BLOCK B3 DATA PAGE 0 PAGE 1-3 PAGE 4-7 PAGE 8-11 PAGE 12-15 PAGE 16-511 31 (001Fh) 32 (0020h) EXTERNAL I/O ON-CHIP MMRs RESERVED ON-CHIP BLOCK B2 RESERVED ON-CHIP BLOCK B0 ON-CHIP BLOCK B1 EXTERNAL ON-CHIP BLOCK B3 DATA PAGE 0 PAGE 1-3 PAGE 4-7 PAGE 8-11 PAGE 12-15 PAGE 16-511 EXTERNAL I/O MEMORY MAPS AFTER A RESET OR CONF 0

1 MP/MC

= 1

2 MP/MC = 0

0 (0000h) 65535 (FFFFh) 5 (0005h) 6 (0006h) 0 (0000h) 65535 (FFFFh) 95 (005Fh) 96 (0060h) 127 (007Fh) 128 (0080h) 511 (01FFh) 512 (0200h) 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) 5 (0005h) 6 (0006h) 0 (0000h) 65535 (FFFFh) 95 (005Fh) 96 (0060h) 127 (007Fh) 128 (0080h) 511 (01FFh) 512 (0200h) 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) PROGRAM 0 (0000h) 255 (00FFh) 256 (0100h) INTERRUPTS AND RESERVED BOOTLOAD ROM RESERVED 65535 (FFFFh) 4095 (0FFFh) 4096 (1000h) EXTERNAL SM320C26B www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 Figure3-2.Memory Maps Aftera Reset or CONF 0 Copyright© 2012,Texas InstrumentsIncorporated FunctionalOverview 9 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

0 (0000h) 31 (001Fh) 32 (0020h) INTERRUPTS AND RESERVED (EXTERNAL) EXTERNAL EXTERNAL 64511 (FBFFh) 64512 (FC00h) 65535 (FFFFh) 65023 (FDFFh) 65024 (FE00h) EXTERNAL 63999 (F9FFh) 64000 (FA00h) ON-CHIP BLOCK B0 PROGRAM 0 (0000h) 255 (00FFh) 256 (0100h) INTERRUPTS AND RESERVED BOOTLOAD ROM EXTERNAL EXTERNAL 64511 (FBFFh) 64512 (FC00h) 65535 (FFFFh) 65023 (FDFFh) 65024 (FE00h) EXTERNAL 63999 (F9FFh) 64000 (FA00h) ON-CHIP BLOCK B0 4095 (0FFFh) 4096 (1000h) RESERVED ON-CHIP MMRs RESERVED ON-CHIP BLOCK B2 RESERVED DOES NOT EXIST ON-CHIP BLOCK B1 EXTERNAL ON-CHIP BLOCK B3 DATA PAGE 0 PAGE 1-3 PAGE 4-7 PAGE 8-11 PAGE 12-15 PAGE 16-511 EXTERNAL I/O ON-CHIP MMRs RESERVED ON-CHIP BLOCK B2 RESERVED DOES NOT EXIST ON-CHIP BLOCK B1 EXTERNAL ON-CHIP BLOCK B3 DATA PAGE 0 PAGE 1-3 PAGE 4-7 PAGE 8-11 PAGE 12-15 PAGE 16-511 EXTERNAL I/O MEMORY MAPS AFTER CONF 1 = 1 5 (0005h) 6 (0006h) 0 (0000h) 65535 (FFFFh) 95 (005Fh) 96 (0060h) 127 (007Fh) 128 (0080h) 511 (01FFh) 512 (0200h) 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) 5 (0005h) 6 (0006h) 0 (0000h) 65535 (FFFFh) 95 (005Fh) 96 (0060h) 127 (007Fh) 128 (0080h) 511 (01FFh) 512 (0200h) 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) SM320C26B SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com Figure3-3.Memory Maps AfterCONF 1

10 FunctionalOverview Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

0 (0000h) 31 (001Fh) 32 (0020h) INTERRUPTS AND RESERVED (EXTERNAL) EXTERNAL EXTERNAL 64511 (FBFFh) 64512 (FC00h) 65535 (FFFFh) 65023 (FDFFh) 65024 (FE00h) 63999 (F9FFh) 64000 (FA00h) ON-CHIP BLOCK B0 PROGRAM 0 (0000h) 255 (00FFh) 256 (0100h) INTERRUPTS AND RESERVED BOOTLOAD ROM EXTERNAL EXTERNAL 64511 (FBFFh) 64512 (FC00h) 65535 (FFFFh) 65023 (FDFFh) 65024 (FE00h) 63999 (F9FFh) 64000 (FA00h) ON-CHIP BLOCK B0 4095 (0FFFh) 4096 (1000h) RESERVED ON-CHIP BLOCK B1 ON-CHIP BLOCK B1 ON-CHIP MMRs RESERVED ON-CHIP BLOCK B2 RESERVED DOES NOT EXIST EXTERNAL ON-CHIP BLOCK B3 DATA PAGE 0 PAGE 1-3 PAGE 4-7 PAGE 8-11 PAGE 12-15 PAGE 16-511 EXTERNAL I/O ON-CHIP MMRs RESERVED ON-CHIP BLOCK B2 RESERVED DOES NOT EXIST EXTERNAL ON-CHIP BLOCK B3 DATA PAGE 0 PAGE 1-3 PAGE 4-7 PAGE 8-11 PAGE 12-15 PAGE 16-511 EXTERNAL I/O MEMORY MAPS AFTER CONF 2 = 1 5 (0005h) 6 (0006h) 0 (0000h) 65535 (FFFFh) 95 (005Fh) 96 (0060h) 127 (007Fh) 128 (0080h) 511 (01FFh) 512 (0200h) 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) 5 (0005h) 6 (0006h) 0 (0000h) 65535 (FFFFh) 95 (005Fh) 96 (0060h) 127 (007Fh) 128 (0080h) 511 (01FFh) 512 (0200h) 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) SM320C26B www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 Figure3-4.Memory Maps AfterCONF 2 Copyright© 2012,Texas InstrumentsIncorporated FunctionalOverview 11 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

0 (0000h) 31 (001Fh) 32 (0020h) INTERRUPTS AND RESERVED (EXTERNAL) EXTERNAL 64511 (FBFFh) 64512 (FC00h) 65535 (FFFFh) 65023 (FDFFh) 65024 (FE00h) 63999 (F9FFh) 64000 (FA00h) ON-CHIP BLOCK B0 ON-CHIP BLOCK B1 ON-CHIP BLOCK B3 ON-CHIP MMRs RESERVED ON-CHIP BLOCK B2 RESERVED DOES NOT EXIST EXTERNAL DOES NOT EXIST DATA PAGE 0 PAGE 1-3 PAGE 4-7 PAGE 8-11 PAGE 12-15 PAGE 16-511 EXTERNAL I/O ON-CHIP MMRs RESERVED ON-CHIP BLOCK B2 RESERVED DOES NOT EXIST DOES NOT EXIST EXTERNAL DOES NOT EXIST DATA PAGE 0 PAGE 1-3 PAGE 4-7 PAGE 8-11 PAGE 12-15 PAGE 16-511 EXTERNAL I/O MEMORY MAPS AFTER CONF 3 = 1 5 (0005h) 6 (0006h) 0 (0000h) 65535 (FFFFh) 95 (005Fh) 96 (0060h) 127 (007Fh) 128 (0080h) 511 (01FFh) 512 (0200h) 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) 5 (0005h) 6 (0006h) 0 (0000h) 65535 (FFFFh) 95 (005Fh) 96 (0060h) 127 (007Fh) 128 (0080h) 511 (01FFh) 512 (0200h) 1023 (03FFh) 1024 (0400h) 1535 (05FFh) 1536 (0600h) 2047 (07FFh) 2048 (0800h) PROGRAM 0 (0000h) 255 (00FFh) 256 (0100h) INTERRUPTS AND RESERVED BOOTLOAD ROM EXTERNAL 64511 (FBFFh) 64512 (FC00h) 65535 (FFFFh) 65023 (FDFFh) 65024 (FE00h) 63999 (F9FFh) 64000 (FA00h) ON-CHIP BLOCK B0 4095 (0FFFh) 4096 (1000h) RESERVED ON-CHIP BLOCK B1 ON-CHIP BLOCK B3 SM320C26B SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com Figure3-5.Memory Maps AfterCONF 3

12 FunctionalOverview Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012

3.7 Interruptsand Subroutines

The SM320C26B has threeexternalmaskable userinterruptsINT2–INT0,availableforexternaldevices thatinterrupttheprocessor.Internalinterruptsare generatedby theserialport(RINT and XINT),by the timer(TINT),and by the softwareinterrupt(TRAP) instruction.Interruptsare prioritizedwithreset(RS) havingthe highestpriorityand the serialporttransmitinterrupt(XINT)havingthe lowestpriority.All interruptlocationsareon two-wordboundariesso thatbranchinstructioncan be accommodated inthose locationsifdesired. A built-inmechanism protectsmulticycleinstructionsfrom interrupts.Ifan interruptoccurs duringa multicycleinstruction,the interruptisnot processeduntilthe instructioniscompleted.Thismechanism appliesbothtoinstructionsthatarerepeatedorbecome multicycledue totheREADY signal.

3.8 ExternalInterface

The SM320C26B supportsa wide range of system interfacingrequirements.Program, data,and I/O addressspaces provideinterfacetomemory and I/O.thusmaximizingsystem throughout.I/Odesignis simplifiedby havingI/Otreatedthesame way as memory. I/Odevicesare mapped intotheI/Oaddress space usingtheprocessor’s externaladdressand databuses inthesame manner as memory-mapped devices.Interfaceto memory and I/Odevicesof varyingspeeds isaccomplishedby usingthe READY line.When transitionsare made withslowerdevices,the SM320C26B processorwaitsuntilthe other devicecompletesitsfunctionand signalsthe processorviathe READY line.Then, the SM320C26B continuesexecution. A full-duplexserialport providescommunication with serialdevices,such as codecs, serialA/D converters,and otherserialsystems.The interfacesignalsare compatiblewithcodecs and many other serialdevices with a minimum of externalhardware. The serialport can also be used for intercommunicationbetween processorsinmultiprocessingapplications. The serialporthas two memory-mapped registers:thedatatransmitregister(DXR) and thedatareceive register(DRR).Both registersoperateineitherthebytemode or16-bitword mode, any can be accessed inthesame manner as any otherdatamemory location.Each registerhas an externalclock,a framing synchronizationpulse,and associatedshiftregisters.One method ofmultiprocessingcan be implemented by programmingone devicetotransmitwhiletheothersareinthereceivemode.

3.9 Multiprocessing

The flexibilityof the SM320C26B allowsconfigurationsto satisfya wide range of system requirements. The SM320C26B can be used as follows:

• A standaloneprocessor
• A multiprocessorwithdevicesinparallel
• A slaveorhostmultiprocessorwithglobalmemory space
• A peripheralprocessorinterfacedviaprocessor-controlledsignalstoanotherdevice For multiprocessingapplications,the SM320C26B has the capabilityof allocatingglobaldata memory space and communicatingwiththatspace viatheBR (busrequest)and READY controlsignals.Global memory is data memory shared by more than one processor.Globaldata memory access must be arbitrated.The 8-bitmemory-mapped GREG (globalmemory allocationregister)specifiespartof the SM320C26B's datamemory as globalexternalmemory. The contentsoftheregisterdeterminethesizeof the globalmemory space. Ifthe currentinstructionaddresses an operand withinthatspace, BR is assertedtorequestcontrolofthebus.The lengthofthememory cycleiscontrolledby theREADY line. The SM320C26B supportsDMA (directmemory access)toitsexternalprogram ordatamemory usingthe HOLD and HOLDA signals.Anotherprocessorcan takecompletecontrolof the SM320C26B's external memory by assertingHOLD low.Thiscauses theSM320C26B toplaceitsaddress,data,and controllines ina high-impedancestate,and assertHOLDA. Copyright© 2012,Texas InstrumentsIncorporated FunctionalOverview 13 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com

3.10 Addressing Modes

The SM320C26B instructionsetprovidesthreememory addressingmodes: direct,indirect,and immediate addressing. Both directand indirectaddressingcan be used toaccessdatamemory. Indirectaddressing,seven bits oftheinstructionword are concatenatedwiththeninebitsofthedatamemory page pointertoform the 16-bitdata memory address.Indirectaddressingaccesses data memory throughthe eightauxiliary registers.Inimmediateaddressing,thedataisbased on a portionoftheinstructionword. In directmemory addressing,the instructionword containsthe lowerseven bitsof the data memory address.Thisfieldisconcatenatedwiththe ninebitsof the data memory page pointerto form the full 16-bitaddress.Thus, memory ispaged inthe directaddressingmode witha totalof 512 pages,each page containing128 words. Eightauxiliaryregister(AR0–AR7) provideflexibleand powerfulindirectaddressing.To selecta specific auxiliaryregister,theauxiliaryregisterpointer(ARP) isloadedwitha valuefrom0 through7 forAR0 –AR7, respectively. There are seven typesofindirectaddressing:auto-incrementor auto-decrement,post-indexingby either addingor subtractingthecontentsofAR0, or singleindirectaddressingwithno incrementor decrement and bit-reversaladdressing(usedinFFTs) withincrementordecrement.Alloperationsareperformedon the currentauxiliaryregisterinthe same cycleas the originalinstruction,followedby anew ARP value beingloaded.

3.11 Repeat Feature

A repeatfeature,used withinstructionssuch as multiplyor accumulate,blockmoves, I/Otransfers,and tableread/writes,allowsa singleinstructiontobe performedup to256 times.The repeatcounter(RPTC) isloadedwitheithera data memory value(RPT instruction)or an immediatevalue(RPTK instruction). The valueofthisoperandisone lessthanthenumber oftimesthatthenextinstructionisexecuted.Those instructionsthatare normallymulticycleare pipelinedwhen using the repeatfeature,and effectively become single-cycleinstructions.

3.12 InstructionSet

The SM320C26 microprocessorimplementsa comprehensiveinstructionsetthatsupportsbothnumeric intensivesignalprocessingoperationsas wellas generalpurposeapplications,such as multiprocessing and highspeed control. For maximum throughput,thenextinstructionisprefetchedwhilethecurrentone isbeingexecuted.Since thesame datalinesareused tocommunicate toexternaldata/programorI/Ospace,thenumber ofcycles may vary depending upon whether the next data operand fetchisfrom internalor externalprogram memory. Highestthroughputisachievedby maintainingdatamemory on-chipand usingeitherinternalor fastprogrammemory. Table3-2liststhesymbolsand abbreviationsand Figure3-6consistsprimarilyofsingle-cycle,single-word instructions.Infrequentlyused branch,I/O,and CALL instructionsare multicycle.The instructionset summary isarrangedaccordingtofunctionand alphabetizedwithineach functionalgrouping.

14 FunctionalOverview Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 Table3-2.InstructionSymbols SYMBOL DEFINITION B 4-bitfieldspecifyinga bitcode CM 2-bitfieldspecifyingcompare mode D Data memory addressfield F0 Formatstatusbit M Addressingmode bit K Immediateoperandfield PA Portaddress(PA0–PA15 arepredefinedassemblersymbolsequalto0 through15,respectively) PM 2-bitfieldspecifyingP registeroutputshiftcode R 3-bitoperandfieldspecifyingauxiliaryregister S 4-bitleft-shiftcode CNF InternalRAM configurationbits X 3-bitaccumulatorleft-shiftfield Copyright© 2012,Texas InstrumentsIncorporated FunctionalOverview 15 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

D D S X S D S S K S S X S S S D D D D D D D D D D K D D D D D D D D D ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS MNEMONIC DESCRIPTION NO. INSTRUCTION BIT CODE MNEMONIC DESCRIPTION NO. WORDS 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 ADD Add to accumulator with shift 1 0 0 0 0 M ADDC Add to accumulator with carry 1 0 1 0 0 0 0 1 1 M ADDH Add to high accumulator 1 0 1 0 0 1 0 0 0 M ADDK Add to accumulator short immediate 1 1 1 0 0 1 1 0 0 ADDS Add to low accumulator with sign extension suppressed 1 0 1 0 0 1 0 0 1 M ADDT Add to accumulator with shift specified by T register 1 0 1 0 0 1 0 1 0 M ADLK Add to accumulator long immediate with shift 2 1 1 0 1 0 0 0 0 0 0 0 1 0 AND AND with accumulator 1 0 1 0 0 1 1 1 0 M ANDK AND immediate with accumulator with shift 2 1 1 0 1 0 0 0 0 0 1 0 0 CMPL Complement accumulator 1 1 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 LAC Load accumulator with shift 1 0 0 1 0 M LACK Load accumulator immediate short 1 1 1 0 0 1 0 1 0 LACT Load accumulator with shift specified by T register 1 0 1 0 0 0 0 1 1 M LALK Load accumulator long immediate with shift 2 1 1 0 1 0 0 0 0 0 0 0 1 NEG Negate accumulator 1 1 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1 NORM Normalize contents of accumulator 1 1 1 0 0 1 1 1 0 M X X X 0 0 1 0 OR OR with accumulator 1 0 1 0 0 1 1 0 1 M ORK OR immediate with accumulator with shift 2 1 1 0 1 0 0 0 0 0 1 0 1 ROL Rotate accumulator left 1 1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 0 ROR Rotate accumulator right 1 1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 1 SACH Store high accumulator with shift 1 0 1 1 0 1 M SACL Store low accumulator with shift 1 0 1 1 0 0 M SBLK Subtract from accumulator long immediate with shift 2 1 1 0 1 0 0 0 0 0 0 1 1 SFL Shift accumulator left 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 0 SFR Shift accumulator right 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 1 SUB Subtract from accumulator with shift 1 0 0 0 1 M SUBB Subtract from accumulator with borrow 1 0 1 0 0 1 1 1 1 M SUBC Conditional subtract 1 0 1 0 0 0 1 1 1 M SUBH Subtract from high accumulator 1 0 1 0 0 0 1 0 0 M SUBK Subtract from accumulator short immediate 1 1 1 0 0 1 1 0 1 SUBS Subtract from low accumulator with sign extension suppressed 1 0 1 0 0 0 1 0 1 M SUBT Subtract from accumulator with shift specified by T register 1 0 1 0 0 0 1 1 0 M XOR Exclusive-OR with accumulator 1 0 1 0 0 1 1 0 0 M XORK Exclusive-OR immediate with accumulator with shift 2 1 1 0 1 0 0 0 0 0 1 1 0 ZAC Zero accumulator 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 ZALH Zero low accumulator and load high accumulator 1 0 1 0 0 0 0 0 0 M ZALR Zero low accumulator and load high accumulator with rounding 1 0 1 1 1 1 0 1 1 M ZALS Zero accumulator and load low accumulator with sign extension suppressed 1 0 1 0 0 0 0 0 1 M SM320C26B SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com Figure3-6.SM320C26B InstructionSet Summary

16 FunctionalOverview Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

R D K R DP R DR D K CM D D D D D D D D D D D D D D D K PM D D D K AUXILIARY REGISTERS AND DA T A P AGE POINTER INSTRUCTIONS MNEMONIC DESCRIPTION NO. INSTRUCTION BIT CODE MNEMONIC DESCRIPTION NO. WORDS 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 ADRK Add to auxiliary register short immediate 1 0 1 1 1 1 1 1 0 CMPR Compare auxiliary register with auxiliary register AR0 1 1 1 0 0 1 1 1 0 0 1 0 1 0 0 LAR Load auxiliary register 1 0 0 1 1 0 M LARK Load auxiliary register short immediate 1 1 1 0 0 0 LARP Load auxiliary register pointer 1 0 1 0 1 0 1 0 1 M 0 0 0 1 LDP Load data memory page pointer 1 0 1 0 1 0 0 1 0 M LDPK Load data memory page pointer immediate 1 1 1 0 0 1 0 0 LRLK Load auxiliary register long immediate 2 1 1 0 1 0 0 0 0 0 0 0 0 0 MAR Modify auxiliary register 1 0 1 0 1 0 1 0 1 M SAR Store auxiliary register 1 0 1 1 1 0 M SBRK Subtract from auxiliary register short immediate 1 0 1 1 1 1 1 1 1 T REGISTER, P REGISTER, AND MUL TIPL Y INSTRUCTIONS MNEMONIC DESCRIPTION NO. INSTRUCTION BIT CODE MNEMONIC DESCRIPTION NO. WORDS 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 APAC Add P register to accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1 LPH Load high P register 1 0 1 0 1 0 0 1 1 M L T Load T register 1 0 0 1 1 1 1 0 0 M L T A Load T register and accumulator previous product 1 0 0 1 1 1 1 0 1 M L TD Load T register, accumulate previous product, and move data 1 0 0 1 1 1 1 1 1 M L TP Load T register and store P register in accumulator 1 0 0 1 1 1 1 1 0 M L TS Load T register and subtract previous product 1 0 1 0 1 1 0 1 1 M MAC Multiply and accumulate 2 0 1 0 1 1 1 0 1 M MACD Multiply and accumulate with data move 2 0 1 0 1 1 1 0 0 M MPY Multiply (with T register, store product in P register) 1 0 0 1 1 1 0 0 0 M MPY A Multiply and accumulate previous product 1 0 0 1 1 1 0 1 0 M MPYK Multiply immediate 1 1 0 1 MPYS Multiply and subtract previous product 1 0 0 1 1 1 0 1 1 M MPYU Multiply unsigned 1 1 1 0 0 1 1 1 1 M P AC Load accumulator with P register 1 1 1 0 0 1 1 1 0 0 0 0 1 0 1 0 0 SPAC Subtract P register from accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 0 1 1 0 SPH Store high P register 1 0 1 1 1 1 1 0 1 M SPL Store low P register 1 0 1 1 1 1 1 0 0 M SPM Set P register output shift mode 1 1 1 0 0 1 1 1 0 0 0 0 0 1 0 SQRA Square and accumulate 1 0 0 1 1 1 0 0 1 M SQRS Square and subtract previous product 1 0 1 0 1 1 0 1 0 M SM320C26B www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 Copyright© 2012,Texas InstrumentsIncorporated FunctionalOverview 17 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

D D D P A D D D D D D D D D D D D D D D D D DP A D D FO BRANCH/CALL INSTRUCTIONS MNEMONIC DESCRITPION NO. INSTRUCTION BIT CODE MNEMONIC DESCRITPION NO. WORDS 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 B Branch unconditionally 2 1 1 1 1 1 1 1 1 1 BACC Branch to address specified by accumulator 1 1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 1 BANZ Branch on auxiliary register not zero 2 1 1 1 1 1 0 1 1 1 BBNZ Branch if TC bit ≠ 0 2 1 1 1 1 1 0 0 1 1 BBZ Branch if TC bit = 0 2 1 1 1 1 1 0 0 0 1 BC Branch on carry 2 0 1 0 1 1 1 1 0 1 BGEZ Branch if accumulator ≥ 0 2 1 1 1 1 0 1 0 0 1 BGZ Branch if accumulator > 0 2 1 1 1 1 0 0 0 1 1 BIOZ Branch on I/O status = 0 2 1 1 1 1 1 0 1 0 1 BLEZ Branch if accumulator ≤ 0 2 1 1 1 1 0 0 1 0 1 BLZ Branch if accumulator < 0 2 1 1 1 1 0 0 1 1 1 BNC Branch on no carry 2 0 1 0 1 1 1 1 1 1 BNV Branch if no overflow 2 1 1 1 1 0 1 1 1 1 BNZ Branch if accumulator ≠ 0 2 1 1 1 1 0 1 0 1 1 BV Branch on overflow 2 1 1 1 1 0 0 0 0 1 BZ Branch if accumulator = 0 2 1 1 1 1 0 1 1 0 1 CALA Call subroutine indirect 1 1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 0 CALL Call subroutine 2 1 1 1 1 1 1 1 0 1 RET Return from subroutine 1 1 1 0 0 1 1 1 0 0 0 1 0 0 1 1 0 I/O AND DA T A MEMORY OPERA TIONS MNEMONIC DESCRITPION NO. INSTRUCTION BIT CODE MNEMONIC DESCRITPION NO. WORDS 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 BLKD Block move from data memory to data memory 2 1 1 1 1 1 1 0 1 M BLKP Block move from program memory to data memory 2 1 1 1 1 1 1 0 0 M DMOV Data move in data memory 1 0 1 0 1 0 1 1 0 M FORT Format serial port registers 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 IN Input data from port 1 1 0 0 0 M OUT Output data to port 1 1 1 1 0 M RFSM Reset serial port frame synchronization mode 1 1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 0 RTXM Reset serial port transmit mode 1 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 0 RXF Reset external flag 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 0 SFSM Set serial port frame synchronization mode 1 1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 1 STXM Set serial port transmit mode 1 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 SXF Set external flag 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 TBLR Table read 1 0 1 0 1 1 0 0 0 M TBLW Table write 1 0 1 0 1 1 0 0 1 M SM320C26B SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com

18 FunctionalOverview Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

D D D D D D D K CNF D D D CONTROL INSTRUCTIONS MNEMONIC DESCRIPTION NO. INSTRUCTION BIT CODE MNEMONIC DESCRIPTION NO. WORDS 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 BIT Test bit 1 1 0 0 1 M BITT Test bit specified by T register 1 0 1 0 1 0 1 1 1 M CONF‡ Configure RAM blocks as Data or program 1 1 1 0 0 1 1 1 0 0 0 1 1 1 1 DINT Disable interrupt 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 1 EINT Enable interrupt 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 IDLE Idle until interrupt 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 1 LST Load status register ST0 1 0 1 0 1 0 0 0 0 M LST1 Load status register ST1 1 0 1 0 1 0 0 0 1 M NOP No operation 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 POP Pop top of stack to low accumulator 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 POPD Pop top of stack to data memory 1 0 1 1 1 1 0 1 0 M PSHD Push data memory value onto stack 1 0 1 0 1 0 1 0 0 M PUSH Push low accumulator onto stack 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 0 RC Reset carry bit 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 RHM Reset hold mode 1 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 0 ROVM Reset overflow mode 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 RPT Repeat instruction as specified by data memory value 1 0 1 0 0 1 0 1 1 M RPTK Repeat instruction as specified by immediate value 1 1 1 0 0 1 0 1 1 RSXM Reset sign-extension mode 1 1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 0 RTC Reset test/control flag 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 0 SC Set carry bit 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 SHM Set hold mode 1 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 1 SOVM Set overflow mode 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1 SST Store status register ST0 1 0 1 1 1 1 0 0 0 M SST1 Store status register ST1 1 0 1 1 1 1 0 0 1 M SSXM Set sign-extension mode 1 1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 1 STC Set test/control flag 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 1 TRAP Software interrupt 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 ‡ This instruction replaces CNFD and CNFP in the SMJ320C25 instruction set. SM320C26B www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 Copyright© 2012,Texas InstrumentsIncorporated FunctionalOverview 19 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com

3.12.1 Development Support

Together,Texas Instrumentsand itsauthorizedthird-partysuppliersofferan extensivelineof development supportproductsto assistthe user in allaspectsof TMS320 second-generation-based designand development.These productsrange from developmentand applicationsoftwaretocomplete hardware developmentand evaluationsystems.Table 3 liststhe developmentsupportproductsforthe second-generationTMS320 devices. System developmentmay beginwiththeuse ofthesimulator,SoftwareDevelopmentSystem (SWDS), or emulator(XDS) along withan assembler/linker.These toolsgivethe TMS320 user variousmeans of evaluation,fromsoftwaresimulationofthesecond-generationTMS320s (simulator)tofull-speedin-circuit emulationwithhardwareand softwarebreakpointtraceand timingcapabilities(XDS). Softwareand hardware can be developed simultaneouslyby using the macro assembler/linker,C compiler,and simulatorforsoftwaredevelopment,theXDS forhardwaredevelopment,and theSoftware DevelopmentSystem forbothsoftwaredevelopmentand limitedhardwaredevelopment. Many third-partyvendors offeradditionaldevelopment supportforthe second-generationTMS320s, includingassembler/linkers,simulators,high-levellanguages, applicationssoftware, algorithm developmenttools,applicationsboards,softwaredevelopmentboards,and in-circuitemulators.Referto the TMS320 Family Development Support Reference Guide (SPRU011 ) forfurtherinformationabout TMS320 developmentsupportproductsofferedby bothTexas Instrumentsand itsthird-partysuppliers. Additionalsupportforthe TMS320 productsconsistsof an extensivelibraryof productand applications documentation.Three-dayDSP designworkshops are offeredby the TI RegionalTechnologyCenters (RTCs).These workshops provideinsightintothe architectureand the instructionset of the second- generationTMS320s as wellas hands-on trainingwiththe TMS320 developmenttools.When technical questionsariseregardingthe TMS320 family,contactthe Texas InstrumentsTMS320 Hotlineat (713) 274–2320.Or,keep informedon thelatestTIand third-partydevelopmentsupporttoolsby accessingthe DSP BulletinBoard Service(BBS) at (713)274–2323. The BBS serves 2400-,1200-,and 300-bps modems. Also,TMS320 applicationsourcecode may be downloadedfromtheBBS. Table3-3givesa completelistofSM320C26B softwareand hardwaredevelopmenttools.

20 FunctionalOverview Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 Table3-3.SM320C26B Softwareand Hardware Support MACRO ASSEMBLER AND LINKER Host Computer OperatingSystem PartNumber DEC VAX VMS TMDS3242250-08 IBM PC MS/PS DOS TMDS3242850-02 VAX ULTRIX TMDS3242260-08 SUN 3 UNIX TMDS3242550-08 C COMPILER AND MACRO ASSEMBLER/LINKER Host Computer OperatingSystem PartNumber DEC VAX VMS TMDS3242255-08 IBM PC MS/PC DOS TMDS3242855-02 VAX ULTRIX TMDS3242265-08 SUN 3 UNIX TMDS3242555-08 SIMULATOR Host Computer OperatingSystem PartNumber DEC VAX VMS TMDS3242251-08 IBM PC MS/PC DOS TMDS3242851-02 EMULATOR Model Power Supply PartNumber XDS/22 INCLUDED TMDS3262292 SOFTWARE DEVELOPMENT SYSTEM ON PC Host Computer OperatingSystem PartNumber IBM PC MS/PC DOS TMDX3268828 IBM PC MS/PC DOS TMDX3268821 (1) (1) Includesassembler/linker Copyright© 2012,Texas InstrumentsIncorporated FunctionalOverview 21 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com

4 ElectricalSpecifications

4.1 AbsoluteMaximum Ratings(1)(2)

Unlessotherwisenoted,thelistofabsolutemaximum ratingsarespecifiedoveroperatingtemperatureranges. Supplyvoltagerange,VCC –0.3V to7 V Inputvoltagerange –0.3V to7 V Outputvoltagerange –0.3V to7 V Continuouspower dissipation 1 W Operatingambienttemperaturerange –55°C to125°C Storagetemperaturerange,Tstg –55°C to150°C (1) Stressesbeyond thoselistedunderAbsoluteMaximum Ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderSection4.3isnotimplied. Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) AllvoltagevaluesarewithrespecttoVSS ,unlessotherwisenoted.

4.2 Thermal Information

68 PINS

θJA Junction-to-ambientthermalresistance(1) 25.6 θJCtop Junction-to-case(top)thermalresistance(2) N/A θJB Junction-to-boardthermalresistance(3) 11.2 °C/W ψJT Junction-to-topcharacterizationparameter(4) 2.9 ψJB Junction-to-boardcharacterizationparameter(5) 10.9 θJCbot Junction-to-case(bottom)thermalresistance(6) 1.1 (1) The junction-to-ambientthermalresistanceundernaturalconvectionisobtainedina simulationon a JEDEC-standard,high-Kboard,as specifiedinJESD51-7,inan environmentdescribedinJESD51-2a. (2) The junction-to-case(top)thermalresistanceisobtainedby simulatinga coldplateteston thepackage top.No specificJEDEC- standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. (3) The junction-to-boardthermalresistanceisobtainedby simulatinginan environmentwitha ringcoldplatefixturetocontrolthePCB temperature,as describedinJESD51-8. (4) The junction-to-topcharacterizationparameter,ψJT,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingθJA,usinga proceduredescribedinJESD51-2a (sections6 and 7). (5) The junction-to-boardcharacterizationparameter,ψJB,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingθJA ,usinga proceduredescribedinJESD51-2a (sections6 and 7). (6) The junction-to-case(bottom)thermalresistanceisobtainedby simulatinga coldplateteston theexposed (power)pad.No specific JEDEC standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. Spacer

4.3 Recommended OperatingConditions(1)

overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Supplyvoltage,VCC 4.5 5 5.5 V Supplyground,VSS 0 V D15 –D0, FSX 2.2 High-levelinputvoltage,VIH CLKIN, CLKR, CLKX 3.50 V Allotherinputs 3 D15 –D0, FSX, CLKIN, CLKR, CLKX 0.8 Low-levelinputvoltage,VIL V Allotherinputs 0.7 High-leveloutputcurrent,IOH 300 µA Low-leveloutputcurrent,IOL 2 mA Operatingfree-airtemperature,TC -55 125 °C (1) TC MAX atmaximum ratedoperatingconditionsatany pointon case TC MIN atinitial(timezero)power up.

22 ElectricalSpecifications Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012

4.4 ElectricalCharacteristics

overrecommended operatingconditions(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT VOH High-leveloutputvoltage VCC = MIN, IOH = MAX 2.4 3 V VOL Low-leveloutputvoltage VCC = MIN, IOH = MAX 0.3 0.6 V High-impedance-stateoutputleakageIOZ VCC = MAX -20 20 µAcurrent II Inputcurrent VI= VSS toVCC -10 10 µA Normal 185 ICC Supplycurrent VCC = MAX, fx = MAX mA Idle/HOLD 100 C I Inputcapacitance 15 pF C O Outputcapacitance 15 pF (1) AlltypicalvaluesareatVCC = 5 V,TA = 25°C. Copyright© 2012,Texas InstrumentsIncorporated ElectricalSpecifications 23 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com

5 Clock Characteristicsand Timing

5.1 InternalClock Option

The internaloscillatorisenabledby connectinga crystalacrossX1 and X2/CLKIN (seeFigure5-1).The frequencyof CLKOUT1 isone-fourththe crystalfundamentalfrequency.The crystalshouldbe either fundamentalorovertonemode, and parallelresonant,withan effectiveseriesresistanceof30 Ω,a power dissipationof 1 mW, and be specifiedat a loadcapacitanceof 20 pF. Note thatovertoneof crystals requirean additionaltuned LC circuit(see the applicationreport,Hardware Interfacingto the TMS320C25).

5.2 InternalClock Option

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fx Inputclockfrequency(1) TA = –55°C MIN 6.7 40 MHz C1, C2 TC = 125°C MAX 10 pF (1) Thisparameterisnotproductiontested. Figure5-1.InternalClock Option

24 ClockCharacteristicsand Timing Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

CL = 80 pF IOH/IOL SM320C26B www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012

5.3 ExternalClock Option

An externalfrequencysourcecan be used by injectingthefrequencydirectlyintoX2/CLKIN withX1 left unconnected.The externalfrequencyinjectedmust conform to the specificationslistedinthe following table.

5.4 SwitchingCharacteristicsOver Recommended OperatingConditions(1)

PARAMETER MIN TYP MAX UNIT tc(C) Cycletime,CLKOUT1/CLKOUT2 100 600 ns td(CIH-C) Delaytime,CLKIN hightoCLKOUT1/CLKOUT2/ STRB high/low 5 32 ns Delaytime,CLKOUT1 hightoCLKOUT2 low,td(C1-C2) Q -6 Q Q + 6 nsDelaytime,CLKOUT2 hightoCLKOUT1 high,etc. tf(C) Falltime,CLKOUT1/CLKOUT2/ STRB 5 ns tr(C) Risetime,CLKOUT1/CLKOUT2/ STRB 5 ns tw(CL) Pulseduration,CLKOUT1/CLKOUT2 low 2Q -8 2Q 2Q + 8 ns tw(CH) Pulseduration,CLKOUT1/CLKOUT2 high 2Q -8 2Q 2Q + 8 ns (1) Q = 1/4tc(C)

5.5 Timing Requirements Over Recommended OperatingConditions(1)

tc(Cl) Cycletime,CLKIN 25 150 ns tw(CIL) Pulseduration,CLKIN low,tc(CI)= 25 ns(2) 10 15 ns tw(CIH) Pulseduration,CLKIN high,tc(CI)= 25 ns (2) 10 15 ns tsu(S) Setuptime,SYNC beforeCLKIN low 5 Q -5 ns th(S) Holdtime,SYNC fromCLKIN low 8 ns (1) Q = 1/4tc(C) (2) Riseand falltimes,assuminga 40–60% dutycycle,areincorporatedwithinthisspecificationCLKIN riseand falltimesmust be lessthan 5 ns. Figure5-2.TestLoad Circuit Copyright© 2012,Texas InstrumentsIncorporated ClockCharacteristicsand Timing 25 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

VIH (MIN) VIL (MAX) VOH (MIN) VOL (MAX) 90% 10% (a) Input 2.4 V (b) Outputs 2.2 V 0.8 V 0.6 V SM320C26B SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com Figure5-3.VoltageReferenceLevels

26 ClockCharacteristicsand Timing Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012

6 Memory and PeripheralInterfaceTiming

6.1 SwitchingCharacteristicsOver Recommended OperatingConditions(1)

PARAMETER MIN TYP MAX UNIT td(C1–S) STRB fromCLKOUT1 (ifSTRB ispresent) Q – 6 Q Q + 6 ns td(C2–S) CLKOUT2 toSTRB (ifSTRB ispresent) –6 0 6 ns tsu(A) AddresssetuptimebeforeSTRB low(2) Q – 12 ns th(A) AddressholdtimeafterSTRB high(2) Q – 8 ns tw(SL) STRB lowpulseduration(nowaitstates)(3) 2Q – 5 2Q 2Q + 5 ns tw(SH) STRB highpulseduration(betweenconsecutivecycles)(3) 2Q ns tsu(D)W Data writesetuptimebeforeSTRB high(nowaitstates) 2Q – 20 ns th(D)W Data writeholdtimefromSTRB high Q – 10 Q ns ten(D) Data bus startsbeingdrivenafterSTRB low(writecycle) 0(4) ns tdis(D) Data bus three-stateafterSTRB high(writecycle) Q Q + 15(4) ns td(MSC) MSC validfromCLKOUT1 –10(4) 0 10 ns (1) Q = 1/4tc(C) (2) A15–A0,PS, DS, IS,R/W, and BR timingsareallincludedintimingsreferencedas ”address”. (3) Delaysbetween CLKOUT1 orCLKOUT2 edges and STRB edges trackeach other,resultingintw(SL) and tw(SH) being2Q withno wait states. (4) Thisparameterisnotproductiontested.

6.2 Timing Requirements Over Recommended OperatingConditions(1)

ta(A) Access time,readdatafromaddresstime(readcycle)(2) 3Q – 40 ns tsu(D)R Setuptime,datareadbeforeSTRB high 23 ns th(D)R Holdtime,datareadfromSTRB high 0 ns td(SL–R) Delaytime,READY validafterSTRB low(nowaitstates) Q – 22 ns td(C2H–R) Delaytime,READY validafterCLKOUT2 high Q – 22(3) ns th(SL–R) Holdtime,READY afterSTRB low(nowaitstates) Q + 3 ns th(C2H–R) Holdtime,READY afterCLKOUT2 high Q + 3(3) ns td(M–R) Delaytime,READY validafterMSC valid 2Q – 25(3) ns th(M–R) Holdtime,READY afterMSC valid 0(3) ns (1) Q = 1/4tc(C) (2) Read dataaccesstimeisdefinedas ta(A)= tsu(A)+ tw(SL) – tsu(D)R + tr(C). (3) Thisparameterisnotproductiontested. Copyright© 2012,Texas InstrumentsIncorporated Memory and PeripheralInterfaceTiming 27 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com

7 RS ,INT,BIO,and XF Timing

7.1 SwitchingCharacteristicsOver Recommended OperatingConditions(1)

overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER MIN TYP MAX UNIT td(RS) Delaytime,CLKOUT1 lowtoresetstateentered 22(2) ns td(IACK) Delaytime,CLKOUT1 toIACK valid –8(2) 0 8 ns td(XF) Delaytime,XF validbeforefallingedge ofSTRB Q – 12 ns (1) Q = 1/4tc(C) (2) Thisparameterisnotproductiontested.

7.2 Timing Requirements Over Recommended OperatingConditions(1)

tsu(IN) Setuptime,INT/BIO/RS beforeCLKOUT1 high(2) 32 ns th(IN) Holdtime,INT/BIO/RS afterCLKOUT1 high(2) 0 ns tw(IN) Pulseduration,INT/BIO low tc(C) ns tw(RS) Pulseduration,RS low 3tc(C) ns (1) Q = 1/4tc(C) (2) RS, INT,and BIO areasynchronousinputsand can occuratany timeduringa clockcycle.However,ifthespecifiedsetuptimeismet, theexactsequence shown inthetimingdiagramwilloccur.INT/BIO falltimemust be lessthan8 ns.

28 RS, INT,BIO,and XF Timing Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012

8 HOLD Timing

8.1 SwitchingCharacteristicsOver Recommended OperatingConditions(1)

overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER MIN TYP MAX UNIT td(C1L-AL) Delaytime,HOLDA lowafterCLKOUT1 low –1(2) 10 ns tdis(AL-A) Disabletime,HOLDA lowtoaddressthree-state 0 ns tdis(C1L-A) Disabletime,addressthree-stateafterCLKOUT1 low(HOLD mode) (3) 20(2) ns td(HH-AH) Delaytime,HOLD hightoHOLDA high 25 ns ten(A-C1L) Enabletime,addressdrivenbeforeCLKOUT1 low(HOLD mode)(3) 8(2) ns (1) Q = 1/4tc(C) (2) Thisparameterisnotproductiontested. (3) A15–A0,PS, DS, IS,STRB, and R/W timingsareallincludedintimingsreferencedas ’”address”.

8.2 Timing Requirements Over Recommended OperatingConditions(1)

td(C2H-H) Delaytime,HOLD validafterCLKOUT2 high Q – 24 ns (1) Q = 1/4tc(C) Copyright© 2012,Texas InstrumentsIncorporated HOLD Timing 29 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com

9 SerialPortTiming

9.1 SwitchingCharacteristicsOver Recommended OperatingConditions(1)

overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER MIN TYP MAX UNIT td(CH-DX) Delaytime,DX validafterCLKX risingedge(2) 80 ns td(FL-DX) Delaytime,DX validafterFSX fallingedge (TXM = 0)(2) 45 ns td(CH-FS) FSX validafterCLKX risingedge (TXM = 1) 45 ns (1) Q = 1/4tc(C) (2) The lastoccurrenceofFSX fallingand CLKX rising.

9.2 Timing Requirements Over Recommended OperatingConditions(1)

fsx Serialportfrequency 1.25 5000 kHz tc(SCK) Serialportclock(CLKX/CLKR) cycletime 200 800000 ns tw(SCK1 Serialportclock(CLKX/CLKR) lowpulseduration(2) 80 ns tw(SCK) Serialportclock(CLKX/CLKR) highpulseduration(2) 80 ns tsu(FS) FSX/FSR setuptimebeforeCLKX/CLKR fallingedge (TXM = 0) 18 ns th(FS) FSX/FSR holdtimeafterCLKX/CLKR fallingedge (TXM = 0) 20 ns tsu(DR) OR setuptimebeforeCLKR fallingedge 10 ns th(DR) OR holdtimeafterCLKR fallingedge 20 ns (1) Q = 1/4tc(C) (2) The dutycycleoftheserialportclockmust be within40–60% .Serialportclock(CLKX/CLKR) riseand falltimesmust be lessthan 25 ns.

30 SerialPortTiming Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

tc(CI) tf(CI) tr(CI) tw(CIH) tw(CIL) th(S) tsu(S) td(CIH-C) td(CIH-C) tw(CL) tc(C) tw(CH) tf(C)tr(C)td(CIH-C) tc(C) tw(CL) tr(C)tf(C) tw(CH) td(C1-C2) td(CIH-C) td(C1-C2) td(C1-C2) td(C1-C2) tsu(S) SM320C26B www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012

10 Timing Diagrams

Timingmeasurements are referencedto and from a low voltageof 0.8 V and a highvoltageof 2.2 V unlessotherwisenoted. Figure10-1.Clock Timing Copyright© 2012,Texas InstrumentsIncorporated TimingDiagrams 31 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

tsu(A) CLKOUT1 CLKOUT2 A15–A0, BR , PS, DS, OR IS R/W READY D15–D0 STRB th(A) th(D)Wtsu(D)W ten(D) tdis(D) V ALID DA TA OUT td(C1-S) td(C1-S) td(C2-S)td(C2-S) tw(SL) tw(SH) th(A)tsu(A) ta(A) tsu(D)R td(SL-R) th(D)R CLKOUT1 CLKOUT2 A15–A0, BR , PS, DS, OR IS R/W READY D15–D0 STRB DA TA IN V ALID th(SL-R) SM320C26B SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com Figure10-2.Memory Read Timing Figure10-3.Memory WriteTiming

32 TimingDiagrams Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

A15-A0, BR, PS, DS, R/W or IS MSC READY D15-D0 (For Read Operation) Data In Data Out th(C2H-R) Valid D15-D0 (For Write Operation) td(C2H-R) td(M-R) th(M-R)td(M-R) td(MSC) td(MSC) th(C2H-R) td(C2H-R) th(M-R) SM320C26B www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 Figure10-4.One Wait-StateMemory Access Timing Copyright© 2012,Texas InstrumentsIncorporated TimingDiagrams 33 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

FETCH N FETCH N + 1 FETCH I FETCH I + 1 tsu(IN) th(IN) tw(IN) td(IACK)tf(IN) td(IACK) CLKOUT1 RS A15-A0 D15-D0 PS STRB Control Signals† IACK Serial Port Control‡ Fetch Location 0 Begin Program Execution Valid Valid td(RS) tsu(IN) th(IN) tsu(IN) tw(RS) † Control signals are DS, IS, R/W, and XF. ‡ Serial port controls are DX and FSX. SM320C26B SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com Figure10-5.Reset Timing Figure10-6.InterruptTiming

34 TimingDiagrams Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

td(XF) PC = N PC = N + 1 PC = N + 2 PC = N + 3 ValidFETCH SXF/RXF Valid Valid Valid CLKOUT1 STRB BIO A15–A0 th(IN) VALID tsu(IN) PC = N PC = N + 1 PC = N + 3 OR BRANCH ADDRESS FETCH NEXT INSTRUCTION FETCH BRANCH ADDRESSFETCH BIOZ PC = N + 2 SM320C26B www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 Figure10-7.BIO Timing Figure10-8.ExternalFlagTiming Copyright© 2012,Texas InstrumentsIncorporated TimingDiagrams 35 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

PS, DS, or IS R/W D15-D0 HOLDA FETCH EXECUTE td(C2H-H)† tdis(C1L-A) tdis(AL-A) td(C1L-AL) In In N N + 1 N + 2 Valid Valid N N - 2 N - 1 N – † HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown occurs; otherwise, a delay of one CLKOUT2 cycle occurs. N + 1 – – SM320C26B SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com Figure10-9.HOLD Timing (PartA)

36 TimingDiagrams Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

PS, DS, or IS R/W D15-D0 HOLDA A15-A0 FETCH EXECUTE td(C2H-H)† In N + 2 N + 2 Valid – – – N N + 2 – – – N N + 1 ten(A-C1L) td(HH-AH) † HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown occurs; otherwise, a delay of one CLKOUT2 cycle occurs. SM320C26B www.ti.com SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 Figure10-10.HOLD Timing (PartB) Copyright© 2012,Texas InstrumentsIncorporated TimingDiagrams 37 SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

(Input, TXM = 0) DX FSX (Output, TXM = 1) tc(SCK) tr(SCK)tw(SCK) tf(SCK) tw(SCK) td(CH-DX) th(FS) td(FL-DX) td(CH-DX)tsu(FS) td(CH-FS) td(CH-FS) N = 1 N = 8,16 tc(SCK) tw(SCK) tw(SCK) tf(SCK)th(DR) th(FS) tsu(DR) tsu(FS) CLKR FSR DR tr(SCK) SM320C26B SGUS069A –NOVEMBER 2012–REVISED NOVEMBER 2012 www.ti.com Figure10-11.SerialPortReceive Timing Figure10-12.SerialPortTransmitTiming

38 TimingDiagrams Copyright© 2012,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLinks:SM320C26B

www.ti.com 5-May-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SM320C26BGBM OBSOLETE CPGA GB 68 TBD Call TI Call TI -55 to 125 SM320C26BGBM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 5-May-2015 Addendum-Page 2 OTHER QUALIFIED VERSIONS OF SM320C26B :

• Catalog: TMS320C26B
• Military: SMJ320C26B NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications

MCPG023A – OCTOBER 1997 – REVISED DECEMBER 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GB (S-CPGA-P68) CERAMIC PIN GRID ARRAY 7893456 J H G F E D B A C 0.800 (20,32) TYP 4040114-14/D 11/01 0.970 (24,63) 0.072 (1,83) 0.088 (2,23) 0.536 (13,61) 0.524 (13,31) 0.950 (24,13)

4 Places

0.050 (1,27) DIA 0.018 (0,46) DIA TYP 0.166 (4,16) 0.194 (4,98) 0.055 (1,39) 0.045 (1,14) 0.100 (2,54) A1 Corner Bottom View NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Index mark may appear on top or bottom depending vendor. D. Pins are located within 0.010 (0,25) diameter of true position relative to each other at maximum material condition and within 0.030 (0,76) diameter relative to the edges of the ceramic. E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit. F. The pins can be gold plated or solder dipped. G. Falls within MIL STD 1835 CMGA1-PN, CMGA13-PN and JEDEC MO-067 AA, MO-066 AA respectively

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic”are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated