TMDS181IRGZR

TMDS181 TI | Alldatasheet

Document overview

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Technical content

IN_CLKp IN_CLKn IN_D[2:0]p IN_D[2:0]n 50Q 50Q50Q 50Q Data Registers SWAP PLL PLL Control SERDES Polarity VBIAS VBIAS OUT_CLKp OUT_D[2:0]p OUT_CLKn OUT_D[2:0]n EQ EQ SDA_CTL SCL_CTL VSADJ TMDS TMDS ACTIVE DDC BLOCK HPD_SNKHPD_SRC 190<Q SDA_SRC SCL_SRC SDA_SNK SCL_SNK SPDIF_IN ARC_OUT GND VDD VCC 1.2V 3.3VVREG GPU HDMI Conn 7.06 lQ Control6 DDC Snoop Block Control Block, I2C Registers, DDC. ARCLocal I2C Control ARC Copyright © 2016, Texas Instruments Incorporated Interface Unit Digital TV Audiovisual Processing Unit HDMI SW/HD TMDS 181 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMDS181, TMDS181I SLASE75D – AUGUST 2015– REVISED SEPTEMBER 2017 TMDS181x6GbpsTMDSRetimer

1 Features

1• HDMI™ Input Port to Output Port With CDR Supporting Up to 6 Gbps Data Rates

• Compatible With HDMI™ Electrical Parameters Up to 6 Gbps in Retimer Mode
• Support 4k2k60p and Up to WUXGA 16-Bit Color Depth or 1080p With Higher Refresh Rates
• Retimes Input Stream to Compensate for Random Jitter
• Adaptive Receiver Equalizer or Programmable Fixed Equalizer
• I2C and Pin Strap Programmable
• Inter-Pair Skew Compensation of 5+ Bits
• Single-Ended Mode ARC Support
• Link Debug Tools Including Eye Diagram After the RX Equalizer
• 48-Pin 7-mm × 7-mm 0.5-mm Pitch VQFN Package
• Extended Commercial Temperature Support 0°C to 85°C (TMDS181)
• Industrial Temperature Support: –40°C to 85°C (TMDS181I)

2 Applications

• Digital TV
• Digital Projector
• Audio/Video Equipment
• Blu-ray™ DVD
• Monitors
• Desktops/ All-in-Ones
• Active Cables

3 Description

The TMDS181x is a digital video interface (DVI) or high-definition multimedia interface (HDMI™ ) retimer. The TMDS181x supports four TMDS channels, audio return channel (SPDIF_IN/ARC_OUT), and digital display control (DDC) interfaces. The TMDS181x supports signaling rates up to 6 Gbps to allow for the highest resolutions of 4k2k60p 24 bits per pixel and up to WUXGA 16-bit color depth or 1080p with higher refresh rates. The TMDS181x can be configured to support the HDMI2.0a standard. The TMDS181x automatically configures itself as a redriver at low data rate (<1.0 Gbps) or as a retimer above this data rate. Redriver mode supports HDMI1.4b with data rates up to 3.4 Gbps The TMDS181x supports dual power supply rails of 1.2 V on VDD and 3.3 V on VCC for power reduction. Several methods of power management are implemented to reduce overall power consumption. TMDS181x supports fixed receive EQ gain or adaptive receive EQ control by I2C or pin strap to compensate for different lengths input cable or board traces. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TMDS181 VQFN (48) 7.00 mm × 7.00 mm TMDS181I (1) For all available packages, see the orderable addendum at the end of the data sheet. SPACE Simplified Schematic

TMDS181, TMDS181I SLASE75D –AUGUST 2015– REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: TMDS181 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Table of Contents

6.7 TMDS Differential Output Electrical

6.8 DDC, I2C, HPD, and ARC Electrical

12.3 Receiving Notification of Documentation Updates 50

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (July 2016) to Revision D Page Changes from Revision B (April 2016) to Revision C Page Changes from Revision A (October 2015) to Revision B Page

• DDC Functional Description , Changed text "address 22h (see Figure 31) through the I2C interface." To: "address

TMDS181, TMDS181I www.ti.com SLASE75D – AUGUST 2015– REVISED SEPTEMBER 2017 Product Folder Links: TMDS181 Submit Documentation FeedbackCopyright © 2015–2017, Texas Instruments Incorporated Changes from Original (August 2015) to Revision A Page

• Recommended Operating Conditions, Updated the note showing the values shown are only for Microcontroller
• Pin Strapping Configuration for HDMI2.0a and HDMI1.4b , Added Note for VSADJ resistor value in Compliance Pin
• Pin Strapping Configuration for HDMI2.0a and HDMI1.4b , Changed De-emphasis value from 0 dB to -2 dB for
• I2C Control for HDMI2.0a and HDMI1.4b, Added Note for VSADJ resistor value in Compliance I2C control section

HPD_SRC SDA_SRC SCL_SRC GND OUT_D0p OUT_D0n SDA_SNK SCL_SNK OE VDD VDD TX_TERM_CTL SCL_CTL NC SPDIF_IN GND SIG_EN VDD ARC_OUT I2C_EN/PIN VDD VCC VDD VCC GND HPD_SNK PRE_SEL EQ_SEL/A0 SDA_CTL IN_D1n IN_D1p IN_D2n IN_D2p IN_D0n IN_D0p IN_CLKn IN_CLKp OUT_D2p OUT_D2n OUT_D1p OUT_D1n OUT_CLKp OUT_CLKn SWAP/POL GND 3738394142434445464748 21 2423222019181716151413 TMDS181, TMDS181I SLASE75D –AUGUST 2015– REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: TMDS181 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated

5 Pin Configuration and Functions

TMDS181, TMDS181I www.ti.com SLASE75D – AUGUST 2015– REVISED SEPTEMBER 2017 Product Folder Links: TMDS181 Submit Documentation FeedbackCopyright © 2015–2017, Texas Instruments Incorporated (1) (H) Logic high (pin strapped to VCC through 65 kΩ resistor); (L) Logic Low (pin strapped to GND through 65 kΩ resistor); (for mid-level = No connect) (2) G = Ground, I = Input, O = Output, P = Power Pin Functions(1) PIN TYPE(2) DESCRIPTION NAME NO. VCC 13, 43 P 3.3 V power supply VDD 14, 23, 24, 37, 48 P 1.2 V power supply GND 7, 19, 41, 30, Thermal pad G Ground MAIN LINK INPUT PINS IN_D2p/n 2, 3 I Channel 2 differential input IN_D1p/n 5, 6 I Channel 1 differential input IN_D0p/n 8, 9 I Channel 0 differential input IN_CLKp/n 11, 12 I Clock differential input MAIN LINK OUTPUT PINS (FAIL SAFE) OUT_D2n/p 34, 35 O TMDS data 2 differential output OUT_D1n/p 31, 32 O TMDS data 1 differential output OUT_D0n/p 28, 29 O TMDS data 0 differential output OUT_CLKn/p 25, 26 O TMDS data clock differential output HOT PLUG DETECT PINS HPD_SRC 4 O Hot plug detect output to source side HPD_SNK 33 I Hot plug detect input from sink side AUDIO RETURN CHANNEL AND DDC PINS SPDIF_IN ARC_OUT

44 I/O SPDIF signal input

Audio return channel output SDA_SRC SCL_SRC

46 I/O Source side TMDS port bidirectional DDC data line

Source side TMDS port bidirectional DDC clock line SDA_SNK SCL_SNK

38 I/O Sink side TMDS port bidirectional DDC data line

Sink side TMDS port bidirectional DDC clock line CONTROL PINS OE 42 I Operation enable/reset pin OE = L: Power-down mode OE = H: Normal operation Internal weak pull up: Resets device when transitions from H to L SIG_EN 17 I Signal detector circuit enable SIG_EN = L: Signal detect circuit disabled: SIG_EN = H: Signal detect circuit enabled: When no valid clock device enters standby mode. Internal weak pull down PRE_SEL 20 I 3 level De-emphasis control when I2C_EN/PIN = Low. PRE_SEL = L: –2 dB PRE_SEL = No Connect: 0 dB PRE_SEL = H: Reserved When I2C_EN/PIN = High de-emphasis is controlled through I2C EQ_SEL/A0 21 I 3 level Input receive equalization pin strap when I2C_EN/PIN = Low EQ_SEL = L: Fixed EQ at 7.5 dB at 3 GHz EQ_SEL = No Connect: Adaptive EQ EQ_SEL = H: Fixed at 14 dB at 3 GHz When I2C_EN/PIN = High address bit 1 Note: 3 level for pin strap programming but 2 level when I2C address I2C_EN/PIN 10 I I2C_EN/PIN = High; puts device into I2C Control Mode I2C_EN/PIN = Low; puts device into pin strap mode Note: I2C CSR is addressable at all times, but features that can be controlled by pin strapping can only be changed by I2C when this pin is pulled high SCL_CTL 15 I I2C clock signal Note: When I2C_EN = Low Pin strapping takes priority and those functions cannot be changed by I2C

TMDS181, TMDS181I SLASE75D –AUGUST 2015– REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: TMDS181 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Pin Functions(1) (continued) PIN TYPE(2) DESCRIPTION NAME NO. SDA_CTL 16 I/0 I2C data signal Note: When I2C_EN = Low Pin strapping takes priority and those functions cannot be changed by I2C VSadj 22 I TMDS-compliant voltage swing control nominal resistor to GND A1 27 I High address bit 2 for I2C programming Weak internal pull down Note: When in Pin Strapping Mode leave pin as No connect TX_TERM_CTL 36 I 3 level Transmit termination control TX_TERM_CTL = H, no transmit termination TX_TERM_CTL = L, transmit termination impedance in approximately 75 to 150 Ω TX_TERM_CTL = No Connect, automatically selects the termination impedance Data rate (DR) > 3.4 Gbps – 75 to 150 Ω differential near end termination 2 Gbps > DR < 3.4 Gbps – 150 to 300 Ω differential near end termination DR < 2 Gbps – no termination Note: If left floating will be in automatic select mode. SWAP/POL 1 I 3 level Input lane SWAP and polarity control pin SWAP/POL = H: receive lanes polarity swap (retimer mode only) SWAP/POL = L: receive lanes swap (redriver and retimer mode) SWAP/POL = No Connect: normal operation NC 18, 40 NA No connect (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-B

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2) MIN MAX UNIT Supply voltage(3) VCC –0.3 4 V VDD –0.3 1.4 Voltage Main link input differential voltage (IN_Dx, IN_CLKx) IIN = 15mA VCC - 0.75V VCC + 0.3V V TMDS outputs ( OUT_Dx) –0.3 4 HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, A1, PRE_SEL, EQ_SEL/A0, I2C_EN/PIN, SIG_EN, TX_TERM_CTL, –0.3 4 HDP_SNK, SDA_SNK, SCL_SNK, SDA_SRC, SCL_SRC –0.3 6 Input Current IIN Main link input current (IN_Dx, IN_CLKx) 15 mA Continuous power dissipation See Thermal Information Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500

TMDS181, TMDS181I www.ti.com SLASE75D – AUGUST 2015– REVISED SEPTEMBER 2017 Product Folder Links: TMDS181 Submit Documentation FeedbackCopyright © 2015–2017, Texas Instruments Incorporated (1) These values are based upon a microcontroller driving the control pins. The pullup/pulldown/floating resistor configuration will set the internal bias to the proper voltage level which will not match the values shown here. (2) This value is based upon a microcontroller driving the OE pin. A passive reset circuit using an external capacitor and the internal pullup resistor will set OE pin properly, but may have a different value than shown due to internal biasing.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Supply voltage nominal value 3.3 V 3.135 3.3 3.465 V VDD Supply voltage nominal value 1.2 V 1.1 1.2 1.27 V TCASE Case temperature 92.7 °C TA Operating free-air temperature TMDS181 0 85 °C TMDS181I –40 85 °C MAIN LINK DIFFERENTIAL PINS VID_PP Peak-to-peak input differential voltage 75 1560 mVpp VIC Input common mode voltage VCC – 0.4 VCC + 0.1 V dR Data rate 0.25 6 Gbps RVSADJ TMDS compliant swing voltage bias resistor nominal 4.5 7.06 kΩ CONTROL PINS VI-DC DC input voltage Control pins –0.3 3.6 V VIL (1) Low-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL pins only 0.3 V Low-level input voltage at OE 0.8 VIM (1) Mid-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL pins only 1 1.2 1.4 V VIH (1) High-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL, OE(2) pins only 2.6 V VOL Low-level output voltage 0.4 V VOH High-level output voltage 2.4 V IIH High-level input current –30 30 µA IIL Low-level input current –25 25 µA IOS Short-circuit output current –50 50 mA IOZ High impedance output current 10 µA ROEPU Pullup resistance on OE pin 150 250 kΩ

TMDS181, TMDS181I SLASE75D –AUGUST 2015– REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: TMDS181 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Test conditions for ΨJB and ΨJT are clarified in the Semiconductor and IC Package Thermal Metrics.

6.4 Thermal Information

THERMAL METRIC(1)(2) TMDS181x UNITRGZ (VQFN)

48 PINS

RθJA Junction-to-ambient thermal resistance 31.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 18.2 °C/W RθJB Junction-to-board thermal resistance 8.1 °C/W ψJT Junction-to-top characterization parameter 0.4 °C/W ψJB Junction-to-board characterization parameter 8.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.2 °C/W (1) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C temperature unless otherwise noted (2) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C temperature unless otherwise noted (3) ICC is a direct result of the source design as the TMDS181x integrated receive termination resistor accounts for 85 to 110 mA. (4) IDD is impacted by ARC usage. Connecting a 500 kΩ resistor to GND at SPDIF reduces the value by more than 20 mA (5) The measurements were made with no active source connected.

6.5 Power Supply Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX(2) UNIT PD1 (3)(4) Device power dissipation (retimer operation) OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V IN_Dx: VID_PP = 1200 mV, 6 Gbps TMDS pattern, VI = 3.3 V, I2C_EN/PIN = L, PRE_SEL= NC, EQ_SEL= NC, SDA_CTL/CLK_CTL = 0 V 800 900 mW PD2 (3)(4) Device power dissipation (redriver operation) OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V IN_Dx: VID_PP = 1200 mV, 2.97 Gbps TMDS pattern, VI = 3.3 V, I2C_EN/PIN = L, PRE_SEL= NC, EQ_SEL= H, SDA_CTL/CLK_CTL = 0 V 500 600 mW PSD1 (3)(4)(5) Device power in standby OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V, HPD = H, No valid input signal 50 100 mW PSD2 (3)(4)(5) Device power in power down OE = L, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V 10 30 mW ICC1 (3)(4) VCC supply current (TMDS 6Gpbs retimer mode) OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V IN_Dx: VID_PP = 1200 mV, 6 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = NC, SDA_CTL/CLK_CTL = 0 V 131 150 mA IDD1 (3)(4) VDD supply current (TMDS 6Gpbs retimer mode) OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V IN_Dx: VID_PP = 1200 mV, 6 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = NC, SDA_CTL/CLK_CTL = 0 V 332 350 mA ICC2 (3)(4) VCC supply current (TMDS 6Gpbs redriver mode) OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V IN_Dx: VID_PP = 1200 mV, 2.97 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V 92 mA IDD2 (3)(4) VDD supply current (TMDS 6Gpbs redriver mode) OE = H, VCC= 3.3 V/3.465 V, VDD = 1.2 V/1.27 V IN_Dx: VID_PP = 1200 mV, 3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V 187 mA ISD1 (5) Standby current OE = H, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V, HPD = H: No valid signal on IN_CLK

3.3 V rail(3) 6 15

1.2 V rail 40 50

(5) Power-down current OE = L, VCC = 3.3 V/3.465 V, VDD = 1.2 V/1.27 V

3.3 V rail(3) 2 5

1.2 V rail 3.5 15

TMDS181, TMDS181I www.ti.com SLASE75D – AUGUST 2015– REVISED SEPTEMBER 2017 Product Folder Links: TMDS181 Submit Documentation FeedbackCopyright © 2015–2017, Texas Instruments Incorporated (1) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted (2) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted

6.6 TMDS Differential Input Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX(2) UNIT DR_RX_DATA_R T TMDS data lanes data rate (Retimer Mode) 0.25 6 Gbps DR_RX_DATA_R D TMDS data lanes data rate (Redriver Mode) 0.25 3.4 Gbps DR_RX_CLK TMDS clock lanes clock rate 25 340 MHz tRX_DUTY Input clock duty circle 40% 50% 60% tCLK_JIT Input clock jitter tolerance 0.3 Tbit tDATA_JIT Input data jitter tolerance Test the TTP2, see Figure 12 150 ps tRX_INTRA Input intrapair skew tolerance Test at TTP2 when DR = 1.6 Gbps, see Figure 12 112 ps tRX_INTER Input interpair skew tolerance 1.8 ns EQH(D) Fixed EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0 = H; fixed EQ gain, test at 6 Gbps 15 dB EQL(D) Fixed EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0 = L; fixed EQ gain, test at 6 Gbps 7.5 dB EQZ(D) Adaptive EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0 = NC; adaptive EQ (Retimer Mode Only) 2 15 dB EQ(c) EQ gain for clock lane IN_CLKn/p EQ_SEL/A0 = H,L,NC 3 dB RINT Input differential termination impedance 85 100 115 Ω VITERM Input termination voltage OE = H 3.3 3.465 V

TMDS181, TMDS181I SLASE75D –AUGUST 2015– REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: TMDS181 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated (1) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted (2) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted

6.7 TMDS Differential Output Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX(2) UNIT VOH Single-ended high level output voltage Data rate ≤1.65 Gbps PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ; VCC – 10 VCC + 10 V Single-ended high level output voltage Data rate >1.65 Gbps and <3.4 Gbps PRE_SEL = NC; TX_TERM_CTL = NC; OE = H; DR = 2.97 Gbps; VSadj = 7.06 kΩ; VCC-200 VCC + 10 Single-ended high level output voltage Data rate >3.4 Gbps and < 6 Gbps(2) PRE_SEL = NC; TX_TERM_CTL = L; OE = H; DR = 6 Gbps; VSadj = 7.06 kΩ; VCC – 400 VCC + 10 VOL Single-ended low level output voltage Data rate ≤1.65 Gbps PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ; VCC – 600 VCC – 400 V Single-ended low level output voltage Data rate >1.65 Gbps and <3.4 Gbps PRE_SEL = NC; TX_TERM_CTL = NC; OE = H; DR = 2.97 Gbps; VSadj = 7.06 kΩ; VCC – 700 VCC – 400 Single-ended low level output voltage Data rate >3.4 Gbps and < 6 Gbps(2) PRE_SEL = NC; TX_TERM_CTL = L; OE = H; DR = 6 Gbps; VSadj = 7.06 kΩ; VCC – 1000 VCC – 400 VSWING_DA Single-ended output voltage swing on data lane PRE_SEL = NC; TX_TERM_CTL = H/NC/L; OE = H; DR = 270 Mbps/2.97/6 Gbps VSadj = 7.06 kΩ; 400 500 600 mV VSWING_CLK Single-ended output voltage swing on clock lane PRE_SEL = NC; TX_TERM_CTL = H; OE = H; Data rate ≤ 3.4 Gbps; VSadj = 7.06 kΩ; 400 500 600 mV PRE_SEL = NC; TX_TERM_CTL = NC; OE = H; Data rate > 3.4 Gbps; VSadj = 7.06 kΩ; 200 300 400 ΔVSWING Change in single-end output voltage swing per 100 Ω ΔVSadj 20 mV ΔVOCM(SS) Change in steady state output common mode voltage between logic levels –5 5 mV VOD(PP) Output differential voltage before pre-emphasis VSADJ = 7.06 kΩ; PRE_SEL = NC see Figure 10 800 1200 mV VOD(SS) Steady state output differential voltage VSADJ = 7.06 kΩ; PRE_SEL = L, see Figure 11 600 1075 mV VOD_range Total TMDS data lanes output differential voltage for HDMI2.0. Retimer Mode Only See Figure 14 3.4 Gbps < Rbit ≤ 3.712 Gps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; VSadj = 7.06 kΩ; 335 mV 3.712 Gbps < Rbit < 5.94 Gbps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; VSadj = 7.06 kΩ; –19.66 × (Rbit 2) + (106.74 × Rbit) + 209.58 5.94 Gbps ≤ Rbit ≤ 6.0 Gbps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; VSadj = 7.06 kΩ; 150 IOS Short-circuit current limit Main link output shorted to GND 50 mA ILEAK Failsafe condition leakage current VCC = 0 V; VDD = 0 V; TMDS Outputs pulled to 3.3 V through 50 Ω resistor; 45 μA RTERM Source termination resistance for HDMI2.0 75 150 Ω

TMDS181, TMDS181I www.ti.com SLASE75D – AUGUST 2015– REVISED SEPTEMBER 2017 Product Folder Links: TMDS181 Submit Documentation FeedbackCopyright © 2015–2017, Texas Instruments Incorporated (1) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted (2) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted

6.8 DDC, I2C, HPD, and ARC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX(2) UNIT DDC AND I2C VI-DC SCL/SDA_SNK, SCL/SDA_SRC DC input voltage –0.3 5.5 V SCL/SDA_CTL, DC input voltage –0.3 3.6 V VIL SCL/SDA_SNK, SCL/SDA_SRC Low level input voltage 0.3 x VCC V SCL/SDA_CTL Low level input voltage 0.3 x VCC V VIH SCL/SDA_SNK, SCL/SDA_SRC high level input voltage 3 V SCL/SDA_CTL high level input voltage 0.7 x VCC V VOL SCL/SDA_CTL, SCL/SDA_SRC low level output voltage I0 = 3 mA and VCC > 2 V 0.4 V I0 = 3 mA and VCC < 2 V 0.2 x VCC fSCL SCL clock frequency fast I2C mode for local I2C control 400 kHz Cbus Total capacitive load for each bus line (DDC and local I2C pins) 400 pF HPD VIH High-level input voltage HPD_SNK 2.1 V VIL Low-level input voltage HPD_SNK 0.8 V VOH High-level output voltage IOH = –500 µA; HPD_SRC, 2.4 3.6 V VOL Low-level output voltage IOL = 500 µA; HPD_SRC, 0 0.1 V ILEAK Failsafe condition leakage current VCC = 0 V; VDD = 0 V; HPD_SNK =

5 V; 40 μA

IH_HPD High-level input current Device powered; VIH = 5 V; IH_HPD includes RpdHPD resistor current µA Device powered; VIL = 0.8 V; IL_HPD includes RpdHPD resistor current RpdHPD HPD input termination to GND VCC = 0 V 150 190 220 kΩ SPDIF AND ARC VEL Operating DC voltage for single mode ARC output Test at ARC_OUT, see Figure 22 0 5 V VIN_DC Operating DC voltage for SPDIF input 0.05 V VSP_SW Signal amplitude of SPDIF input 0.2 0.5 0.6 V VElSWING Signal amplitude on the ARC output Test at ARC_OUT, 55 Ω external termination resistor, see Figure 22 0.4 0.5 0.6 V CLK_ARC Signal frequency on ARC Test at ARC_OUT, see Figure 22 3.687 5.645 ±0.1% 13.517 MHz Duty cycle Output clock duty cycle 45% 50% 55% Data rate SPDIF input DR 7.373 11.29 27.034 Mbps tEDGE Rise/fall time for ARC output From 10% to 90% voltage level 0.4 UI R_IN_SPDIF Input termination resistance for SPDIF 75 Ω Rest Single mode output termination resistance

0.1 MHz to 128× the maximum

frame rate 36 55 75 Ω

6.9 Power-Up and Operation Timing Requirements

Figure 1. Power-Up Timing for TMDS181 Figure 2. CDR Timing for TMDS181

TMDS181, TMDS181I www.ti.com SLASE75D – AUGUST 2015– REVISED SEPTEMBER 2017 Product Folder Links: TMDS181 Submit Documentation FeedbackCopyright © 2015–2017, Texas Instruments Incorporated (1) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted (2) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted

6.10 TMDS Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX(2) UNIT REDRIVER MODE dR Data rate (redriver mode) 250 3400 Mbps tPLH Propagation delay time (low to high) 250 600 ps tPHL Propagation delay time (high to low) 250 800 ps tT1(1.4b) Transition time (rise and fall time); measured at 20% and 80% levels for data lanes. TMDS clock meets tT3 for all three times. TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; 1.48 Gbps and 2.97 Gbps data lines, 148 MHz and 297 MHz clock 75 ps tT3 TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; 1.48 Gbps, 2.97 Gbps 100 ps tSK_INTRA Intra-pair output skew Default setting for internal intra-pair skew adjust, TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps; See Figure 8 40 ps tSK_INTER Inter-pair output skew Default setting for internal inter-pair skew adjust, TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps; See Figure 8 100 ps tJITD1(1.4b) Total output data jitter HDMI1.4b DR = 2.97 Gbps, PRE_SEL = NC, EQ_SEL/A0 = NC ; . See Figure 12 at TTP3

0.2 Tbit

tJITC1(1.4b) Total output clock jitter CLK = 25 MHz, 74.25 MHz, 75 MHz, 150 MHz, 297 MHz 0.25 Tbit RETIMER MODE dR Data rate (retimer mode) 0.25 6 Gbps dXVR Automatic redriver to retimer crossover (when selected) Measured with input signal applied = 200 mVpp 0.75 1 1.25 Gbps fCROSSOVER Crossover frequency hysteresis 250 MHz PLLBW Data retimer PLL bandwidth Default loop bandwidth setting 0.4 1 MHz tACQ Input clock frequency detection and retimer acquisition time 180 µs IJT1 Input clock jitter tolerance Tested when data rate >1.0Gbps 0.3 Tbit tT1(2.0) Transition time (rise and fall time); measured at 20% and 80% levels for data lanes. TMDS clock meets tT3 for all three times. TX_TERM_CTL = L; PRE_SEL = NC; 6 Gbps data lines, 45 ps tT1 (1.4b) TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps and 2.97 Gbps data lines, 148 MHz and 297 MHz clock 75 ps tT3 TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data lines,

148 MHz, 297 MHz clock

tDCD OUT_CLK ± duty cycle 40% 50% 60% tSK_INTER Inter-pair output skew Default setting for internal inter-pair skew adjust, TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data lines, 148 MHz, 297 MHz clock; See Figure 8

0.2 Tch

tSK_INTRA Intra-pair output skew Default setting for internal intra-pair skew adjust, TX_TERM_CTL = NC; PRE_SEL = NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data lines, 148 MHz, 297 MHz clock; See Figure 8

0.15 Tbit

tJITC1(1.4b) Total output clock jitter CLK = 25 MHz, 74.25 MHz, 75 MHz, 150 MHz, 297 MHz 0.25 Tbit

TMDS181, TMDS181I SLASE75D –AUGUST 2015– REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: TMDS181 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated TMDS Switching Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX(2) UNIT tJITC1(2.0) DR = 6 Gbps: CLK = 150 MHz 0.3 Tbit tJITD2 Total output data jitter See Figure 14 3.4 Gbps < Rbit ≤ 3.712 Gps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H 0.4 Tbit 3.712 Gbps < Rbit < 5.94 Gbps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H –0.0332Rbit2 + 0.2312Rbit + 0.1998 5.94 Gbps ≤ Rbit ≤ 6.0 Gbps TX_TERM_CTL = NC; PRE_SEL = NC; OE = H 0.6 (1) The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted (2) The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted

6.11 HPD Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX(2) UNIT tPD(HPD) Propagation delay from HPD_SNK to HPD_SRC; rising edge and falling edge(2) See Figure 16; not valid during switching time 40 120 ns tT(HPD) HPD logical disconnected timeout See Figure 17 2 ms (1) Cb = total capacitance of one bus line in pF.

6.12 DDC and I2C Switching Characteristics

over operating free-air temperature range (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr Rise time of both SDA and SCL signals VCC = 3.3 V 300 ns tf Fall time of both SDA and SCL signals 300 ns tHIGH Pulse duration, SCL high 0.6 μs tLOW Pulse duration, SCL low 1.3 μs tSU1 Setup time, SDA to SCL 100 ns tST, STA Setup time, SCL to start condition 0.6 μs tHD,STA Hold time, start condition to SCL 0.6 μs tST,STO Setup time, SCL to stop condition 0.6 μs t(BUF) Bus free time between stop and start condition 1.3 μs tPLH1 Propagation delay time, low-to-high-level output Source to sink: 100kbps pattern; Cb(Sink) = 400 pF(1); see Figure 20 360 ns tPHL1 Propagation delay time, high-to-low-level output 230 ns tPLH2 Propagation delay time, low-to-high-level output Sink to source: 100kbps pattern; Cb(Source) = 100 pF(1); see Figure 21 250 ns tPHL2 Propagation delay time, high-to-low-level output 200 ns

6.13 Typical Characteristics

Figure 3. Current vs Data Rate Redriver Mode Figure 4. Current vs Data Rate Retimer Mode Figure 5. VSADJ vs VOD

7 Parameter Measurement Information

Figure 6. TMDS Main Link Test Circuit

TMDS181, TMDS181I SLASE75D –AUGUST 2015– REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: TMDS181 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TMDS181 is a DVI or HDMI™ retimer. The TMDS181 supports four TMDS channels, audio return channel (SPDIF_IN/ARC_OUT), hot plug detect, and DDC interfaces. The TMDS181 supports signaling rates up to 6 Gbps in retimer mode to allow for the highest resolutions of 4k2k60p 24 bits per pixel and up to WUXGA 16-bit color depth or 1080p with higher refresh rates. In redriver mode it supports HDMI1.4b with data rates up to 3.4 Gbps. The TMDS181 can be configured to support the HDMI2.0a standard which includes higher data rate, lower clock swing, and clock frequency. The TMDS181 can automatically configure itself as a redriver at low data rate (<1.0 Gbps) or as a retimer above this data rate. For passing compliance and reducing system-level design issues, several features are included such as TMDS output amplitude adjust using an external resistor on the VSADJ pin and source termination selection control. Device operation and configuration can be programmed by pin strapping or I2C. Four TMDS181s can be used on one I2C bus when I2C_EN enable and device address set by A0/A1. To reduce active power, the TMDS181 supports dual power supply rails of 1.2 V on VDD and 3.3 V on VCC. There are several methods of power management, such as going into power-down mode using three methods:

• HPD is low
• Writing a 1 to register 09h[3]
• De-asserting OE De-asserting OE clears the I2C registers, thus once reasserted the device must be reprogrammed if I2C was used for device setup. Upon return to normal active operation from reasserted OE or reasserted HPD, the TMDS181 requires the source to write a 1 to the TMDS_CLOCK_RATIO_STATUS bit for the TMDS181 to resume 1/40th clock mode. The TMDS181 does not reset this bit based upon a DDC read transaction. The SIG_EN pin enables the signal detect circuit that provides an automatic power-management feature during normal operation. When no valid signal is present on the inputs, the device will enter standby mode. By disabling the detect circuit, the receiver block is always on. DDC bridge supports the HDMI2.0 SCDC communication, 100 Kbps data rate default and 400 kbps adjustable by software. TMDS181 supports both fixed EQ gain control or adaptive equalization to compensate for different lengths of input cables or board traces. The EQ gain can be software adjusted by I2C control or selection between two fixed values or adaptive (Retimer Mode Only) equalization by pin strapping EQ_SEL pin. The customer can pull up or down TX_TERM_CTL through a 65 kΩ resistor to change the termination impedance for improved output performance when working in HDMI1.4b or leave it not connected. When not connected, the TMDS181 in conjunction with the rate detect automatically changes its output termination to meet HDMI1.4b or HDMI2.0a needs. For HDMI1.4b a transmitter termination of 150 Ω to 300 Ω is allowed for data rates above 2 Gbps to compensate for reflections. The automatic termination selection will configure the TMDS181 for this. It is important to note that there are times that this is not the best solution and no termination may be needed to pass compliance. For HDMI2.0a the 75 Ω to 150 Ω transmitter termination is required and the link will not work if this is not set. The TMDS181 supports the audio return channel to support HDMI1.4b. To make implementation easier, the TMDS181 supports input pin swapping and input polarity swap. When swapping the input pins, IN_CLK and IN_D2 swap and IN_D1 and IN_D0 swap with each other. Swap works in both retimer and redriver mode. Polarity swap exchanges the N and P channel polarity in each input lane and is only available during retimer mode. Lane swap and polarity swap can be implemented at the same time in retimer mode. Two temperature gradient versions of the device are available: extended commercial temperature range 0ºC to 85ºC (TMDS181) and industrial temperature range from –40ºC to 85ºC (TMDS181I).

IN_CLKp IN_CLKn IN_D[2:0]p IN_D[2:0]n 50Q 50Q50Q 50Q Control Block, I2C Registers Local I2C Control I2C_EN/PIN EQ_SEL/A0 PRE_SEL Data Registers SWAP PLL PLL Control SERDES VBIAS VBIAS EQ_SEL OUT_CLKp OUT_D[2:0]p OUT_CLKn OUT_D[2:0]n SWAPPolarityPLL BWSTBYPWR DN EQ EQ EQ_CTL SDA_CTL SCL_CTL VSADJ SWAP/POL TX_TERM_CTL OE TERM_SEL PRE_SEL Enable TMDS TMDS SIG_EN SIG_DET_OUT SIG_DET_OUT ACTIVE DDC BLOCK HPD_SNKHPD_SRC 190<Q SDA_SRC SCL_SRC SDA_SNK SCL_SNK DDC Snoop Block ARC Function SPDIF_IN ARC_OUT GND VDD VCC 1.2V 3.3VVREG Copyright © 2016, Texas Instruments Incorporated SIGNAL DETECT TMDS181, TMDS181I www.ti.com SLASE75D – AUGUST 2015– REVISED SEPTEMBER 2017 Product Folder Links: TMDS181 Submit Documentation FeedbackCopyright © 2015–2017, Texas Instruments Incorporated

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Reset Implementation

When OE is de-asserted, control signal inputs are ignored; the HDMI inputs and outputs are high impedance. It is critical to transition the OE from a low level to a high level after the VCC supply has reached the minimum recommended operating voltage. Achieve this transition by a control signal to the OE input, or by an external capacitor connected between OE and GND. To ensure the TMDS181 is properly reset, the OE pin must be de- asserted for at least 100 μs before being asserted. When OE is reasserted, the TMDS181 must be

and Figure 25 show both OE implementations. Figure 24. External Capacitor Controlled OE Figure 25. OE Input from Active Controller

8.3.2 Operation Timing

there is no rail sequence requirement.

8.3.3 Swap and Polarity Working

register 0x09h bit 7 for SWAP enable. Lane swap function works in both redriver and retimer mode. redriver level, the polarity swap is lost.

36 TERM_CTL

Table 2. SWAP Function(1) Figure 26. TMDS181 Swap Function

8.3.4 TMDS Inputs

the local I2C register when in retimer mode.

8.3.5 TMDS Inputs Debug Tools

PATTERN VERIFIER CONTROL/STATUS Register. uses the I2C link to download the data that can be plotted for an eye diagram. This is available per data lane.

8.3.6 Receiver Equalizer

Figure 27. Adaptive EQ Gain Curve for >3.4 Gbps

8.3.7 Input Signal Detect Block

default disabled. Implementer should activate this function in normal operation for power saving.

8.3.8 Audio Return Channel

8.3.9 Transmitter Impedance Control

HDMI2.0a standard requires a termination impedance in the 75 Ω to 150 Ω range for data rates >3.4 Gbps. 75 Ω to 150 Ω transmitter termination is required and the link will not work if this is not set.

Table 3. TX Termination Control

• DR > 3.4 Gbps – 75 Ω to 150 Ω differential near end termination
• 2 Gbps > DR < 3.4 Gbps – 150 Ω to 300 Ω differential near-end termination
• DR < 2 Gbps – No termination

8.3.10 TMDS Outputs

mA current sink capability, which provides a typical 500 mV voltage drop across a 50 Ω termination resistor. Figure 28. TMDS Driver and Termination Circuit output voltages based on the different VSADJ settings.

8.3.11 Pre-Emphasis/De-Emphasis

which will accomplish the same pre-emphasis setting, see Figure 30.

Figure 29. Output Pre-Emphasis Using Pin Strapping

Figure 30. Output Pre-Emphasis Using I2C

8.4 Device Functional Modes

8.4.1 Retimer Mode

TMDS outputs. Input jitter within the CDR’s PLL bandwidth, < 1 MHz will be transferred to the TMDS outputs. (default). The retimer operates at about 1 Gbps to 6 Gbps DR. active (default) or programmed to be disabled to avoid sending invalid clock or data to the downstream receiver.

TMDS181, TMDS181I SLASE75D –AUGUST 2015– REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: TMDS181 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Device Functional Modes (continued)

8.4.2 Redriver Mode

The TMDS181 also has a redriver mode that can be enabled through I2C, at reg0Ah[1:0] DEV_FUNC_MODE, which compensates for ISI channel loss. In this mode, power is reduced as the CDR and PLL are turned off. When in automatic mode, the TMDS181 is in redriver mode for data rates <1.0 Gbps. By using I2C, the device can be put in redriver mode for the complete data range of 250 Mbps to 3.4 Gbps. This is done by writing a 00 to register 0Ah[1:0]. If the link has excessive random jitter, then retimer mode is the best operating mode. When in redriver mode, the device only compensates for ISI loss. When in redriver mode compliance is not guaranteed as skew compensation and retiming functions are disabled. If a significant amount of random jitter is present, the system may not pass compliance at the connector. 8.4.3 DDC Training for HDMI2.0a Data Rate Monitor As part of discovery, the source reads the sink’s E-EDID information to understand the capabilities of the sink. Part of this read is HDMI Forum Vendor Specific Data Block (HF-VSDB) MAX_TMDS_Character_Rate byte to determine the data rate supported. Depending upon the value, the source writes to slave address 0xA8 offset 0x20 bit1, TMDS_CLOCK_RATIO_STATUS. The TMDS181 snoops this write to determine the TMDS clock ratio and thus sets its own TMDS_CLOCK_RATIO_STATUS bit accordingly. If a 1 is written, then the TMDS clock is set to 1/40th of TMDS bit period. If a 0 is written, then the TMDS clock is set to 1/10th of TMDS bit period. The TMDS181 defaults to 1/10th of TMDS bit period unless a 1 is written to address 0xA8 offset 0x20 bit 1. When HPD is deasserted, this bit is reset to default values. If the source does not write this bit, the TMDS181 will not be configured for TMDS clock 1/40th mode in support of HDMI2.0a. As the TMDS181 is in the system link, but not recognized as part of the link, it is possible that the source could read the sink EDID where this bit is set and does not rewrite this bit. If the TMDS181 has entered a power-down state, this bit is cleared and does not re-set on a read. To work properly, the bit has to be set again with a write by the source.

8.4.4 DDC Functional Description

The TMDS181 solves sink/source level issues by implementing a master/slave control mode for the DDC bus. When the TMDS181 detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC, it will transfer the data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK detects the feedback from the downstream device, the TMDS181 will pull up or pull down the SDA_SRC bus and deliver the signal to the source. The DDC link defaults to 100 kbps but can be set to various values including 400 kbps by setting the correct value to address 0Bh through the I2C interface. The DDC lines are 5 V tolerant when the device is powered off. NOTE The TMDS181 utilizes clock stretching for DDC transactions. As there are sources and sinks that do not perform this function correctly a system may not work correctly as DDC transactions are incorrectly transmitted/received. To overcome this a snoop configuration can be implemented where the SDA/SCL from the source is connected directly to the SDA/SCL sink. The TMDS181 will need its SDA_SNK and SCL_SNK pins connected to this link in order to correctly configure the TMDS_CLOCK_RATIO_STATUS bit. Care must be taken when this configuration is being implemented as the voltage levels for DDC between the source and sink may be different, 3.3 V vs 5 V; See Figure 35 and See Figure 36

8.4.5 Mode Selection Functional Description

Mode selection definition: This bit lets the receiver know where the device is located in a system for the purpose of centering the AEQ point. The TMDS181 is targeting sink applications, so the default value is 1, which will center the EQ at 12 to 13 dB depending upon TMDS_CLOCK_RATIO_STATUS value (see Equalization Control Register). If the TMDS181 is in a source application, the value should be changed to a value of 0, which centers the EQ at 6.5 to 7.5 dB depending upon the TMDS_CLOCK_RATIO_STATUS value.

8.5 Register Maps

8.5.1 Local I2C Overview

(January 2000), and supports the fast mode transfer up to 400 kbps. Figure 31. TMDS181 I2C Device Address Description run at 400 kHz supporting fast-mode I2C operation.

1. The master initiates a write operation by generating a start condition (S), followed by the TMDS181 7-bit address and a

zero-value W/R bit to indicate a write cycle.

1. The TMDS181 acknowledges the address cycle.
2. The master presents the sub-address (I2C register within TMDS181) to be written, consisting of one byte of data, MSB-
3. The TMDS181 acknowledges the sub-address cycle.
4. The master presents the first byte of data to be written to the I2C register.
5. The TMDS181 acknowledges the byte transfer.
6. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an

acknowledge from the TMDS181.

1. The master terminates the write operation by generating a stop condition (P).

The following procedure is used to read the TMDS181 I2C registers.

1. The master initiates a read operation by generating a start condition (S), followed by the TMDS181 7-bit address and a

one-value W/R bit to indicate a read cycle.

1. The TMDS181 acknowledges the address cycle.
2. The TMDS181 transmits the contents of the memory registers MSB-first starting at register 00h.
3. The TMDS181 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte

transfer; the I2C master acknowledges reception of each data byte transfer.

1. If an ACK is received, the TMDS181 transmits the next byte of data.
2. The master terminates the read operation by generating a stop condition (P).

address specified is needed before performing the read operation.

reserved fields not described return zeros, and writes are ignored.

8.5.2 Local I2C Control Bit Access TAG Convention

description, and the field access tags. Table 4 describes the field access tags. Table 4. Field Access Tags

8.5.3 CSR Bit Field Definitions

8.5.3.1 ID Registers

Table 5. ID Registers Field Descriptions 08h 7:0 REV _ID. This field identifies the device revision.

8.5.3.2 MISC CONTROL Register

Table 6. MISC CONTROL Register Field Descriptions 09h 7 1’b0 LANE_SWAP. This field swaps the input lanes as per Figure 26. 6 1’b0 LANE_POLARITY swaps the input data and clock lanes polarity. state when no valid data detect. 1:0 2’b10 I2C_DR_CTL. I2C data rate supported for configuring device.

400 Kbps mode)

1 – HPD_SNK does not pass through to the HPD_SRC. 5 1’b1 EQ_ADA_EN. This field enables the equalizer functioning state. 4 1’b1 EQ_EN. This field enables the equalizer. 2 1’b0 APPLY_RXTX_CHANGES, Self-clearing write-only bit. to the respective registers do not take immediate effect. low, I2CPD_EN = 1 or there is no HDMI clock applied and SIGN_EN is high. 1:0 2’b01 DEV_FUNC_MODE. This field selects the device working function mode. When changing crossover point, need to toggle PD_EN or toggle external HPD_SNK.

Table 6. MISC CONTROL Register Field Descriptions (continued) 4:3 2'b00 TX_TERM_CTL. Controls termination for HDMI TX. value whenever HPD_SNK is de-asserted for greater than 2 ms. 0 1'b0 DDC_TRAIN_SETDISABLE; This field indicate the DDC training block function status. If disabled the device will only work in HDMI1.x or DVI modes. 1:0 2’b00 HDMI_TWPST1[1:0]. HDMI de-emphasis FIR post-cursor-1 signed tap weight.

8.5.3.3 Equalization Control Register

Table 7. Equalization Control Register Field Descriptions

(1) If PV_DP_EN is used to monitor TMDS data path errors the counters for lanes 0, 1, 2, and 3 are ignored.

8.5.3.4 RX PATTERN VERIFIER CONTROL/STATUS Register

Table 8. RX PATTERN VERIFIER CONTROL/STATUS Register Field Description(1) of the PRBS generator. 1 bit per lane. subsequently deasserted low. 1 bit per lane. 10h 7 1’b0 PV_CP20. Customer pattern length 20/16 bits. TST_INTQ[0] and PV_DP_EN is non-zero.

Table 8. RX PATTERN VERIFIER CONTROL/STATUS Register Field Description(1) (continued) 20h 7 1’b0 Power Down Status Bit.

34 TMDS_D2n

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.2 Typical Applications

9.2.1 Source Side Application

Figure 32. TMDS181 in Source Side Application

9.2.1.1 Design Requirements

the system to work properly. Two voltage rails are required to support the lowest power consumption possible. conventions, it is necessary to confirm that the link between the source and the TMDS181 are correctly mapped. Table 9. Design Parameters

9.2.1.2 Detailed Design Procedure

trace and connector when compliance is required at the connector. To design in the TMDS181 for a source side application, the designer must understand the following.

• Determine the loss profile between the GPU/chipset and the HDMI/DVI connector.
• Based upon this loss profile and signal swing, determine the optimal location for the TMDS181 in order to pass source electrical compliance, usually within 2 to 3 inches of the connector.
• Use the typical application Figure 32 for information on control pin resistors.
• The TMDS181 has a receiver adaptive equalizer, but can also be configured using EQ_SEL control pin.
• Set the VOD, pre-emphasis and termination levels appropriately to support compliance by using the appropriate VSADJ resistor value and setting PRE_SEL and TX_TERM_CTL control pins.
• The thermal pad must be connected to ground.
• See schematics in Figure 32 on recommended decoupling capacitors from VCC pins to ground.

9.2.1.3 Application Curves

Figure 33. Input Eye After 3M Cable at 5.94Gbps Figure 34. Output Eye from TMDS181 after 3M Input Cable

9.2.2 Sink Side Application

implement sink application as per Figure 36 to address this. Designing the TMDS181 into a sink side application requires similar care as for a source side application. capability, the circuit shown in Figure 35 is required. To design in the TMDS181 for a source side application, the designer must understand the following.

• Determine the loss profile between the RX/chipset and the HDMI/DVI connector
• Based upon this loss profile and signal swing, determine the optimal location for the TMDS181 to pass sink electrical compliance.
• Use the typical application Figure 35 for information on control pin resistors.
• The TMDS181 has a receiver adaptive equalizer, but can also be configured using EQ_SEL control pin.
• Set the VOD, pre-emphasis and termination levels appropriately to support a link between TMDS181 and HDMI RX/chipset by using the appropriate VSADJ resistor value and setting PRE_SEL and TX_TERM_CTL control pins.
• The thermal pad must be connected to ground.
• See schematics in Figure 35 on recommended decoupling capacitors from VCC pins to ground.
• Because the HDMI ecosystem supporting 4k2kp60 is not mature, TI recommends to design the TMDS181 into the sink application as shown in Figure 36.

5 V HPD Implementation

Figure 35. TMDS181 in Sink Side Application (Including 5 V HPD Implementation)

Figure 36. TMDS181 in Sink Side Application

9.2.3 Application Chain Showing DDC Connections

repeater delay/time of flight considerations for the maximum bus speed requirements. Figure 37. Typical Series Application

9.2.3.1 Detailed Design Procedure

9.2.3.1.1 DDC Pullup Resistors

The pullup resistor value is determined by two requirements.

1. The maximum sink current of the I2C buffer: The maximum sink current is 3 mA or slightly higher for an I2C driver

supporting standard-mode I2C operation.

1. The maximum transition time on the bus: The maximum transition time, T, of an I2C bus is set by an RC time constant.

of k under different threshold combinations.

• R is the pullup resistor value.
• C is the total load capacitance. (2) (3)

Table 10. Value k upon Different Input Threshold Voltages R(max) as shown in Table 11. Table 11. Pullup Resistor Upon Different Threshold Voltages and 800 pF Loads a maximum 800-pF load capacitance for a standard-mode I2C bus.

9.2.3.1.2 Compliance Testing

compliance testing. As each system is different there are many features in the TMDS181 to help tune the circuit. when using I2C as this provides more fine tuning capability.

• VSADJ Resistor = 7.06 kΩ: Note: This value may be changed in order to improve Intra-pair skew margin but will increase output VOD so care must be taken to avoid VOD and VL compliance issues.
• PRE_SEL = L for -2 dB (For Intra-pair Skew)
• TX_TERM_CTL = NC for Auto Select.
• VSADJ Resistor = 7.06 kΩ: This value may be changed in order to improve Intra-pair skew but will increase VOD so care must be taken to avoid VOD and VL compliance issues. The VOD can be increased or decreased by using I2C Reg0Ch[7:2]
• PRE_SEL = Reg0Ch[1:0] = 01 for -2 dB (Labeled HDMI_TWPST)
• TX_TERM_CTL = NC for Auto Select. – Reg0Bh[4:3] = 00 → No TX Term; HDMI1.4b < 2 Gbps (This may be best value for all HDMI1.4b) – Reg0Bh[4:3] = 01 → 150 Ω to 300 Ω; HDMI1.4b > 2 Gbps – Reg0Bh[4:3] = 11 → 75 Ω to 150 Ω; HDMI2.0a

10 Power Supply Recommendations

operates in three different working states.

• Power-down mode: – OE = Low puts the device into its lowest power state by shutting down all function blocks. – When OE is reasserted, the transitions from L → H create a reset, and if the device is programmed through I2C, it must be reprogrammed. – Writing a 1 to register 09h[3]. – OE = High, HPD_SNK = Low
• Standby mode: HPD_SNK = High, but no valid clock signal detect on clock lane.
• Normal operation: Working in redriver or retimer
• When HPD asserts, the device CDR and output enables based on the signal detector circuit result.
• HPD_SRC = HPD_SNK in all conditions. The HPD channel is operational when VCC is over 3 V. NOTE 1. When the TMDS181 is put into a power-down state, the I2C registers are cleared. This is important as the TMDS_CLOCK_RATIO_STATUS bit will be cleared. If cleared and HDMI2.0 resolutions are to be supported, the TMDS181 expects the source to write a 1 to this bit location. If this does not happen, the PLL will not be set properly and no video may be evident. 2. Power performance of the TMDS181 is highly dependent upon the HDMI transmitter architecture driving the TMDS181 receiver. The TMDS181 has integrated the termination resistors, which increases the power consumption on the 3.3 V rail by as much as 400 mW. This is the power required by the HDMI transmitter to switch and not needed by the TMDS181 to operate properly.

Table 12. Power-Up and Operation Timing Requirements

11 Layout

11.1 Layout Guidelines

For the TMDS181 on a high-K board: It is required to solder the PowerPAD™ onto the thermal land to ground. TMDS181 can operate over the full temperature range by soldering the PowerPAD onto the thermal land.

• Routing the high-speed TMDS traces on the top layer avoids the use of vias (and their discontinuities) and allows for clean interconnects from the HDMI connectors to the retimer inputs and outputs. It is important to match the electrical length of these high-speed traces to minimize both inter-pair and intra-pair skew.
• Placing a solid ground plane next to the high-speed single layer establishes controlled impedance for transmission link interconnects and provides an excellent low-inductance path for the return current flow.
• Placing a power plane next to the ground plane creates an additional high-frequency bypass capacitance.
• Routing slower-speed control signals on the bottom layer allows for greater flexibility because these signal links usually have margin to tolerate discontinuities such as vias.
• If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to the stack to keep symmetry. This makes the stack mechanically stable and prevents it from warping. Also, the power and ground plane of each power system can be placed closer together, thus increasing the high- frequency bypass capacitance significantly.

Figure 38. Recommended 4- or 6-Layer PCB Stack

11.2 Layout Example

A. If ARC is not used, tie a 500 kΩ resistor to GND at the SPDIF_IN pin. Figure 39. Layout Example – Source Side

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

use a document tag, identified as [Document Tag], instead of the complete document title to simplify the text.

1. [HDMI] High-definition Multimedia Interface Specification Version 1.4b October, 2011
2. [HDMI] High-definition Multimedia Interface Specification Version 2.0a March, 2015
3. [HDMI] High-definition Multimedia Interface CTS Version 1.4b October, 2011
4. [HDMI] High-definition Multimedia Interface CTS Version 2.0k June, 2015
5. [I2C] The I2C-Bus specification version 2.1 January 2000

12.2 Related Links

resources, tools and software, and quick access to sample or buy. Table 13. Related Links

12.3 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.5 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments. Blu-ray is a trademark of Blu-ray Disc Association. All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary

This glossary lists and explains terms, acronyms, and definitions.

TMDS181, TMDS181I www.ti.com SLASE75D – AUGUST 2015– REVISED SEPTEMBER 2017 Product Folder Links: TMDS181 Submit Documentation FeedbackCopyright © 2015–2017, Texas Instruments Incorporated

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 30-Jun-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TMDS181IRGZR Active Production VQFN (RGZ) | 48 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TMDS181I TMDS181IRGZR.A Active Production VQFN (RGZ) | 48 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TMDS181I TMDS181IRGZT Active Production VQFN (RGZ) | 48 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TMDS181I TMDS181IRGZT.A Active Production VQFN (RGZ) | 48 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TMDS181I TMDS181IRGZTG4 Active Production VQFN (RGZ) | 48 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TMDS181I TMDS181IRGZTG4.A Active Production VQFN (RGZ) | 48 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TMDS181I TMDS181RGZR Active Production VQFN (RGZ) | 48 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR 0 to 85 TMDS181 TMDS181RGZR.A Active Production VQFN (RGZ) | 48 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR 0 to 85 TMDS181 TMDS181RGZRG4 Active Production VQFN (RGZ) | 48 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TMDS181 TMDS181RGZRG4.A Active Production VQFN (RGZ) | 48 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TMDS181 TMDS181RGZT Active Production VQFN (RGZ) | 48 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR 0 to 85 TMDS181 TMDS181RGZT.A Active Production VQFN (RGZ) | 48 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR 0 to 85 TMDS181 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 30-Jun-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMDS181IRGZR VQFN RGZ 48 2500 367.0 367.0 38.0 TMDS181IRGZT VQFN RGZ 48 250 210.0 185.0 35.0 TMDS181IRGZTG4 VQFN RGZ 48 250 210.0 185.0 35.0 TMDS181RGZR VQFN RGZ 48 2500 367.0 367.0 38.0 TMDS181RGZRG4 VQFN RGZ 48 2500 367.0 367.0 38.0 TMDS181RGZT VQFN RGZ 48 250 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRGZ 48 PLASTIC QUADFLAT PACK- NO LEAD7 x 7, 0.5 mm pitch 4224671/A

www.ti.com PACKAGE OUTLINE C 48X 0.30 0.18 4.1 0.1 48X 0.5 0.3

1 MAX

(0.2) TYP 0.05 0.0044X 0.5 5.5 2X 5.5 B 7.15 6.85 A 7.15 6.85 VQFN - 1 mm max heightRGZ0048B PLASTIC QUAD FLATPACK - NO LEAD 4218795/B 02/2017 PIN 1 INDEX AREA 0.08 C SEATING PLANE 12 25 13 24 48 37 (OPTIONAL) PIN 1 ID

0.1 C B A

0.05 EXPOSED THERMAL PAD

49 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 2.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

48X (0.24) 48X (0.6) ( 0.2) TYP VIA 44X (0.5) (6.8) (6.8) (1.115) TYP ( 4.1) (R0.05) TYP (0.685) TYP (1.115) TYP (0.685) TYP VQFN - 1 mm max heightRGZ0048B PLASTIC QUAD FLATPACK - NO LEAD 4218795/B 02/2017 SYMM 13 24 3748 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 48X (0.6) 48X (0.24) 44X (0.5) (6.8) (6.8) (1.37) TYP (R0.05) TYP ( 1.17) (1.37) TYP VQFN - 1 mm max heightRGZ0048B PLASTIC QUAD FLATPACK - NO LEAD 4218795/B 02/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:12X SYMM 13 24 3748

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