TMDS171IRGZR.A

Texas Instruments

TMDS171/I 3.4 Gbps TMDS RETIMER REVISED SEPTEMBER 2017

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PDF pages: 63

Technical content

IN_CLKp/n OUT_CLKp/n IN_D1p/n OUT_D1p/n IN_D0p/n OUT_D0p/n OUT_D2p/nIN_D2p/n

3.3 V t 5 V

SDA_SRC SCL_SRC SDA_SNK SCL_SNK HPD_SRC HPD_SNK SDA_CTL SCL_CTL 3.3 V TMDS RX DDC HPD I2C OE VSADJ ARC_OUT SPDIF_IN SPDIF Copyright © 2016, Texas Instruments Incorporated Interface Unit Audiovisual Processing Unit HDMI SW/HD TMDS 171 Digital TV Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMDS171, TMDS171I SLLSEN7E – OCTOBER 2015–REVISED SEPTEMBER 2017 TMDS171/I3.4GbpsTMDSRETIMER

1 Features

1• HDMI Input Port to Output Port with CDR Supporting up to 3.4 Gbps Data Rates

Compatible with HDMI1.4b Electrical Parameters.
Support for 4k2k30p and up to WUXGA 12-bit Color Depth or 1080p with Higher Refresh Rates™
Retimes Input Stream to Compensate for Random Jitter
Adaptive Receiver Equalizer or Programmable Fixed Equalizer
I2C and Pin Strap Programmable
Inter-Pair Skew Compensation of 5+ Bits
Link Debug Tools Including Eye Diagram After RX Equalizer
Single Ended Mode ARC Support
48-pin 7mm x 7mm 0.5 mm Pitch VQFN Package
Extended Commercial Temperature Support 0°C – 85°C (TMDS171)
Industrial Temperature Support -40°C – 85°C (TMDS171I)

2 Applications

Digital TV
Digital Projector
Audio/Video Equipment
Blu-Ray DVD
Monitors
Desktops/ All-in-Ones
Active Cables

3 Description

12.2 Receiving Notification of Documentation Updates 54

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision D (August 2016) to Revision E Page Changes from Revision C (April 2016) to Revision D Page Changes from Revision B (February 2016) to Revision C Page

Changed pin 36 Description From: TX_TERM_CTL = L: 150 - 300 Ω To: TX_TERM_CTL = L: Reserved in the Pin
Changed text "address 22h through the I2C interface" To: "address 0Bh through the I2C interface" DDC Functional

Changed Pin 44 From: AUX_SRCn To: ARC_OUT Pin 45 From: AUX_SRCn To: SPDIF_IN in the Pin Configuration Changes from Original (October 2015) to Revision A Page

HPD_SRC SDA_SRC SCL_SRC GND OUT_D0p OUT_D0n SDA_SNK SCL_SNK OE VDD VDD TX_TERM_CTL SCL_CTL NC SPDIF_IN 4142434445464748 GND SIG_EN VDD ARC_OUT I2C_EN/PIN VDD VCC VDD VCC GND HPD_SNK PRE_SEL EQ_SEL/A0 SDA_CTL IN_D1n IN_D1p IN_D2n IN_D2p IN_D0n IN_D0p IN_CLKn IN_CLKp OUT_D2p OUT_D2n OUT_D1p OUT_D1n OUT_CLKp OUT_CLKn SWAP/POL GND GND TMDS171, TMDS171I SLLSEN7E –OCTOBER 2015– REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: TMDS171 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated

5 Pin Configuration and Functions

RGZ (QFN) Package

48 Pins

TMDS171, TMDS171I www.ti.com SLLSEN7E – OCTOBER 2015– REVISED SEPTEMBER 2017 Product Folder Links: TMDS171 Submit Documentation FeedbackCopyright © 2015–2017, Texas Instruments Incorporated (1) (1) G = Ground, I = Input, O = Output, P = Power (2) (H) Logic High (Pin strapped to VCC through 65 kΩ resistor); (L) Logic Low (Pin strapped to GND through 65 kΩ resistor); (Mid-Level = No connect) Pin Functions PIN I/O(1) DESCRIPTION NAME NO. VCC 13, 43 P 3.3 V Power Supply VDD 14, 23, 24, 37, 48 P 1.2 V Power Supply GND 7, 19, 41, 30 G Ground Thermal Pad G Ground MAIN LINK INPUT PINS (FAIL SAFE) IN_D2p/n 2, 3 I Channel 2 Differential Input IN_D1p/n 5, 6 I Channel 1 Differential Input IN_D0p/n 8, 9 I Channel 0 Differential Input IN_CLKp/n 11, 12 I Clock Differential Input MAIN LINK OUTPUT PINS (FAIL SAFE) OUT_D2n/p 34, 35 O TMDS Data 2 Differential Output OUT_D1n/p 31, 32 O TMDS Data 1 Differential Output OUT_D0n/p 28, 29 O TMDS Data 0 Differential Output OUT_CLKn/p 25, 26 O TMDS Clock Differential Output HOT PLUG DETECT PINS HPD_SRC 4 O Hot Plug Detect Output to source side HPD_SNK 33 I Hot Plug Detect Input from sink side AUDIO RETURN CHANNEL and DDC PINS SPDIF_IN 45 I SPDIF signal input ARC_OUT 44 O Audio return channel output SDA_SRC 47 I/O Source Side TMDS Port Bidirectional DDC Data line SCL_SRC 46 I/O Source Side TMDS Port Bidirectional DDC Clock line SDA_SNK, 39 I/O Sink Side TMDS Port Bidirectional DDC Data Line SCL_SNK 38 I/O Sink Side TMDS Port Bidirectional DDC Clock Line CONTROL PINS(2) OE 42 I Operation Enable/Reset Pin OE = L: Power Down Mode OE = H: Normal Operation Internal weak pull up: Resets device when transitions from H to L SIG_EN 17 I Signal detector circuit enable SIG_EN = L: Signal Detect Circuit Disabled: Term resistors always connected (Default) SIG_EN = H: Signal Detect Circuit Enabled: When no valid clock device enters Standby Mode. Internal weak pull down PRE_SEL 20 I 3-Level De-emphasis Control when I2C_EN/PIN = Low. PRE_SEL = L: -2 dB PRE_SEL = No Connect: 0 dB PRE_SEL = H: Reserved When I2C_EN/PIN = High; De-emphasis is controlled through I2C EQ_SEL/A0 21 I Input Receive Equalization pin strap when I2C_EN/PIN = Low EQ_SEL = L: Fixed EQ at 7.5 dB EQ_SEL = No Connect: Adaptive EQ EQ_SEL = H: Fixed at 14 dB When I2C_EN/PIN = High Address Bit 1 Note: 3 level for pin strap programming but 2 level when I2C address I2C_EN/PIN 10 I I2C_EN/PIN = High; Puts Device into I2C Control Mode I2C_EN/PIN = Low; Puts Device into Pin Strap Mode SCL_CTL 15 I/O I2C Clock Signal when I2C_EN/PIN = High. Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be changed by I2C SDA_CTL 16 I/O I2C Data Signal when I2C_EN/PIN = High Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be changed by I2C VSadj 22 I TMDS Output Voltage Swing Control; Nominal 7.06 kΩ Resistor to GND

TMDS171, TMDS171I SLLSEN7E –OCTOBER 2015– REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: TMDS171 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Pin Functions (continued) PIN I/O(1) DESCRIPTION NAME NO. A1 27 I High address bit 2 for I2C programming Weak internal pull down. Note: When I2C_EN/PIN = Low for Pin Strapping Mode leave this pin as No connect TX_TERM_CTL 36 I 3-Level Transmit Termination Control TX_TERM_CTL = H: No transmit Termination TX_TERM_CTL = L: Reserved TX_TERM_CTL = No Connect: Automatically selects the termination impedance 2 Gbps > DR ≤ 3.4 Gbps – 150 - 300 Ω differential near end termination DR < 2 Gbps – no termination Note: If left floating; the device will be in Automatic Select Mode. DR stands for Data Rate SWAP/POL 1 I 3-Level Receive Polarity Swap and Receive Lane Swap control pin SWAP/POL = H: Receive Lanes Polarity Swap (Retimer Mode Only) SWAP/POL = L: Receive Lanes (Retimer and Redriver Mode) Swap SWAP/POL = No Connect, Normal Operation NC 18, 40 – No connect (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-B

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)(3) MIN MAX UNIT Supply Voltage Range VCC –0.3 4 V VDD –0.3 1.4 Voltage Range Main Link Input Differential Voltage (IN_Dx, IN_CLKx); IIN = 15mA VCC - 0.75 V VCC + 0.3 V TMDS Outpus ( OUT_Dx) –0.3 4 HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, A1, PRE_SEL, EQ_SEL/A0, I2C_EN/PIN, SIG_EN, TX_TERM_CTL, –0.3 4 HDP_SNK, SDA_SNK, SCL_SNK, SDA_SRC, SCL_SRC –0.3 6 Input Current IIN Main Link Input Differential Voltage (IN_Dx, IN_CLKx); 15 mA Continuous power dissipation See Thermal Information Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±500

TMDS171, TMDS171I www.ti.com SLLSEN7E – OCTOBER 2015– REVISED SEPTEMBER 2017 Product Folder Links: TMDS171 Submit Documentation FeedbackCopyright © 2015–2017, Texas Instruments Incorporated (1) These values are based upon a microcontroller driving the control pins. The pull up/down/floating resistor configuration will set control pins properly which will have a different value than shown due to internal biasing. (2) This value is based upon a microcontroller driving the OE pin. A passive reset circuit using an external capacitor and the internal pullup resistor will set OE pin properly, but may have a different value than shown due to internal biasing.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Supply Voltage Nominal Value 3.3 V 3.135 3.3 3.465 V VDD Supply Voltage Nominial Value 1.2 V 1.1 1.2 1.27 V TSTG Storage temperature –65 150 °C TCASE Case temperature 92.7 °C TA Operating free-air temperature (TMDS171) 0 85 °C Operating free-air temperature (TMDS171I) –40 85 °C MAIN LINK DIFFERENTIAL PINS VID(PP) Peak-to-peak input differential voltage 75 1560 mVpp VIC Input Common Mode Voltage VCC – 0.4 VCC + 0.1 V dR Data rate 0.25 3.4 Gbps R(VSADJ) TMDS compliant swing voltage bias resistor 1% 7.06 KΩ CONTROL PINS VI(DC) DC Input Voltage –0.3 3.6 V VIL (1) Low-level input voltage OE 0.8 V Low-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL pins only(1) 0.3 V VIM (1) Mid-Level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL pins only(1) 1 1.2 1.4 V VIH (1) High-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL, OE(2) pins only(1) 2.6 V VOL Low-level output voltage 0.4 V VOH High-level output voltage 2.4 V IIH High level input current 30 30 µA IIL Low level input current –25 25 µA IOS Short circuit output current –50 50 mA IOZ High impedance output current 10 µA R(OEPU) Pull up resistance on OE pin 150 250 KΩ (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) RGZ (QFN) UNIT RθJA Junction-to-ambient thermal resistance 31.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 18.2 RθJB Junction-to-board thermal resistance 8.1 ψJT Junction-to-top characterization parameter 0.4 ψJB Junction-to-board characterization parameter 8.1 RθJC(bot) Junction-to-case (bottom) thermal resistance 3.2

TMDS171, TMDS171I SLLSEN7E –OCTOBER 2015– REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: TMDS171 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated (1) ICC is a direct result of the source design as the TMDS171 integrated receive termination resistor accounts for 85 mA to 100 mA. (2) IDD is impacted by ARC usage. Connecting a 500 KΩ resistor to GND at SPDIF reduces the value by more than 20 mA. (3) The measurements were made with no active source connected.

6.5 Electrical Characteristics

The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C temperature. The Typical rating is simulated at 3.3 VCC and 1.2 V VDD and at 27°C temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supply P(D1) (1)(2) Device power Dissipation (Retimer Operation) OE = H, VCC = 3.3 V / 3.465 V, VDD = 1.2 V / 1.27 V IN_Dx: VID_PP = 1200 mV, I2C_EN/PIN = L, PRE_SEL= H, EQ_CTL= H, SDA_CTL/CLK_CTL = 0 V 3.4 Gbps TMDS pattern, VI = 3.3 V; VSADJ = 7.06 kΩ 675 875 mW P(D2) (1)(2) Device power Dissipation (Redriver Operation) 400 600 mW P(SD1) (1)(2)(3) Device power in Standby OE = H, VCC = 3.3 V / 3.465 V VDD = 1.2 V / 1.27 V , HPD = H, No Valid input Signal 50 100 mW P(SD2) (1)(2)(3) Device power in PowerDown OE = L, VCC = 3.3 V / 3.465 V VDD = 1.2 V / 1.27 V 10 30 mW ICC1 (1)(2) VCC Supply current (TMDS 3.4 Gpbs Retimer Mode) OE = H, VCC = 3.3 V / 3.465 V VDD = 1.2 V / 1.27 V IN_Dx: VID_PP = 1200 mV,

3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H,

EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H 80 140 mA IDD1 (1)(2) VDD Supply current (TMDS 3.4 Gpbs Retimer Mode) 286 325 mA ICC2 (1)(2) VCC Supply current (TMDS 3.4 Gpbs Redriver Mode) OE = H, VCC = 3.3 V / 3.465 V VDD = 1.2 V / 1.27 V IN_Dx: VID_PP = 1200 mV, EQ_CTL = H, SDA_CTL/CLK_CTL = 0V, SLEW_CTL = H 51 mA IDD2 (1)(2) VDD Supply current (TMDS 3.4 Gpbs Redriver Mode) 188 mA I(SD1) (3) Standby current OE = H, VCC = 3.3 V / 3.465 V VDD = 1.2 V / 1.27 V HPD = H: No valid signal on IN_CLK 3.3V Rail(1) 6 15 mA 1.2V Rail 40 50 I(SD2) (3) PowerDown current OE = L, VCC = 3.3 V / 3.465 V VDD = 1.2 V / 1.27 V 3.3V Rail(1) 2 5 mA 1.2V Rail 3.5 15 TMDS Differential Input D(R_RX_DATA) TMDS data lanes data rate 0.25 3.4 Gbps D(R_RX_CLK) TMDS clock lanes clock rate 25 340 MHz tRX_DUTY Input clock duty circle 40% 50% 60% tCLK_JIT Input clock jitter tolerance 0.3 Tbit tDATA_JIT Input data jitter tolerance Test the TTP2 See Figure 11 150 ps tRX_INTRA Input intra-pair skew tolerance Test at TTP2 when DR = 1.6 Gbps See Figure 11 112 ps tRX_INTER Input inter-pair skew tolerance 1.8 ns EQH(D) Fixed EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0=H; Fixed EQ gain, test at 3.4 Gbps 14 dB EQL(D) Fixed EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0=L; Fixed EQ gain, test at 3.4 Gbps 7.5 EQZ(D) Adaptive EQ gain for data lane IN_D(0,1,2)n/p EQ_SEL/A0=NC; adaptive EQ 2 14 EQ(C) EQ gain for clock lane IN_CLKn/p EQ_SEL/A0=H,LNC 0 R(INT) Input differential termination impedance 90 100 115 Ω TMDS Differential Output VOH Single-ended high level output voltage PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ VCC - 10mV VCC + 10mV V PRE_SEL = NC; TX_TERM_CTL = H; OE = NC; DR = 2.97 Gbps; VSadj = 7.06 kΩ VCC - 200mV VCC + 10mV VOL Single-ended low level output voltage No Pre-emphasis, Load is 50 Ω pull ups to 3.135 V and 3.465 V PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ VCC - 600mV VCC - 400mV PRE_SEL = NC; TX_TERM_CTL = H; OE = NC; DR = 2.97 Gbps; VSadj = 7.06 kΩ VCC - 700mV VCC - 400mV

TMDS171, TMDS171I www.ti.com SLLSEN7E – OCTOBER 2015– REVISED SEPTEMBER 2017 Product Folder Links: TMDS171 Submit Documentation FeedbackCopyright © 2015–2017, Texas Instruments Incorporated Electrical Characteristics (continued) The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C temperature. The Typical rating is simulated at 3.3 VCC and 1.2 V VDD and at 27°C temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(SWING_DA) Single-ended output voltage swing on data lane PRE_SEL = NC; TX_TERM_CTL = H/NC; OE = NC; DR = ≤ 3.4 Gbps; VSadj = 7.06 kΩ 400 500 600 mV V(SWING_CLK) Single-ended output voltage swing on clock lane PRE_SEL = NC; TX_TERM_CTL = H/NC; OE = NC; DR = ≤ 3.4 Gbps; VSadj = 7.06 kΩ 400 500 600 ΔV(SWING) Change in single-end output voltage swing per 100Ω ΔVSadj ΔVOCM(SS) Change in steady state output common mode voltage between logic levels –5 5 VOD(PP) Initial output differential voltage before steady state when pre-emphasis or de- emphasis is implemented VSadj = 7.06 kΩ; PRE_SEL = NC, See Figure 8 800 1200 VOD(SS) Steady state output differential voltage VSadj = 7.06 kΩ; PRE_SEL = L, See Figure 9 600 1075 IOS Short circuit current limit Main link output shorted to GND 50 mA ILEAK Failsafe condition leakage current VCC = 0 V; VDD = 0 V; TMDS Outputs pulled to 3.3V through 50 Ω resistor 45 µA R(TERM) Source Termination resistance 150 300 Ω DDC and I2C VI-DC SCL/SDA_SNK, SCL/SDA_SRC DC input voltage –0.3 5.5 V SCL/SDA_CTL, DC input voltage –0.3 3.6 V VIL SCL/SDA_SNK, SCL/SDA_SRC Low level input voltage 0.3 x VCC V SCL/SDA_CTL Low level input voltage 0.3 x VCC V VIH SCL/SDA_SNK, SCL/SDA_SRC high level input voltage 3 V SCL/SDA_CTL high level input voltage 0.7 x VCC V VOL SCL/SDA_CTL, SCL/SDA_SRC low level output voltage IO = 3 mA and VCC > 2 V 0.4 V IO = 3 mA and VCC < 2 V 0.2 x VCC V fSCL SCL clock frequency fast I2C mode for local I2C control 400 kHz Cbus Total capacitive load for each bus line (DDC and local I2C pins) 400 pF HPD VIH High-level input voltage HPD_SNK 2.1 V VIL Low-level input voltage HPD_SNK 0.8 VOH High-level output voltage IOH = -500 µA; HPD_SRC 2.4 3.6 VOL Low-level output voltage IOL = -500 µA; HPD_SRC 0 0.1 ILEAK Failsafe condition leakage current VCC = 0 V; VDD = 0 V; HPD_SNK = 5 V 40 IH(HPD) High level input current Device powered; VIH = 5 V; IH(HPD) includes Rpd(HPD) resistor current 40 µA Device powered; VIL = 0.8 V; IH(HPD) includes Rpd(HPD) resistor current 30 Rpd(HPD) HPD input termination to GND; VCC < 0 V 150 190 220 kΩ SPDIF and ARC V(EL) Operating DC voltage for single mode ARC output Test at ARC_OUT, see Figure 19 0 5 V

TMDS171, TMDS171I SLLSEN7E –OCTOBER 2015– REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: TMDS171 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Electrical Characteristics (continued) The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C temperature. The Typical rating is simulated at 3.3 VCC and 1.2 V VDD and at 27°C temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN(DC) Operating DC voltage for SPDIF input 0.05 V V(SP_SW) Signal amplitude of SPDIF input 0.2 0.5 0.6 V V(ElSWING) Signal amplitude on the ARC output Test at ARC_OUT, 75 Ω external termination resistor, see Figure 19 0.4 0.5 0.6 V CLK(ARC) Signal frequency on ARC Test at ARC_OUT, see Figure 19 3.687 5.645±0. 1% 13.517 MHz Duty Cycle Output Clock Duty cycle 45% 50% 55% Data Rate SPDIF Input DR 7.373 11.29 27.034 Mbps tEDGE The rise/fall time for ARC output From 10% to 90% voltage level, see Figure 19 0.4 UI R(IN_SPDIF) The Input Termination resistance for SPDIF 75 Ω R(EST) Single mode Output Termination resistance 0.1 MHz to 128 times the maximum frame rate 36 55 75 Ω

6.6 Switching Characteristics

The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C temperature. The Typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TMDS Redriver Mode DR Data rate (Redriver mode) 250 3400 Mbps tPLH Propagation delay time (low to high) 250 600 ps tPHL Propagation delay time (high to low) 250 800 tT1 Transition time (rise and fall time); measured at 20% and 80% levels for Data Lanes. TX_TERM_CTL=L; PRE_SEL=NC; Data Rate 3.4 Gbps; Clock 340 MHz 75 tSK1(T) Intra-pair output skew TX_TERM_CTL=NC; PRE_SEL=NC; 40 tSK2(T) Inter-pair output skew TX_TERM_CTL=NC; PRE_SEL=NC; 100 tJITD1 Total output data jitter DR = 750 Mbps, PRE_SEL = NC, EQ_SEL/A0 = NC. See Figure 5 at TTP3 0.2 Tbit tJITC1 Total output clock jitter 0.25 TMDS Retimer Mode DR Data rate (retimer mod ) 1.2 3.4 Gbps d(XVR) Automatic redriver to Retimer Cross- Over Measured with input signal applied from 0 to 200 mVPP 0.75 1.00 1.25 Gbps f(CROSSOVE Crossover frequency hysteresis 250 MHz PLL(BW) Data Retimer PLL bandwidth Default loop bandwidth setting 0.4 1 MHz tACQ Input Clock Frequency Detection and Retimer Acquisition Time 180 µs IJT1 Input Clock Jitter Tolerance Tested when data rate > 1.0 Gbps 0.3 Tbit tT1 Transition time (rise and fall time); measured at 20% and 80% levels for Data Lanes. TMDS 75 ps tDCD OUT_CLK ± duty cycle 40% 50% 60% tSK_INTER Inter-pair output skew Default setting for internal inter-pair skew adjust, PRE_SEL = NC; TX_TERM_CTL = NC, DR ≤ 3.4 Gbps; See Figure 6

0.2 Tch

TMDS171, TMDS171I www.ti.com SLLSEN7E – OCTOBER 2015– REVISED SEPTEMBER 2017 Product Folder Links: TMDS171 Submit Documentation FeedbackCopyright © 2015–2017, Texas Instruments Incorporated Switching Characteristics (continued) The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C temperature. The Typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) The Maximum rating is simulated at 3.465 V VCC and 1.27 V VDD (2) Cb = total capacitance of one bus line in pF. tSK_INTRA Intra-pair output skew Default setting for internal intra-pair skew adjust, PRE_SEL = NC; TX_TERM_CTL = NC, DR ≤ 3.4 Gbps; See Figure 6

0.15 Tbit

tJITC2 Total output clock jitter CLK Rate ≤ 340 MHz 0.25 Tbit tJITD2 Total output data jitter DR ≤ 3.4 Gbps; See Figure 11 0.2 Tbit HPD tPD(HPD) Propagation delay from HPD_SNK to HPD_SRC; rising edge and falling edge(1) see Figure 13; not valid during switching time 40 120 ns tT(HPD) HPD logical disconnected timeout see Figure 14 2 ms DDC and I2C tr Rise time of both SDA and SCL signals VCC = 3.3 V 300 ns tf Fall time of both SDA and SCL signals 300 tHIGH Pulse duration, SCL high 0.6 µs tLOW Pulse duration, SCL low 1.3 tSU1 Setup time, SDA to SCL 100 ns tST,STA Setup time, SCL to start condition 0.6 µs tHD,STA Hold time, start condition to SCL 0.6 tST,STO Setup time, SCL to stop condition 0.6 t(BUF) Bus free time between stop and start condition 1.3 tPLH1 Propagation delay time, low-to-high- level output Source to Sink:100 kbps pattern; Cb(Sink) = 400 pF(2); see Figure 17 360 ns tPHL1 Propagation delay time, high-to-low- level output 230 tPLH2 Propagation delay time, low-to-high- level output Sink to Source: 100 kbps pattern; Cb(Source) = 100 pF(2); see Figure 18 250 tPHL2 Propagation delay time, high-to-low- level output 200

6.7 Typical Characteristics

Figure 1. Current vs Data Rate Redriver Mode Figure 2. Current vs Data Rate Retimer Mode Figure 3. VOD vs VSadj

7 Parameter Measurement Information

Figure 4. TMDS Main Link Test Circuit

8 Detailed Description

8.1 Overview

The TMDS171 is a digital video interface (DVI) or high-definition multimedia interface (HDMI) retimer. The TMDS171 supports four TMDS channels, Audio Return Channel (SPDIF_IN/ARC_OUT), Hot Plug Detect, and a Digital Display Control (DDC) interfaces. The TMDS171 supports signaling rates up to 3.4 Gbps to allow for the highest resolutions of 4k2k30p 24 bits per pixel and up to WUXGA 12-bit color depth or 1080p with higher refresh rates. The TMDS171 can automatically configure itself as a re-driver at low data rate (< 1 Gbps) or as a re-timer above this data rate. For passing compliance and reducing system level design issues several features have been included such as TMDS output amplitude adjust using an external resistor on the VSADJ pin and source termination selection control. Device operation and configuration can be programmed by pin strapping or I2C. Four TMDS171s can be used on one I2C bus when I2C_EN enable and device address set by A0/A1. To reduce active power the TMDS171 supports dual power supply rails of 1.2 V on VDD and 3.3 V on VCC. The TMDS171 supports several methods of power management. It can enter power down mode using three methods; (1) HPD is low; (2) Writing an 1 to register 09h[3]; or (3) de-asserting OE. If using OE, the device must be reprogrammed via I2C if it was originally programmed this way. The SIG_EN pin enables the signal detect circuit that provides an automatic power-management feature during normal operation. When no valid signal is present on the inputs the device enters Stand by mode. By disabling the detect circuit the receiver block is always on. DDC bridge supports 100 Kbps data rate default and 400 kbps adjustable by software. TMDS171 supports both fixed EQ gain control or adaptive equalization to compensate for different lengths of input cables or board traces. The EQ gain can be software adjusted by I2C control or selection between two fixed values or adaptive equalization by pin strapping EQ_SEL pin. Implementers can use the TX_TERM_CTL pin to change the transmitter termination impedance for better output performance when working in HDMI1.4b or leave it floating. When floating the TMDS171 in conjunction with the rate detect will automatically change its output termination to be compatible with HDMI1.4b requirements. The TMDS171 supports single ended mode audio return channel. To assist in ease of implementation the TMDS171 supports receive lane swapping and receive polarity swap. When swapping the input lanes IN_CLK and IN_D2 swap and IN_D1 and IN_D0 swap with each other. Swap works in both retimer and redriver mode. Polarity swap will swap the receive pins n and p channel polarity in each lane and is only available during retimer mode. Both lane swap and polarity swap can be implemented at the same time in retimer mode using I2C control. Two versions of the device are offered to support extended commercial temperature range 0ºC to 85ºC (TMDS171) or industrial operational temperature range from -40ºC to 85ºC (TMDS171I).

IN_CLKp IN_CLKn IN_D[2:0]p IN_D[2:0]n SIGNAL DETECT 50Q 50Q50Q 50Q Control Block, I2C Registers Local I2C Control I2C_EN/PIN EQ_SEL/A0 PRE_SEL Data Registers SWAP PLL PLL Control SERDES VBIAS VBIAS EQ_SEL TEST OUT_CLKp OUT_D[2:0]p OUT_CLKn OUT_D[2:0]n SWAP Polarity PLL BW STBY PWR DN EQ EQ EQ_CTL SDA_CTL SCL_CTL VSADJ SWAP/POL TX_TERM_CTL OE TEST/A1 TERM_SEL PRE_SEL Enable TMDS TMDS SIG_EN SIG_EN SIG_EN SIG_DET_OUT SIG_DET_OUT ACTIVE DDC BLOCK HPD_SNKHPD_SRC 130<Q SDA_SRC SCL_SRC SDA_SNK SCL_SNK ARC Function SPDIF_IN ARC_OUT GND VDD VCC 1.05V 3.3VVREG Copyright © 2016, Texas Instruments Incorporated TMDS171, TMDS171I www.ti.com SLLSEN7E – OCTOBER 2015– REVISED SEPTEMBER 2017 Product Folder Links: TMDS171 Submit Documentation FeedbackCopyright © 2015–2017, Texas Instruments Incorporated

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Reset Implementation

When OE is de-asserted, control signal inputs are ignored; the HDMI inputs and outputs are high impedance. It is critical to transition the OE from a low level to high after the VCC supply has reached the minimum recommended operating voltage. This is achieved by a control signal to the OE input, or by an external capacitor connected between OE and GND. To insure the TMDS171 is properly reset, the OE pin must be de-asserted for at least 100 μs before being asserted. When OE is re-asserted the TMDS171 will have to be reprogrammed if it

shown in Figure 21 and Figure 22. Figure 21. External Capacitor Controlled OE Figure 22. OE Input from Active controller

8.3.2 Operation Timing

Figure 24, Table 1. If OE is held low until VDD and VCC become stable there is no rail sequence requirement. Figure 23. Power up Timing for TMDS171

Figure 24. CDR Timing for TMDS171 Table 1. Power Up and Operation Timing Requirements

8.3.3 Swap and Polarity Working (Retimer Mode Only)

losing polarity swap. When the data rate drops to the redriver level, the polarity swap is lost. Table 2. SWAP Pin Mapping

36 TERM_CTL

Figure 25. TMDS171 Swap Function

8.3.4 TMDS Inputs

8.3.5 TMDS Inputs Debug Tools

implementer to determine how the link between the source and TMDS171 is performing on all three data lanes. See CSR BIT FIELD DEFINITIONS – RX PATTERN VERIFIER CONTROL/STATUS register.

8.3.6 Receiver Equalizer

the various EQ settings through local I2C control.

Figure 26. Adaptive EQ Gain Curve

8.3.7 Input Signal Detect Block

function in normal operation for power saving.

8.3.8 Audio Return Channel

default after initialization.

8.3.9 Transmitter Impedance Control

36, TX_TERM_CTL, offers a selection option to choose the output termination impedance value. Table 3. TX Termination Control

2 Gbps > DR < 3.4 Gbps – 150 - 300 Ω differential near end termination
DR < 2 Gbps – no termination

8.3.10 TMDS Outputs

sink capability, which provides a typical 500 mV voltage drop across a 50 Ω termination resistor. Figure 27. TMDS Driver and Termination Circuit signals are high impedance when OE = high. Both supplies being active are the normal operating condition. Table 11 for detail. Figure 1 shows the different output voltages based on the different VSADJ settings.

8.3.11 Pre-Emphasis/De-Emphasis

I2C, reg0Ch[1:0] is used to make these adjustments. Figure 28. Pre-emphasis Using Pin Strapping

Figure 29. Pre-emphasis Using I2C

8.4 Device Functional Modes

8.4.1 Retimer Mode

Clock and Data Recovery Circuits (CDR) are used to track, sample and retime the equalized data bit streams. the TMDS outputs. Input jitter within the CDR’s PLL bandwidth, < 1 MHz, is transferred to the TMDS outputs. JTOL for 480 Mbps the PLL must be forced to lock.

8.4.2 Redriver Mode

present, the system may not pass compliance at the connector.

8.4.3 DDC Functional Description

The TMDS171 solves sink/source level issues by implementing a master/salve control mode for the DDC bus. When the TMDS171 detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC, it transfers the data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK detects the feedback from the downstream device, the TMDS171 pulls up or pulls down the SDA_SRC bus and delivers the signal to the source. The DDC link defaults to 100 kbps but can be set to various values including 400 kbps by setting the correct value to address 0Bh through the I2C interface. The DDC lines are 5 V tolerant when the device is powered off. The HPD goes to high impedance when VCC is under low power conditions < 1.5 V. NOTE The TMDS171 utilizes clock stretching for DDC transactions. As there are sources and sinks that do not perform this function correctly as system may not work correctly as DDC transactions are incorrectly transmitted/recieved. To overcome this a snoop configuration can be implemented where the SDA/SCL from the source is connected directly to the SDA/SCL sink. The TMDS171 will need its SDA_SNK and SCL_SNK pins connected to this link.

8.4.4 Mode Selection Functional Description

Mode Selection Definition: reg0Ah[7] is the mode select register, see Table 9. This bit lets the receiver know where the device is located in a system for the purpose of centering the AEQ point. The TMDS171 is targeting sink or dock applications so the default value is 1 which centers the EQ at 12 dB to 13 dB, see Table 12. If the TMDS171 is in a source application the value should be changed to a 0 which centers the EQ at 6.5 dB to 7.5 dB.

8.5 Register Maps

8.5.1 Local I2C Overview

Table 4. TMDS171 I2C Device Address Description V tolerant and only support 3.3 V. Local I2C buses run at 400 kHz supporting fast-mode I2C operation.

The master initiates a write operation by generating a start condition (S), followed by the TMDS171 7-bit
The TMDS171 acknowledges the address cycle
The master presents the sub-address (I2C register within TMDS171) to be written, consisting of one byte of
The TMDS171 acknowledges the sub-address cycle
The master presents the first byte of data to be written to the I2C register
The TMDS171 acknowledges the sub-address cycle
TMDS171 acknowledges the byte transfer
The master may continue presenting additional bytes of data to be written, with each byte transfer completing
The master terminates the write operation by generating a stop condition (P)
The master initiates a read operation by generating a start condition (S), followed by the TMDS171 7-bit
The TMDS171 acknowledges the address cycle
The TMDS171 transmit the contents of the memory registers MSB-first starting at register 00h.
The TMDS171 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after
If an ACK is received, the TMDS171 transmits the next byte of data
The master terminates the read operation by generating a stop condition (P)

zeros, and writes are ignored.

8.5.1.1 BIT Access Tag Conventions

description, and the field access tags. The field access tags are described in Table 5. Table 5. Access Tags

8.5.2 CSR Bit Field Definitions, DEVICE_ID (offset: 00000000 ≈ 00000111) (reset:00h ≈ 07h)

Figure 30. CSR Bit Field Definitions, DEVICE_ID (00h ≈ 07h) Table 6. CSR Bit Field Definitions, DEVICE_ID (00h ≈ 07h) preceded by one space characters.

8.5.3 CSR Bit Field Definitions, REV _ID (offset: 00001000) (reset: 01h)

Figure 31. CSR Bit Field Definitions, REV _ID (08h) Table 7. CSR Bit Field Definitions, REV _ID (08h) 7:0 REV _ID R 01h This field identifies the device revision.

8.5.4 CSR BIT Field Definitions – Misc Control (offset: 00001001) (reset: 02h)

Figure 32. CSR Bit Field Definitions – Misc Control (09h) Table 8. CSR Bit Field Definitions – Misc Control (09h) 7 Lane_SWAP R/W/U 1’b0 This field Swaps the input lanes as per Figure 25. 6 LANE_POLARITY R/W/U 1’b0 Swaps the input Data and Clock lanes polarity.

5 Reserved R 1’b0 Reserved

4 SIG_EN R/W/U 1’b0 This field enable the clock lane activity detect circuitry. always works in normal operation. enter the standby state when no valid data detect.

3 PD_EN R/W 1’b0 0 – Normal working (default)

2 HPD_AUTO_PWRDWN_DISABLE R/W 1’b0 0 – Automatically enters power down mode based on HPD_SNK

1:0 I2C_DR_CTL R/W 2’b10 I2C data rate supported for configuring device.

8.5.5 CSR BIT Field Definitions – Misc Control (offset: 00001010) (reset: B1h)

Figure 33. CSR Bit Field Definitions – Misc Control (0Ah) Table 9. CSR Bit Field Definitions – Misc Control (0Ah)

7 Application Mode Selection R/W 1’b1 See Mode Selection

HPD_SRC whether held in the de-asserted state. 1 – HPD_SNK will not pass through to the HPD_SRC.

5 EQ_ADA_EN R/W 1’b1 This field enable the equalizer functioning state; Writes are

4 EQ_EN R/W 1’b1 This field enable the Equalizer; Writes are ignored when

3 Reserved R 1’b0 Reserved

2 APPLY_RXTX_CHANGES W 1’b0 Self-clearing write-only bit. HDMI clock applied and SIG_EN is high. 1:0 DEV_FUNC_MODE. R/W 2’b01 This field selects the Device Working Function Mode.

8.5.6 CSR BIT Field Definitions – Misc Control (offset: 00001011) (reset: 00h)

Figure 34. CSR Bit Field Definitions – Misc Control (0Bh) Table 10. CSR Bit Field Definitions – Misc Control (0Bh)

2 DDC_DR_SEL R/W 1’b0 Defines the DDC output speed for both DDC bridge and AUX-

8.5.7 CSR BIT Field Definitions – Misc Control (offset: 00001100) (reset: 00h)

Figure 35. CSR Bit Field Definitions – Misc Control (0Ch) Table 11. CSR Bit Field Definitions – Misc Control (0Ch) overridden by selecting one of the following values. 1:0 HDMI_TWPST1[1:0] R/W/U 2’b00 HDMI pre-emphasis FIR post-cursor-1 signed tap weight.

8.5.8 CSR BIT Field Definitions – Equalization Control Register (offset: 00001101) (reset: 01h)

Figure 36. CSR BIT Field Definitions – Equalization Control Register (0Dh) Table 12. CSR BIT Field Definitions – Equalization Control Register (0Dh) 2:1 Clock Lane EQ R/W 13’b000 - Sets Fixed EQ Values.

0 Reserved R 1’b1 Reserved

8.5.9 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00001110) (reset: 00h)

Figure 37. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Eh) Table 13. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Eh) cycle of the PRBS generator. 1 bit per lane. asserted low. 1 bit per lane.

8.5.10 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00001111) (reset: 00h)

Figure 38. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Fh) Table 14. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Fh) 7:4 PV_SYNC[3:0] R/U 4’b0000 Pattern verification mismatch detected. 1 bit per lane. 3:0 PV_LD[3:0] R/U 4’b0000 Pattern search/training in progress. 1 bit per lane.

8.5.11 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010000) (reset: 00h)

Figure 39. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (10h) Table 15. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (10h) 7 PV_CP20 R/W 1’b0 Customer pattern length 20/16 bits.

6 Reserved R 1’b0 Reserved

8.5.12 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010001) (reset: 00h)

Figure 40. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (11h) Table 16. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (11h) 7 PV_CP[7:0] R/W ‘h00 Custom pattern data.

8.5.13 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010010) (reset: 00h)

Figure 41. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (12h) Table 17. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (12h) 7 PV_CP[15:8] R/W ‘h00 Custom pattern data.

8.5.14 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010011) (reset: 00h)

Figure 42. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (13h) Table 18. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (13h) 3:0 PV_CP[19:16] R/W 4’b0000 Custom pattern data. Used when PV_CP20 = 1’b1.

8.5.15 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010100) (reset: 00h)

Figure 43. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (14h) Table 19. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (14h) 2:0 PV_THR[2:0] R/W 3’b000 Pattern-verifier retain threshold.

8.5.16 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010101) (reset: 00h)

Figure 44. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (15h) Table 20. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (15h) 7 DESKEW_CMPLT R 1’b0 Indicates that TMDS lane deskew has completed when high. 4 BERT_CLR R/S/U 1’b0 Clear BERT counter (on rising edge). 3 TST_INTQ_CLR R/S/U 1’b0 Clear latched interrupt flag. 2:0 TST_SEL[2:0] R/W 3’b000 Test interrupt source select.

8.5.17 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010110) (reset: 00h)

Figure 45. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (16h) Table 21. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (16h) TST_INT[0] and TST_INTQ[0] and PV_DP_EN is non-zero.

8.5.18 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010111) (reset: 00h)

Figure 46. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (17h) Table 22. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (17h) 3:0 RTST_INT[3:0] R/U 4’b0000 Test interrupt flag. 1 bit per lane.

8.5.19 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011000) (reset: 00h)

Figure 47. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (18h) Table 23. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (18h)

8.5.20 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011001) (reset: 00h)

Figure 48. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (19h) Table 24. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (19h)

8.5.21 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011010) (reset: 00h)

Figure 49. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ah) Table 25. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ah)

8.5.22 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011011) (reset: 00h)

Figure 50. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Bh) Table 26. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Bh)

8.5.23 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011100) (reset: 00h)

Figure 51. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ch) Table 27. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ch)

8.5.24 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011101) (reset: 00h)

Figure 52. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Dh) Table 28. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Dh)

8.5.25 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011110) (reset: 00h)

Figure 53. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Eh) Table 29. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Eh)

8.5.26 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011111) (reset: 00h)

Figure 54. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Fh) Table 30. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Fh)

8.5.27 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00100000) (reset: 00h)

Figure 55. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (20h) Table 31. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (20h) 7 PWR_DWN_STATUS R 1’b0 Power Down Status Bit.

Table 31. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (20h) (continued)

6 STB_STATUS R 1’b0 Standby Status Bit

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

to extend the cable length even further.

9.1.1 Application Chain Showing DDC Connections

limited by repeater delay/time of flight considerations for the maximum bus speed requirements. Figure 56. Typical Series Application

9.1.2 DDC Pull Up Resistors

resistor value is determined by two requirements.

The maximum sink current of the I2C buffer: The maximum sink current is 3 mA or slightly higher for an I2C

driver supporting standard-mode I2C operation.

The maximum transition time on the bus:

Table 32. Value k upon Different Input Threshold Voltages is allowed, Rup(min) can be as low as 1.375 kΩ. at 300 ns according to I2C specification. 50 pF, R(max) can be calculated as shown in Table 33. Table 33. Pull-Up Resistor Upon Different Threshold Voltages and 800-pF Loads

34 TMDS_D2n

a maximum 800 pF load capacitance for a standard-mode I2C bus.

9.2 Source Side Application

Figure 57. TMDS171 in Source Side Application

9.2.1 Design Requirements

device. Table 34 provides information on expected values in order to perform properly. Table 34. Design Parameters

9.2.2 Detailed Design Procedure

and connector when compliance is required at the connector.

Determine the loss profile between the GPU/chipset and the HDMI/DVI connector.
Based upon this loss profile and signal swing determine optimal location for the TMDS171, in order to pass source electrical compliance. Usually within 2”-3”of the connector
Use the typical application Figure 57 for information on control pin resistors.
The TMDS171 has a receiver adaptive equalizer but can also be configured using EQ_SEL control pin.
Set the VOD, Pre-emphasis, termination, and edge rate levels appropriately to support compliance by using the appropriate VSADJ resistor value and setting PRE_SEL, and TX_TERM_CTL control pins.
The thermal pad must be connected to ground.
See Figure 57 for recommended decouple capacitors from VCC and VDD pins to Ground

9.2.3 Application Curves

Figure 58. 1080p Compliance Eye Figure 59. 4k2k30 Compliance Eye

9.2.4 Sink Side Application

and behavior of the HDMI RX/Scalar. Figure 60. TMDS171 in Sink Side Application, 5 V HPD Implementation

9.2.4.1 Design Requirements

See Table 35 for the Sink Side design example parameters. Table 35. Design Parameters

9.2.4.2 Detailed Design Procedure

To design in the TMDS171 the following need to be understood for a source side application.

Determine the loss profile between the RX/chipset and the HDMI/DVI connector.
Based upon this loss profile and signal swing determine optimal location for the TMDS171, in order to pass sink electrical compliance.
Use the typical application Figure 56 for information on control pin resistors.
The TMDS171 has a receiver adaptive equalizer but can also be configured using EQ_SEL control pin.
Set the VOD, Pre-emphasis, termination, and edge rate levels appropriately to support link between TMDS171 and HDMI RX/Chipset by using the appropriate VSADJ resistor value and setting PRE_SEL and TX_TERM_CTL control pins.
The thermal pad must be connected to ground.
See Figure 60 for recommended decouple caps from VCC and VDD pins to Ground.

9.3 System Examples

sources are supporting clock stretching as per standard. Figure 61. TMDS171 in Sink Side Application

10 Power Supply Recommendations

To minimize the power consumption of customer application, TMDS171 used the dual power supply. VCC is 3.3 V with 5% range to support the I/O voltage. The VDD is 1.2 V with 1.1 V to 1.27 V range to supply the internal digital control circuit. TMDS171 operates in 3 different working states.

o Power down Mode: – OE = Low puts the device into its lowest power state by shutting down all function blocks. – When OE is re-asserted the transitions from L→H will create a reset and if the device is programmed through I2C it must to be reprogrammed. – Writing a 1 to register 09h[3]. – OE = High, HPD_SNK = Low
Standby Mode: HPD_SNK = High but no valid clock signal detect on clock lane.
Normal operation: Working in Redriver or Retimer
When HPD assert, the device CDR and output will enable based on the signal detector circuit result.
HPD_SRC = HPD_SNK in all conditions.

Table 36. Power Up and Operation Timing Requirements

11 Layout

11.1 Layout Guidelines

operate over the full temperature range by soldering the PowerPAD onto the thermal land without vias. allowing 545 mW power dissipation at 70°C ambient temperature. TI recommends six layers as the TMDS171 is a two voltage rail device.

Routing the high-speed TMDS traces on the top layer avoids the use of vias. (and the introduction of their inductances) and allows for clean interconnects from the HDMI connectors to the retimer inputs and outputs. It is important to match the electrical length of these high speed traces to minimize both inter-pair and intra- pair skew.
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission link interconnects and provides an excellent low –inductance path for the return current flow.
Placing a power plane next to the ground plane creates an additional high-frequency bypass capacitance.
Routing slower seed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to the stack to keep symmetry. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be place closer together, thus increasing the high frequency bypass capacitance significantly.

Figure 62. Recommended 4 or 6 Layer PCB Stack

11.2 Layout Example

Figure 63. Layout

12 Device and Documentation Support

12.1 Related Documentation

[HDMI] High-definition Multimedia Interface Specification Version 1.4b October, 2011 [HDMI] High-definition Multimedia Interface CTS Version 1.4b October, 2011 [I2C] The I2C-Bus specification version 2.1 January 2000

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments. is a trademark of ~HDMI.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 31-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TMDS171IRGZR Active Production VQFN (RGZ) | 48 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TMDS171I TMDS171IRGZR.A Active Production VQFN (RGZ) | 48 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TMDS171I TMDS171IRGZT Active Production VQFN (RGZ) | 48 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TMDS171I TMDS171IRGZT.A Active Production VQFN (RGZ) | 48 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TMDS171I TMDS171IRGZTG4 Active Production VQFN (RGZ) | 48 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TMDS171I TMDS171IRGZTG4.A Active Production VQFN (RGZ) | 48 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TMDS171I TMDS171RGZR Active Production VQFN (RGZ) | 48 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR 0 to 70 TMDS171 TMDS171RGZR.A Active Production VQFN (RGZ) | 48 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR 0 to 70 TMDS171 TMDS171RGZT Active Production VQFN (RGZ) | 48 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR 0 to 70 TMDS171 TMDS171RGZT.A Active Production VQFN (RGZ) | 48 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR 0 to 70 TMDS171 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 31-Oct-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMDS171IRGZR VQFN RGZ 48 2500 367.0 367.0 38.0 TMDS171IRGZT VQFN RGZ 48 250 210.0 185.0 35.0 TMDS171IRGZTG4 VQFN RGZ 48 250 210.0 185.0 35.0 TMDS171RGZR VQFN RGZ 48 2500 367.0 367.0 38.0 TMDS171RGZT VQFN RGZ 48 250 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRGZ 48 PLASTIC QUADFLAT PACK- NO LEAD7 x 7, 0.5 mm pitch 4224671/A

www.ti.com PACKAGE OUTLINE C 48X 0.30 0.18 4.1 0.1 48X 0.5 0.3

1 MAX

(0.2) TYP 0.05 0.0044X 0.5 5.5 2X 5.5 B 7.15 6.85 A 7.15 6.85 VQFN - 1 mm max heightRGZ0048B PLASTIC QUAD FLATPACK - NO LEAD 4218795/B 02/2017 PIN 1 INDEX AREA 0.08 C SEATING PLANE 12 25 13 24 48 37 (OPTIONAL) PIN 1 ID

0.1 C B A

0.05 EXPOSED THERMAL PAD

49 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 2.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

48X (0.24) 48X (0.6) ( 0.2) TYP VIA 44X (0.5) (6.8) (6.8) (1.115) TYP ( 4.1) (R0.05) TYP (0.685) TYP (1.115) TYP (0.685) TYP VQFN - 1 mm max heightRGZ0048B PLASTIC QUAD FLATPACK - NO LEAD 4218795/B 02/2017 SYMM 13 24 3748 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 48X (0.6) 48X (0.24) 44X (0.5) (6.8) (6.8) (1.37) TYP (R0.05) TYP ( 1.17) (1.37) TYP VQFN - 1 mm max heightRGZ0048B PLASTIC QUAD FLATPACK - NO LEAD 4218795/B 02/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:12X SYMM 13 24 3748

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Product Information

TMDS171IRGZR.A specifications and overview.

Summary

TMDS171/I 3.4 Gbps TMDS RETIMER REVISED SEPTEMBER 2017

Description

TMDS171/I 3.4 Gbps TMDS RETIMER REVISED SEPTEMBER 2017

Source title TMDS171IRGZR.A Datasheet(PDF) - Texas Instruments

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