TMS320C511A TI1 | Alldatasheet
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SPRS053 – FEBRUARY 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Powerful 16-Bit TMS320C511A CPU /C006820-, 20.8-, and 21.7-ns Single-Cycle Instruction Execution Time With 5-V Operation /C0068Single-Cycle 16 × 16-Bit Multiply/Add /C0068128K Words of Total Data/Program Space /C00686 × 4K × 16-Bit Single-Access On-Chip Program ROM /C00681K × 16-Bit Dual-Access On-Chip Program/Data RAM /C0068Full-Duplex Synchronous Serial Port for Code/Decode (CODEC) Interface /C0068Hardware or Software Wait-State Generation Capability /C0068Repeat Instructions for Efficient Use of Program Space /C0068Multiply-by-Two and Divide-by-Two Clocking Options /C0068Block Moves for Data/Program Management /C0068On-Chip Scan-Based Emulation Logic /C0068100-Pin Quad Flat Package (PJ Suffix) and 100-Pin Thin Quad Flat Package (PZ Suffix) /C0068Low-Power Dissipation and Power-Down Modes: – 47 mA (2.35 mA/MIPS) at 5 V, 40-MHz Clock (Average) – 3 mA at 5 V, 40-MHz Clock (Typical IDLE2) – 5 mA at 5 V, Clocks Off (Typical STANDBY) /C0068High-Performance Static CMOS Technology /C0068Databus Keepers
description
The TMS320C511A is a member of the ’C5x generation of the Texas Instruments (TI ) TMS320 digital signal processors (DSPs). This device is fabricated with static CMOS integrated circuit technology, and its architectural design is based on that of an earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of the ’C511A device. The ’C511A executes up to 50 MIPS (million instructions per second). The ’C5x generation DSPs, like the ’C511A, offer these advantages: /C0068Enhanced TMS320 architecture for increased performance and versatility /C0068Modular architecture for fast development of spin-off devices /C0068Advanced integrated-circuit processing technology for increased performance /C0068Source code for ’C1x and ’C2x DSPs is upward-compatible with ’C5x generation devices like the ’C511A /C0068Enhanced TMS320 instruction set for faster algorithms and for optimized high-level language operation /C0068New static-design techniques for minimizing power consumption and maximizing radiation hardness Table 1 lists the characteristics of the ’C511A processor: the capacity of on-chip RAM and ROM, the number of serial and parallel I/O ports, the execution time of one machine cycle, and the type of package with total pin count. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TI is a trademark of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated
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description (continued) TMS320C511A–PJ PACKAGE (TOP VIEW) VDDD VSSD VSSD TMS VDDD NC † TCK VSSD VSSD INT1 INT2 INT3 INT4 NMI DR VSSI FSR CLKR VDDA VSSA 100 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 SSA DDI TDI CLKMD1 A11 A12 A13 A14 A10 A15 MP/MC D10 D11 D12 D13 D14 V TRST CLKX HOLD READY BIO RS V V TOUT V V D15 DDA SSI SSC SSC SSC SSI EMU1/OFF EMU0 VDDC NC † VDDI VDDI CLKOUT1 XF HOLDA NC † DX VSSC FSX CLKMD2 VSSI VSSI TDO VDDC X2/CLKIN CLKMD3 BR STRB R/W PS IS DS VSSC WE RD V V V † NC = No connect (this pin is reserved)
SPRS053 – FEBRUARY 1997 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 description (continued) INT3 INT2 INT1 HOLDA TMS320C511A - PZ PACKAGE (TOP VIEW) †NC = No connect (this pin is reserved) EMU1/OFF VSSC RS READY HOLD BIO TRST VSSC MP/MC D15 D14 D12 D11 D10 VDDD 1EMU0 TOUT D13 VSSC RD VDDA A15 A14 A13 A12 A11 A10 CLKMD1 VSSA VSSA VDDI WE TDI 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 DDCV CLKOUT1 XF NC DX CLKMD2 TDO CLKMD3 BR R/W DS DDIV DDIV SSIV SSIV DDCV SSCV STRB PS IS 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SSDV TMS TCK SSDV DDDV INT4 NMI DR CLKR FSR FSX X2/CLKIN VSSA VSSI CLKX VSSC VSSC SSIV SSCV DDAV SSDV SSDV
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Table 1. Characteristics of the ’C511A Processor † Note that 16 of the 64K parallel I/O ports are memory-mapped. BR I/O/Z Bus request. BR arbitrates global memory and external DMA. RS I Reset. RS initializes the device and sets the program counter (PC) to zero. MP/MC I Microprocessor/microcomputer mode select. MP/MC enables internal ROM. HOLD I HOLD puts the parallel interface (I/F) bus in the high-impedance state after the current cycle. HOLDA O/Z Hold acknowledge. HOLDA indicates that the external bus is in hold state. XF O/Z External flag output. XF is set/cleared through software. BIO I I/O branch input. BIO implements conditional branches. TOUT O/Z Timer output signal. TOUT indicates output of the internal timer. DX O/Z Serial transmit-data output. DX is in the high-impedance state when not transmitting.
SPRS053 – FEBRUARY 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Functions for a TMS320C511A Device in the PJ/PZ Package (Continued) SIGNAL TYPE DESCRIPTION EMULATION/IEEE 1149.1 (JTAG) INTERFACE TDI I IEEE 1149.1 test-access-port scan data input TDO O/Z IEEE 1149.1 test-access-port scan data output TMS I IEEE 1149.1 test-access-port mode-select input TCK I IEEE 1149.1 test-access-port clock input TRST I IEEE 1149.1 test-access-port reset (with pulldown resistor). TRST disables JTAG when low. EMU0 I/O/Z Emulation control 0. EMU0 is reserved for emulation use. EMU1/OFF I/O/Z Emulation control 1. EMU1/OFF puts outputs in the high-impedance state when low. CLOCK GENERATION AND CONTROL X1 O Divide-by-two oscillator output X2/CLKIN I Divide-by-two clock/oscillator input CLKMD1, CLKMD2, CLKMD3 I Clock-mode select inputs CLKOUT1 O/Z Device system-clock output POWER SUPPLY CONNECTIONS VDDA S Supply connection, address-bus output VDDD S Supply connection, data-bus output VDDC S Supply connection, control output VDDI S Supply connection, internal logic VSSA S Supply connection, address-bus output VSSD S Supply connection, data-bus output VSSC S Supply connection, control output VSSI S Supply connection, internal logic Legend: I = Input O = Output Z = High impedance S = Supply architecture The ’C511A’s advanced Harvard-type architecture maximizes processing power by maintaining two memory bus structures — program and data — for full-speed execution. Instructions support data transfers between the two spaces. This architecture permits coefficients that are stored in program memory to be read into the RAM, thereby eliminating the need for a separate coefficient ROM. It also makes available immediate instructions and subroutines based on computed values. Increased throughput on the ’C511A for many DSP applications is accomplished by means of single-cycle multiply/accumulate instructions with a data-move option, up to eight auxiliary registers with a dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing. The architecture emphasizes overall speed, communication, and flexibility in processor configuration. Control signals and instructions provide floating-point support, block-memory transfers, communication to slower off-chip devices, and multiprocessing implementations (see the functional block diagram). Table 2 explains the symbols that are used in the functional block diagram.
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Table 2. Symbols Used in Functional Block Diagram
SPRS053 – FEBRUARY 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram Data Bus Program Bus Shifter(0–7) D15–D0 RBIT† A15–A0 DBMR(16) MUX 16 16 ACCB(32) ACCL(16)ACCH(16)C ALU(32) SFR(0–16) MUX MUX SFL(0–16) MUX PREG(32) Multiplier TREG0(16) MUX MUX B1 (512x16) B2 (32x16) DARAM B0 (512x16) DARAM from IR
7 LSB
DP(9) MUX 1616 ARAU(16) ARB(3) ARP(3) Program Bus 1616 CBSR2(16) CBSR1(16) AR7(16) AR6(16) AR5(16) AR3(16) AR2(16) AR1(16) AR0(16) ARCR(16) INDX(16) TOUT TCR PRD TIM Timer CLKR FSR DR FSX CLKX DX DRR DXR SPC Serial Port 1 TREG2(4) TREG1(5) BRCR(16) GREG(16) IFR(16) IMR(16) RPTC(16) PMST(16) ST1(16) ST0(16) BMAR(16) IR(16) PFC(16) MCS(16) PASR(16) Compare PAER(16) (8x16) Stack PC(16) MUX NMI WE RD CLKMD3 X2/CLKIN CLKOUT1 4INT(1–4) MP/MC RS HOLDA HOLD XF BR READY STRB R/W PS DS IS CLKMD2 CLKMD1 Control Data Bus Program Bus Data Bus Data Bus CBER2(16) CBER1(16) AR4(16) BIO MUX MUX NOTE A: Symbol descriptions appear in Table 2. † ROM protection feature Data/Prog SFL (–6, 0, 1, 4) PLU (16) Data Address Instruction Program ROM ’C511A 24K
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The 32-bit arithmetic logic unit (ALU) and accumulator (ACC) implement a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle. The ALU is a general-purpose arithmetic/logic unit that operates on 16-bit words taken from data memory or derived from immediate instructions. In addition to the usual arithmetic instructions, the ALU can perform Boolean operations, facilitating the bit manipulation ability required of a high-speed controller. One input to the ALU is always supplied by the ACC, and the other input can be furnished from the product register (PREG) of the multiplier, the accumulator buffer (ACCB), or the output of the scaling shifter (which has been read from data memory or from the ACC). After the ALU performs the arithmetic or logical operation, the result is stored in the ACC where additional operations, such as shifting, can be performed. Data input to the ALU can be scaled by the scaling shifter. The 32-bit ACC is split into two 16-bit segments for storage in data memory. Shifters at the output of the ACC provide a left shift of 0 to 7 places. This shift is performed while the data is being transferred to the data bus for storage. The contents of the ACC remain unchanged. When the postscaling shifter is used on the high word of the ACC (bits 31–16), the most significant bits (MSBs) are lost and the least significant bits (LSBs) are filled with bits shifted in from the low word (bits 15–0). When the postscaling shifter is used on the low word, the LSBs are filled with zeros. The ’C511A supports floating-point operations for applications requiring a large dynamic range. By performing left shifts, the normalization instruction (NORM) is used to normalize fixed-point numbers contained in the ACC. The four bits of TREG1 (the temporary register for dynamic shift count) define a variable shift through the scaling shifter for the ADDT/LACT/SUBT instructions (add to/load to/subtract from ACC with shift specified by TREG1). These instructions are useful in denormalizing a number (that is, converting from floating point to fixed point). They are also useful for executing an automatic gain control (AGC) going into a filter. The single-cycle 1-bit to 16-bit right shift of the ACC efficiently aligns the ACC’s contents. This, coupled with the 32-bit temporary buffer on the ACC, enhances the effectiveness of the ALU in extended-precision arithmetic. The ACCB provides a temporary storage place for a fast save of the ACC. The ACCB also can be used as an input to the ALU. The minimum or maximum value in a string of numbers is found by comparing the contents of the ACCB with the contents of the ACC. The minimum or maximum value is placed in both registers, and, if the condition is met, the carry bit (C) is set to 1. The minimum and maximum functions are executed by the CRLT and CRGT instructions, respectively. See Table 4 for a list of ’C511A instructions. scaling shifters The ’C511A provides a scaling shifter that has a 16-bit input connected to the data bus and a 32-bit output connected to the ALU. This scaling shifter produces a left shift of 0 to 16 bits on the input data. The shift count is specified by a constant embedded in the instruction word or by the value in TREG1. The LSBs of the output are filled with zeros; the MSBs may either be filled with zeros or sign-extended, depending upon the value of the sign-extension mode (SXM) bit of status register ST1. The ’C511A also contains several other shifters that allow it to perform numerical scaling, bit extraction, extended-precision arithmetic, and overflow prevention. These shifters are connected to the output of the product register and the ACC. parallel logic unit The parallel logic unit (PLU) is a second logic unit, additional to the main ALU, that executes logic operations on data without affecting the contents of the ACC. The PLU provides the bit-manipulation ability required of a high-speed controller and simplifies control/status register operations. The PLU provides a direct logic operation path to data memory space and can set, clear, test, or toggle multiple bits directly in a data memory location, a control/status register, or any register that is mapped into data memory space.
SPRS053 – FEBRUARY 1997 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 16 × 16-bit parallel multiplier The ’C511A uses a 16 × 16-bit hardware multiplier that is capable of computing a signed or an unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned) instruction, perform a signed multiply operation in the multiplier. That is, two numbers being multiplied are treated as 2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers associated with the multiplier: TREG0, a 16-bit temporary register that holds one of the operands for the multiplier, and PREG, the 32-bit product register that holds the product. Four product-shift modes (PM) are available at the PREG’s output. These shift modes are useful for performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products. The PM field of status register ST1 specifies the PM. The multiply instruction (MPY) allows the product to be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit 2s-complement numbers. A 4-bit shift is used in conjunction with the MPY instruction with a short-immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by a 13-bit number. Finally, the output of PREG can, instead, be right-shifted 6 bits to enable the execution of up to 128 consecutive multiply/accumulates without the possibility of overflow. The load-TREG0 (LT) instruction normally loads TREG0 to provide one operand (from the data bus), and the MPY instruction provides the second operand (also from the data bus). A multiplication also can be performed with a short- or long-immediate operand by using the MPY instruction with an immediate operand. A product is obtained every two cycles except when a long-immediate operand is used. Four multiply/accumulate instructions (MAC, MACD, MADD, and MADS as defined in Table 4) fully utilize the computational bandwidth of the multiplier, allowing both operands to be processed simultaneously. The data for these operations is transferred to the multiplier during each cycle through the program and data buses. This facilitates single-cycle multiply/accumulates when used with repeat (RPT and RPTZ) instructions. In these instructions, the coefficient addresses are generated by the PC, while the data addresses are generated by the auxiliary register arithmetic unit. This allows the repeated instruction to access the values sequentially from the coefficient table and step through the data in any of the indirect addressing modes. The RPTZ instruction also clears the accumulator and the product register to initialize the multiply/accumulate operation. The MACD and MADD instructions, when repeated, support filter constructs (weighted running averages) so that as the sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to eliminate the oldest sample. Circular addressing with MAC and MADS instructions also can be used to support filter implementation. auxiliary registers and auxiliary-register arithmetic unit (ARAU) The ’C511A provides a register file containing eight auxiliary registers (AR0–AR7). The auxiliary registers are used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register addressing allows placement of the data memory address of an instruction operand into one of the auxiliary registers. These registers are referenced with a 3-bit auxiliary-register pointer (ARP) that is loaded with a value from 0 through 7, designated AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded from data memory, the accumulator, the product register, or by an immediate operand defined in the instruction. The contents of these registers can be stored in data memory or used as inputs to the central arithmetic logic unit (CALU). These registers are accessible as memory-mapped locations within the ’C5x data-memory space. The auxiliary register file (AR0–AR7) is connected to the ARAU. The ARAU can autoindex the current auxiliary register while the data memory location is being addressed. Indexing can be performed either by adding or subtracting 1 or by the contents of the INDX register. As a result, accessing tables of information does not require the CALU for address manipulation; therefore, the CALU is free for other operations in parallel.
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The ’C511A implements three separate address spaces for program memory, data memory, and input/output (I/O). Each space accommodates a total of 64K 16-bit words (see Figure 1). Within the 64K words of data space, the 256 to 32K words at the top of the address range can be defined to be external global memory in increments of powers of two, as specified by the contents of the global-memory allocation register (GREG). Access to global memory is arbitrated using the global memory bus request (BR ) signal. The ’C511A device includes a considerable amount of on-chip memory to aid in system performance and integration including ROM and dual-access RAM (DARAM). Refer to Table 1 for the amount and types of memory available on this device. On the ’C511A, the first 96 (0–5Fh) data-memory locations are allocated for memory-mapped registers. This memory-mapped register space contains various control and status registers including those for the CPU, serial port, timer, and software wait-state generators. Additionally, the first 16 I/O port locations are mapped into this data-memory space, allowing them to be accessed either as data memory using single-word instructions or as I/O locations with two-word instructions. Two-word instructions allow access to the full 64K words of I/O space. The ’C511A contains 24K words of mask-programmable on-chip ROM located in program memory space. This ROM can be programmed with contents unique to to any particular application. The ROM is enabled or disabled by the state of the MP/MC control input upon resetting the device or by manipulating the MP/MC bit in the PMST status register after reset. The ROM occupies the first 24K words of internal program space (0–5FFFh) when enabled (which is the lowest block of program memory). When disabled, these addresses are located in the device’s external program-memory space. The ’C511A also has a mask-programmable option that provides security protection for the contents of on-chip ROM. When this internal option bit is programmed, no externally-originating instruction can access the on-chip ROM. This feature can be used to provide security for proprietary algorithms. The ’C511A also provides a total of 1 056 16-bit words of on-chip data RAM, divided into three separate blocks: block 0 (B0), block 1 (B1), and block 2 (B2). Of the 1056 words, 544 words (blocks B1 and B2) are always data memory and 512 words (block B0) are programmable as either data or program memory. A data-memory size of 1056 words allows the ’C511A to handle a data array of 1 024 words (512 words if on-chip RAM is used for program memory) while still leaving 32 locations for intermediate storage. When using block B0 as program memory, instructions can be downloaded from external program memory into on-chip RAM and then executed. The CLRC CNF (configure block B0 as data memory) and SETC CNF (configure block B0 as program memory) instructions allow dynamic configuration of the memory maps through software. Regardless of the configuration, code still can be executed from external program memory. When using on-chip RAM, ROM, or high-speed external memory, the ’C511A runs at full speed with no wait states. The ability of the DARAM to allow two accesses to be performed in one cycle, coupled with the parallel nature of the ’C511A architecture, enables the device to perform three concurrent memory accesses in any given machine cycle. Externally, the READY line can be used to interface the ’C511A to slower, less expensive external memory. Downloading programs from slow off-chip memory to on-chip RAM can speed processing while cutting system costs.
Figure 1. TMS320C511A Memory Map
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interrupts and subroutines The ’C511A implements four general-purpose interrupts, INT4–INT1, along with reset (RS) and the nonmaskable interrupt (NMI), which are available for external devices to request the attention of the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT), and by the software-interrupt (TRAP, INTR, and NMI) instructions. Interrupts are prioritized with RS having the highest priority, followed by NMI, and INT4 having the lowest priority. Additionally, any interrupt except RS and NMI can be masked individually with a dedicated bit in the interrupt-mask register (IMR) and can be cleared, set, or tested using its own dedicated bit in the interrupt-flag register (IFR). The reset and NMI functions are not maskable. All interrupt vector locations are on two-word boundaries so that branch instructions can be accommodated in those locations. While normally located at program memory address 0, the interrupt vectors can be remapped to the beginning of any 2K-word page in program memory by modifying the contents of the interrupt vector pointer (IPTR) located in the PMST status register. A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle instruction, the interrupt is not processed until the instruction completes execution. This mechanism applies to instructions that are repeated (using the RPT instruction) and to instructions that become multicycle because of wait states. Each time an interrupt is serviced or a subroutine is entered, the PC is pushed onto an internal hardware stack, providing a mechanism for returning to the previous context. The stack contains eight locations, allowing interrupts or subroutines to be nested up to eight levels deep. In addition to the eight-level hardware PC stack, eleven key CPU registers are equipped with an associated single-level stack or shadow register into which the registers’ contents are saved upon servicing an interrupt. The contents are restored into their particular CPU registers once a return-from-interrupt instruction (RETE or RETI) is executed. The registers that have the shadow-register feature include the ACC and buffer, product register, status registers, and several other key CPU registers. The shadow-register feature allows sophisticated context save and restore operations to be handled automatically in cases where nested interrupts are not required or if interrupt servicing is performed serially. power-down modes The ’C511A implements several power-down modes in which the ’C5x core enters a dormant state and dissipates considerably less power. A power-down mode is invoked either by executing the IDLE/IDLE2 instructions or by driving the HOLD input low. When the HOLD signal initiates the power-down mode, on-chip peripherals continue to operate; this power-down mode is terminated when HOLD goes inactive. While the ’C511A is in a power-down mode, all internal contents are maintained; this allows operation to continue unaltered when the power-down mode is terminated. All CPU activities are halted when the IDLE instruction is executed, but the CLKOUT1 pin remains active. The peripheral circuits continue to operate, allowing peripherals such as serial ports and timers to take the CPU out of its powered-down state. A power-down mode, when initiated by an IDLE instruction, is terminated upon receipt of an interrupt. The IDLE2 instruction is used for a complete shutdown of the core CPU as well as all on-chip peripherals. In IDLE2, the power is reduced significantly because the entire device is stopped. The power-down mode is terminated by activating any of the external interrupt pins (RS , NMI, INT1, INT2, INT3, and INT4) for at least five machine cycles. bus-keeper circuitry The ’C511A device provides built-in bus-keeper circuitry which holds the last state driven on the data bus by either the DSP or an external device after the bus is no longer being driven. This capability prevents excess power consumption caused by a floating bus, thereby allowing optimization of power consumption without the need for external pullup resistors.
SPRS053 – FEBRUARY 1997 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 external interface The ’C511A supports a wide range of system-interfacing requirements. Program, data, and I/O address spaces provide interface to memory and I/O, maximizing system throughput. The full 16-bit address and data bus, along with the PS , DS, and IS space select signals, allow addressing of 64K 16-bit words in each of the three spaces. Input/output design is simplified by having I/O treated the same way as memory. Input/output devices are mapped into the I/O address space using the processor’s external address and data buses in the same manner as memory-mapped devices. The ’C511A external parallel interface provides various control signals to facilitate interfacing to the device. The R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal provides a timing reference for all external cycles. For convenience, the device also provides the RD and the WE output signals, which indicate a read and a write cycle, respectively, along with timing information for those cycles. The availability of these signals minimizes external gating necessary for interfacing external devices to the ’C511A. Interface to memory and I/O devices of varying speeds is accomplished by using the READY line. When transactions are made with slower devices, the ’C511A processor waits until the other device completes its function and signals the processor through the READY line. Once a ready indication is provided back to the ’C511A from the external device, execution continues. The bus request (BR ) signal is used in conjunction with the other ’C511A interface signals to arbitrate external global-memory accesses. Global memory is external data-memory space in which the BR signal is asserted at the beginning of the access. When an external global-memory device receives the the bus request, the external device responds by asserting the READY signal after the global-memory access is arbitrated and completed. serial port The ’C511A provides a high-speed full-duplex serial port that allows direct interface with other ’C511A devices, CODECs, and other devices in a system. This serial port is capable of operating at up to one-fourth the machine cycle rate (CLKOUT1). The serial port uses two memory-mapped registers for data transfer: the data-transmit register (DXR) and the data-receive register (DRR). Both registers can be accessed in the same manner as any other memory location. The transmit and receive sections of the serial port each have associated clocks, frame-synchronization pulses, and serial-shift registers. Serial data can be transferred either in bytes or in 16-bit words. Serial port receive and transmit operations can generate their own maskable transmit and receive interrupts (XINT and RINT), allowing serial-port transfers to be managed through software. The ’C511A serial port is double-buffered and fully static. The ’C511A serial port can be used to activate one of the various methods of multiprocessing on the device. This can be accomplished by programming one device to transmit while the others are in the receive mode, thereby broadcasting a serial transfer to multiple receiving devices simultaneously. software wait-state generators Software wait-state generation is incorporated in the ’C511A without any external hardware for interfacing with slower off-chip memory and I/O devices. The circuitry consists of 16 wait-state generating circuits and is user-programmable to operate with 0, 1, 2, 3, or 7 wait states. For off-chip memory accesses, these wait-state generators are mapped on 16K-word boundaries in program memory, data memory, and the I/O ports.
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The ’C511A features a 16-bit timing circuit with a 4-bit prescaler. This timer clocks between one-half and one thirty-second the machine rate of the device itself, depending on the programmable timer’s divide-down ratio. This timer can be stopped, restarted, reset, or disabled by specific status bits. The timer can be used to generate CPU interrupts periodically. The timer is decremented by one at every CLKOUT1 cycle. A timer interrupt (TINT) and a pulse that is equal to the duration of a CLKOUT1 cycle on the external TOUT pin are generated each time the counter decrements to zero. The timer provides a convenient means of performing periodic I/O or other functions. When the timer is stopped, the internal clocks to the timer are shut off, allowing the device to run in a low-power mode of operation. JTAG interface The JTAG interface is for emulation purposes only. The JTAG scan logic is interfaced with other internal scanning logic circuitry, which has access to all of the on-chip resources. The ’C511A can perform on-board emulation by means of the JTAG serial scan pins and the emulation-dedicated pins. multiprocessing The flexibility of the ’C511A allows configurations to satisfy a wide range of system requirements. The device can be used in a variety of system configurations, including but not limited to the following: /C0068A stand-alone processor /C0068A multiprocessor with devices in parallel /C0068A slave/host multiprocessor with global-memory space /C0068A peripheral processor interfaced through processor-controlled signals to another device For multiprocessing applications, the ’C5x can allocate global-memory space and communicate with that space by the BR and ready-control signals. Global memory is data memory that is shared by more than one device. Global-memory access must be arbitrated. The 8-bit memory-mapped global-memory-allocation register (GREG) specifies part of the ’C511A’s data memory as external global memory. The contents of the register determine the size of the global-memory space. If the current instruction addresses an operand within that space, BR is asserted to request control of the bus. The length of the memory cycle is controlled by the READY line. The ’C511A supports direct memory access to its external program, data, and I/O spaces using the HOLD and HOLDA signals. Another device can take complete control of the ’C511A’s external-memory interface by asserting HOLD low. This causes the ’C511A to place its address, data, and control lines in the high-impedance state, and to assert HOLDA. When external memory is being accessed, program execution from on-chip memory can proceed concurrently when the device is in the hold mode. Multiple ’C511As can be interconnnected through the serial port. This form of interconnection allows information to be transferred at high speed while using a minimum number of signal connections. A complete full-duplex serial-port interconnection between multiple processors can be accomplished with as few as four signal lines. If more than two devices are being interconnected, one device may be programmed to transmit while the others are in the receive mode, thereby broadcasting a serial transfer to multiple receiving devices simultaneously. instruction set The ’C511A microprocessor implements a comprehensive instruction set that supports numeric-intensive signal-processing operations and general-purpose applications such as multiprocessing and high-speed control. Source code for the ’C1x and ’C2x DSPs is upward-compatible with the ’C5x generation devices like the ’C511A.
SPRS053 – FEBRUARY 1997 15POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 instruction set (continued) For maximum throughput, the next instruction is prefetched while the current one is being executed. Because the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an instruction requires to execute varies, depending on whether the next data-operand fetch is from internal or external memory. Highest throughput is achieved by maintaining data memory on chip and by using either internal or fast external program memory. addressing modes The ’C511A instruction set provides six basic memory-addressing modes: direct, indirect, immediate, register, memory-mapped, and circular addressing. In direct addressing, the instruction word contains the lower seven bits of the data-memory address. This field is concatenated with the nine bits of the data-memory page pointer (DP) to form the 16-bit data-memory address. Therefore, in the direct-addressing mode, data memory is effectively paged with a total of 512 pages, each page containing 128 words. Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers (AR0–AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively. There are seven types of indirect addressing: autoincrement or autodecrement, postindexing by either adding or subtracting the contents of AR0, single-indirect addressing with no increment or decrement, and bit-reversed addressing [used in Fast Fourier Transforms (FFTs)] with increment or decrement. All operations are performed on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary register and ARP can be modified. In immediate addressing, the actual operand data is provided in a portion of the instruction word or words. There are two types of immediate addressing: short and long. In short-immediate addressing, the data is contained in the lower eight bits in a single-word instruction. In long-immediate addressing, the data is contained in the second word of a two-word instruction. The immediate-addressing mode is useful for data that does not need to be stored or used more than once during the course of program execution, such as initialization values, constants, and so on. The register-addressing mode uses operands in CPU registers either explicitly, such as with a direct reference to a specific register, or implicitly with instructions that intrinsically reference certain registers. In either case, operand reference is simplified because 16-bit values can be used without specifying a full 16-bit operand address or immediate value. Memory-mapped addressing provides easy access to memory-mapped registers located on page zero of data memory. The flexibility of memory-mapped addressing results because accesses using this addressing mode are made independent of actual DP value and without having to provide a complete address of the memory location being accessed. Commonly used on-board registers can be accessed with a simplified addressing scheme. Circular addressing is the most sophisticated ’C511A addressing mode. This addressing mode allows specified buffers in memory to be accessed sequentially with a pointer that automatically wraps around to the beginning of the buffer when the last location is accessed. A total of two independent circular buffers can be allocated at any given time. Five dedicated registers are allocated for circular addressing: a beginning-of-buffer and an end-of-buffer register for each of the two independent circular buffers and a control register. Additionally, one of the auxiliary registers is used as the pointer into the circular buffer. All registers used in circular addressing must be properly initialized prior to performing any circular-buffer access.
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addressing modes (continued) The circular-addressing mode allows circular buffers, which permit data structures used in finite impulse response (FIR) filters, convolution and correlation algorithms, and waveform generators. Having the capability to access circular buffers automatically with no overhead allows these types of data structures to be used most efficiently. repeat feature The repeat function can be used with instructions such as multiply/accumulates (MAC and MACD), block moves (BLDD and BLPD), I/O transfers (IN/OUT), and table read/writes (TBLR/TBLW). These instructions, although normally multicycle, are pipelined when the repeat feature is used, and they effectively become single-cycle instructions. For example, the table-read instruction may take three or more cycles to execute, but when the instruction is repeated, a table location can be read every cycle. The repeat counter (RPTC) is a 16-bit register that, when loaded with a number N, causes the next single instruction to be executed N + 1 times. The RPTC register is loaded by either the RPT or the RPTZ instruction. This results in a maximum of 65536 executions of a given instruction. RPTC is cleared by reset. The RPTZ instruction clears both ACC and PREG before the next instruction starts repeating. Once a repeat instruction (RPT or RPTZ) is decoded, all interrupts, including NMI (except reset), are masked until the completion of the repeat loop. However, the device responds to the HOLD signal while executing an RPT/RPTZ loop. The ’C5x also implements a block-repeat feature that provides zero-overhead looping for FOR and DO loops. The function is controlled by three registers (PASR, PAER, and BRCR) and the BRAF bit in the PMST register. The block-repeat counter register (BRCR) is loaded with a loop count of 0 to 65535. Then, execution of the RPTB (repeat block) instruction loads the block-repeat-address start register (PASR) with the address of the instruction following the RPTB instruction and loads the block-repeat-address end register (PAER) with its long-immediate operand. The long-immediate operand is the address of the instruction following the last instruction in the loop minus one. (The repeat block must contain at least three instruction words.) Execution of the RPTB instruction automatically sets active the BRAF bit. With each PC update, the PAER contents are compared to the PC. If they are equal, the BRCR contents are compared to zero. If the BRCR contents are greater than zero, BRCR is decremented and the PASR is loaded into the PC, thereby starting the loop over. If not, the BRAF bit is set low and the processor resumes execution past the end of the code’s loop. The equivalent of a WHILE loop can be implemented by setting the BRAF bit to zero if the exit condition is met. The program then completes the current pass through the loop but does not go back to the top. To exit, the bit must be reset at least four instruction words before the end of the loop. It is possible to exit block-repeat loops and return to them without stopping and restarting the loop. Branches, calls, and interrupts do not necessarily affect the loop. When program control is returned to the loop, loop execution is resumed. instruction set summary This section summarizes the operational codes (opcodes) of the instruction set for the ’C5x DSPs. The instruction set is a superset of the ’C1x and ’C2x instruction sets. The instructions are arranged according to function and are alphabetized by mnemonic within each category. The symbols in Table 3 describe the opcode symbols used in Table 4. The Texas Instruments ’C5x assembler accepts ’C2x instructions as well as ’C5x instructions. The number of words that an instruction occupies in program memory is specified in column 4 of Table 4. In these cases, different forms of the instruction occupy a different number of words. For example, the ADD instruction occupies one word when the operand is a short-immediate value or two words if the operand is a long-immediate value. The number of cycles that an instruction requires to execute is listed in column 5 of Table 4. All instructions are assumed to be executed from internal program memory and internal data dual-access memory. The cycle timings are for single-instruction execution, not for repeat mode.
cycle to the cycle time shown because all peripherals perform these accesses over the internal peripheral bus. Table 3. Opcode Symbols is ANDed with the conditions. If any bits are set, the conditions are met.
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Table 4. TMS320C511A Instruction Set Opcodes
0010 SHFT IAAA AAAA
0001 SHFT IAAA AAAA
0011 SHFT IAAA AAAA
Table 4. TMS320C511A Instruction Set Opcodes (Continued)
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0100 BITX IAAA AAAA
debug software and hardware modules.
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(SPRU052), which contains information about TMS320-related products from other companies in the industry. To receive copies of TMS320 literature, contact the Literature Response Center at 800/477-8924. availability, contact the nearest TI field sales office or authorized distributor. Table 5. TMS320C511A Development-Support Tools through fully qualified production devices/tools (TMS/TMDS). This development flow is defined below. PC-DOS and OS/2 are trademarks of International Business Machines Corp. SPARC is a trademark of SPARC International, Inc. WIN is a trademark of Microsoft Corp. HP is a trademark of Hewlett-Packard Company. XDS is a trademark of Texas Instruments Incorporated.
of the device have been demonstrated fully. TI’s standard warranty applies. expected end-use failure rate still is undefined. Only qualified production devices are to be used. complete device name for any TMS320 or TMX320 family member. Figure 2. Device Nomenclature describes in detail the fifth-generation TMS320 products, is also currently available. code and object code for many DSP algorithms and utilities. The BBS can be reached at 713/274-2323.
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absolute maximum ratings over operating case temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VDD Supply voltage 4.75 5 5.25 V VSS Supply voltage 0 V X2/CLKIN 3 VDD +0.3 VIH High-level input voltage CLKX, CLKR 2.5 VDD +0.3 V All other inputs 2 VDD +0.3 VIL Low level input voltage X2/CLKIN, CLKX, CLKR – 0.3 0.7 VVIL Low-level input voltage All other inputs – 0.3 0.8 V IOH High-level output current (see Note 2) – 300 mA IOL Low-level output current 2 mA TC Operating case temperature 0 85 °C NOTE 2: Figure 3 shows the test load circuit: Figure 4 and Figure 5 show the voltage reference levels. electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High-level output voltage (see Note 2)IOH = – 300 mA 2.4 3 V VOL Low-level output voltage (see Note 2)IOL = 2 mA 0.3 0.6 V IOZ High-impedance output current BR (with internal pullup) –500 20 mAIOZ g (VDD = 5.25 V) All other 3-state outputs –2 0 20 mA TRST (with internal pulldown) –1 0 800 II Input current (VI=V SS to VDD ) TMS, TCK, TDI (with internal pullups)–500 10 mAII Input current (VI = VSS to VDD ) X2/CLKIN –5 0 50 mA All other inputs –1 0 10 VDD = 5.25 V, fx = 92 MHz 102 IDD(core) Supply current, core CPU VDD = 5.25 V, fx = 96 MHz 106 mA() VDD = 5.25 V, fx = 100 MHz 110 VDD = 5.25 V, fx = 92 MHz 69 IDD(pins) Supply current, pins VDD = 5.25 V, fx = 96 MHz 72 mA() VDD = 5.25 V, fx = 100 MHz 75 IDD(standby) Supply current, standby IDLE2, divide-by-two clock mode, clocks shut off 5 mA C i Input capacitance 15 pF C o Output capacitance 15 pF † Typical values are at VDD = 5 V, ambient-air temperature = 25°C, unless otherwise specified. NOTE 2: Figure 3 shows the test load circuit; Figure 4 and Figure 5 show the voltage reference levels.
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PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their meanings: Letters and symbols and their meanings: a access time H High c cycle time (period) L Low d delay time V Valid dis disable time Z High impedance en enable time f fall time h hold time r rise time su setup time t transition time v valid time w pulse duration (width) X Unknown, changing, or don’t care level
Table 6. PLL Clock Option for TMS320C511A an external crystal (fundamental frequency) connected to the on-chip oscillator. 0 Hz but is tested at fx = 6.7 MHz to meet device test time requirements. Figure 6. Internal Clock Option specifications are subject to change without notice.
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specifications listed in the timing requirements table. approaching 0 Hz but is tested at tc(CO) = 300 ns to meet device test time requirements. approaching 0 Hz, but is tested at a minimum of tc(Cl) = 150 ns to meet device test time requirements. § Values are derived from characterization data and are not tested. Figure 7. External Divide-by-Two Clock Timing specifications are subject to change without notice.
SPRS053 – FEBRUARY 1997 29POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 CLOCK CHARACTERISTICS AND TIMING (CONTINUED) PLL clock generator option An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. This external frequency is multiplied by the factors shown in Table 6 to generate the internal machine cycle. A multiplication factor of 2 is available on the ’C511A device. Refer to Table 6 for the appropriate configuration of the CLKMD1, CLKMD2, and CLKMD3 pins to generate this desired PLL multiplication factor. The external frequency injected must conform to the specifications listed in the timing requirements table. switching characteristics over recommended operating conditions [H = 0.5 tc(CO)] (see Figure 8) PARAMETER ’320C511A-92 ’320C511A-96 UNITPARAMETER MIN TYP MAX MIN TYP MAX UNIT tc(CO) Cycle time, CLKOUT1 21.7 55 20.8 50 ns tf(CO) Fall time, CLKOUT1 4 4 ns tr(CO) Rise time, CLKOUT1 4 4 ns tw(COL) Pulse duration, CLKOUT1 low H – 3† H H + 2† H – 3† H H + 2† ns tw(COH) Pulse duration, CLKOUT1 high H – 3† H H + 2† H – 3† H H + 2† ns td(CIH-COH) Delay time, X2/CLKIN high to CLKOUT1 high 1 8 15 1 8 15 ns td(TP) Delay time, transitory phase—PLL synchronized after X2/CLKIN supplied 1500tc(CI)† 1500tc(CI)† ns PARAMETER ’320C511A-100 UNITPARAMETER MIN TYP MAX UNIT tc(CO) Cycle time, CLKOUT1 20 45 ns tf(CO) Fall time, CLKOUT1 4 ns tr(CO) Rise time, CLKOUT1 4 ns tw(COL) Pulse duration, CLKOUT1 low H – 3† H H + 2† ns tw(COH) Pulse duration, CLKOUT1 high H – 3† H H + 2† ns td(CIH-COH) Delay time, X2/CLKIN high to CLKOUT1 high 1 8 15 ns td(TP) Delay time, transitory phase—PLL synchronized after X2/CLKIN supplied 1500tc(CI)† ns † Values are assured by design and are not tested. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
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restarting clock from IDLE2 in this mode. ‡ Values are derived from characterization data and are not tested. Figure 8. PLL Clock Generator Timing specifications are subject to change without notice.
SPRS053 – FEBRUARY 1997 31POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MEMORY AND PARALLEL I/O INTERFACE READ switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 9) PARAMETER ’320C511A-92 ’320C511A-96 ’320C511A-100 UNIT MIN MAX MIN MAX tsu(AV-RDL) Setup time, address valid before RD low† H – 7‡ H – 6‡ ns th(RDH-AV) Hold time, address valid after RD high† 0‡ 0‡ ns tw(RDL) Pulse duration, RD low§¶# H – 2 H + 2 H – 2 H + 2 ns tw(RDH) Pulse duration, RD high§¶# H – 2 H – 2 ns td(CO-ST) Delay time, CLKOUT1 to STRB rising or falling edge§¶ – 2 2 – 2 2 ns td(CO-RD) Delay time, CLKOUT1 to RD rising or falling edge§¶ – 3 1 – 3 1 ns td(RDH-WEL) Delay time, RD high to WE low 2H – 4 2H – 4 ns timing requirements over recommended ranges of supply voltage and operating case temperature [H = 0.5tc(CO)] (see Figure 9) ’320C511A-92 ’320C511A-96 ’320C511A-100 UNIT MIN MAX MIN MAX MIN MAX UNIT ta(RD-AV) Access time, read data from address valid 2H – 6.7† 2H – 8.8† 2H – 8† ns ta(RDL-RD) Access time, read data after RD low H – 3 H – 3 H – 3 ns tsu(RD-RDH) Setup time, read data before RD high 3 3 3 ns th(RDH-RD) Hold time, read data after RD high 2 2 2 ns † A0–A15, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address. ‡ See Figure 10 for address-bus timing variation with load capacitance. § These timings are for the cycles following the first cycle after reset, which is always seven wait states. ¶ Values are derived from characterization data and are not tested. # Timings are valid for zero wait-state cycles only. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
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MEMORY AND PARALLEL I/O INTERFACE WRITE switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 9) PARAMETER ’320C511A-92 ’320C511A-96 ’320C511A-100 UNIT MIN MAX MIN MAX tsu(AV-WEL) Setup time, address valid before WE low† H–4 ‡ H–3 ‡ ns tsu(WDV-WEH) Setup time, write data valid before WE high 2H – 14 2H §¶ 2H – 14 2H §¶ ns th(WEH-AV) Hold time, address valid after WE high† H–7 ‡ H–7 ‡ ns th(WEH-WDV) Hold time, write data valid after WE high H–4 H+7 § H–4 H+7 § ns tw(WEL) Pulse duration, WE low§¶ 2H – 2 2H + 2 2H – 2 2H + 2 ns tw(WEH) Pulse duration, WE high§ 2H – 2 2H – 2 ns td(CO-ST) Delay time, CLKOUT1 to STRB rising or falling edge§ –2 2 –2 2 ns td(CO-WE) Delay time, CLKOUT1 to WE rising or falling edge§ –1 3 –1 3 ns td(WEH-RDL) Delay time, WE high to RD low 3H – 7 3H – 7 ns ten(WEL-BUd) Enable time, WE low to data bus driven –4 § –4 § ns † A0–A15, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address. ‡ See Figure 10 for address-bus timing variation with load capacitance. § Values are derived from characterization data and are not tested. ¶ This value holds true for zero wait states or one software wait state only. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
read or immediately followed by an external read require three machine cycles. B. Refer to Appendix B of TMS320C5x User’s Guide (literature number SPRU056) for logical timings of external interface. Figure 9. Memory and Parallel I/O Interface Read and Write Timing
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Figure 10. Address-Bus Timing Variation With Load Capacitance
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require an extra half-cycle to ensure internal synchronization. ‡ These values are derived from characterization data and are not tested. § If in IDLE2, add 4H to these timings. Figure 13. Reset, Interrupt, and BIO Timings specifications are subject to change without notice.
Figure 14. TOUT and XF Timing Example specifications are subject to change without notice.
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† HOLD is not acknowledged until current external access request is complete. ‡ This parameter includes all memory control lines. § Values are derived from characterization data and are not tested. Figure 15. External DMA Timing specifications are subject to change without notice.
† Values are assured by design but are not tested. of 0 Hz but tested at a much higher frequency to minimize test time. § Values are derived from characterization data and are not tested. Figure 16. Serial-Port Receive Timing specifications are subject to change without notice.
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† Values are derived from characterization data and are not tested. ‡ Values are assured by design but are not tested. of 0 Hz but tested at a much higher frequency to minimize test time. th(CXH-FXL) specifications are met. independent of the source of CLKX. Figure 17. Serial-Port Transmit Timing of External Clocks and External Frames specifications are subject to change without notice.
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PJ (R-PQFP-G100) PLASTIC QUAD FLATPACK 4040012/B 03/95 0,15 NOM 18,0014,20 17,2013,80 12,35 TYP 0,25 0,70 1,10 0,10 MIN Gage Plane 18,85 TYP 100 20,20 19,80 23,20 24,00 3,10 MAX 2,70 TYP 0,20 0,40 Seating Plane 0,15 0,65 M0,13 0°–10° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package. Thermal Resistance Characteristics PARAMETER °C/W R Q JA 78 R Q JC 13
SPRS053 – FEBRUARY 1997 43POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 4040149/B 11/96 26 0,13 NOM Gage Plane 0,25 0,45 0,75 0,05 MIN 0,27 12,00 TYP 0,17 100 SQ SQ15,80 16,20 13,80 1,35 1,45 1,60 MAX 14,20 0°–7° Seating Plane 0,08 0,50 M0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 Thermal Resistance Characteristics PARAMETER °C/W R Q JA 58 R Q JC 10
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