Sensor

TMCS1100A4QDRQ1

Texas Instruments

TMCS1100-Q1 AEC-Q100, 1% High-Precision, Basic Isolation Hall-Effect Current Sensor With 짹600-V Working Voltage

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TMCS1100-Q1 AEC-Q100, 1% High-Precision, Basic Isolation Hall-Effect Current Sensor With ±600-V Working Voltage

1 Features

AEC-Q100 qualified for automotive applications – Temperature Grade 1: –40°C to 125°C, TA
Functional Safety-Capable – Documentation available to aid functional safety system design
Total error: ±0.4% typical, ±0.9% maximum, –40°C to 85°C – Sensitivity error: ±0.4% – Offset error: 7 mA – Offset drift: 0.04 mA/°C – Linearity error: 0.05%
Lifetime and environmental drift: <±0.5%
3-kVRMS isolation rating
Robust 600-V lifetime working voltage
Bidirectional and unidirectional current sensing
External reference voltage
Operating supply range: 3 V to 5.5 V
Signal bandwidth: 80 kHz
Multiple sensitivity options: – TMCS1100A1-Q1: 50 mV/A – TMCS1100A2-Q1: 100 mV/A – TMCS1100A3-Q1: 200 mV/A – TMCS1100A4-Q1: 400 mV/A
Safety related certifications – UL 1577 Component Recognition Program – IEC/CB 62368-1

2 Applications

Motor and load control
Inverter and H-bridge current measurements
Power factor correction
Overcurrent protection
DC and AC power monitoring

3 Description

The TMCS1100-Q1 is a galvanically isolated Hall- effect current sensor capable of DC or AC current measurement with high accuracy, excellent linearity, and temperature stability. A low-drift, temperature- compensated signal chain provides < 1% full-scale error across the device temperature range. The input current flows through an internal 1.8-m Ω conductor that generates a magnetic field measured by an integrated Hall-effect sensor. This structure eliminates external concentrators and simplifies design. Low conductor resistance minimizes power loss and thermal dissipation. Inherent galvanic insulation provides a 600-V lifetime working voltage and 3-kVRMS basic isolation between the current path and circuitry. Integrated electrical shielding enables excellent common-mode rejection and transient immunity. The output voltage is proportional to the input current with four sensitivity options. Fixed sensitivity allows the TMCS1100-Q1 to operate from a single 3-V to 5.5-V power supply, eliminates ratiometry errors, and improves supply noise rejection. The current polarity is considered positive when flowing into the positive input pin. The VREF input pin provides a variable zero-current output voltage, enabling bidirectional or unidirectional current sensing. The TMCS1100-Q1 draws a maximum supply current of 6 mA, and all sensitivity options are specified over the operating temperature range of –40°C to +125°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TMCS1100-Q1 SOIC (8) 4.90 mm × 3.90 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Bridge DriverPassive / PFC Rectifier DC V+ DC V– Controller Current Sense Loads Current Sense Current SenseControl Control TMCS1100-Q1 TMCS1100-Q1 TMCS1100-Q1 AC Typical Application TMCS1100-Q1 SBOSA43 – JUNE 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

13.3 Receiving Notification of Documentation Updates..40

14 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES June 2021 * Initial release. TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

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5 Device Comparison

Table 5-1. Device Comparison PRODUCT SENSITIVITY BIDIRECTIONAL LINEAR MEASUREMENT RANGE, VREF = VS / 2(1) UNIDIRECTIONAL LINEAR MEASUREMENT RANGE, VREF = VGND (1) ΔVOUT / ΔIIN+, IN– VS = 5 V VS = 3.3 V VS = 5 V VS = 3.3 V TMCS1100A1-Q1 50 mV/A ±46 A(2) ±29 A(2) 1 A to 96 A(2) 1 A to 62 A(2) TMCS1100A2-Q1 100 mV/A ±23 A(2) ±14.5 A 0.5 A to 48 A(2) 0.5 A to 31 A(2) TMCS1100A4-Q1 400 mV/A ±5.75 A -- 0.125 A to 12 A -- (1) Linear range limited by swing to supply and ground. (2) Current levels must remain below both allowable continuous DC/RMS and transient peak current safe operating areas to not exceed device thermal limits. See the Safe Operating Area section.

6 Pin Configuration and Functions

3IN± 6 VREF 4IN± 5 GND Not to scale Figure 6-1. D Package 8-Pin SOIC Top View Table 6-1. Pin Functions PIN I/O DESCRIPTION NO. NAME

1 IN+ Analog input Input current positive pin

2 IN+ Analog input Input current positive pin

3 IN– Analog input Input current negative pin

4 IN– Analog input Input current negative pin

5 GND Analog Ground

6 VREF Analog input Zero current output voltage reference

7 VOUT Analog output Output voltage

8 VS Analog Power supply

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VS Supply voltage GND – 0.3 6 V Analog input VREF GND – 0.3 (VS) + 0.3 V Analog output VOUT GND – 0.3 (VS) + 0.3 V TJ Junction temperature –65 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN+,VIN– (1) Input voltage –600 600 VPK VS Operating supply voltage, TMCS1100A1-Q1-A3-Q1 3 5 5.5 V VS Operating supply voltage, TMCS1100A4-Q1 4.5 5 5.5 V TA (2) Operating free-air temperature –40 125 °C (1) VIN+ and VIN– refer to the voltage at input current pins IN+ and IN–, relative to pin 5 (GND). (2) Input current safe operating area is constrained by junction temperature. Recommended condition based on the TMCS1100EVM . Input current rating is derated for elevated ambient temperatures.

7.4 Thermal Information

THERMAL METRIC(1) TMCS1100 -Q1 (2) UNITD (SOIC)

8 PINS

RθJA Junction-to-ambient thermal resistance 36.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.7 °C/W RθJB Junction-to-board thermal resistance 9.6 °C/W ΨJT Junction-to-top characterization parameter –0.1 °C/W ΨJB Junction-to-board characterization parameter 11.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Applies when device mounted on TMCS1100EVM . For more details, see the Safe Operating Area section. TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

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7.5 Power Ratings

VS = 5.5 V, VREF = GND, TA = 125℃, TJ = 150℃, device soldered on TMCS1100EVM . PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PD Maximum power dissipation (both sides) 673 mW PD1 Maximum power dissipation (current input, side-1) IIN = 16 A 640 mW PD2 Maximum power dissipation by (side-2) VS = 5.5 V, IQ = 6mA, no VOUT load 33 mW

7.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT GENERAL CLR External clearance(1) Shortest terminal-to-terminal distance through air 4 mm CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface 4 mm DTI Distance through the insulation Minimum internal gap (internal clearance) 60 µm CTI Comparative tracking index DIN EN 60112; IEC 60112 >400 V Material group II Overvoltage category Rated mains voltage ≤ 150 VRMS I-IV Rated mains voltage ≤ 300 VRMS I-III VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 600 VPK VIOWM Maximum working isolation voltage AC voltage (sine wave); Time Dependent Dielectric Breakdown test, see Insulation Lifetime. 424 VRMS DC voltage 600 VDC VIOTM Maximum transient isolation voltage VTEST = VIOTM = 4242VPK, t = 60 s (qualification); VTEST = 1.2 × VIOTM = 5090VPK, t = 1 s (100% production)

4242 VPK

VIOSM Maximum surge isolation voltage(2) Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.3 × VIOSM = 7800VPK (qualification)

6000 VPK

qpd Apparent charge(3) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM = 4242VPK, tini = 60 s; Vpd(m) = 1.2 × VIORM = 700VPK, tm = 10 s pC Method a: After environmental tests subgroup 1, Vini = VIOTM = 4242VPK, tini = 60 s; Vpd(m) = 1.2 × VIORM = 700VPK, tm = 10 s Method b3: At routine test (100% production) and preconditioning (type test) Vini = 1.2 × VIOTM = 5090VPK, tini = 1 s; Vpd(m) = 1.2 × VIOTM = 5090VPK, tm = 1 s CIO Barrier capacitance, input to output(4) VIO = 0.4 sin (2πft), f = 1 MHz 0.6 pF RIO Isolation resistance, input to output(4) VIO = 500 V, TA = 25°C >1012 Ω VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 Ω VIO = 500 V at TS = 150°C >109 Ω Pollution degree 2 UL 1577 VISO Withstand isolation voltage VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 × VISO, t = 1 s (100% production)

3000 VRMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Take care to maintain the creepage and clearance distance of the board design to make sure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications. (2) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TMCS1100-Q1

(3) Apparent charge is electrical discharge caused by a partial discharge (pd). (4) All pins on each side of the barrier tied together creating a two-terminal device

7.7 Safety-Related Certifications

UL 1577 Component Recognition Program Certified according to IEC 62368-1 CB File number: E181974 Certificate number: US-36733-UL

7.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IS Safety input current (side 1)(1) RθJA = 36.6°C/W, TJ = 150°C, TA = 25°C, see Thermal Derating Curve, Side 1. 30 A IS Safety input, output, or supply current (side 2)(1) RθJA = 36.6°C/W, VI = 5 V, TJ = 150°C, TA = 25°C, see Thermal Derating Curve, Side 2. 0.68 PS Safety input, output, or total power(1) RθJA = 36.6°C/W, TJ = 150°C, TA = 25°C, see Thermal Derating Curve, Both Sides. 3.4 W TS Safety temperature(1) 150 ℃ (1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on the TMCS1100EVM . Use these equations to calculate the value for each parameter: TJ = TA + RθJA × P, where P is the power dissipated in the device. TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature. PS = IS × VI, where VI is the maximum input voltage. TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

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7.9 Electrical Characteristics

at TA = 25°C, VS = 5 V, VREF = 2.5 V (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT OUTPUT Sensitivity(7) TMCS1100A1-Q1 50 mV/A TMCS1100A2-Q1 100 mV/A TMCS1100A3-Q1 200 mV/A TMCS1100A4-Q1 400 mV/A Sensitivity error 0.05 V ≤ VOUT ≤ VS – 0.2 V, TA= 25ºC ±0.2% ±0.7% Sensitivity error, including lifetime and environmental drift (5) 0.05 V ≤ VOUT ≤ VS – 0.2 V, TA= 25ºC -0.47% ±1.02% Sensitivity error 0.05 V ≤ VOUT ≤ VS – 0.2 V, TA= –40ºC to +85ºC ±0.4% ±0.85% 0.05 V ≤ VOUT ≤ VS – 0.2 V, TA= –40ºC to Nonlinearity error VOUT = 0.5 V to VS – 0.5 V ±0.05% VOE Output voltage offset error(1) TMCS1100A1-Q1 ±0.4 ±3 mV TMCS1100A2-Q1 ±0.6 ±5 mV TMCS1100A3-Q1 ±0.8 ±8 mV TMCS1100A4-Q1 ±2.2 ±19 mV Output voltage offset drift TMCS1100A1-Q1, TA= –40ºC to +125ºC ±3.7 ±12 µV/℃ TMCS1100A2-Q1, TA= –40ºC to +125ºC ±4 ±19 µV/℃ TMCS1100A3-Q1, TA= –40ºC to +125ºC ±8.2 ±35 µV/℃ TMCS1100A4-Q1, TA= –40ºC to +125ºC ±26 ±138 µV/℃ IOS Offset error, RTI(1) (3) TMCS1100A1-Q1 ±8 ±60 mA TMCS1100A2-Q1 ±6 ±50 mA TMCS1100A3-Q1 ±4 ±40 mA TMCS1100A4-Q1 ±5.5 ±47.5 mA Offset error temperature drift, RTI(3) TMCS1100A1-Q1, TA= –40ºC to +125ºC ±74 ±240 µA/°C TMCS1100A2-Q1, TA= –40ºC to +125ºC ±40 ±190 µA/°C TMCS1100A3-Q1, TA= –40ºC to +125ºC ±41 ±175 µA/°C TMCS1100A4-Q1, TA= –40ºC to +125ºC ±65 ±345 µA/°C PSRR Power-supply rejection ratio TMCS1100A1-Q1-A3-Q1, VS = 3 V to 5.5 V, VREF = VS/2, TA= –40ºC to +125ºC ±1 ±2 mV/V TMCS1100A4-Q1, VS = 4.5 V to 5.5 V, VREF = VS/2, TA= –40ºC to +125ºC ±1 ±3 mV/V CMTI Common mode transient immunity 50 kV/µs CMRR Common mode rejection ratio, RTI(3) DC to 60Hz 5 uA/V RVRR Reference voltage rejection ratio, output referred VREF = 0.5 V to 4.5 V, TMCS1100A1-Q1- A3-Q1 1 3.5 mV/V VREF = 0.5 V to 4.5 V, TMCS1100A4-Q1 1.5 8 mV/V Noise density, RTI(3) TMCS1100A1-Q1 380 μA/√Hz TMCS1100A2-Q1 330 μA/√Hz TMCS1100A3-Q1 300 μA/√Hz TMCS1100A4-Q1 225 μA/√Hz INPUT RIN Input conductor resistance IN+ to IN– 1.8 mΩ Input conductor resistance temperature drift TA= –40ºC to +125ºC 4.4 μΩ/°C www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TMCS1100-Q1

at TA = 25°C, VS = 5 V, VREF = 2.5 V (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT G Magnetic coupling factor TA= 25ºC 1.1 mT/A IIN,max Allowable continuous RMS current (4) TA= 25ºC 30 A TA= 85ºC 25 A TA= 105ºC 22.5 A TA= 125ºC 16 A VREF Reference input voltage VGND VS V VREF input current VREF = GND, VS ±1 ±5 µA VREF external source impedance Maximum source impedance of external circuit driving VREF 5 kΩ VOLTAGE OUTPUT ZOUT Closed loop output impedance f = 1 Hz to 1 kHz 0.2 Ω f = 10 kHz 2 Ω Maximum capacitive load No sustained oscillation 1 nF Short circuit output current VOUT short to ground, short to VS 90 mA Swing to VS power-supply rail RL = 10 kΩ to GND, TA= –40ºC to +125ºC VS – 0.02 VS – 0.1 V Swing to GND, current driven RL = 10 kΩ to GND, TA= –40ºC to +125ºC VGND + 5 VGND + 10 mV Swing to GND, zero current TMCS1100A1-Q1-A3-Q1, RL = 10 kΩ to GND, TA= –40ºC to +125ºC, VREF = GND, IIN = 0 A VGND + 5 VGND + 20 mV TMCS1100A4-Q1, RL = 10 kΩ to GND, TA= –40ºC to +125ºC, VREF = GND, IIN = 0 A VGND + VGND + 55 mV FREQUENCY RESPONSE BW Bandwidth(6) –3-dB Bandwidth 80 kHz SR Slew rate(6) Slew rate of output amplifier during single transient step. 1.5 V/µs tr Response time(6) Time between the input current step reaching 90% of final value to the sensor output reaching 90% of its final value, for a 1V output transition. 6.5 µs tp Propagation delay(6) Time between the input current step reaching 10% of final value to the sensor output reaching 10% of its final value, for a 1V output transition. 4 µs tr,SC Current overload response time(6) Time between the input current step reaching 90% of final value to the sensor output reaching 90% of its final value. Input current step amplitude is twice full scale output range. 5 µs tp,SC Current overload propagation delay(6) Time between the input current step reaching 10% of final value to the sensor output reaching 10% of its final value. Input current step amplitude is twice full scale output range. 3 µs Current overload recovery time Time from end of current causing output saturation condition to valid output 15 µs POWER SUPPLY IQ Quiescent current TA = 25ºC 4.5 5.5 mA TA = –40ºC to +125ºC 6 mA TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

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at TA = 25°C, VS = 5 V, VREF = 2.5 V (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT Power on time Time from VS > 3 V to valid output 25 ms (1) Excludes effect of external magnetic fields. See the Accuracy Parameters section for details to calculate error due to external magnetic fields. (2) Excluding magnetic coupling from layout deviation from recommended layout. See the Layout section for more information. (3) RTI = referred-to-input. Output voltage is divided by device sensitivity to refer signal to input current. See the Parameter Measurement Information section. (4) Thermally limited by junction temperature. Applies when device mounted on TMCS1100EVM . For more details, see the Safe Operating Area section. (5) Lifetime and environmental drift specifications based on three lot AEC-Q100 qualification stress test results. Typical values are population mean+1σ from worst case stress test condition. Min/max are tested device population mean±6σ; devices tested in AEC- Q100 qualification stayed within min/max limits for all stress conditions. See Lifetime and Environmental Stability section for more details. (6) Refer to the Transient Response section for details of frequency and transient response of the device. (7) Centered parameter based on TMCS1100EVM PCB layout. See Layout section. Device must be operated below maximum junction temperature. www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TMCS1100-Q1

7.10 Typical Characteristics

Temperature (°C) Sensitivity Error (%) -50 -25 0 25 50 75 100 125 150 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 Figure 7-1. Sensitivity Error vs. Temperature Temperature (°C) Input Current Offset (mA) -50 -25 0 25 50 75 100 125 150 -80 -60 -40 -20 A4 Figure 7-2. Input Offset Current vs. Temperature Temperature (°C) Non-linearity (%) -50 -25 0 25 50 75 100 125 150 0.05 0.1 0.15 0.2 0.25 Figure 7-3. Non-Linearity vs. Temperature Sensitivity Error (%) Population -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 D023 All sensitivities Figure 7-4. Sensitivity Error Production Distribution IOS (mA) Population -60 -52 -44 -36 -28 -20 -12 D024 TMCS1100A1-Q1 Figure 7-5. Input Offset Current Production Distribution IOS (mA) Population -50 -45 -40 -35 -30 -25 -20 -15 -10 D025 TMCS1100A2-Q1 Figure 7-6. Input Offset Current Production Distribution TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

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Frequency (Hz) Closed-loop Output Impedance (:) 10 100 1k 10k 100k 1M 0.1 100 Figure 7-13. Output Impedance vs. Frequency Temperature (°C) Quiescent Current (mA) -50 -25 0 25 50 75 100 125 150 4.2 4.4 4.6 4.8 5.2 A4 Figure 7-14. Quiescent Current vs. Temperature VREF (V) VOE (mV) -15 -10 Figure 7-15. Output Voltage Offset vs. VREF Frequency (Hz) Referred-to-Input Current Noise (uA/Hz) 150 200 250 300 350 400 10 100 1k 10k 100k A4 Figure 7-16. Input-Referred Noise vs. Frequency Time (4Ps/div) Input Current (A) Output Voltage (V) -15 0.5 0 1 15 1.5 30 2 45 2.5 60 3 75 3.5 90 4 IIN Figure 7-17. Voltage Output Step, Rising Time (4Ps/div) Input Current (A) Output Voltage (V) -15 0.5 0 1 15 1.5 30 2 45 2.5 60 3 75 3.5 90 4 IIN V2 Figure 7-18. Voltage Output Step, Falling TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

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Time (4Ps/div) Input Current (A) Output Voltage (V) -10 -2 0 -1 10 0 20 1 30 2 40 3 50 4 60 5 70 6 IIN VOUT Figure 7-19. Current Overload Response Figure 7-20. Startup Transient Response Temperature (°C) RIN (m:) -50 -25 0 25 50 75 100 125 150 1.4 1.5 1.6 1.7 1.8 1.9 2.1 2.2 2.3 2.4 Figure 7-21. Input Conductor Resistance vs. Temperature

7.10.1 Insulation Characteristics Curves

Ambient Temperature (°C) Safety Limiting Current (A) 0 20 40 60 80 100 120 140 160 Figure 7-22. Thermal Derating Curve for Safety- Limiting Current, Side 1 Ambient Temperature (°C) Safety Limiting Current (A) 0 20 40 60 80 100 120 140 160 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Figure 7-23. Thermal Derating Curve for Safety- Limiting Current, Side 2 www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TMCS1100-Q1

Ambient Temperature (°C) Saftey Limiting Power (W) 0 20 40 60 80 100 120 140 160 0.5 1.5 2.5 3.5 Figure 7-24. Thermal Derating Curve for Safety-Limiting Power TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

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8 Parameter Measurement Information

8.1 Accuracy Parameters

The ideal first-order transfer function of the TMCS1100-Q1 is given by Equation 1, where the output voltage is a linear function of input current. The accuracy of the device is quantified both by the error terms in the transfer function parameters, as well as by nonidealities that introduce additional error terms not in the simplified linear model. See Total Error Calculation Examples for example calculations of total error, including all device error terms. VOUT = S × IIN + VREF (1) where

VOUT is the analog output voltage.
S is the ideal sensitivity of the device.
IIN is the isolated input current.
VREF is the voltage applied to the reference voltage input. where
VOUT is the analog output voltage.
S is the ideal sensitivity of the device.
IIN is the isolated input current.
VOUT,0A is the zero current output voltage for the device variant.

8.1.1 Sensitivity Error

Sensitivity is the proportional change in the sensor output voltage due to a change in the input conductor current. This sensitivity is the slope of the first-order transfer function of the sensor, as shown in Figure 8-1. The sensitivity of the TMCS1100-Q1 is tested and calibrated at the factory for high accuracy. VOUT (V) IIN (A)IFS± S = Slope (V/A) VREF IFS+ best fit linear VREF VOUT, 0 A VOE VNL VREF + VFS+ VREF ± VFS± Figure 8-1. Sensitivity, Offset, and Nonlinearity Error www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TMCS1100-Q1

Deviation from ideal sensitivity is quantified by sensitivity error, defined as the percent variation of the best-fit measured sensitivity from the ideal sensitivity. When specified over a temperature range, this is the worst-case sensitivity error at any temperature within the range. eS = [(Sfit – Sideal) / Sideal] × 100% (2) where

eS is the sensitivity error.
Sfit is the best fit sensitivity.
SIdeal is the ideal sensitivity.

8.1.2 Offset Error and Offset Error Drift

Offset error is the deviation from the ideal output voltage with zero input current through the device. Offset error can be referred to the output as a voltage error V OE or referred to the input as a current offset error I OS. Offset error is a single error source, however, and must only be included once in error calculations. The output voltage offset error of the TMCS1100-Q1 is the error in the zero current output voltage from the VREF pin voltage as in Equation 3. OE OUT,0A REFV V V (3) where

VOUT,0A is the device output voltage with zero input current. The offset error includes the magnetic offset of the Hall sensor and any offset voltage errors of the signal chain. The input referred (RTI) offset error is the output voltage offset error divided by the sensitivity of the device, shown in Equation 4. Refer the offset error to the input of the device to allow for easier total error calculations and direct comparison to input current levels. No matter how the calculations are done, the error sources quantified by VOE and IOS are the same, and should only be included once for error calculations. OS OEI V / S (4) Offset error drift is the change in the input-referred offset error per degree Celsius change in ambient temperature. This parameter is reported in µA/°C. To convert offset drift to an absolute offset for a given change in temperature, multiply the drift by the change in temperature and convert to percentage, as in Equation 5. q OS OS,25 C OS,drift I , T IN AI I T Ce % I (5) where
IOS,drift is the specified input-referred device offset drift.
ΔT is the temperature range from 25°C. TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

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8.1.3 Nonlinearity Error

Nonlinearity is the deviation of the output voltage from a linear relationship to the input current. Nonlinearity voltage, as shown in Figure 8-1 , is the maximum voltage deviation from the best-fit line based on measured parameters, calculated by Equation 6. VNL = VOUT,MEAS – (IMEAS × Sfit + VOUT,0A) (6) where

VOUT,MEAS is the voltage output at maximum deviation from best fit.
IMEAS is the input current at maximum deviation from best fit.
Sfit is the best-fit sensitivity of the device.
VOUT,0A is the device zero current output voltage. Nonlinearity error (e NL) for the TMCS1100-Q1 is the nonlinearity voltage specified as a percentage of the full-scale output range (VFS), as shown in Equation 7. NL NL FS Ve 100% * V (7)

8.1.4 Power Supply Rejection Ratio

Power supply rejection ratio (PSRR) is the change in device offset due to variation of supply voltage from the nominal 5 V. The error contribution at the input current of interest can be calculated by Equation 8. S PSRR IN PSRR * (V 5) Se (%) I (8) where

VS is the operational supply voltage.
S is the device sensitivity.

8.1.5 Common-Mode Rejection Ratio

Common-mode rejection ratio (CMRR) quantifies the effective input current error due to a varying voltage on the isolated input of the device. Due to magnetic coupling and galvanic isolation of the current signal, the TMCS1100-Q1 has very high rejection of input common-mode voltage. Percent error contribution from input common-mode variation can be calculated by Equation 9. CM CMRR IN CMRR * Ve (%) I (9) where

VCM is the maximum operational AC or DC voltage on the input of the device.

8.1.6 Reference Voltage Rejection Ratio

The voltage applied to the VREF pin sets the zero current output voltage for the TMCS1100-Q1. Ideally, the zero current output voltage directly tracks V REF. Light internal mismatch can cause minor errors, however. When the reference voltage deviates from half of the supply, an additional effective output offset error is introduced into the device transfer function. The reference voltage rejection ratio (RVRR) is the effective change in output offset voltage due to this deviation. Error due to reference rejection can be calculated by Equation 10. www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TMCS1100-Q1

S REF V IN VRVRR * (V ) 2 S e (%) I (10)

8.1.7 External Magnetic Field Errors

The TMCS1100-Q1 does not have stray field-rejection capabilities, so external magnetic fields from adjacent high-current traces or nearby magnets can impact the output measurement. The total sensitivity (S) of the device is comprised of the initial transformation of input current to magnetic field quantified as the magnetic coupling factor (G), as well as the sensitivity of the Hall element and the analog circuitry that is factory calibrated to provide a final sensitivity. The output voltage is proportional to the input current by the device sensitivity, as defined in Equation 11. Hall VS G * S * A (11) where

S is the TMCS1100-Q1 sensitivity in mV/A.
G is the magnetic coupling factor in mT/A.
SHall is the sensitivity of the Hall plate in mV/mT.
AV is the calibrated analog circuitry gain in V/V. An external field, BEXT, is measured by the Hall sensor and signal chain, in addition to the field generated by the leadframe current, and is added as an extra input term in the total output voltage function: OUT EXT Hall V IN Hall V OUT,0AV B * S * A I * G * S * A V (12) Observable from Equation 12 is that the impact of an external field is an additional equivalent input current signal, IBEXT, shown in Equation 13. This effective additional input current has no dependence on Hall or analog circuitry sensitivity, so all gain variants have equivalent input-referred current error due to external magnetic fields. EXT EXT B BI G (13) This additional current error generates a percentage error defined by Equation 14. EXT EXT B IN B Ge (%) I (14)

8.2 Transient Response Parameters

The transient response of the TMCS1100-Q1 is impacted by the 250 kHz sampling rate as defined in Transient Response. Figure 8-2 shows the TMCS1100-Q1 response to an input current step sufficient to generate a 1V output change. The typical 4us sampling window can be observed as a periodic step. This sampling window dominates the response of the device, and the response will have some probabilistic nature due to alignment of the input step and the sampling window interval. TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

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Time (4Ps/div) Input Current (A) Output Voltage (V) -15 0.5 0 1 15 1.5 30 2 45 2.5 60 3 75 3.5 90 4 IIN Figure 8-2. Transient Step Response

8.2.1 Slew Rate

Slew rate (SR) is defined as the V OUT rate of change for a single integration step’s output transition, as shown in Figure 8-3. Because the device often requires two sampling windows to reach a full 90% settling of its final value, this slew rate is not equal to the 10%-90% transition time for the full output swing. tr Input Current 10% 90% tp SR VOUT response tr Input Current 10% 90% tp SR VOUT response 1V tr Input Current 10% 90% tp SR VOUT response s Sample Window 4 s Sample Window 4 s Sample Window Figure 8-3. Small Current Input Step Transient Response

8.2.2 Propagation Delay and Response Time

Propagation delay is the time period between the input current waveform reaching 10% of its final value and VOUT reaching 10% of its final value. This propagation delay is heavily dependent upon the alignment of the input current step and the sampling period of the TMCS1100-Q1, as shown for several different sampling window cases in Figure 8-3. Response time is the time period between the input current reaching 90% of its final value and the output reaching 90% of its final value, for an input current step sufficient to cause a 1-V transition on the output. Figure 8-3 shows the response time of the TMCS1100-Q1 under three different time cases. Unless a step input occurs directly during the beginning of one sampling window the response time will include two sampling intervals.

8.2.3 Current Overload Parameters

Current overload response parameters are the transient behavior of the TMCS1100-Q1 to an input current step consistent with a short circuit or fault event. Tested amplitude is twice the full scale range of the device, or 10V / Sensitivity in V/A. Under these conditions, the TMCS1100-Q1 output will respond faster than in the case of a small input current step due to the higher input amplitude signal. Response time and propagation delay are measured in a similar manner to the case of a small input current step, as shown in Figure 8-4. www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TMCS1100-Q1

10% 90% tp SR VOUT response ûIIN =

10 V / S

Figure 8-4. Current Overload Transient Response Current overload recovery time is the required time for the device output to exit a saturated condition and return to normal operation. The transient response of the device during this recovery period from a current overload is shown in Current Overload Response.

8.2.4 CMTI, Common-Mode Transient Immunity

CMTI is the capability of the device to tolerate a rising/falling voltage step on the input without disturbance on the output signal. The device is specified for the maximum common-mode transition rate under which the output signal will not experience a greater than 200-mV disturbance that lasts longer than 1 µs. Higher edge rates than the specified CMTI can be supported with sufficient filtering or blanking time after common-mode transitions. TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

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8.3 Safe Operating Area

The isolated input current safe operating area (SOA) of the TMCS1100-Q1 is constrained by self-heating due to power dissipation in the input conductor. Depending upon the use case, the SOA is constrained by multiple conditions, including exceeding maximum junction temperature, Joule heating in the leadframe, or leadframe fusing under extremely high currents. These mechanisms depend on pulse duration, amplitude, and device thermal states. Current SOA strongly depends on the thermal environment and design of the system-level board. Multiple thermal variables control the transfer of heat from the device to the surrounding environment, including air flow, ambient temperature, and printed-circuit board (PCB) construction and design. All ratings are for a single TMCS1100-Q1 device on the TMCS1100EVM, with no air flow in the specified ambient temperature conditions. Device use profiles must satisfy both continuous conduction and short-duration transient SOA capabilities for the thermal environment under which the system will be operated.

8.3.1 Continuous DC or Sinusoidal AC Current

The longest thermal time constants of device packaging and PCBs are in the order of seconds; therefore, any continuous DC or sinusoidal AC periodic waveform with a frequency higher than 1 Hz can be evaluated based on the RMS continuous-current level. The continuous-current capability has a strong dependence upon the operating ambient temperature range expected in operation. Figure 8-5 shows the maximum continuous current-handling capability of the device on the TMCS1100EVM. Current capability falls off at higher ambient temperatures because of the reduced thermal transfer from junction-to-ambient and increased power dissipation in the leadframe. By improving the thermal design of an application, the SOA can be extended to higher currents at elevated temperatures. Using larger and heavier copper power planes, providing air flow over the board, or adding heat sinking structures to the area of the device can all improve thermal performance. Ambient Temperature (qC) Maximum Continuous RMS Current (A) -55 -35 -15 5 25 45 65 85 105 125 D012 Figure 8-5. Maximum Continuous RMS Current vs. Ambient Temperature www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TMCS1100-Q1

8.3.2 Repetitive Pulsed Current SOA

For applications where current is pulsed between a high current and no current, the allowable capabilities are limited by short-duration heating in the leadframe. The TMCS1100-Q1 can tolerate higher current ranges under some conditions, however, for repetitive pulsed events, the current levels must satisfy both the pulsed current SOA and the RMS continuous current constraint. Pulse duration, duty cycle, and ambient temperate all impact the SOA for repetitive pulsed events. Maximum Repetitive Pulsed Current vs. Pulse Duration , Maximum Repetitive Pulsed Current vs. Pulse Duration , Maximum Repetitive Pulsed Current vs. Pulse Duration , and Maximum Repetitive Pulsed Current vs. Pulse Duration illustrate repetitive stress levels based on test results from the TMCS1100EVM under which parametric performance and isolation integrity was not impacted post- stress for multiple ambient temperatures. At high duty cycles or long pulse durations, this limit approaches the continuous current SOA for a RMS value defined by Equation 15. IN , RMS IN , PI I * D (15) where

IIN,RMS is the RMS input current level
IIN,P is the pulse peak input current
D is the pulse duty cycle Current Pulse Duration (s) Allowable Current (A) 0.001 0.01 0.1 1 10 100 150 200 250 D016 10% 25% 50% 75% TA = 25°C Figure 8-6. Maximum Repetitive Pulsed Current vs. Pulse Duration Current Pulse Duration (s) Allowable Current (A) 0.001 0.01 0.1 1 10 100 120 140 160 D017 10% 25% 50% 75% TA = 85°C Figure 8-7. Maximum Repetitive Pulsed Current vs. Pulse Duration Current Pulse Duration (s) Allowable Current (A) 0.001 0.01 0.1 1 10 100 120 140 D018 10% 25% 50% 75% TA = 105°C Figure 8-8. Maximum Repetitive Pulsed Current vs. Pulse Duration Current Pulse Duration (s) Allowable Current (A) 0.001 0.01 0.1 1 10 100 120 D019 10% 25% 50% 75% TA = 125°C Figure 8-9. Maximum Repetitive Pulsed Current vs. Pulse Duration TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

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8.3.3 Single Event Current Capability

Single higher-current events that are shorter duration can be tolerated by the TMCS1100-Q1, because the junction temperature does not reach thermal equilibrium within the pulse duration. Figure 8-10 shows the short- circuit duration curve for the device for single current-pulse events, where the leadframe resistance changes after stress. This level is reached before a leadframe fusing event, but should be considered an upper limit for short duration SOA. For long-duration pulses, the current capability approaches the continuous RMS limit at the given ambient temperature. Pulse Duration (s) Fuse Current (A) 0.001 0.01 0.1 1 10 100 1000 D004 D004 TA = 25°C TA = 125°C Figure 8-10. Single-Pulse Leadframe Capability www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TMCS1100-Q1

9 Detailed Description

9.1 Overview

The TMCS1100-Q1 is a precision Hall-effect current sensor, featuring a 600-V basic isolation working voltage, < 1% full-scale error across temperature, and an external reference voltage enabling unidirectional or bidirectional current sensing Input current flows through a conductor between the isolated input current pins. The conductor has a 1.8-m Ω resistance at room temperature for low power dissipation and a 20-A RMS continuous current handling capability up to 105°C ambient temperature on the TMCS1100EVM. The low-ohmic leadframe path reduces power dissipation compared to alternative current measurement methodologies, and does not require any external passive components, isolated supplies, or control signals on the high-voltage side. The magnetic field generated by the input current is sensed by a Hall sensor and amplified by a precision signal chain. The device can be used for both AC and DC current measurements and has a bandwidth of 80 kHz. There are multiple fixed-sensitivity device variants for a wide option of linear sensing ranges, and the TMCS1100-Q1 can operate with a low voltage supply from 3 V to 5.5 V. The TMCS1100-Q1 is optimized for high accuracy and temperature stability, with both offset and sensitivity compensated across the entire operating temperature range.

9.2 Functional Block Diagram

IN± Hall Element Bias Temperature Compensation Offset Cancellation VREF VOUTPrecision Amplifier Output Amplifier Isolation Barrier VS GND Reference Sampling

9.3 Feature Description

9.3.1 Current Input

Input current to the TMCS1100-Q1 passes through the isolated side of the package leadframe through the IN+ and IN– pins. The current flow through the package generates a magnetic field that is proportional to the input current, and measured by a galvanically isolated, precision, Hall sensor IC. As a result of the electrostatic shielding on the Hall sensor die, only the magnetic field generated by the input current is measured, thus limiting input voltage switching pass-through to the circuitry. This configuration allows for direct measurement of currents with high-voltage transients without signal distortion on the current-sensor output. The leadframe conductor has a nominal resistance of 1.8 m Ω at 25°C, and has a typical positive temperature coefficient as defined in the Electrical Characteristics table.

9.3.2 Input Isolation

The separation between the input conductor and the Hall sensor die due to the TMCS1100-Q1 construction provides inherent galvanic isolation between package pins 1-4 and pins 5-8. Insulation capability is defined according to certification agency definitions and using industry-standard test methods as defined in the Insulation Specifications table. Assessment of device lifetime working voltages follow the VDE 0884-11 standard for basic insulation, requiring time-dependent dielectric breakdown (TDDB) data-projection failure rates of less than 1000 part per million (ppm), and a minimum insulation lifetime of 20 years. The VDE standard also requires an additional safety margin of 20% for working voltage, and a 30% margin for insulation lifetime, translating into a minimum required lifetime of 26 years at 509 VRMS for the TMCS1100-Q1. TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

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Figure 9-1 shows the intrinsic capability of the isolation barrier to withstand high-voltage stress over the lifetime of the device. Based on the TDDB data, the intrinsic capability of these devices is 424 VRMS with a lifetime of > 100 years. Other factors such as operating environment and pollution degree can further limit the working voltage of the component in an end system. Figure 9-1. Insulation Lifetime

9.3.3 High-Precision Signal Chain

The TMCS1100-Q1 uses a precision, low-drift signal chain with proprietary sensor linearization techniques to provide a highly accurate and stable current measurement across the full temperature range of the device. The device is fully tested and calibrated at the factory to account for any variations in either silicon or packaging process variations. The full signal chain provides a fixed sensitivity voltage output that is proportional to the current through the leadframe of the isolated input.

9.3.3.1 Temperature Stability

The TMCS1100-Q1 includes a proprietary temperature compensation technique which results in significantly improved parametric drift across the full temperature range. This compensation technique accounts for changes in ambient temperature, self-heating, and package stress. A zero-drift signal chain architecture and Hall sensor temperature stabilization methods enable stable sensitivity and minimize offset errors across temperature, and drastically improves system-level performance across the required operating conditions. Figure 9-2 shows the offset error across the full device ambient temperature range. Figure 9-3 shows the typical sensitivity. There are no other external components introducing errors sources; therefore, the high intrinsic accuracy and stability over temperature directly translates to system-level performance. As a result of this high precision, even a system with no calibration can reach < 1% of total error current-sensing capability. Temperature (°C) Input Current Offset (mA) -50 -25 0 25 50 75 100 125 150 -80 -60 -40 -20 Figure 9-2. Offset Error Drift Across Temperature Temperature (°C) Sensitivity Error (%) -50 -25 0 25 50 75 100 125 150 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 A4 Figure 9-3. Sensitivity Drift Across Temperature www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TMCS1100-Q1

9.3.3.2 Lifetime and Environmental Stability

The same compensation techniques used in the TMCS1100-Q1 to reduce temperature drift also greatly reduce lifetime drift due to aging, stress, and environmental conditions. Typical magnetic sensors suffer from up to 2% to 3% of sensitivity drift due to aging at high operating temperatures. The TMCS1100-Q1 has greatly improved lifetime drift, as defined in the Electrical Characteristics for total sensitivity error measured after the worst case stress test during a three lot AEC-Q100 qualification. All other stress tests prescribed by an AEC-Q100 qualification caused lower than the specified sensitivity error, and were within the bounds specified within the Electrical Characteristics table. Figure 9-4 shows the total sensitivity error after the worst-case stress test, a Highly Accelerated Stress Test (HAST) at 130°C and 85% relative humidity (RH), while Figure 9-5 and Figure 9-6 show the sensitivity and offset error drift after a 1000 hour, 125°C high temperature operating life stress test as specified by AEC-Q100. This test mimics typical device lifetime operation, and shows the likely device performance variation due to aging is vastly improved compared to typical magnetic sensors. Sensitivity Drift (%) Unit Count 100 120 140 160 D020 Figure 9-4. Sensitivity Error After 130°C, 85% RH HAST Sensitivity Drift (%) Unit Count 100 120 140 160 180 200 D021 Figure 9-5. Sensitivity Error Drift After AEC-Q100 High Temperature Operating Life Stress Test IOS Drift (mA) Unit Count 100 120 -50 -40 -30 -20 -10 0 10 20 30 40 50 D022 Figure 9-6. Input-Referred Offset Drift After AEC-Q100 High Temperature Operating Life Stress Test

9.3.3.3 Frequency Response

The TMCS1100-Q1 signal chain has a spectral response atypical of a linear analog system due to its discrete time sampling. The 250-kHz sampling interval implies an effective Nyquist frequency of 125 kHz, which limits spectral response to below this frequency. Higher frequency content than this frequency will be aliased down to lower spectrums. The TMCS1100-Q1 bandwidth is defined by the –3-dB spectral response of the entire signal chain which is constrained by the sampling frequency. Normalized gain and phase plots across frequency are shown below in Figure 9-7 and Figure 9-8, all variants have the same bandwidth and phase response. Signal content beyond the 3-dB bandwidth level will still have significant fundamental frequency transmission through the signal chain, but at increasing distortion levels TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

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Frequency (Hz) Gain (dB) 10 100 1k 10k 100k 1M All gains 80kHz -3dB Figure 9-7. Normalized Gain, All Variants Frequency (Hz) Phase (°) -180 -150 -120 -90 -60 -30 10 100 1k 10k 100k Figure 9-8. Normalized Phase, All Variants

9.3.3.4 Transient Response

The TMCS1100-Q1 signal chain includes a precision analog front end followed by a sampled integrator. At the end of each integration cycle, the signal propagates to the output. Depending on the alignment of a change in input current relative to the sampling window, the output might not settle to the final signal until the second integration cycle. Figure 9-9 shows a typical output waveform response to a 10-kHz sine wave input current. For a slowly varying input current signal, the output is a discrete time representation with a phase delay of the integration sampling window. Adding a first order filter of 100 kHz effectively smooths the output waveform with minimal impact to phase response. Time (s) Output Voltage (V) Input Current (A) 0 -5 0.5 -4 1 -3 1.5 -2 2 -1 2.5 0 3 1 3.5 2 4 3 4.5 4 5 5 5.5 6 D015 VOUT Input Current VOUT, 100 kHz Filter Figure 9-9. Response Behavior to 10-kHz Sine Wave Input Current Figure 9-10 shows two transient waveforms to an input-current step event, but occurring at different times during the sampling interval. In both cases, the full transition of the output takes two sampling intervals to reach the final output value. The timing of the current event relative to the sampling window determines the proportional amplitude of the first and second sampling intervals. www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TMCS1100-Q1

Time (4Ps/div) Input Current (A) Output Voltage (V) -15 0.5 0 1 15 1.5 30 2 45 2.5 60 3 75 3.5 90 4 IIN Figure 9-10. Transient Response to Input-Current Step Sufficient for 1-V Output Swing The output value is effectively an average over the sampling window; therefore, a large-enough current transient can drive the output voltage to near the full scale range in the first sample response. This condition is likely to be true in the case of a short-circuit or fault event. Figure 9-11 shows an input-current step twice the full scale measurable range with two output voltage responses illustrating the effect of the sampling window. The relative timing and size of the input current transition determines both the time and amplitude of the first output transition. In either case, the total response time is slightly longer than one integration period. Time (4Ps/div) Input Current (A) Output Voltage (V) -10 -2 0 -1 10 0 20 1 30 2 40 3 50 4 60 5 70 6 IIN Figure 9-11. Transient Response to a Large Input Current Step

9.3.4 External Reference Voltage Input

The reference voltage provided externally to the TMCS1100-Q1 on the VREF pin determines the zero current output voltage, V OUT,0A. This zero-current output level along with sensitivity determine the measurable input current range of the device, and allows for unidirectional or bidirectional sensing, as described in the Absolute Maximum Ratings table. Figure 9-12 illustrates the transfer function of the TMCS1100A2 -Q1 with varying V REF voltages of 0 V, 1.25 V, and 2.5 V. By shifting the zero current output voltage of the device, the dynamic range of measurable input current can be modified. TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

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Input Current (A) Output Voltage (V) -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 0.5 1.5 2.5 3.5 4.5 D002 VREF = 0 V VREF = 1.25 V VREF = 2.5 V Figure 9-12. Output Voltage Relationship to Input Current With Varying VREF Voltages The input voltage on this pin can be provided by any external voltage source or potential, such as a discrete precision reference, a voltage divider, ADC reference, or ground. The VREF pin is sampled by the internal circuitry at approximately 1 MHz, then buffered and provided to the signal chain of the device. An apparent DC load of approximately 1 µA will be observed by the external reference. To prevent errors due to sampling settling, keep the source impedance below the level specified in the Electrical Characteristics table.

9.3.5 Current-Sensing Measurable Ranges

The TMCS1100-Q1 can be configured to allow for bidirectional or unidirectional measurable current ranges based on the external voltage on the VREF pin. The output voltage is limited by V OUT swing to either supply or ground. Linear output swing range to both VS and GND is calculated by equations Equation 16 and Equation 17. VOUT,max = VS – SwingVS (16) VOUT,min = SwingGND (17) Rearranging the transfer function of the device to solve for input current, and substituting V OUT,max and VOUT,min yields the maximum and minimum measurable input current ranges as shown in Equation 18 and Equation 19. IIN,MAX+ = (VOUT,max – VREF) / S (18) IIN,MAX- = (VREF – VOUT,min) / S (19) where

IIN,MAX+ is the maximum linear measurable positive input current.
IIN,MAX- is the maximum linear measurable negative input current.
S is the sensitivity of the device variant. Setting V REF to the middle of the output swing range provides bidirectional measurement capability, whereas setting V REF close to the ground provides a unidirectional measurement. Custom ranges with nonuniform positive and negative input current ranges can be achieved by appropriately scaling the V REF potential relative to the full output voltage range.

9.4 Device Functional Modes

9.4.1 Power-Down Behavior

As a result of the inherent galvanic isolation of the device, very little consideration must be paid to powering down the device, as long as the limits in the Absolute Maximum Ratings table are not exceeded on any pins. The isolated current input and the low-voltage signal chain can be decoupled in operational behavior, as either can be energized with the other shut down, as long as the isolation barrier capabilities are not exceeded. The low-voltage power supply can be powered down while the isolated input is still connected to an active high-voltage signal or system. www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TMCS1100-Q1

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

10.1 Application Information

The key feature sets of the TMCS1100-Q1 provide significant advantages in any application where an isolated current measurement is required.

Galvanic isolation provides a high isolated working voltage and excellent immunity to input voltage transients.
Hall based measurement simplifies system level solution without the need for a power supply on the high voltage (HV) side.
An input current path through the low impedance conductor minimizes power dissipation.
Excellent accuracy and low temperature drift eliminate the need for multipoint calibrations without sacrificing system performance.
An external reference input maximizes flexibility for unidirectional or bidirectional measurement with custom dynamic ranges, and improves accuracy at the system level.
A wide operating supply range enables a single device to function across a wide range of voltage levels. These advantages increase system-level performance while minimizing complexity for any application where precision current measurements must be made on isolated currents. Specific examples and design requirements are detailed in the following section.

10.1.1 Total Error Calculation Examples

Total error can be calculated for any arbitrary device condition and current level. Error sources considered should include input-referred offset current, power-supply rejection, input common-mode rejection, sensitivity error, nonlinearity, VREF to VOUT gain error, and the error caused by any external fields. Compare each of these error sources in percentage terms, as some are significant drivers of error and some have inconsequential impact to current error. Offset ( Equation 20 ), CMRR ( Equation 22 ), PSRR ( Equation 21 ), VREF gain error (Equation 23), and external field error (Equation 24) are all referred to the input, and so, are divided by the actual input current I IN to calculate percentage errors. For calculations of sensitivity error and nonlinearity error, the percentage limits explicitly specified in the Electrical Characteristics table can be used. OS OS I IN Ie (%) I (20) S PSRR IN PSRR * (V 5) Se (%) I (21) CM CMRR IN CMRR * Ve (%) I (22) REF S REF V IN VRVRR * (V ) 2 S e (%) I (23) TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

Product Folder Links: TMCS1100-Q1

B IN B Ge (%) I (24) When calculating error contributions across temperature, only the input offset current and sensitivity error contributions vary significantly. For determining offset error over a given temperature range ( ΔT), use Equation 25 to calculate total offset error current. Sensitivity error is specified for both –40°C to 85°C and –40°C to 125°C. The appropriate specification should be used based on application operating ambient temperature range. q OS OS,25 C OS,drift I , T IN AI I T Ce % I (25) To accurately calculate the total expected error of the device, the contributions from each of the individual components above must be understood in reference to operating conditions. To account for the individual error sources that are statistically uncorrelated, a root sum square (RSS) error calculation should be used to calculate total error. For the TMCS1100-Q1, only the input referred offset current (I OS), CMRR, and PSRR are statistically correlated. These error terms are lumped in an RSS calculation to reflect this nature, as shown in Equation 26 for room temperature and Equation 27 for across a given temperature range. The same methodology can be applied for calculating typical total error by using the appropriate error term specification. OS REF EXT 2 2 2 2 2 RSS I PSRR CMRR V B S NLe (%) e e e e e e e (26) OS, T REF EXT 2 2 2 2 2 RSS, T I PSRR CMRR V B S, T NLe (%) e e e e e e e '' ' (27) The total error calculation has a strong dependence on the actual input current; therefore, always calculate total error across the dynamic range that is required. These curves asymptotically approach the sensitivity and nonlinearity error at high current levels, and approach infinity at low current levels due to offset error terms with input current in the denominator. Key figures of merit for any current-measurement system include the total error percentage at full-scale current, as well as the dynamic range of input current over which the error remains below some key level. Figure 10-1 illustrates the RSS maximum total error as a function of input current for a TMCS1100A2 at room temperature and across the full temperature range with VS of 5 V. Input Current (A) RSS Max Total Error (%) 0 5 10 15 20 25 D007 RSS Max Error, 25°C Figure 10-1. RSS Error vs. Input Current

10.1.1.1 Room Temperature Error Calculations

For room-temperature total-error calculations, specifications across temperature and drift are ignored. As an example, consider a TMCS1100-Q1 A1 with a supply voltage (V S) of 3.3 V , a V REF of 1.5 V, and a worst-case www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TMCS1100-Q1

common-mode excursion of 600 V to calculate operating-point-specific parameters. Consider a measurement error due to an external magnetic field of 30 µT, roughly the Earth's magnetic field strength. The full-scale current range of the device in specified conditions is slightly greater than 28 A; therefore, calculate error at both 25 A and 12.5 A to highlight error dependence on the input-current level. Table 10-1 shows the individual error components and RSS maximum total error calculations at room temperature under the conditions specified. Relative to other errors, the additional error from CMRR is negligible, and can typically be ignored for total error calculations. Table 10-1. Total Error Calculation: Room Temperature Example ERROR COMPONENT SYMBOL EQUATION % MAX TOTAL ERROR AT IIN = 25 A % MAX TOTAL ERROR AT IIN = 12.5 A Input offset error eIos OS OS I IN PSRR error ePSRR S PSRR IN PSRR * (V 5) CMRR error eCMRR CM CMRR IN CMRR * Ve (%) I 0.01% 0.02% VREF error eVREF REF S REF V IN VRVRR * (V ) 2 S External Field error eBext EXT EXT B IN B Sensitivity error eS Specified in Electrical Characteristics 0.7% 0.7% Nonlinearity error eNL Specified in Electrical Characteristics 0.05% 0.05% RSS total error eRSS OS REF EXT 2 2 2 2 2 RSS I PSRR CMRR V B S NLe (%) e e e e e e e 0.88% 1.28%

10.1.1.2 Full Temperature Range Error Calculations

To calculate total error across any specific temperature range, Equation 26 and Equation 27 should be used for RSS maximum total errors, similar to the example for room temperatures. Conditions from the example in Room Temperature Error Calculations have been replaced with their respective equations and error components for a –40°C to 85°C temperature range below in Table 10-2. Table 10-2. Total Error Calculation: –40°C to 85°C Example ERROR COMPONENT SYMBOL EQUATION % MAX TOTAL ERROR AT IIN = 25 A % MAX TOTAL ERROR AT IIN = 12.5 A Input offset error eIos,ΔT q OS OS,25 C OS,drift I , T IN AI I T Ce % I 0.28% 0.56% PSRR error ePSRR S PSRR IN PSRR * (V 5) TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

Product Folder Links: TMCS1100-Q1

Table 10-2. Total Error Calculation: –40°C to 85°C Example (continued) ERROR COMPONENT SYMBOL EQUATION % MAX TOTAL ERROR AT IIN = 25 A % MAX TOTAL ERROR AT IIN = 12.5 A CMRR error eCMRR CM CMRR IN CMRR * Ve (%) I 0.01% 0.02% VREF error eVREF REF S REF V IN VRVRR * (V ) 2 S External Field error eBext EXT EXT B IN B Sensitivity error eS,ΔT Specified in Electrical Characteristics 0.85% 0.85% Nonlinearity error eNL Specified in Electrical Characteristics 0.05% 0.05% RSS total error eRSS,ΔT OS, T REF EXT 2 2 2 2 2 RSS, T I PSRR CMRR V B S, T NLe (%) e e e e e e e '' ' 1.03% 1.43% www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TMCS1100-Q1

10.2 Typical Application

Inline sensing of inductive load currents, such as motor phases, provides significant benefits to the performance of a control systems, allowing advanced control algorithms and diagnostics with minimal postprocessing. A primary challenge to inline sensing is that the current sensor is subjected to full HV supply-level PWM transients driving the load. The inherent isolation of an in-package Hall-effect current sensor topology helps overcome this challenge, providing high common-mode immunity, as well as isolation between the high-voltage motor drive levels and the low-voltage control circuitry. Figure 10-2 illustrates the use of the TMCS1100-Q1 in such an application, driving the inductive load presented by a three phase motor. TMCS1100-Q1 IN+ IN– VREF VOUT VS GND 5 V 2.5 V TMCS1100-Q1 TMCS1100-Q1 Figure 10-2. Inline Motor Phase Current Sensing

10.2.1 Design Requirements

For current sensing of a three-phase motor application, make sure to provide linear sensing across the expected current range, and make sure that the device remains within working thermal constraints. A single TMCS1100- Q1 for each phase can be used, or two phases can be measured, and the third phase calculated on the motor- controller host processor. For this example, consider a nominal supply of 5 V but a minimum of 4.9 V to include for some supply variation. Maximum output swings are defined according to TMCS1100-Q1 specifications, and a full-scale current measurement of ±20 A is required. Table 10-3. Example Application Design Requirements DESIGN PARAMETER EXAMPLE VALUE VS,nom 5 V VS,min 4.9 V IIN,FS ±20 A TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

Product Folder Links: TMCS1100-Q1

10.2.2 Detailed Design Procedure

The TMCS1100-Q1 application design procedure has two key design parameters: the sensitivity version chosen (A1-A4) and the reference voltage input. Further consideration of noise and integration with an ADC can be explored, but is beyond the scope of this application design example. The TMCS1100-Q1 transfer function is effectively a transimpedance with a variable offset set by VREF, defined by Equation 28. u OUT IN REFV I S V (28) Design of the sensing solution first focuses on maximizing the sensitivity of the device while maintaining linear measurement over the expected current input range. The linear output voltage range is constrained by the TMCS1100-Q1 linear swing to ground, Swing GND, and swing to supply, Swing VS. With the previous parameters, the maximum linear output voltage range is the range between VOUT,max and VOUT,min, as defined by Equation 29 and Equation 30. SOUT,max S,min VV V Swing (29) OUT,min GNDV Swing (30) For a bidirectional current-sensing application, a sufficient linear output voltage range is required from V REF to both ground and the power supply. Design parameters for this example application are shown in Table 10-4 along with the calculated output range. Table 10-4. Example Application Design Parameters DESIGN PARAMETER EXAMPLE VALUE SwingVS 0.2 V SwingGND 0.05 V VOUT,max 4.7 V VOUT,min 0.05 V VOUT,max - VOUT,min 4.65 V These design parameters result in a maximum linear output voltage swing of 4.65 V. To determine which sensitivity variant of the TMCS1100-Q1 most fully uses this linear range, calculate the maximum current range by Equation 31 for a unidirectional current (IU,MAX), and Equation 32 for a bidirectional current (IB,MAX). OUT,max OUT,min U , MAX A x V V I S ! (31) OUT,max OUT,min B, MAX A x V V I 2 S ! u (32) where

SA<x> is the sensitivity of the relevant A1-A4 variant. Table 10-5 shows such calculation for each gain variant of the TMCS1100-Q1 with the appropriate sensitivities. Table 10-5. Maximum Full-Scale Current Ranges With 4.65-V Output Range SENSITIVITY VARIANT SENSITIVITY IU,MAX IB,MAX TMCS1100A1-Q1 50 mV/A 93 A ±46.5 A TMCS1100A2-Q1 100 mV/A 46.5 A ±23.2A TMCS1100A3-Q1 200 mV/A 23.2 A ±11.6A TMCS1100A4-Q1 400 mV/A 11.6 A ±5.8 A www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TMCS1100-Q1

In general, select the highest sensitivity variant that provides for the desired full-scale current range. For the design parameters in this example, the TMCS1100A2 -Q1 with a sensitivity of 0.1 V/A is the proper selection because the maximum-calculated ±23.2 A linear measurable range is sufficient for the desired ±20-A full-scale current. After selecting the appropriate sensitivity variant for the application, the zero-current reference voltage defined by the V REF input pin is defined. Manipulating Equation 28 and using the linear range defined by V OUT,max, VOUT,min, and the full-scale input current, I IN,FS, calculate the maximum and minimum V REF voltages allowed to remain within the linear measurement range, shown in Equation 33 and Equation 34. uREF,max OUT,max IN , FSV V I S (33) uREF,min OUT,min IN ,FSV V I S (34) Any value of V REF can be chosen between V REF,max and VREF,min to maintain the required linear sensing range. If the allowable V REF range is not wide enough or does not include a desired V REF voltage, the analysis must be repeated with a lower sensitivity variant of the TMCS1100-Q1. Equation 28 can be manipulated to solve for the maximum allowable current in either direction by using the selected V REF voltage and the maximum linear voltage ranges as in Equation 35 and Equation 36. OUT,max REF MAX V V I S (35) OUT,min REF MAX V V I S (36) Table 10-6 shows the respective values for the example design parameters in Table 10-4. In this case, a V REF of 2.5 V has been selected such that the zero current output is half of the nominal power supply. This example VREF design value provides a linear input current-sensing range of –24.5 A to +22 A, with the positive current defined as current flowing into the IN+ pin. Table 10-6. Example VREF Limits and Associated Current Ranges REFERENCE PARAMETER EXAMPLE VALUE MAXIMUM LINEAR CURRENT SENSING RANGE IMAX+ IMAX– VREF,min 2.05 V 26.5 A –20 A VREF,max 2.7 V 20 A –26.5 A Selected VREF 2.5 V 22 A –24.5 A TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

Product Folder Links: TMCS1100-Q1

After selecting a V REF for the application design, an appropriate source must be defined. Multiple implementations are possible, but could include:

Resistor divider from the supply voltage
Resistor divider from an ADC full-scale reference
Dedicated or preexisting voltage reference IC
DAC or reference voltage from a system microcontroller Each of these options has benefits, and the error terms, noise, simplicity, and cost of each implementation must be weighed. In the current design example, any of these options are potentially available as a 2.5-V V REF is midrail of the power supply, a common IC reference voltage, and might already be available in the system. If the primary consideration for the current application design is to maximize precision while minimizing temperature drift and noise, a dedicated voltage reference must be chosen. For this case, the LM4030C-2.5 can be chosen for to optimize system accuracy without significant cost addition. Figure 10-3 depicts the current-sense system design as discussed. TMCS1100-Q1 IN+ IN– VREF VOUT VS GND 5 V To ADC / MCU LM4030C-2.5 2.5 V 0.15%, 30 ppm/ C IIN 0.1 μF Figure 10-3. TMCS1100-Q1 Example Current-Sense System Design

11 Power Supply Recommendations

The TMCS1100-Q1 only requires a power supply (VS) on the low-voltage isolated side, which powers the analog circuitry independent of the isolated current input. V S determines the full-scale output range of the analog output VOUT, and can be supplied with any voltage between 3 V and 5.5 V. To filter noise in the power-supply path, place a low-ESR decoupling capacitor of 0.1 µF between V S and GND pins as close as possible to the supply and ground pins of the device. To compensate for noisy or high-impedance power supplies, add more decoupling capacitance. The TMCS1100-Q1 power supply V S can be sequenced independently of current flowing through the input. However, there is a typical 25-ms delay between V S reaching the recommended operating voltage and the analog output being valid. Within this delay V OUT transfers from a high impedance state to the active drive state, during which time the output voltage could transition between GND and V S. If this behavior must be avoided, a stable supply voltage to VS should be provided for longer than 25 ms prior to applying input current. www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TMCS1100-Q1

12 Layout

12.1 Layout Guidelines

The TMCS1100-Q1 is specified for a continuous current handling capability on the TMCS1100EVM, which uses 3-oz copper pour planes. This current capability is fundamentally limited by the maximum device junction temperature and the thermal environment, primarily the PCB layout and design. To maximize current-handling capability and thermal stability of the device, take care with PCB layout and construction to optimize the thermal capability. Efforts to improve the thermal performance beyond the design and construction of the TMCS1100EVM can result in increased continuous-current capability due to higher heat transfer to the ambient environment. Keys to improving thermal performance of the PCB include:

Use large copper planes for both input current path and isolated power planes and signals.
Use heavier copper PCB construction.
Place thermal via farms around the isolated current input.
Provide airflow across the surface of the PCB. The TMCS1100-Q1 senses external magnetic fields, so make sure to minimize adjacent high-current traces in close proximity to the device. The input current trace can contribute additional magnetic field to the sensor if the input current traces are routed parallel to the vertical axis of the package. Figure 12-1 illustrates the most optimal input current routing into the TMCS1100-Q1. As the angle that the current approaches the device deviates from 0° to the horizontal axis, the current trace contributes some additional magnetic field to the sensor, increasing the effective sensitivity of the device. If current must be routed parallel to the package vertical axis, move the routing away from the package to minimize the impact to the sensitivity of the device. Terminate the input current path directly underneath the package lead footprint, and use a merged copper input trace for both the IN+ and IN– inputs. IIN,} IIN,0 1IN+ 8 VS 2IN+ 7 VOUT 3IN± 6 VREF 4IN± 5 GND IIN,} IIN,0 Figure 12-1. Magnetic Field Generated by Input Current Trace In addition to thermal and magnetic optimization, make sure to consider the PCB design required creepage and clearance for system-level isolation requirements. Maintain required creepage between solder stencils, as shown in Figure 12-2, if possible. If not possible to maintain required PCB creepage between the two isolated sides at board level, add additional slots or grooves to the board. If more creepage and clearance is required for system isolation levels than is provided by the package, the entire device and solder mask can be encapsulated with an overmold compound to meet system-level requirements. TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

Product Folder Links: TMCS1100-Q1

IN± VS GND Solder Mask Creepage Cu Plane Cu Plane Figure 12-2. Layout for System Creepage Requirements

12.2 Layout Example

An example layout, shown in Figure 12-3 , is from the TMCS1100EVM. Device performance is targeted for thermal and magnetic characteristics of this layout, which provides optimal current flow from the terminal connectors to the device input pins while large copper planes enhance thermal performance. Figure 12-3. Recommended Board Top (Left) and Bottom (Right) Plane Layout www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TMCS1100-Q1

13 Device and Documentation Support

13.1 Device Support

13.1.1 Development Support

For development tool support see the following:

TMCS1100EVM
TMCS1100 TI-TINA Model
TMCS1100 TINA-TI Reference Design

13.2 Documentation Support

13.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, TMCS1100EVM User's Guide
Texas Instruments, Enabling Precision Current Sensing Designs with Nonratiometric Magnetic Current Sensors
Texas Instruments, Low-Drift, Precision, In-Line Isolated Magnetic Motor Current Measurements
Texas Instruments, Isolation Glossary

13.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

13.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

13.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

13.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

Product Folder Links: TMCS1100-Q1

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] .041 [1.04] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) SOIC - 1.75 mm max heightD0008B SMALL OUTLINE INTEGRATED CIRCUIT 4221445/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold ﬂash, protrusions, or gate burrs. Mold ﬂash, protrusions, or gate burrs shall not exceed .006 [0.15], per side. 4. This dimension does not include interlead ﬂash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A TYPICAL DETAIL A SCALE 2.800 www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TMCS1100-Q1

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] (.217) [5.5] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] 8X (.055) [1.4] 8X (.024) [0.6] 6X (.050 ) [1.27] (R.002 ) [0.05] TYP SOIC - 1.75 mm max heightD0008B SMALL OUTLINE INTEGRATED CIRCUIT 4221445/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSDE METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE:6X SYMM 4 5 SEE DETAILS IPC-7351 NOMINAL .150 [3.85] CLEARANCE / CREEPAGE SYMM HV / ISOLATION OPTION .162 [4.1] CLEARANCE / CREEPAGE SYMM 4 5 SEE DETAILS SYMM TMCS1100-Q1 SBOSA43 – JUNE 2021 www.ti.com

Product Folder Links: TMCS1100-Q1

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] 8X (.055) [1.4] 8X (.024) [0.6] 6X (.050 ) [1.27] (.217) [5.5] (R.002 ) [0.05] TYP SOIC - 1.75 mm max heightD0008B SMALL OUTLINE INTEGRATED CIRCUIT 4221445/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have diﬀerent recommendations for stencil design. HV / ISOLATION OPTION .162 [4.1] CLEARANCE / CREEPAGE BASED ON .005 INCH [0.127 MM] THICK STENCIL SOLDER PASTE EXAMPLE SCALE:6X SYMM SYMM 4 5 IPC-7351 NOMINAL .150 [3.85] CLEARANCE / CREEPAGE SYMM SYMM 4 5 www.ti.com TMCS1100-Q1 SBOSA43 – JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: TMCS1100-Q1

www.ti.com 26-Jun-2021 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TMCS1100A1QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 Q100A1 TMCS1100A2QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 Q100A2 TMCS1100A3QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 Q100A3 TMCS1100A4QDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 Q100A4 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 26-Jun-2021 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMCS1100-Q1 :

Catalog : TMCS1100 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 27-Jun-2021 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMCS1100A1QDRQ1 SOIC D 8 2500 350.0 350.0 43.0 TMCS1100A2QDRQ1 SOIC D 8 2500 350.0 350.0 43.0 TMCS1100A3QDRQ1 SOIC D 8 2500 350.0 350.0 43.0 TMCS1100A4QDRQ1 SOIC D 8 2500 350.0 350.0 43.0 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jun-2021 Pack Materials-Page 2

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Product Information

TMCS1100A4QDRQ1 specifications and overview.

Summary

TMCS1100-Q1 AEC-Q100, 1% High-Precision, Basic Isolation Hall-Effect Current Sensor With 짹600-V Working Voltage

Description

TMCS1100-Q1 AEC-Q100, 1% High-Precision, Basic Isolation Hall-Effect Current Sensor With 짹600-V Working Voltage

Source title TMCS1100A4QDRQ1 Datasheet(PDF) - Texas Instruments

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