TMC93LC46

TMC93LC46 ETC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 15

Technical content

1K/2K/2K/4K/16K-Bit Microwire Serial EEPROM

FEATURES

I High speed operation: – 93LC46/56/57/66 : 1MHz – 93LC86 : 3MHz I Low power CMOS technology I 1.8 to 6.0 volt operation I Selectable x8 or x16 memory organization I Self-timed write cycle with auto-clear I Hardware and software write protection I Power-up inadvertant write protection I 1,000,000 Program/erase cycles I 100 year data retention I Commercial, industrial and automotive temperature ranges I Sequential read (except TMC 93LC46) I Program enable (PE) pin (TMC 93LC86 only) 93LC46/56/57/66/86 F02 PIN CONFIGURATION CMOS EEPROM floating gate technology. The devices are designed to endure 1,000,000 program/erase cycles and have a data retention of 100 years. The devices are available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP packages.

DESCRIPTION

The 93LC46/56/57/66/86 are 1K/2K/2K/4K/16K-bit Serial EEPROM memory devices which are configured as either registers of 16 bits (ORG pin at V C C ) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The 93LC46/56/ 57/66/86 are manufactured using TMC ’s advanced PIN FUNCTIONS Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC +1.8 to 6.0V Power Supply GND Ground ORG Memory Organization NC No Connection PE* Program Enable BLOCK DIAGRAM Note: When the ORG pin is connected to VCC, the x16 organiza- tion is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization. © 2002 by TMC VCC ORG GND DI CS SK DO NC (PE*) VCC ADDRESS DECODER MEMORY ARRAY ORGANIZATION DATA REGISTER MODE DECODE LOGIC CLOCK GENERATOR OUTPUT BUFFER DOSK CS DI ORG GND PE* Doc. No. 1023, Rev. G CS SK DI DO VCC NC (PE*) ORG GND CS SK DI DO VCC ORG GND VCC CS SK ORG GND DO DI CS SK DI DO VCC ORG GND NC (PE*) NC (PE*) NC (PE*)

Doc. No. 1023, Rev. G D.C. OPERATING CHARACTERISTICS V CC = +1.8V to +6.0V, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Units ICC1 Power Supply Current f SK = 1MHz 3 mA (Operating Write) V CC = 5.0V ICC2 Power Supply Current f SK = 1MHz 500 µA (Operating Read) V CC = 5.0V ISB1 Power Supply Current CS = 0V 10 µA (Standby) (x8 Mode) ORG=GND ISB2 (5) Power Supply Current CS=0V 0 µA (Standby) (x16Mode) ORG=Float or V CC ILI Input Leakage Current V IN = 0V to VCC 1 µA ILO Output Leakage Current V OUT = 0V to VCC ,1 µA (Including ORG pin) CS = 0V VIL1 Input Low Voltage 4.5V ≤ VCC < 5.5V -0.1 0.8 V VIH1 Input High Voltage 4.5V ≤ VCC < 5.5V 2 V CC + 1 V VIL2 Input Low Voltage 1.8V ≤ VCC < 4.5V 0 V CC x 0.2 V VIH2 Input High Voltage 4.8V ≤ VCC < 4.5V V CC x 0.7 V CC +1 V VOL1 Output Low Voltage 4.5V ≤ VCC < 5.5V 0.4 V IOL = 2.1mA VOH1 Output High Voltage 4.5V ≤ VCC < 5.5V 2.4 V IOH = -400µA VOL2 Output Low Voltage 1.8V ≤ VCC < 4.5V 0.2 V IOL = 1mA VOH2 Output High Voltage 1.8V ≤ VCC < 4.5V V CC - 0.2 V IOH = -100µA ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with Package Power Dissipation *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min Typ Max Units N END (3) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte TDR (3) Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP (3) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts ILTH (3)(4) Latch-Up JEDEC Standard 17 100 mA Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is V CC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V. (5) Standby Current (ISB2)=0µA (<900nA) for 93LC46/56/57/66, (ISB2)=2µA for 93LC86.

Doc. No. 1023, Rev. G PIN CAPACITANCE Symbol Test Conditions Min Typ Max Units C OUT (3) Output Capacitance (DO) V OUT =0V 5 pF C IN(3) Input Capacitance (CS, SK, DI, ORG) V IN=0V 5 pF Note: (1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE and ERASE commands. (2) Applicable only to 93LC86 (3) This parameter is tested initially and after a design or process change that affects the parameter. INSTRUCTION SET Instruction Device Start Opcode Address Data Comments PE (2) Type Bit x8 x16 x8 x16 READ 93LC46 1 10 A6-A0 A5-A0 Read Address AN–A0 93LC56(1) 1 10 A8-A0 A7-A0 93LC66 1 10 A8-A0 A7-A0 93LC57 1 10 A7-A0 A6-A0 93LC86 1 10 A10-A0 A9-A0 X ERASE 93LC46 1 11 A6-A0 A5-A0 Clear Address AN–A0 93LC56(1) 1 11 A8-A0 A7-A0 93LC66 1 11 A8-A0 A7-A0 93LC57 1 11 A7-A0 A6-A0 93LC86 1 11 A10-A0 A9-A0 I WRITE 93LC46 1 01 A6-A0 A5-A0 D7-D0 D15-D0 Write Address AN–A0 93LC56(1) 1 01 A8-A0 A7-A0 D7-D0 D15-D0 93LC66 1 01 A8-A0 A7-A0 D7-D0 D15-D0 93LC57 1 01 A7-A0 A6-A0 D7-D0 D15-D0 93LC86 1 01 A10-A0 A9-A0 D7-D0 D15-D0 I EWEN 93LC46 1 00 11XXXXX 11XXXX Write Enable 93LC56 1 00 11XXXXXXX 11XXXXXX 93LC66 1 00 11XXXXXXX 11XXXXXX 93LC57 1 00 11XXXXXX 11XXXXX 93LC86 1 00 11XXXXXXXXX 11XXXXXXXX X EWDS 93LC46 1 00 00XXXXX 00XXXX Write Disable 93LC56 1 00 00XXXXXXX 00XXXXXX 93LC66 1 00 00XXXXXXX 00XXXXXX 93LC57 1 00 00XXXXXX 00XXXXX 93LC86 1 00 00XXXXXXXXX 00XXXXXXXX X ERAL 93LC46 1 00 10XXXXX 10XXXX Clear All Addresses 93LC56 1 00 10XXXXXXX 10XXXXXX 93LC66 1 00 10XXXXXXX 10XXXXXX 93LC57 1 00 10XXXXXX 10XXXXX 93LC86 1 00 10XXXXXXXXX 10XXXXXXXX I WRAL 93LC46 1 00 01XXXXX 01XXXX D7-D0 D15-D0 Write All Addresses 93LC56 1 00 01XXXXXXX 01XXXXXX D7-D0 D15-D0 93LC66 1 00 01XXXXXXX 01XXXXXX D7-D0 D15-D0 93LC57 1 00 01XXXXXX 01XXXXX D7-D0 D15-D0 93LC86 1 00 01XXXXXXXXX 01XXXXXXXX D7-D0 D15-D0 I

Doc. No. 1023, Rev. G Limits VCC =V CC =V CC = Test 1.8V-6V 2.5V-6V 4.5V-5.5V SYMBOL PARAMETER Conditions Min Max Min Max Min Max Units tCSS CS Setup Time 200 100 50 ns tCSH CS Hold Time 0 0 0 ns tDIS DI Setup Time 200 100 50 ns tDIH DI Hold Time 200 100 50 ns tPD1 Output Delay to 1 1 0.5 0.15 µs tPD0 Output Delay to 0 1 0.5 0.15 µs tHZ (1) Output Delay to High-Z 400 200 100 ns tEW Program/Erase Pulse Width 5 5 5 ms tCSMIN Minimum CS Low Time 1 0.5 0.15 µs tSKHI Minimum SK High Time 1 0.5 0.15 µs tSKLOW Minimum SK Low Time 1 0.5 0.15 µs tSV Output Delay to Status Valid 1 0.5 0.1 µs SK MAX Maximum Clock Frequency DC 500 DC 1000 DC 3000 kHz A.C. CHARACTERISTICS (93 LC46/56/57/66) Limits VCC =V CC =V CC = Test SYMBOL PARAMETER Conditions Min Max Min Max Min Max Units tCSS CS Setup Time 200 100 50 ns tCSH CS Hold Time 0 0 0 ns tDIS DI Setup Time 400 200 100 ns tDIH DI Hold Time 400 200 100 ns tPD1 Output Delay to 1 1 0.5 0.25 µs tPD0 Output Delay to 0 1 0.5 0.25 µs tHZ (1) Output Delay to High-Z 400 200 100 ns tEW Program/Erase Pulse Width 10 10 10 ms tCSMIN Minimum CS Low Time 1 0.5 0.25 µs tSKHI Minimum SK High Time 1 0.5 0.25 µs tSKLOW Minimum SK Low Time 1 0.5 0.25 µs tSV Output Delay to Status Valid 1 0.5 0.25 µs SK MAX Maximum Clock Frequency DC 250 DC 500 DC 1000 kHz A.C. CHARACTERISTICS (93 LC86) NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. C L = 100pF (3) C L = 100pF (3)

Doc. No. 1023, Rev. G A.C. TEST CONDITIONS Input Rise and Fall Times≤ 50ns Input Pulse Voltages 0.4V to 2.4V 4.5V ≤ VCC ≤ 5.5V Timing Reference Voltages 0.8V, 2.0V 4.5V ≤ VCC ≤ 5.5V Input Pulse Voltages 0.2V CC to 0.7VCC 1.8V ≤ VCC ≤ 4.5V Timing Reference Voltages 0.5VCC 1.8V ≤ VCC ≤ 4.5V POWER-UP TIMING (1)(2) SYMBOL PARAMETER Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (3) The input levels and timing reference points are shown in “AC Test Conditions” table.

regardless of the write enable/disable status. contents of all memory bits return to a logical “1” state. cleared before the WRAL command is executed. Figure 4. Erase Instruction Timing

Plastic DIP Outline Dimensions 8-pin DIP (300mil) Outline Dimensions Symbol Dimensions in mil Min. Nom. Max. A 355 /c190 375 B 240 /c190 260 C 125 /c190 135 D 125 /c190 145 E1 6 /c190 20 F5 0 /c190 70 G /c190 100 /c190 H 295 /c190 315 I 335 /c190 375 /c97 0/c176/c190 15/c176

Package Information

/G20 /G20 /G61 /G38 /G35 /G34 /G31 /G41 /G42 /G43 /G44 /G45 /G46._ /G47 /G48 /G49

8-pin SOP (150mil) Outline Dimensions Symbol Dimensions in mil Min. Nom. Max. A 228 /c190 244 B 149 /c190 157 C1 4 /c190 20 C/c162 189 /c190 197 D5 3 /c190 69 E /c190 50 /c190 F4 /c190 10 G2 2 /c190 28 H4 /c190 12 /c97 0/c176/c190 10/c176 /G44 /G46._ /G43 /G27 /G47 /G48 /G61 /G45 /G38 /G31 /G41 /G42 /G43 /G34 /G35

Symbol Description Dimensions in mm W Carrier Tape Width 12.0+0.3 /c450.1 P Cavity Pitch 8.0/c1770.1 E Perforation Position 1.75/c1770.1 F Cavity to Perforation (Width Direction) 5.5/c1770.1 D Perforation Diameter 1.55/c1770.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4.0/c1770.1 P1 Cavity to Perforation (Length Direction) 2.0/c1770.1 A0 Cavity Length 6.4/c1770.1 B0 Cavity Width 5.20/c1770.1 K0 Cavity Depth 2.1/c1770.1 t Carrier Tape Thickness 0.3/c1770.05 C Cover Tape Width 9.3 /G50 /G44 /G31 /G57 /G50 /G31 /G50 /G30 /G44 /G45 /G46._ /G74 /G4B /G30 /G42 /G30 /G41 /G30 /G43