TMC3533 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

  • 8-bit resolution
  • 80, 50, and 30 megapixels per second
  • ±0.5 LSB linearity error
  • Sync, blank, and white controls
  • Independent sync current output
  • 1.0V p-p video into 37.5W or 75W load
  • Enhancement of the ADV7120 – Internal bandgap voltage reference – Double-buffered data for low distortion – Power-down sleep mode
  • Double-buffered data for low distortion
  • TTL-compatible inputs
  • Low glitch energy
  • Single +3.3V±5% V olt power supply

Applications

  • Video and graphics displays
  • Image processing systems
  • Video signal conversion
  • Broadcast television equipment
  • Digital synthesis

Description

The TMC3533 is a high-speed triple 8-bit D/A converter especially suited for video and graphics applications. It offers 8-bit resolution, TTL-compatible inputs, low power consumption, a power-down sleep mode, and requires only a single +3.3V±5% V olt power supply. It has single-ended current outputs, SYNC and BLANK control inputs, and a separate current source for adding sync pulses to any D/A converter output. WHITE and SLEEP control inputs are available on PLCC parts. It is ideal for generating analog RGB from digital RGB and driving computer display and video monitors. Three speed grades are available: 30, 50, and 80 Msps. The TMC3533 triple D/A converter is available in a 44-lead plastic J-leaded PLCC. It is also available in a 48-lead plastic LQFP package. It is fabricated on a sub-micron CMOS pro- cess with performance guaranteed from 0°C to 70°C. Block Diagram 8 bit D/A Converter SYNC SYNC CLOCK SLEEP [PLCC only] IOS G 7-0 COMP 65-3533-01 +1.235V Ref IOG BLANK 8 bit D/A Converter 8B7-0 IOB 8 bit D/A Converter 8R 7-0 IOR R REF VREF WHITE [PLCC only] [LQFP only] TMC3533 Triple Video D/A Converter 8 bit, 80 Msps, 3.3V

source allows sync to be added to any D/A converter output. source which is brought off the chip through the IOS pin. Figure 1. Nominal Output Levels tered on the rising edge of CLK. BLANK gates the D/A inputs and sets the pedestal voltage. inputs and the pedestal are disabled. power-down state. This function operates asynchronously. converter with a net resistive load of 37.5 Ohms. as close as possible to the power pins. to the outputs of any D/A converter a potential problem.

Table 1. Output Voltage versus Input Code, SYNC, BLANK , and WHITE

  1. Pin functions White and Sleep are not available.

S function is internally tied to IOG pin.

TMC3533 PRODUCT SPECIFICATION 4 REV. 0.9.1 11/24/99 Pin Descriptions Pin Name Pin Number Value Pin Function DescriptionLQFP PLCC Clock and Pixel I/O CLK 26 27 TTL Clock Input. The clock input is TTL-compatible and all pixel data is registered on the rising edge of CLK. It is recommended that CLK be driven by a dedicated TTL buffer to avoid reflection induced jitter, overshoot, and undershoot. R 7-0 G 7-0 B7-0 47-40 9-2 23-16 6-1, 44-43 14-7 25-18 TTL Red, Green, and Blue Pixel Inputs. The R, G, and B digital inputs are TTL-compatible and registered on the rising edge of CLK. Controls SYNC 11 16 TTL Sync Pulse Input. Bringing SYNC LOW, turns off a 40 IRE (7.62 mA) current source which forms a sync pulse on any D/A converter output connected to IO S. SYNC is registered on the rising edge of CLK along with pixel data and has the same pipeline latency as BLANK and pixel data. SYNC does not override any other data and should be used only during the blanking interval. If the system does not require sync pulses, SYNC and IOS should be connected to GND. BLANK 10 15 TTL Blanking Input. When BLANK is LOW, pixel inputs are ignored and the D/A converter outputs are driven to the blanking level. BLANK is registered on the rising edge of CLK and has the same two-pipe latency as SYNC and Data. WHITE — 26 TTL Force Full Scale Input. When WHITE is HIGH, pixel inputs are ignored and the D/A converter outputs are driven to their full- scale output level. A BLANK input overwrites a WHITE input. WHITE is register on the rising edge of CLK and has the same two-pipe latency as SYNC and Data. SLEEP — 28 TTL Power-down Control Input. When HIGH, SLEEP places the D/ A converter in a low-power-dissipation mode. The D/A current sources and the digital processing are disabled. The last data loaded into the input and D/A registers is retained. This control is asynchronous. Video Outputs IO R IOG IOB 0.714 V p-p Red, Green, and Blue Data Outputs. The current source outputs of the D/A converters are capable of driving RS-343A/ SMPTE-170M compatible levels into doubly-terminated 75 Ohm lines. Sync pulses may be added to any D/A output. IO S 32 (connected to IOG ) 37 0.714 V p-p SYNC Current Output. When this pin is connected to any of the D/A converter outputs, a 40 IRE offset can be added to the video level. When the SYNC input is LOW, the current is turned off, bring the sync tip voltage to 0.0V. If no sync pulse is required, IO S should be grounded. When SYNC is HIGH, the current flowing out of IOS is: IOS = 3.64 (VREF / RREF ) Voltage Reference V REF 35 41 +1.235 V Voltage Reference Input/Output. An internal voltage source of +1.235 Volts is output on this pin. An external +1.235 Volt reference may be applied here which overrides the internal reference. Decoupling V REF to GND with a 0.1µF ceramic capacitor is required.

Figure 2. Equivalent Digital Input Circuit Figure 3. Equivalent Analog Output Circuit

Figure 4. Equivalent Analog Input Circuit

  1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if

Operating Conditions are not exceeded.

  1. Applied voltage must be current limited to specified range.
  2. Forcing voltage must be limited to specified range.
  3. Current is specified as conventional current flowing into the device.

PRODUCT SPECIFICATION TMC3533 REV. 0.9.1 11/24/99 7 Operating Conditions

Electrical Characteristics

Notes: 1. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C 2. Minimum/Maximum values with VDD = Max and TA = Min 3. VREF = 1.235V, RLOAD = 37.5W , RREF = 572W Parameter Min Nom Max Units VDD Power Supply Voltage 3.135 3.3 3.465 V fS Conversion Rate TMC3533-30 30 Msps TMC3533-50 50 Msps TMC3533-80 80 Msps t PWH CLK Pulsewidth, HIGH 4 ns tPWL CLK Pulsewidth, LOW 4 ns ts Input Data Setup Time 3 ns th Input Date Hold Time 2 ns VREF Reference Voltage, External 1.0 1.235 1.5 V C C Compensation Capacitor 0.1 µF R L Output Load 37.5 W VIH Input Voltage, Logic HIGH 2.0 V DD V VIL Input Voltage, Logic LOW GND 0.8 V TA Ambient Temperature, Still Air 0 70 °C Parameter Conditions 3 Min Typ 1 Max Units IDD Power Supply Current2 VDD = Max TMC3533-30 TMC3533-50 TMC3533-80 105 mA mA mA I DDS Power Supply Current, Sleep Mode VDD = Max 3 mA PD Total Power Dissipation 2 VDD = Max TMC3533-30 TMC3533-50 TMC3533-80 330 330 346 mW mW mW R O Output Resistance 100 k W C O Output Capacitance I OUT = 0mA 30 pF IIH Input Current, HIGH V DD = Max, VIN = 3.0V -1 µA IIL Input Current, LOW V DD = Max, VIN = 0.4V 1 µA IREF VREF Input Bias Current 0 ±100 µA VREF Reference Voltage Output 1.235 V VOC Output Compliance Referred to V DD -0.4 0 +1.5 V C DI Digital Input Capacitance 4 10 pF

TMC3533 PRODUCT SPECIFICATION 8 REV. 0.9.1 11/24/99 Switching Characteristics Notes: 1. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C. 2. VREF = 1.235V, RLOAD = 37.5W , RREF = 572W . System Performance Characteristics Notes: 1. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C. 2. VREF = 1.235V, RLOAD = 37.5W , RREF = 572W . Timing Diagram Parameter Conditions 2 Min Typ 1 Max Units tD Clock to Output Delay V DD = Min 10 15 ns tSKEW Output Skew 1 2 ns tR Output Risetime 10% to 90% of Full Scale 3 4 ns tF Output Falltime 90% to 10% of Full Scale 3 4 ns tSET Output Settling Time to 3%/FS 15 ns Parameter Conditions 2 Min Typ 1 Max Units ELI Integral Linearity Error VDD , VREF = Nom ±0.1 ±0.25 %/FS ELD Differential Linearity Error VDD , VREF = Nom ±0.1 ±0.25 %/FS EDM DAC to DAC Matching V DD , VREF = Nom 7 10 % IOFF Output Off Current V DD = Max, R, G, B = 000h SYNC = BLANK = 0 20 nA PSRR Power Supply Rejection Ratio 0.05 %/% CLK PIXEL DATA & CONTROLS OUTPUT 65-3503-04 DataN DataN+1 DataN+2 tPWL tS tH 50% 3%/FS 90% 10% tD tSET tF tR tPWH 1/fS

TMC3533 PRODUCT SPECIFICATION 10 REV. 0.9.1 11/24/99 Mechanical Dimensions – 44-pin PLCC Package D e E A .165 .180 4.19 4.57 Symbol Inches Min. Max. Min. Max. Millimeters Notes E1 J A A2 B D3/E3 J – C – ccc C LEAD COPLANARITY A1 .090 .120 2.29 3.05 A2 .020 .51 —— B .013 .021 .33 .53 D/E .685 .695 17.40 17.65 D1/E1 .650 .656 16.51 16.66 D3/E3 .500 BSC 12.7 BSC e .050 BSC 1.27 BSC J .042 .056 1.07 1.42 2 ND/NE 11 11 N4 4 4 4 ccc .004 0.10—— B1 .026 .032 .66 .81 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982 Corner and edge chamfer (J) = 45° Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)

PRODUCT SPECIFICATION TMC3533 REV. 0.9.1 11/24/99 11 Mechanical Dimensions – 48-pin LQFP Package D E1E e PIN 1 IDENTIFIER B Base Plane Seating Plane See Lead Detail C 0.063" Ref (1.60mm) L -C- ccc C LEAD COPLANARITY A2A α A .055 .063 1.40 1.60 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .001 .005 .05 .15 .057 1.45A2 .053 1.35 B .006 .010 .17 .27 D/E D1/E1 .019 BSC .346 .362 8.8 9.2 .268 .284 6.8 7.2 .50 BSCe L .017 .029 .45 .75 6 α 0° 7° 0° 7° N4 8 4 8 12 12ND ccc .004 0.08 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982. Dimensions "D1" and "E1" do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. Pin 1 identifier is optional. Dimension ND: Number of terminals. Dimension ND: Number of terminals per package edge. "L" is the length of terminal for soldering to a substrate. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum B dimension by more than 0.08mm. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. To be determined at seating place —C—

TMC3533 PRODUCT SPECIFICATION 11/24/99 0.0m 002 Stock#DS30003533 Ó 1999 Fairchild Semiconductor Corporation DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

Ordering Information

Rate (Msps) Temperature Range Screening Package Package Marking TMC3533R2C30 30 Msps T A = 0˚C to 70˚C Commercial 44-Lead PLCC 3533LR2C30 TMC3533R2C50 50 Msps T A = 0˚C to 70˚C Commercial 44-Lead PLCC 3533LR2C50 TMC3533R2C80 80 Msps T A = 0˚C to 70˚C Commercial 44-Lead PLCC 3533LR2C80 TMC3533KRC30 30 Msps T A = 0˚C to 70˚C Commercial 48-Lead LQFP 3533LKRC30 TMC3533KRC50 50 Msps T A = 0˚C to 70˚C Commercial 48-Lead LQFP 3533LKRC50 TMC3533KRC80 80 Msps T A = 0˚C to 70˚C Commercial 48-Lead LQFP 3533LKRC80