TMC3033 CADEKA | Alldatasheet

Document overview

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Technical content

Features

  • 10-bit resolution
  • 80, 50, and 30 megapixels per second
  • Sync and blank controls
  • Sync on green D/A output
  • 1.0V p-p video into 37.5 W or 75 W load
  • Enhancement of AD V7122 – Internal bandgap voltage reference – Double-buffered data for low distortion
  • TTL-compatible inputs
  • Low glitch energy
  • Single +3.3 Volt 5% power supply

Applications

  • V ideo signal conversion – RGB – YC B C R – Composite, Y, C
  • Multimedia systems
  • Image processing
  • True-color graphics systems (1 billion colors)
  • Broadcast television equipment
  • High-Definition Television (HDTV) equipment
  • Direct digital synthesis

Description

The TMC3033 is a high-speed triple 10-bit D/A converter especially suited for video and graphics applications. It offers 10-bit resolution, TTL-compatible inputs, low power consumption, and requires only a single +3.3 Volt 5% power supply. It has single-ended current outputs, SYNC and BLANK control inputs, and a separate current source for adding sync pulses to the Green D/A converter output. It is ideal for generating analog RGB from digital RGB and driving computer display and video monitors. Three speed grades are available: 30, 50, and 80 Msps. The TMC3033 triple D/A converter is available in a 44-lead plastic J-leaded PLCC and 48-lead plastic LQFP package. It is fabricated on a sub-micron CMOS process with perfor- mance guaranteed from 0 C to 70 Block Diagram 10 bit D/A Converter 10 bit D/A Converter 10 bit D/A Converter 10G 9-0 BLANK SYNC CLK IOG IOB IOR VREF R REF COMP 65-3003-01 +1.235V Ref 10B9-0 10R 9-0 TMC3033 Triple Video D/A Converter 10 bit, 80 Msps Rev. 1.0.0 www .cadeka.com

and video transmission lines at pixel rates of up to 80 Msps. added to the green D/A converter output. brings that D/A output to 0.0 Volts during the sync tip. BLANK gates the D/A inputs and sets the pedestal voltage. inputs and the pedestal are disabled. Figure 1. Nominal Output Levels converter with a net resistive load of 37.5 Ohms. as close as possible to the power pins. to the outputs of any D/A converter a potential problem.

Table 1. Output Voltage versus Input Code, SYNC , and BLANK

TMC3033 PRODUCT SPECIFICATION Pin Descriptions Pin Name Pin Number Value DescriptionPLCC LQFP Clock and Pixel I/O CLK 29 26 TTL Clock. The clock input is TTL-compatible and all pixel data is registered on the rising edge of CLK. It is recommended that CLK be driven by a dedicated TTL buffer to avoid reflection induced jitter, overshoot, and undershoot. R 9-0 5, 4, 3, 2, 1, 44, 43, 42, 41, 40 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37 TTL Red pixel data inputs. The Red digital input is TTL- compatible and registered on the rising edge of CLK. G 9-0 15, 14, 13, 12, 11, 10, 9, 8, 7, 6 48, 9, 8, 7, 6, 5, 4, 3, 2, 1 TTL Green pixel data inputs. The Green digital input is TTL- compatible and registered on the rising edge of CLK. B 9-0 28, 27, 26, 25, 24, 23, 22, 21, 20, 23, 22, 21, 20, 19, 18, 17, 16, 15, TTL Blue pixel data inputs. The Blue digital input is TTL- compatible and registered on the rising edge of CLK. Controls SYNC 17 11 TTL Sync pulse Input. Bringing SYNC LOW, turns off a 40 IRE (7.62 mA) current source which forms a sync pulse on the Green D/A converter output. SYNC is registered on the rising edge of CLK along with pixel data and has the same pipeline latency as BLANK and pixel data. SYNC does not override any other data and should be used only during the blanking interval. Since this is a single-supply D/A and all signals are positive-going, sync is added to the bottom of the Green D/A range. So turning SYNC OFF means turning the current source ON. When a sync pulse is desired, the current source is turned OFF. If the system does not require sync pulses from the Green D/A converter, SYNC should be connected to GND. BLANK 16 10 TTL Blanking Input. When BLANK is LOW, pixel inputs are ignored and the D/A converter outputs are driven to the blanking level. BLANK is registered on the rising edge of CLK and has the same pipeline latency as SYNC . Video Outputs IO R 36 33 0.714 Vp-p Red D/A output. The current source outputs of the D/A converters are capable of driving RS-343A/SMPTE-170M compatible levels into doubly-terminated 75 Ohm lines. IO G 35 32 1 V p-p Green D/A output. The current source outputs of the D/A converters are capable of driving RS-343A/SMPTE-170M compatible levels into doubly-terminated 75 Ohm lines. Sync pulses may be added to the Green D/A output. IO B 32 29 0.714 Vp-p Blue D/A output. The current source outputs of the D/A converters are capable of driving RS-343A/SMPTE-170M compatible levels into doubly-terminated 75 Ohm lines.

Figure 2. Equivalent Digital Input Circuit Figure 3. Equivalent Analog Output Circuit Voltage Reference output/input. F ceramic capacitor is required. blank to full-scale voltage.

Figure 4. Equivalent Analog Input Circuit

  1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if

Operating Conditions are not exceeded.

  1. Applied voltage must be current limited to specified range.
  2. Forcing voltage must be limited to specified range.
  3. Current is specified as conventional current flowing into the device.

PRODUCT SPECIFICATION TMC3033 Operating Conditions

Electrical Characteristics

Notes: 1. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C. 2. Minimum/Maximum values with VDD = Max and TA = Min. 3. VREF = 1.235V, RLOAD = 37.5W , RREF = 572W Parameter Min Nom Max Units VDD Power Supply Voltage 3.135 3.3 3.465 V fS Conversion Rate TMC3033-30 30 Msps TMC3033-50 50 Msps TMC3033-80 80 Msps tPWH CLK Pulsewidth, HIGH 5.2 ns tPWL CLK Pulsewidth, LOW 5.2 ns ts Input Data Setup Time 3.6 ns th Input Date Hold Time 2 ns VREF Reference Voltage, External 1.0 1.235 1.5 V C C Compensation Capacitor 0.1 mF R L Output Load 37.5 W VIH Input Voltage, Logic HIGH 2.0 VDD V VIL Input Voltage, Logic LOW GND 0.8 V TA Ambient Temperature, Still Air 0 70 °C Parameter Conditions3 Min Typ1 Max Units IDD Power Supply Current2 VDD = Max TMC3033-30 90 mA TMC3033-50 95 TMC3033-80 132 PD Total Power Dissipation2 VDD = Max TMC3033-30 300 mW TMC3033-50 315 TMC3033-80 435 R O Output Resistance 100 kW C O Output Capacitance IOUT = 0mA 30 pF IIH Input Current, HIGH VDD = Max, VIN = 2.4V -1 mA IIL Input Current, LOW VDD = Max, VIN = 0.4V 1 mA IREF VREF Input Bias Current 0 –100 mA VREF Reference Voltage Output 1.235 V VOC Output Compliance Referred to VDD -0.4 0 +1.5 V C DI Digital Input Capacitance 4 10 pF

TMC3033 PRODUCT SPECIFICATION Switching Characteristics Notes: 1. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C. 2. VREF = 1.235V, RLOAD = 37.5W , RREF = 572W . System Performance Characteristics Notes: 1. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C. 2. VREF = 1.235V, RLOAD = 37.5W , RREF = 572W . Timing Diagram Parameter Conditions2 Min Typ1 Max Units tD Clock to Output Delay VDD = Min 10 15 ns tSKEW Output Skew 1 2 ns tR Output Risetime 10% to 90% of Full Scale 3 4 ns tF Output Falltime 90% to 10% of Full Scale 3 4 ns tSET Output Settling Time to 3%/FS 15 ns Parameter Conditions2 Min Typ1 Max Units ELI Integral Linearity ErrorVDD , VREF = Nom –0.1 –0.25 %/FS ELD Differential Linearity ErrorVDD , VREF = Nom –0.1 –0.25 %/FS EDM DAC to DAC Matching VDD , VREF = Nom 7 10 % VOF Output Offset Current VDD = Max, R, G, B = 000h 20 mA PSR Power Supply Rejection 0.05 %/% CLK PIXEL DATA & CONTROLS OUTPUT 65-3003-03 DataN DataN+1 DataN+2 tPWL tS tH 50% 3%/FS 90% 10% tD tSET tF tR tPWH 1/fS

TMC3033 PRODUCT SPECIFICATION Mec hanical Dimensions – 44-Lead PLCC Package D e E A .165 .180 4.19 4.57 Symbol Inches Min. Max. Min. Max. Millimeters Notes E1 J A A2 B D3/E3 J – C – ccc C LEAD COPLANARITY A1 .090 .120 2.29 3.05 A2 .020 .51— — B .013 .021 .33 .53 D/E .685 .695 17.40 17.65 D1/E1 .650 .656 16.51 16.66 D3/E3 .500 BSC 12.7 BSC e .050 BSC 1.27 BSC J .042 .056 1.07 1.42 2 ND/NE 11 11 N 44 44 ccc .004 0.10— — B1 .026 .032 .66 .81 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982 Corner and edge chamfer (J) = 45° Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)

PRODUCT SPECIFICATION TMC3033 Mec hanical Dimensions – 48-Lead LQFP Package D E1E e PIN 1 IDENTIFIER B Base Plane Seating Plane See Lead Detail C 0.063" Ref (1.60mm) L -C- ccc C LEAD COPLANARITY A2A α A .055 .063 1.40 1.60 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .001 .005 .05 .15 .057 1.45A2 .053 1.35 B .006 .010 .17 .27 D/E D1/E1 .019 BSC .346 .362 8.8 9.2 .268 .284 6.8 7.2 .50 BSCe L .017 .029 .45 .75 6 α 0° 7° 0° 7° N 48 48 12 12ND ccc .004 0.08 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982. Dimensions "D1" and "E1" do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. Pin 1 identifier is optional. Dimension ND: Number of terminals. Dimension ND: Number of terminals per package edge. "L" is the length of terminal for soldering to a substrate. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum B dimension by more than 0.08mm. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. To be determined at seating place —C—

TMC3033 PRODUCT SPECIFICATION 3/3/99 0.0m 001 Stock#DS30003033

Ordering Information

Rate (Msps) Temperature Rang e Screening Package Package Marking TMC3033R2C30 30 Msps TA = 0°C to 70°C Commercial 44-Lead PLCC 3033R2C30 TMC3033R2C50 50 Msps TA = 0°C to 70°C Commercial 44-Lead PLCC 3033R2C50 TMC3033R2C80 80 Msps TA = 0°C to 70°C Commercial 44-Lead PLCC 3033R2C80 TMC3033KRC30 30 Msps TA = 0°C to 70°C Commercial 48-Lead LQFP 3033KRC30 TMC3033KRC50 50 Msps TA = 0°C to 70°C Commercial 48-Lead LQFP 3033KRC50 TMC3033KRC80 80 Msps TA = 0°C to 70°C Commercial 48-Lead LQFP 3033KRC80