TMC2242C FAIRCHILD | Alldatasheet
Document overview
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Technical content
Features
- Pin-compatible upgrade of TMC2242B
- User-selectable interpolate d.c. gain, 0 dB or -6 dB
- True unity d.c. gain in all “0 db” modes
- 40 MSPS performance in equal-rate filter modes
- 40 and 60 MSPS speed grades in all other modes
- User-selectable 2:1 decimation, 1:2 interpolation, and equal-rate filter modes, plus unfiltered bypass/delay mode
- Defeatable p x/sin( p x) compensation filter
- Passband ripple <0.014 dB
- Stopband rejection >56 dB
- Dedicated 12-bit two’s complement or unsigned input bus
- 16-bit two’s complement or unsigned output bus with user-selectable rounding to 8 to 16 effective bits
- Programmable limiter prevents overflow or clips to CCIR601 levels
- New double-latency modes match Y channel data flow to slower-sampled C B and C R data flows
- New dual-channel interpolation and decimation for YUV422
Applications
- Digital-to-Analog Converter Prefiltering with optional x/sinx correction
- 1:2 interpolation
- Analog-to-Digital Converter Postfiltering
- 2:1 decimation
- Low-ripple low-pass (0 to 0.2 f s ) filter
Description
The TMC2242C, a linear-phase low-pass half-band digital filter with fixed coefficients, can be used to halve or double the sampling rate of a digital signal. When used as a decimat- ing post-filter with a double-speed oversampling A/D con- verter, it greatly reduces the cost and complexity of the required analog antialiasing pre-filters. When used as an interpolating pre-filter with a double-speed oversampling D/A converter, it greatly reduces the complexity and cost of the necessary analog post-filter, particularly when its x/sin(x) correction filter is engaged. The TMC2242C user selects the mode of operation (deci- mate, interpolate, equal-rate, bypass, x/sin(x))and rounding. The part can accept 12-bit two’s complement or unsigned data at up to 60 MHz and can output saturated two’s comple- ment or offset binary data rounded to from 8 to 16 bits. Within the speed grade I/O limit, the output sample rate may be 1/2, 1, or 2 times the input sample rate. Two-channel modes permit it to interpolate or to decimate two multi- plexed data streams (such as video C B and C R ) jointly. The filter response is flat to within 0.014 dB up to 0.21f s (e.g. 5.75MHz at a 27MHz clock rate), with stopband attenu- ation greater than 56dB above 0.29f s . Symmetric-coefficient filters such as the TMC2242C always have linear phase response. Half-band response is -6 dB. Fabricated on an advanced submicron CMOS process, the TMC2242C is available in a 44-lead PLCC package. Perfor- mance is guaranteed from 0 to 70 C and over a power supply range of 4.75 to 5.25V . Block Diagram SI11-0 TCO RND OEDEC INT SYNC SO 15-0 SO 3-0 ROUND LIMIT X/SIN(X) FILTER FIR FILT ZERO INSERT DECIMATE CONTROL 65-2242C-01 TMC2242C Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz Rev. 1.0.0
clock cycles, inserting zeroes on the remaining clock cycles. mode, it must remain low after the first incoming data value. must remain low after the first incoming data value. Table 1. Operating Modes
- These modes limit to 15 bits (SO
- These modes, which double the chip’s overall group delay
- These modes accommodate multiplexed two-channel da-
Table 2. Package Interconnections connection to a data bus with other drivers.
44 Lead PLCC 44 Lead MQFP
PRODUCT SPECIFICATION TMC2242C Pin Descriptions Pin Name Pin Number Pin Function DescriptionPLCC MQFP Dedicated Timing Controls CLK 42 36 Clock . The chip operates from a single-phase master clock, to whose rising edges all timing parameters are referenced. All internal registers are strobed on every rising edge of CLK, although the output register is strobed on alternate rising edges during decimation. In all modes, the frequency applied to CLK is the higher of the input and output data sampling rates. During interpolation, the chip reads its input bus on alternate rising edges of CLK. SYNC 43 37 Synchronization . During interpolation, the chip accepts input data on alternate rising edges of CLK and inserts zeroes on the remaining cycles. If SYNC is HIGH during CLK rising edge 0 and LOW during CLK rising edge 1, the chip will accept data on CLK 1 and insert a zero on CLK 2. Thereafter, if SYNC is either held LOW or fed a square wave of half the CLK frequency, the part will continue to accept data on odd-numbered CLK edges and to stuff zeroes on even- numbered edges. Similarly, during decimation, the output data change only on alternate clock cycles. If the user operates SYNC as above, each even- numbered rising edge of CLK will trigger a change in the output. In all other modes, the state of SYNC doesn’t affect operation of the chip. Dedicated Data Input Port SI 11-0 40, 37-30, 27-25 34, 31-24, 21-19 Input Data . A 12-bit two’s complement or unsigned input word is registered by the rising edges of CLK. SI is the LSB. Dedicated Data Output Port SO 15-0 4-11, 14-21 42-44, 1-5, 8-15 Output Data MSBs . When OE is LOW, the 12 most significant bits of the filter’s output emerge here, following each rising edge of CLK. The format may be two’s complement, unsigned, or inverted offset binary. Bits SO 15-4 correspond to input bits SI 11-0 , respectively. An on-chip limiter prevents overflows and underflows in the output data. Dual Function Data Output/Control Input Pins SO 3-2 Output Data . These pins serve as data outputs when RND is LOW. When RND is HIGH, they become additional filter mode controls (Table 1). SO Output Data 2 nd LSB. This pin is a data output when RND 2-1 are LOW. When either RND or RND is HIGH, it becomes an additional rounding control. SO Output Data LSB . This pin is a data output if and only if all RND bits are LOW. Otherwise, it augments the data I/O format controls. Dedicated Static Controls (Set state before first desired data input.) INT, DEC 44, 1 38, 39 Interpolate and Decimate. Jointly with SO 3-2 , these bits select the chip’s overall operating mode, as discussed earlier in Table 1 TCO 2 40 Output format control. When TCO is HIGH, the output data are in two’s complement format. When TCO is LOW, they are inverted offset binary, unless SO is HIGH and RND is nonzero, in which case they are unsigned. RND 2-0 22-24 16-18 Round and output tristate. Selects output rounding position and active bus width 8-16 bits. All outputs at and below the rounding bit position are tristated, allowing the 4 LSBs to become control inputs. Active, Asynchronous Control OE 34 1 Output enable. LOW activates output bus from SO down to the effective LSB, as chosen by RND 2-0 . All drivers at and below the rounding point are disabled, as are all drivers when OE is HIGH.
PRODUCT SPECIFICATION TMC2242C Notes: 1. Rounding Operation Detail A. If RND 2-0 = 00X, do not drive SO , externally. 2. I/O Format Operation Detail RND 2-0 SO Output Rounding
000 Output
A SO 15-0 (16 bits)
001 Output
A SO 15-1 (15 bits)
010 X SO
(14 bits)
011 X SO
(13) 100 0 SO 15-4 (12) 100 1 SO 15-8 (8) 101 0 SO 15-5 (11) 110 1 SO 15-6 (10)
111 X SO
(9) RND SO TCO In Format Out Format
0 Output 0 2’s Comp Inverted
0 Output 1 2’s Comp 2’s Comp
0 0 0 2’s Comp Inverted Offset >0 0 1 2’s Comp 2’s Comp >0 1 0 Unsigned Unsigned >0 1 1 Unsigned 2’s Comp Absolute Maximum Ratings (beyond which the device may be damaged) Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. Parameter Conditions Min Max Units Supply Voltage -0.5 7.0 V Input Voltage -0.5 V DD + 0.5 V Output Applied Voltage2 -0.5 V DD + 0.5 V Externally Forced Current3,4 -3.0 +6.0 mA Short Circuit Duration Single output in HIGH state to ground 1 sec Operating Temperature (Case) -20 110 °C Junction Temperature 140 °C Lead Soldering Temperature 10 seconds 300 °C Storage Temperature -65 150 °C
PRODUCT SPECIFICATION TMC2242C Operating Conditions
Electrical Characteristics
Conditions Min Nom Max Units VDD Power Supply Voltage 4.75 5.0 5.25 V fCLK Clock frequency TMC2242C 40 MHz TMC2242C-1 60 MHz tPWH CLK pulse width, HIGH 6 ns tPWL CLK pulse width, LOW 6 ns tS Input Data Set-up Time 6 ns tH Input Data Hold Time 0 ns VIH Input Voltage, Logic HIGH 2.0 V VIL Input Voltage, Logic LOW 0.8 V IOH Output Current, Logic HIGH -2.0 mA IOL Output Current, Logic LOW 4.0 mA TA Ambient Temperature, Still Air 0 70 °C P arameter Conditions Min Typ Max Units IDD Total Power Supply Current VDD = Max, CLOAD =25pF, fCLK =Max TMC2242C 150 mA TMC2242C-1 220 mA I DDU Power Supply Current, Unloaded VDD = Max, OE = HIGH, fCLK =Max TMC2242C 135 mA TMC2242C-1 200 mA I DDQ Power Supply Current, Quiescent VDD = Max, CLK = LOW 5 mA C PIN I/O Pin Capacitance 5 pF IIH Input Current, HIGH V DD = Max, VIN = VDD –10 mA IIH (PD) Input Current, HIGH (Pulldown SO0–SO3) VDD = Max, VIN = VDD -10 +150 mA IIL Input Current, LOW V DD = Max, VIN = 0 V –10 mA IOZH Leakage Current, HIGH OE = HIGH, VOUT = VDD –10 mA IOZH (PD) Leakage Current, HIGH (Pulldown SO0–SO3) OE = HIGH, VOUT = VDD -10 +150 mA IOZL Leakage Current, LOW OE = HIGH, VOUT = 0 V –10 mA IOS Short-Circuit Current VDD = Max, Output = HIGH, one pin to ground, one second duration max. -90 -150 mA VOH Output Voltage, HIGH SO15-0, IOH = Max 2.4 V VOL Output Voltage, LOW SO15-0, I OL = Max 0.4 V Parameter Conditions Min Typ Max Units tDO Output Delay Time C LOAD = 25 pF 15 ns tHO Output Hold Time C LOAD = 25 pF 2.5 ns tENA Output Enable Time C LOAD = 0 pF 15 ns tDIS Output Disable Time C LOAD = 0 pF 30 ns
- Inverted offset binary is the same as unsigned, except that all bits are complemented.
- In -6 dB interpolation modes, the two’s complement sign bit is replicated in SI
- In -6 dB interpolation mode, the unsigned MSB is preceded by a 0 in SO15.
- A leading minus sign denotes the two’s complement sign bit.
- In all operating modes except “interpolate -6 dB,” dc gain is exactly unity.
Table 4. Rounded LSBs as a function of RND2-0
- The “r” indicates that the trailing significant output bit has been rounded to the nearest 1/2 LSB. All output drivers at and
below the rounding bit are disabled, allowing the lower output bits to be used as control inputs. 1 = 1, format is 8 bits, viz: SO15…SO8r z…z. Table 5. Steady-State Output Values and Limit Triggers
- Full-scale values are minima and maxima permitted by on-chip limiter. Transient overshoots arising from large input signal
transitions will be clipped to these limits. Unsigned 2’s Comp. Unsigned 2’s Comp. Unsigned 2’s Comp. Unsigned 2’s Comp.
400 C00 2000 E000 4000 C000 1/4-scale 1/2-scale –
1 C000 1 00001 80001 zero full-scale –
Figure 11. Decimate Mode – Two-Channel Figure 12. Interpolate Mode – Two-Channel Figure 13. Threshold Levels for Three State Measurements *In two-channel modes, sync must be left low after the first data input. *In two-channel modes, sync must be left low after the first data input.
69 Y 71 C
Figure 12. Decimating Oversampled Video With a Low Cost 8-bit A/D Note: Data buses are unsigned binary. Figure 13. Interpolating Digital Video Signals before Reconstruction
75 Ohm
28.636 MHz (NTSC D2)
75 Ohm D 7-0
27.000 MHz (D1)
14.318 MHz (NTSC D2)
13.500 MHz (D1)
13.500 MHz (D1) 65-2242C-13
TMC2242C PRODUCT SPECIFICATION Notes:
PRODUCT SPECIFICATION TMC2242C Mechanical Dimensions – 44-Pin PLCC Package D e E .165 .180 4.19 4.57 m bol Inches Min. Max. Min. Max. Millimeters Notes E1 J A2 B D3/E3 J – C – ccc C LEAD COPLANARITY .090 .120 2.29 3.05 .020 .51 —— .013 .021 .33 .53 .685 .695 17.40 17.65 E1 .650 .656 16.51 16.66 E3 .500 BSC 12.7 BSC .050 BSC 1.27 BSC .042 .056 1.07 1.42 2 /NE 11 11 44 44 .004 0.10—— .026 .032 .66 .81 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982 Corner and edge chamfer (J) = 45° Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)
TMC2242C PRODUCT SPECIFICATION Mechanical Dimensions – 44-Lead MQFP Package D E1E e PIN 1 IDENTIFIER B Base Plane Seating Plane See Lead Detail C 0.063" Ref (1.60mm) L -C- ccc C LEAD COPLANARITY A2A a A .077 .093 1.95 2.35 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .000 .010 .00 .25 .083 2.11A2 .077 1.95 B .012 .018 .30 .46 D/E .510 .530 12.95 13.45 D1/E1 .390 .398 9.90 10.10 .032 BSC .81 BSCe L .026 .037 .66 .94 6 C .005 .009 .13 .23a 0° 7° 0° 7° N4 4 4 4 11 11ND ccc .004 0.10—— Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982. Dimensions "D1" and "E1" do not include mold protrusion. Pin 1 identifier is optional. Dimension N: number of terminals. Dimension ND: Number of terminals per package edge. "L" is the length of terminal for soldering to a substrate. "B" includes lead finish thickness.
TMC2242C PRODUCT SPECIFICATION 6/1/99 0.0m 004 Stock#DS7002242C Ó 1998 Fairchild Semiconductor Corporation DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
Ordering Information
Product Number Temperature Range Speed Grade Screening Package Package Marking TMC2242CR2C 0 °C to 70°C 40 MHz Commercial 44-Lead PLCC 2242CR2C TMC2242CR2C1 0 °C to 70°C 60 MHz Commercial 44-Lead PLCC 2242CR2C1 TMC2242CKTC 0 °C to 70°C 40 MHz Commercial 44-Lead MQFP 2242CKTC TMC2242CKTC1 0 °C to 70°C 60 MHz Commercial 44-Lead MQFP 2242CKTC1