TMC2242A CADEKA | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 16

Technical content

Features

  • TMC2242A and TMC2242B are pin-compatible with TMC2242
  • User selectable interpolate gain, -6 dB or 0 dB (2242B)
  • 30, 40 and 60 MHz speed grades
  • User selectable 2:1 decimation, 1:2 interpolation, and equal-rate filter modes
  • Passband ripple < 0.01 dB
  • Stopband rejection 59.4 dB from 0.28 to 0.50 x f s
  • Cascading two TMC2242A or TMC2242B meets CCIR 601 low-pass filter requirement
  • Dedicated 12-bit 2's complement input data port and 16-bit output data port with user-selectable rounding from 9 to 16 bits
  • Tw o's complement or offset binary output format
  • Built-in limiter prevents overflow
  • Single +5 Volt power supply operation
  • Small 44-Lead PLCC and 44-Lead MQFP

Applications

  • Low-cost video filtering
  • Chrominance bandwidth limiter
  • Simple, inexpensive video D/A post-filters
  • Reduced cost and complexity for A/D anti-aliasing filters
  • High-performance digital low-pass filters
  • Digital waveform reconstruction post-filtering
  • Telecommunications
  • Direct digital synthesis
  • Radar

Description

The TMC2242A and TMC2242B are fixed-coefficient lin- ear-phase half-band (low-pass) digital filters. They can be used to halve or double the sampling rate of a digital signal. When used as a decimating post-filter with a double-speed oversampling A/D converter, they greatly reduce the cost and complexity of anti-aliasing filters required ahead of the A/D converter. When used as an interpolating pre-filter with a double-speed oversampling D/A converter, the TMC2242A and TMC2242B significantly reduce the design complexity and production cost of reconstruction filters used on D/A outputs. The TMC2242A and TMC2242B user selects the mode of operation (decimate, interpolate, or equal-rate) and round- ing. The TMC2242A and TMC2242B accept 12-bit 2's com- plement data at up to 60 MHz and output saturated (overflow-protected) 2's complement or offset binary data rounded to from 9 to 16 bits. W ithin the speed grade I/O limit, the output sample rate may be 1/2, 1, or 2 times the input sample rate. Block Diagram SI11-0 CLK DEC INT SYNC 12 12 12 12 16 16 16 SO 15-0 TCO RND 2-0

55 Tap

Decimate, Equal Rate 1-1-1-1 65-2242A-01 TMC2242A/TMC2242B Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz Rev. 1.2.0 www .cadeka.com

PRODUCT SPECIFICATION TMC2242A/TMC2242B The filter response is flat to within 0.01 dB from 0.00 to 0.22 x f s , with stopband attenuation greater than 59.4 dB from 0.28 x f s to the Nyquist frequency. The response is 6 dB down at 0.25 x f s . Symmetric-coefficient filters such as the TMC2242A and TMC2242B have linear phase response. Full compliance with the CCIR-601 standard of 12 dB atten- uation at 0.25 x f s is achieved by cascading two parts. The TMC2242A and TMC2242B are fabricated on an advanced submicron CMOS process. They are available in a 44-lead J-lead PLCC package. Performance is guaranteed from 0 C to 70 Functional Description The TMC2242A and TMC2242B implement a fixed-coeffi- cient linear-phase Finite Impulse Response (FIR) filter of 55 effective taps, with special rate-matching input and output structures to facilitate 2:1 decimation and 1:2 interpolation. The faster of either the input or output registers will operate at the guaranteed maximum clock rate (speed grade). The total internal pipeline latency from the input of an impulse to the corresponding output peak (digital group delay) is 34 cycles; the 55-value output response begins after 7 clock cycles and ends after 61 cycles. To perform interpolation, the chip slows the effective input register clock rate to half the output rate. It internally inserts zeroes between the incoming data samples to "pad" the input data rate to match the output rate. To perform decimation, the chip sets the output register clock rate to half of the input rate. One output is then obtained for every two inputs. For interpolation, the user should bring SYNC HIGH for at least one clock cycle, returning it LOW with the first desired input data value. When interpolating, the chip will then con- tinue to accept a new data input on each alternate rising edge of the clock. When decimating, the chip will present one out- put value for every two clock cycles. The user may leave SYNC LOW or toggle it once per rising clock edge, with equivalent performance. The output data format is two's complement if TCO is HIGH, inverted offset binary if LOW. The user can tailor the output data word width to his/her system requirements using the Rounding control. As shown in Table 4, the output is half-LSB rounded to the resolution selected by the value of RND 2-0 . The asynchronous three-state output enable control simplifies connection to a data bus with other drivers. Table 1. Operating Modes

  1. With 15-bit overflow protection. All other modes on both

(continued)

44 Lead PLCC 44 Lead MQFP

TMC2242A/TMC2242B PRODUCT SPECIFICATION Pin Descriptions Pin Name Pin Number Pin Function DescriptionPLCC MQFP Timing Controls INT 44 38 Interpolate. When INT is LOW and DEC is HIGH, the input data register runs at 1/2 the CLK rate and zeros are inserted in the data stream between valid input values, reducing gain by 6dB. The TMC2242A and TMC2242B interpolate and output results at the full CLK rate. DEC 13 9 Decimate. When DEC is LOW and INT is HIGH, the input data register runs at the full CLK rate. In this mode, the TMC2242A and TMC2242B decimate and output results at 1/2 the CLK rate. When INT = DEC, the TMC2242A is in equal rate mode. When both INT and DEC are HIGH, the TMC2242B is likewise in equal-rate mode, but when both INT and DEC are LOW, the TMC2242B interpolates with unity gain. In equal-rate mode, the input and output sample rates equal the chip clock rate. SYNC 43 37 Synchronization. Incoming data are synchronized by holding SYNC HIGH on CLK N–1 and LOW on CLK N when the first input data word is present on SI 11-0 If DEC = INT=1 (equal rate mode), SYNC is inactive. SYNC may be held LOW until resynchronization is desired, or it may be toggled at 1/2 the CLK rate. CLK 42 36 Clock. The TMC2242A and TMC2242B operate from a single master clock. All internal registers, except the output register in decimation mode, are strobed on the rising edge of CLK. All timing parameters are referenced to the rising edge of CLK. Data Inputs SI 11-0 40, 37-30, 27-25 34, 31-24, 21-19 Input Data Port. A 12-bit 2's-complement input word is registered by the rising edge of CLK. In Interpolate Mode, SI 11-0 is registered on every other CLK (synchronized by SYNC). SI is the MSB. Data Outputs SO 15-0 4-11, 14-21 42-44, 1-5, 8-15 Output Data Port. A 16-bit 2's-complement output result is available after the rising edge of CLK. In Decimate Mode, SO 15-0 is registered on every other CLK (synchronized by SYNC). SO 15-0 is rounded according to the state of RND 2-0 SO is the MSB. The limiter circuitry ensures that for internal overflow, a valid full-scale output (7FFF or 8000) will be generated. With the TMC2242B in interpolate mode with -6dB gain, limits are 3FFF and C000 (TCO=1). Output Controls OE 34 1 Output Enable. When LOW, SO 15-0 are enabled. When HIGH, SO 15-0 are in a high-impedance state. OE is asynchronous with respect to CLK. TCO 2 40 Output Format. When TCO is HIGH, output data are in signed 2's-complement format. When LOW, the output is inverted offset binary. RND 2-0 22-24 16-18 Rounding Select. These inputs set the position of the effective LSB of the output result. Outputs below the rounding bit are zeroed (Table 4). Power V DD 13,29, 7, 23, Supply Voltage. +5 Volt power inputs. These should come from the same power source and be decoupled to GND. GND 12,28, 39,41 6, 22, 33, 35 Ground. Ground inputs should be connected to the system digital ground plane.

PRODUCT SPECIFICATION TMC2242A/TMC2242B Absolute Maximum Ratings (beyond which the device may be damaged) Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. Operating Conditions Parameter Conditions Min Max Units Supply Voltage -0.5 7.0 V Input Voltage -0.5 V DD + 0.5 V Output Applied Voltage -0.5 V DD + 0.5 V Externally Forced Current 3,4 -3.0 +6.0 mA Short Circuit Duration Single output in HIGH state to ground 1 sec Operating Temperature (Case) -20 110 C Junction Temperature 140 C Lead Soldering Temperature 10 seconds 300 C Storage Temperature -65 150 C Parameter Conditions Min Nom Max Units V DD Power Supply Voltage 4.75 5.0 5.25 V f CLK Clock frequency TMC2242A, B 30 MHz TMC2242A-1,B-1 40 MHz TMC2242A-2,B-2 60 MHz t PWH CLK pulse width, HIGH 6 ns t PWL CLK pulse width, LOW 6 ns t S Input Data Set-up Time 6 ns t H Input Data Hold Time 1 ns V IH Input Voltage, Logic HIGH 2.0 V V IL Input Voltage, Logic LOW 0.8 V I OH Output Current, Logic HIGH -2.0 mA I OL Output Current, Logic LOW 4.0 mA T A Ambient Temperature, Still Air 0 70 C

TMC2242A/TMC2242B PRODUCT SPECIFICATION

Electrical Characteristics

Parameter Conditions Min Typ Max Units I DD Total Power Supply Current V DD = Max, C LOAD =25pF, f CLK =Max TMC2242A,B 150 mA TMC2242A-1,B-1 195 mA TMC2242A-2,B-2 290 mA I DDU Power Supply Current, Unloaded V DD = Max, OE = HIGH, f CLK =Max TMC2242A,B 120 mA TMC2242A-1,B-1 155 mA TMC2242A-2,B-2 230 mA I DDQ Power Supply Current, Quiescent V DD = Max, CLK = LOW 5 mA C PIN I/O Pin Capacitance 5 pF I IH Input Current, HIGH V DD = Max, V IN = V DD m A I IL Input Current, LOW V DD = Max, V IN = 0 V m A I OZH Leakage Current, HIGH OE = HIGH, V OUT = V DD m A I OZL Leakage Current, LOW OE = HIGH, VOUT = 0 V ±10 mA IOS Short-Circuit Current VDD = Max, Output = HIGH, one pin to ground, one second duration max. -20 -80 mA VOH Output Voltage, HIGH SO15-0, IOH = Max 2.4 V VOL Output Voltage, LOW SO15-0, I OL = Max 0.4 V Parameter Conditions Min Typ Max Units tDO Output Delay Time C LOAD = 25 pF 15 ns tHO Output Hold Time C LOAD = 25 pF 2.5 ns tENA Output Enable Time C LOAD = 0 pF 12 ns tDIS Output Disable Time C LOAD = 0 pF 12 ns

Table 2. Impulse Response Table 3. Step Response

4018 DC Gain

  1. A leading minus sign denotes the two’s complement sign bit.
  2. When TCO=0, the most significant bit of the output is positive instead of negative.
  3. In all operating modes except INT = 0 and DEC = 1, the gain is approximately unity. When INT = 0 and DEC = 1, the output
  4. The "r" indicates that the trailing significant output bit has been rounded to the nearest 1/2 LSB. (Internally, the chip adds 1 to

Table 5. TMC2242A Steady-State Output Values and Limiter Triggers (L) versus Input Data

801 FFFF (L) 8000 (L) C007 / C017 BFF8 / BFE8 - full-scale

Table 6. TMC2242B Steady-State Output Values and Limiter Triggers (L) versus Input Data Figure 1. Frequency Response

801 FFFF 8000 (L) BFFF C000 (L) - full-scale

801 FFFF (L) 8000 (L) - full-scale

Figure 9. Threshold Levels for Three State Measurements 9-bit rounded decimated output on SO15-7. Figure 10. Decimating Oversampled Video With a Low Cost 8-bit A/D Note: Data buses are unsigned binarys; TMC2242 input is two’s complement. Figure 11. Interpolating Digital Video Signals before Reconstruction

75 Ohm

28.636 MHz (NTSC D2)

75 Ohm D 6-0

27.000 MHz (D1)

14.318 MHz (NTSC D2)

13.500 MHz (D1)

11 LSB

PRODUCT SPECIFICATION TMC2242A/TMC2242B Notes:

TMC2242A/TMC2242B PRODUCT SPECIFICATION Notes:

PRODUCT SPECIFICATION TMC2242A/TMC2242B Mechanical Dimensions – 44-Pin PLCC Package D e E A .165 .180 4.19 4.57 Symbol Inches Min. Max. Min. Max. Millimeters Notes E1 J A A2 B D3/E3 J – C – ccc C LEAD COPLANARITY A1 .090 .120 2.29 3.05 A2 .020 .51 —— B .013 .021 .33 .53 D/E .685 .695 17.40 17.65 D1/E1 .650 .656 16.51 16.66 D3/E3 .500 BSC 12.7 BSC e .050 BSC 1.27 BSC J .042 .056 1.07 1.42 2 ND/NE 11 11 N4 4 4 4 ccc .004 0.10—— B1 .026 .032 .66 .81 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982 Corner and edge chamfer (J) = 45¡ Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)

TMC2242A/TMC2242B PRODUCT SPECIFICATION Mechanical Dimensions – 44-Lead MQFP Package D E1E e PIN 1 IDENTIFIER B Base Plane Seating Plane See Lead Detail C 0.063" Ref (1.60mm) L -C- ccc C LEAD COPLANARITY A2A a A .077 .093 1.95 2.35 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .000 .010 .00 .25 .083 2.11A2 .077 1.95 B .012 .018 .30 .46 D/E .510 .530 12.95 13.45 D1/E1 .390 .398 9.90 10.10 .032 BSC .81 BSCe L .026 .037 .66 .94 6 C .005 .009 .13 .23a 0¡ 7¡ 0¡ 7¡ N4 4 4 4 11 11ND ccc .004 0.10—— Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982. Dimensions "D1" and "E1" do not include mold protrusion. Pin 1 identifier is optional. Dimension N: number of terminals. Dimension ND: Number of terminals per package edge. "L" is the length of terminal for soldering to a substrate. "B" includes lead finish thickness. 44 Lead Metric Quad Flat Pack (MQFP) – 3.2mm Footprint Rev 1.0 11/28/95

TMC2242A/TMC2242B PRODUCT SPECIFICATION 5/20/98 0.0m 001 Stock#DS7002242A O rdering Information Product Number Temperature Rang e Speed Grade Screening Package Package Marking TMC2242AR2C 0°C to 70°C 30 MHz Commercial 44-Lead PLCC 2242AR2C TMC2242AR2C1 0°C to 70°C 40 MHz Commercial 44-Lead PLCC 2242AR2C1 TMC2242AR2C2 0°C to 70°C 60 MHz Commercial 44-Lead PLCC 2242AR2C2 TMC2242BR2C 0°C to 70°C 30 MHz Commercial 44-Lead PLCC 2242BR2C TMC2242BR2C1 0°C to 70°C 40 MHz Commercial 44-Lead PLCC 2242BR2C1 TMC2242BR2C2 0°C to 70°C 60 MHz Commercial 44-Lead PLCC 2242BR2C2 TMC2242AKTC 0°C to 70°C 30 MHz Commercial 44-Lead MQFP 2242AKTC TMC2242AKTC1 0°C to 70°C 40 MHz Commercial 44-Lead MQFP 2242AKTC1 TMC2242AKTC2 0°C to 70°C 60 MHz Commercial 44-Lead MQFP 2242AKTC2 TMC2242BKTC 0°C to 70°C 30 MHz Commercial 44-Lead MQFP 2242BKTC TMC2242BKTC1 0°C to 70°C 40 MHz Commercial 44-Lead MQFP 2242BKTC1 TMC2242BKTC2 0°C to 70°C 60 MHz Commercial 44-Lead MQFP 2242BKTC2