Logic IC

TMC22152AKHC

Cadeka Microcircuits LL...

The TMC22x5yA family of Digital Video Decoders offers unprecedented, broadcast-quality video processing performance in a single chip. It accepts line-locked or subcarrier locked composite,…

Manufacturer: Cadeka Microcircuits LL...

Document: 84 Pages / 554Kb

Request Quote Download Datasheet Read online HTML view

More from Cadeka Microcircuits LL... Browse T parts

Online Datasheet

Read TMC22152AKHC online.

TMC22X5YA CADEKA | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 84

Technical content

Features

Very high performance, low cost
Adaptive comb-based decoding
Multiple pin-compatible versions - 3-line, 2-line, and band-split - 8- and 10-bit processing
Internal digital linestores
Supports NTSC/PAL ﬁeld and NTSC frame based decoding
Multiple input formats - CCIR-601/624 (D1), D2, CVBS, YC
Multiple output formats - CCIR-601/624 (D1), RGB, YC B C R
10-18 Mpps data rate
Parallel and serial control interface
Single +5V power supply

Applications

Studio television equipment
Personal computer video input
MPEG and JPEG compression inputs

Description

The TMC22x5yA f amily of Digital V ideo Decoders offers unprecedented, broadcast-quality video processing perfor- mance in a single chip. It accepts line-locked or subcarrier- locked composite, YC, or D1 digital video and produces dig- ital components in a variety of formats. An internal three-line adaptive comb decoder structure pro- duces optimal picture quality with a wide range of source material. NTSC/PAL ﬁeld and NTSC frame based decoding is supported with external memory. Full comb programma- bility allows the user to tailor the decoder’s response to a particular systems goals. A family of products offers 3-line, 2-line, and simple decod- ers in 8-bit and 10-bit versions—all in a pin and software- compatible format. Serial and parallel control ports are pro- vided. These submicron CMOS devices are packaged in a 100-lead Metric Quad Flat Pack (MQFP).

Related Products

TMC22071 Genlocking V ideo Digitizer
TMC22x9x 8 bit Digital V ideo Encoders
TMC2081 Digital V ideo Mixer
TMC3003 Triple 10-bit D/A Converter
TMC1185 10 bit A/D converter
TMC2192 10 bit video encoder
TMC2072 Enhanced Genlocking V ideo Digitizer Block Diagram 65-22x5y-01 Input Processor Output ProcessorAdaptive Comb Filter VIDEOA 9-0 VIDEOB 9-0 G/Y9-0 MASTER 1-0 BUFFER CLOCK HSYNC VSYNC LDV DHSYNC DVSYNC DREF FID2-0 B/Cb9-0 R/Cr9-0 SERA1-0 SA 2-0RESETSETR/W SDACS SCLD 7-0 Parallel Control Serial ControlGlobal Control Internal Sync Pulse Generator Y/C Split0 Y/C Split1Linestore1 Linestore2 Y/C Split2 Chroma Demod Comb Fail Burst Locked Loop TMC22x5yA Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit www .cadeka.com

TMC22x5yA PRODUCT SPECIFICATION Table of Contents C Decimating C Multiplexed YCB C R Output (TRS Words Inserted)... 58

PRODUCT SPECIFICATION TMC22x5yA assumed to be luminance and the high frequency portion is processed as chrominance to ﬁnd the magnitude and phase of the chrominance vector. These three components are then compared across the (0H & 1H) and (1H & 2H) taps of the comb ﬁlter to produce the difference in luminance, chromi- nance magnitude, and chrominance phase. These differences are then translated in the user-programmable lookup table to produce the “K” signal which controls the complementary mix between the output of the comb ﬁlter and the simple bandsplit decoder. That is, the “K” signals controls how much of the combed high frequency luminance signal is sub- tracted from the simple bandsplit chrominance for chroma combs, or added to the low frequency output of the bandsplit for luma comb ﬁlters. Output Processor The demodulated chrominance signal and the luminance signal are passed through a programmable output matrix, producing RGB, YUV , or YC B C R . When the clock is at 27MHz, a D1 signal can be produced on the R/V output with the embedded TRS words ﬁxed to the external HSYNC and VSYNC timing. Parallel and Serial Microprocessor Interfaces The parallel microprocessor interface employs 12 pins, the serial port uses 5. A single pin, SER , selects between the two interface modes. In parallel interface mode, one address line is decoded for access to the internal control register and its pointer. Controls are reached by loading a desired address through the 8-bit D 7-0 port, followed by the desired data (read or write) for that address. The control register address pointer auto-increments to address 3Fh and then remains there. A 2-line serial interface may also be used for initialization and control. The same set of registers accessed by the paral- lel port is available to the serial port. The device address in the serial interface is selected via pins SA 2-0. The RESET pin sets all internal state machines to their ini- tialized conditions and places the decoder in a power-down mode. All register data are maintained while in power-down mode. Pin Assignments G/Y1 G/Y0 LDV GND V DD B/Cb9 B/Cb8 B/Cb7 B/Cb6 B/Cb5 B/Cb4 B/Cb3 B/Cb2 B/Cb1 B/Cb0 GND V DD R/Cr9 R/Cr8 R/Cr7 R/Cr6 R/Cr5 R/Cr4 R/Cr3 R/Cr2 R/Cr R/Cr0 GND VDD DREF FID FID1 FID2 DHSYNC DVSYNC D GND VDD GND V DD HSYNC VSYNC BUFFER Pin Name Pin Name RESET SET SER SA SA1 SA2 GND SDA SCL CS R/W A GND VDD VIDEOB0 VIDEOB1 VIDEOB2 VIDEOB3 VIDEOB4 VIDEOB5 VIDEOB6 VIDEOB7 VIDEOB8 VIDEOB9 GND VIDEOA0 VIDEOA1 VIDEOA2 VIDEOA3 VIDEOA4 VIDEOA5 VIDEOA6 VIDEOA7 VIDEOA8 VIDEOA9 MASTER0 MASTER1 CLOCK GND V DD GND G/Y G/Y8 G/Y7 G/Y6 G/Y5 G/Y4 G/Y3 G/Y2 100 Pin Name Pin Name 65-22x5y-03 31 50 81100

TMC22x5yA PRODUCT SPECIFICATION Pin Descriptions Pin Name Pin Number Value Pin Function Description Inputs VIDEOA 82, 81, 80, 79, 78, 77 TTL Video input A. An 8 or 10 bit data input to the input multiplexer. For 8-bit versions (TMC2205yA) the data are left-justified (VIDEOA9-2). VIDEOB 9-0 75, 74, 73, 72, 71, 70, 69, 68, 67, 66 TTL Video input B. An 8 or 10 bit data input to the input multiplexer. For 8-bit versions (TMC2205yA) the data are left-justified (VIDEOB9-2). VSYNC 49 TTL Vertical sync input. A vertical sync signal (active low) occurring at the start of the first vertical sync pulse in a vertical field group. A falling edge of VSYNC which is coincident with a falling edge of HSYNC indicates field 1. This signal is active only when SPGIP1-0 = 00. HSYNC 48 TTL Horizontal sync input. A horizontal sync signal (active low) occurring at the falling edge of the video sync. This signal is active only when SPGIP 1-0 = 00. MASTER 1-0 88, 87 TTL Master decoder control.

00 Adaptive comb decoder

01 Simple bandsplit decoder

10 Reserved

11 Flat notched luma and simple bandsplit chroma

BUFFER 50 TTL Control register select. This signal switches between two sets of registers which control the gain or hue values in the output matrix. When BUFFER = 0, registers 17-1F are active. When BUFFER = 1, registers 27-2F take control. CLOCK 89 TTL Master processing clock. The clock signal can either be at twice the pixel data rate in the line locked modes, or at four times the subcarrier frequency in the subcarrier mode. The interpretation of the CLOCK signal is set by the CKSEL register bit. SET 52 TTL Programmable function pin. The function specified by the SET register is active when SET is low. The decoder returns to its previous operation when SET goes high. Outputs G/Y 97, 98, 99, 100, 1, 2 TTL Green or Luminance digital output. For 8-bit versions (TMC2205yA) the data are left-justified (G/Y9-2). 11, 12, 13, 14, TTL Blue or CB digital output. For 8-bit versions (TMC2205y) the data are left-justified (B/CB 9-2). 22, 23, 24, 25, 26, 27 TTL Red or CR digital output. For 8-bit versions (TMC2205yA) the data are left-justified (R/CR 9-2). DVSYNC 35 TTL Vertical sync output. The DVSYNC signal occurs once per field and lasts for 1 video line. DHSYNC 34 TTL Horizontal sync output. The DHSYNC signal occurs once per line and lasts for 64 clock periods. LDV 3 TTL Data synchronization output. LDV can be an internally or externally generated clock signal. The internal LDV signal is produced when the CLOCK input is at twice the pixel data rate (PXCK); and is a pixel data rate clock phase locked to the falling edge of the HSYNC. The external LDV can be selected under software control, and must be at the CLOCK, or a sub multiple of the CLOCK, frequency.

PRODUCT SPECIFICATION TMC22x5yA DREF 30 TTL Decoder reference signal. This is a dual function pin, controlled by register 24, that can function as an active video output indicator or output as a clamp pulse. When set to the active video output function, the DREF pin is HIGH during the video portion of each line and LOW during the horizontal and vertical blanking levels. When set to output a clamp pulse, the clamp pulse is controlled by register 24 and 25 allowing a user to program when a 0.5 µSec pulse is output relative to HSYNC. FID 2-0 33, 32, 31 TTL Field identification output. A 3 bit field ident from the DRS signal. µP Interface D 7-0 45, 44, 43, 42, 41, 38, 37, 36 TTL Parallel control port data I/O. All control parameters are loaded into and read back over this 8 bit data port. A1-0 63, 62 TTL Parallel control port address inputs. These pins govern whether the microprocessor interface selects a table/register address or reads/ writes table/register contents. CS 60 TTL Parallel control port chip select. When CS is high the microprocessor interface port, D7-0, is set to HIGH impedance and ignored. When CS is LOW, the microprocessor can read or write parameters over D7-0. R/W 61 TTL Parallel control port read/write control. When R/W and CS are LOW, the microprocessor can write to the control registers or XLUT over D 7-0. When R/W is HIGH and CS is LOW, it can read the contents of any selected XLUT address or control register over D7-0. RESET 51 TTL Chip master reset. Bringing RESET LOW sets the software reset control bit, SRESET, LOW and disables the digital outputs. If HRESET is LOW the decoder outputs remain disabled after RESET goes HIGH until the SRESET bit is set high by the host. If HRESET is HIGH when RESET goes HIGH the decoder the internal state machines are enabled. SER 53 TTL Serial/parallel interface select. This pin will select between a parallel (HIGH) or serial (LOW) interface port. SDA 58 R-Bus Serial data interface. Bi-directional serial interface to the control port. SCL 59 R-Bus Serial interface clock. SA 2-0 56, 55, 54 TTL Serial Address. Three bits providing the lsbs of the serial chip ID used to identify the decoder. Power Supply V DD 5, 17, 29, 40, 47, 65, 91 +5 V Power Supply. Positive power supply for digital circuits, +5V. GND 4, 16, 28, 39, 46, 57, 64, 76, 90, 92 0.0 V Ground. Ground for digital circuits, 0V. Pin Descriptions (cont.) Pin Name Pin Number Value Pin Function Description

TMC22x5yA PRODUCT SPECIFICATION Control Register Map The TMC22x5yA is initialized and controlled by a set of registers which determine the operating modes. An external controller is employed to write and read the Control Registers through either the 8-bit parallel or 2-line serial interface port. The parallel port, D 7-0, is governed by pins CS, R/W, and A1-0. The serial port is controlled by SDA and SCL. Reg Bit Name Function Global Control 00 7 SRST Software reset 00 6 HRST Hardware reset 00 5-3 SET SET pin function 00 2 DHVEN Output H&V sync enable 00 1-0 STD Selects video standard Input Processor Control 01 7 reserved, set to zero 01 6 IPMUX Input mux control 01 5 IP8B 8 bit input format 01 4 TDEN TRS detect enable 01 3 TBLK TRS blank enable 01 2 IPCMSB Chroma input msb invert 01 1 ABMUX AB mux control 01 0 CKSEL Input clock rate select Burst Loop Control 02 7 BLLRST BLL auto. reset enable 02 6 VIPEN Video Input Processor enable 02 5-4 LOCK Global lock mode 02 3 BLM BLL lock mode 02 2 KILD Color kill disable 02 1 DMODBY Demod bypass 02 0 CINT C BC R interpolation enable Chroma Processor Control 03 7-5 BLFS Burst loop filter select 03 4 CCEN Chroma coring enable 03 3-2 CCOR Chroma coring threshold 03 1 GAUBY Gaussian filter bypass 03 0 GAUSEL Gaussian filter select Burst Threshold 04 7-0 BTH Burst threshold Pedestal 05 7-0 PED Pedestal level Luma Processor Control 06 7-6 reserved, set to zero 06 5 ANEN Adaptive notch enable 06 4 ANR Adaptive notch rounding 06 3-2 ANT Adaptive notch threshold 06 1 ANSEL Adaptive notch select 06 0 NOTCH Notch enable Comb Processor Control 07 7 LS1BY Line store 1 bypass 07 6 LS1IN Line store 1 input 07 5 LS2DLY Line store 2 delay 07 4 SPLIT Line store 2 data width 07 3 BSFBY Bandsplit filter bypass 07 2 BSFSEL Bandsplit filter select 07 1 BSFMSB Inverts msb of bandsplit filter 07 0 GRSDLY Delays input to GRS decode by 1H Mid-Sync Level 08 7-0 MIDS Mid-sync level Extended DRS 09 7-4 PCKF Clock rate 09 3-0 VSTD Video standard Output Control 0A 7 OP8B Output rounded to 8 bits 0A 6-5 OPLMT Output limit select 0A 4-3 MSEN Mixed sync enable 0A 2 OPCMSB Chroma output msb invert 0A 1 YBAL Luma color correction 0A 0 BUREN Output burst enable 0B 7 FMT422 Enables C BC R output mux 0B 6 CDEC C BC R decimation enable 0B 5 YUVT Enables D1 output 0B 4-2 reserved, set to zero 0B 1 DRSEN DRS output enable 0B 0 DRSCK DRS data rate Comb Filter Control 0C 7-6 ADAPT Adaption mode 0C 5 YCES YC input error signal control 0C 4 YCSEL luma/chroma comb filter select 0C 3-0 COMB Comb filter architecture Reg Bit Name Function

PRODUCT SPECIFICATION TMC22x5yA 0D 7-6 CEST Chroma error signal transform 0D 5 CESG Chroma error signal gain 0D 4 YESG Luma error signal gain 0D 3 CESTBY Chroma error signal bypass 0D 2 XFEN XLUT filter enable 0D 1 FAST Adaption speed select 0D 0 YWBY Luma weighting bypass 0E 7-6 XIP XLUT input select 0E 5-4 XSF XLUT special function 0E 3-2 YMUX Y output select 0E 1-0 CMUX C output select 0F 7 reserved, set to zero 0F 6-5 CAT Adaption Threshold 0F 4 DCES D1 C BC R error signal 0F 3-2 IPCF Comb filter input select 0F 1 YCCOMP YC or Composite input select 0F 0 SYNC Sync processor select Sync Pulse Generator 10 7-0 STS 7-0 Sync to sync 8 lsbs 11 7-0 STB Sync to burst 12 7-0 BTV Burst to video 13 7-0 AV 7-0 Active video line 8 lsbs 14 7-6 reserved, set to zero 14 5-4 AV 9-8 Active video line 2 msbs 14 3 reserved, set to zero 14 2-0 STS 10-8 Sync to sync 3 msbs 15 7 reserved, set to zero 15 6-2 VINDO Number of lines in vertical window 15 1 VDIV Action inside VINDO 15 0 VDOV Action outside VINDO 16 7-6 reserved, set to zero 16 5-4 NFDLY new field detect delay 16 3-2 SPGIP SPG input select 16 1-0 MSIP Mixed sync separator input select Buffered register set 0 Active when BUFFER pin set LOW 17 7-0 SG0 7-0 Msync gain, 8 lsbs 18 7-0 YG0 7-0 Y gain, 8 lsbs 19 7-0 UG0 7-0 U gain, 8 lsbs Reg Bit Name Function 1A 7-0 VG0 7-0 V gain, 8 lsbs 1B 7-6 YG0 9-8 Y gain, 2 msbs 1B 5-3 UG0 10-8 U gain, 3 msbs 1B 2 reserved, set to zero 1B 1-0 VG0 9-8 V gain, 2 msbs 1C 7-0 YOFF0 7-0 Y offset, 8 lsbs 1D 7-3 reserved, set to zero 1D 2 YOFF0

8 Y offset, msb

1D 1-0 SG0 7-0 Msync gain, 2 msbs 1E 7-1 SYSPH0 6-0 7 lsbs of phase 1E 0 VAXISO V axis flip 1F 7-0 SYSPH014-7 8 msbs of phase Normalized Subcarrier Frequency 20 7-4 FSC 3-0 Bottom 4 bits of fSC 20 3-0 reserved, set to zero 21 7-0 FSC 11-4 Lower 8 bits of fSC 22 7-0 FSC 19-12 Middle 8 bits of fSC 23 7-0 FSC 27-20 Top 8 bits of fSC Clamp Control 24 7 DRFSEL Clamp pulse enable 24 6 PFLTBY Phase filter enable 24 5-4 CLPSEL 1-0 Int. clamp selection 24 3 VCLPEN Clamp bypass 24 2-0 BAND 2-0 Clamp offset 25 7-0 CPDLY 7-0 Clamp pulse delay Output Format Control 26 7-6 reserved, set to zero 26 5 LDVIO LDV clock select 26 4 OPCKS Output clock select 26 3 DPCEN DPC enable 26 2-0 DPC Decoder product code Buffered register set 1 Active when BUFFER pin set HIGH 27 7-0 SG1 7-0 Msync gain, 8 lsbs 28 7-0 YG1 7-0 Y gain, 8 lsbs 29 7-0 UG1 7-0 U gain, 8 lsbs 2A 7-0 VG1 7-0 V gain, 8 lsbs 2B 7-6 YG1 9-8 Y gain, 2 msbs 2B 5-3 UG1 10-8 U gain, 3 msbs 2B 2 reserved, set to zero 2B 1-0 VG1 9-8 V gain, 2 msbs 2C 7-0 YOFF1 7-0 Y offset, 8 lsbs 2D 7-3 reserved, set to zero Reg Bit Name Function

TMC22x5yA PRODUCT SPECIFICATION 10 REV. 1.0.0 2/4/03 2D 2 YOFF1 8 Y offset, msb 2D 1-0 SG1 7-0 Msync gain, 2 msbs 2E 7-1 SYSPH1 6-0 7 lsbs of phase 2E 0 VAXIS1 V axis flip 2F 7-0 SYSPH114-7 8 msbs of phase Video Measurement 30 7 set to zero 30 6 LGF Line grab flag 30 5 LGEN Line grab enable 30 4 LGEXT Ext line grab enable 30 3 reserved, set to zero 30 2 PGG Pixel grab gate 30 1 PGEN Pixel grab enable 30 0 PGEXT Ext pixel grab enable 31 7-0 PG 7-0 Pixel grab, 8 lsbs 32 7-0 LG 7-0 Line grab, 8 lsbs 33 7 reserved, set to zero 33 6-4 FG Field grab number 33 3 LG

8 Msb of line grab

33 2-0 PG 10-8 Pixel grab, 3 msbs 34 7-0 GY 9-2 G/Y grab, 8 msbs 35 7-0 BU 9-2 B/U grab, 8 msbs 36 7-0 RV 9-2 R/V grab, 8 msbs 37 7-6 reserved 37 5-4 GY 1-0 G/Y grab, 2 lsbs 37 3-2 BU 1-0 B/U grab, 2 lsbs 37 1-0 RV 1-0 R/V grab, 2 lsbs 38 7-0 Y 9-2 Luma grab, 8 msbs 39 7-0 M 9-2 Msync grab, 8 msbs 3A 7-0 U 9-2 U grab, 8 msbs 3B 7-0 V 9-2 V grab, 8 msbs 3C 7-6 Y 1-0 Luma grab, 2 lsbs 3C 5-4 M 1-0 Msync grab, 2 lsbs 3C 3-2 U 1-0 U grab, 2 lsbs 3C 1-0 V 1-0 V grab, 2 lsbs Test Control 3D 7-0 TEST Must be set to zero 3E 7-0 TEST Must be set to zero Vertical Blanking Control 3F 7 VBIT20 V bit control 3F 6 PEDDIS Pedestal control 3F 5-0 CCDEN 5-0 Closed caption control Auto-increment stops at 3F Reg Bit Name Function Notes: 1. Functions are listed in the order of reading and writing. 2. For each register listed above up to register 3F, all bits not specified are reserved and must be set to zero to ensure proper operation. Status - Read Only 40 7-0 DDSPH DDS phase, 8 msbs 41 7 LINEST Pixel count reset 41 6 BGST Start of burst gate 41 5 VACT2 Half line flag 41 4 PALODD PAL Ident 41 3 VFLY Vertical count reset 41 2 FGRAB Field grab 41 1 LGRAB Line grab 41 0 PGRAB Pixel grab 42 7 FLD Field flag (F in D1 output) 42 6 VBLK Vertical blanking (V in D1 output) 42 5 HBLK Horizontal blanking (H in D1 output) 42 4-0 LID Line identification 43 7 YGO Y/G overflow 43 6 YGU Y/G underflow 43 5 UBO C B/B overflow 43 4 UBU C B/B underflow 43 3 VRO C R /R overflow 43 2 VRU C R /R underflow 43 1-0 reserved 44 7 MONO Color kill active 44 6-0 FPERR Frequency/Phase error 45 7-0 DRS DRS signal 46 7-0 PARTID Reads back xx h 48- 7-0 reserved 4B 7 PKILL Phase kill from comb fail 4B 6-5 CFSTAT Comb filter status 4B 4-0 XOP XLUT output 4C- FF 7-0 reserved Reg Bit Name Function

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 11 Control Register Deﬁnitions Global Control Register (00) 76543210 SRST HRST SET DHVEN STD Reg Bit Name Description 00 7 SRST Software reset. When LOW, resets and holds internal state machines and disables outputs. When HIGH (normal), starts and runs state machines and enables outputs. This bit is ignored while HRST is high. 00 6 HRST Hardware reset. When HRST is HIGH, SRST is forced low when RESET pin is taken LOW. State machines are reset and held. When HRST is low the RESET pin can be taken HIGH at any time. The state machines remain disabled until SRST is programmed HIGH. When HRST is high the state machines are enabled as soon as the RESET pin goes HIGH. 00 5-3 SET SET pin function. These bits control the set function when the SET pin goes low. A = all outputs high-impedance B = internal state machines C = burst locked loop The first SET pulse after a software or hardware reset, with SET = 111, causes a toggle to SET = 010. 00 2 DHVEN Output H&V sync enable. Disables DHSYNC and DVSYNC signals when HIGH. 00 1-0 STD Selects video standard. Selects video standard. SET Function 000 Reset and hold A, B, & C. 001 Set output to BLUE and flywheel B & C. (RGB outputs) Set output to "color" and flywheel B & C (YC BC R outputs)

010 Hold A, lock B & C to external input

011 Reset C only

100 Reset B & C

101 Set output to BLUE and lock B & C to input video (RGB output)

110 Line and pixel grab depending on VMCR

6-0 (reg 30) 111 Toggle reset function of SET = 010. For each SET = 0 pulse the chip operation will change from normal to that of SET = 010 or visa versa.SET Function

00 NTSC

10 PAL/M

11 All PAL standards except PAL/M

TMC22x5yA PRODUCT SPECIFICATION 12 REV. 1.0.0 2/4/03 Control Register Deﬁnitions (continued) Input Processor Control (01) 76543210 Reserved IPMUX IP8B TDEN TBLK IPCMSB ABMUX CKSEL Reg Bit Name Description 01 7 Reserved Reserved, set to zero. 01 6 IPMUX Input mux control. Used to select the Video Input Processor, D1, or D2 data as the VA input to the input processor. VIDEOA is selected for VA and VIDEOB is selected for VB when IPMUX is set LOW. VIDEOB is selected for VA and VIDEOA for VB when IPMUX is set HIGH. For YC inputs, the luma data must be passed through the VA input and chroma through the VB input. IPMUX should be set LOW for line locked composite inputs. 01 5 IP8B 8 bit input format. Bottom two bits of inputs VIDEOA 9-0 and VIDEOB9-0 are set to zero when HIGH. 01 4 TDEN TRS detect enable. When HIGH, the TRS words embedded in incoming video are used to reset the horizontal and vertical state machines. When LOW the externally provided or internally generated HSYNC and VSYNC are used to reset the horizontal and vertical state machines. 01 3 TBLK TRS blank enable. Blanks the TRS and AUX data words when HIGH. For line locked and D1 data, the TRS and AUX data words are set to the luma and chroma blanking levels as appropriate. For D2 (4*f SC ) data, the TRS and AUX data words are set to the sync tip level. 01 2 IPCMSB Chroma input msb invert. The msb of the chroma or CBC R data are inverted when HIGH. 01 1 ABMUX AB mux control. Selects the primary and secondary inputs to the decoder from the DA and DB outputs of the input processor. When ABMUX is LOW, DA is selected as the primary and DB as the secondary decoder input. 01 0 CKSEL Input clock rate select. Set HIGH for line locked clocks and LOW for subcarrier locked clocks. Line locked clocks should be at twice the pixel data rate, and the subcarrier clock should be at four times the subcarrier frequency.

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 13 Control Register Deﬁnitions (continued) Burst Loop Control (02) 76543210 BLLRST VIPEN LOCK BLM KILD DMODBY CINT Reg Bit Name Description 02 7 BLLRST BLL reset enable. When LOW, the automatic BLL reset is disabled. When HIGH, the BLL will be reset if the BLL loses lock and fails to reacquire lock within 8 fields. input devices. Active only when LOCK1-0 = 10. 02 5-4 LOCK Global Lock mode. Sets the decoder locking mode. 02 3 BLM BLL lock mode. Sets the decoder burst locking mode. 02 2 KILD Color kill disable. Color killer is disabled when HIGH. 02 1 DMODBY Demod bypass. Chroma data bypasses the demodulator when HIGH. 02 0 CINT C B C R interpolation enable. Interpolation of CBC R input data from 0:2:2 to 0:4:4 is enabled when HIGH. VIPEN Function

0 Video Input Processor Interface

1 TMC22071 Interface

00 Line Locked Mode

01 Subcarrier Locked Mode

10 Video Input Processor Mode

11 D1 Mode

0 Frequency Lock

1 Phase Lock

02 6 VIPEN Video Input Processor enable. Selects interface protocol for CADEKA video

TMC22x5yA PRODUCT SPECIFICATION 14 REV. 1.0.0 2/4/03 Control Register Deﬁnitions (continued) Chroma Processor Control (03) 76543210 BLFS CCEN CCOR GAUBY GAUSEL Reg Bit Name Description 03 7-5 BLFS Burst loop filter select. 03 4 CCEN Chroma coring enable. Enables Chroma Coring when HIGH. 03 3-2 CCOR Chroma coring threshold. Sets the Chroma Coring threshold. 03 1 GAUBY Gaussian filter bypass. The chroma data bypasses the Gaussian LPF when HIGH. 03 0 GAUSEL Gaussian LPF select. Selects the Gaussian filter response to be used on the demodulated chrominance. See Figure 22 for filter responses. BLFS f S (Mpps) Recommended Criteria 000 13.5 PAL, Line-Locked YC 000 15 PAL, Line-Locked YC 001 12.27 NTSC, Line-Locked YC 001 13.5 PAL, Line-Locked Composite 010 13.5 NTSC, Line-Locked YC 010 15 PAL, Line-Locked Composite 011 14.32 NTSC, Subcarrier-Locked YC 011 17.73 PAL, Subcarrier-Locked Composite 100 17.73 PAL, Subcarrier-Locked YC 101 13.5 NTSC, Line-Locked Composite 110 12.27 NTSC, Line-Locked Composite 111 14.32 NTSC, Subcarrier-Locked Composite CCOR Function 00 1 lsb 01 2 lsb 10 3 lsb 11 4 lsb GAUSEL Function 0 Select Gaussian LPF resp. 2 1 Select Gaussian LPF resp. 1

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 15 Control Register Deﬁnitions (continued) Burst Threshold (04) 76543210 BTH Reg Bit Name Description 04 7-0 BTH Burst threshold. The 8 bit value to be compared against the demodulated U and V component data. If over 127 lines occur in a field in which the burst is below this threshold, then the color is set to chroma black for the next field. Pedestal (05) 76543210 PED Reg Bit Name Description 05 7-0 PED Pedestal level. An 8 bit magnitude subtracted from the luma data to remove the setup before processing by the output matrix. Luma Processor Control (06) 76543210 Reserved ANEN ANR ANT YSEL NOTCH Reg Bit Name Description 06 7-6 Reserved Reserved, set to zero. 06 5 ANEN Adaptive notch enable. Enables adaptive notch when HIGH. 06 4 ANR Adaptive notch rounding. Sets adaptive notch rounding point. 06 3-2 ANT Adaptive notch threshold level. Sets the adaptive notch threshold. 06 1 YSEL Adaptive notch select. Selects adaptive notch filter response. 06 0 NOTCH Notch enable. Adaptive notch filter ANF3 selected when HIGH and ANEN is HIGH, non-adaptive notch filter selected when HIGH and ANEN is LOW. Function may be overridden by XSF (Reg 0E, bits 5-4). ANR Function

0 Round to 10 bits

1 Round to 8 bits

00 Magnitude difference less than 32

01 Magnitude difference less than 24

10 Magnitude difference less than 16

11 Magnitude difference less than 8

0 Adaptive notch response ANF1

1 Adaptive notch response ANF2

TMC22x5yA PRODUCT SPECIFICATION 16 REV. 1.0.0 2/4/03 Control Register Deﬁnitions (continued) Comb Processor Control (07) 76543210 LS1BY LS1IN LS2DLY SPLIT BSFBY BSFSEL BSFMSB GRSDLY Reg Bit Name Description 07 7 LS1BY Line store 1 bypass. Bypasses linestore 1 when HIGH. 07 6 LS1IN Line store 1 input. Selects the input of linestore 1: 07 5 LS2DLY Line store 2 delay. LSTORE2 uses STS to store 1H when LOW and uses VL to store SAV to EAV (or max count) when HIGH. 07 4 SPLIT Line store 2 delay. Splits data through LSTORE2, 9 bits chroma and 7 bits luma when HIGH (chroma combs) and 8 bits chroma and 8 bits luma when LOW (luma comb). 07 3 BSFBY Bandsplit filter bypass. Bandsplit filter is bypassed when HIGH. 07 2 BSFSEL Bandsplit filter select. Selects the bandsplit filter to be used: 07 1 BSFMSB Inverts msb of bandsplit filter. When HIGH, inverts the msb of the input to the bandsplit filter. 07 0 GRSDLY Delays input to GRS decode. When HIGH, delays the input to the GRS extraction circuit by 1H. Genlock only. Mid-Sync Level (08) 76543210 MIDS Reg Bit Name Description 08 7-0 MIDS Mid sync level. Sets the mid point of syncs for the mixed sync separator, in the subcarrier locked mode. LS1IN Function

0 Primary Input

1 Secondary Input

0 Select bandsplit filter response 1

1 Select bandsplit filter response 2

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 17 Control Register Deﬁnitions (continued) Extended DRS (09) 76543210 PCKF VSTD Reg Bit Name Description 09 7-4 PCKF Clock rate. 09 3-0 VSTD Video Standard. Selects the video standard. PCKF Function 0000 13.50 MHz 0001 reserved 0010 reserved 0011 reserved 0100 14.32 MHz 0101 17.73 MHz 0110 reserved 0111 reserved 1000 12.27 MHz 1001 14.75 MHz 1010 15.00 MHz 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved VSTD Function

0000 NTSC-M

0001 NTSC-EIAJ

1000 PAL-B, G, H, I

1001 PAL-M

1010 PAL-N (Argentina, Paraguay, Uruguay)

1011 PAL-N (Jamaica)

TMC22x5yA PRODUCT SPECIFICATION 18 REV. 1.0.0 2/4/03 Control Register Deﬁnitions (continued) Notes: 1. To enable “super blacks” and disable syncs of the output simply set MSEN[1] HIGH and the sync gain to zero. Output Control (0A) 76543210 OP8B OPLMT OPLMT MSEN OPCMSB YBAL BUREN Reg Bit Name Description 0A 7 OP8B Output rounded to 8 bits. Rounds the outputs to 8 bits when HIGH. The two lsbs are set to zero. 0A 6-5 OPLMT Output limit select. Sets the output format and limiters: 0A 4-3 MSEN Mixed sync enable. Sets composite sync output format: 0A 2 OPCMSB Chroma output msb invert. Inverts the msb of the CBC R or Chroma output when HIGH. 0A 1 YBAL Luma color correction. Setting this bit HIGH forces the chroma to zero whenever the luma equals or exceeds the luma limit. 0A 0 BUREN Output burst enable. When HIGH, passes the burst through on the chroma channel. Sets the burst region to zero when LOW. OPLMT Function

00 RGB output format

01 YC BC R output format

C BC R limited to ±504

10 RGB output format

11 YC BC R output format

C BC R limited to ±448 MSEN Function

00 No sync, & “super blacks” disabled

01 No sync, & “super blacks” disabled

10 Sync on G/Y output only, & “super blacks” enabled

11 Sync on RGB outputs, & “super blacks” enabled

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 19 Control Register Deﬁnitions (continued) Output Control (0B) 76543210 FMT422 CDEC YUVT Reserved DRSEN DRSCK Reg Bit Name Description 0B 7 FMT422 Enables CB C R output mux. When HIGH, multiplexes the CB and CR data onto the same data bus. The chroma or multiplexed CBC R output appears on the B/CB output. The R/CR output is forced low. 0B 6 CDEC C B C R decimation enable. When HIGH, the CBC R data are decimated to 0:2:2 in the output processor. 0B 5 YUVT Enables D1 output. When HIGH, enables 4:2:2 multiplexed YCBC R onto the R/CR data output with TRS words inserted into the output data stream. The Y data are still available on the G/Y output and multiplexed CBC R is available on the B/U output. 0B 4-2 Reserved Reserved, set to zero. 0B 1 DRSEN DRS output enable. When HIGH, enables the DRS onto the G/Y output. 0B 0 DRSCK DRS data rate. Sets the DRS output data rate. DRSCK Function

0 Embeds data bytes (8 bits) at PCK

1 Embeds data nibbles (4 bits) at

TMC22x5yA PRODUCT SPECIFICATION 20 REV. 1.0.0 2/4/03 Control Register Deﬁnitions (continued) Comb Filter Control (0C) 76543210 ADAPT YCES YCSEL COMB Reg Bit Name Description 0C 7-6 ADAPT Adaption mode. Sets the 3-line comb filter adaption mode in NTSC. 0C 5 YCES YC input error signal control. Error signal control for YC input, luma comb. 0C 4 YCSEL Luma/chroma comb filter select. Selects luma or chroma comb filter. 0C 3-0 COMB Comb filter architecture. ADAPT[1:0] Function

00 Adapts to best of 3 types of line based comb filters in NTSC

only.

01 Adapts to the best of two field or frame based comb filters

in NTSC only. 10 3 line (tap) comb only. Never adapts to a 2 line (tap) filter. The higher set of comb filter error signals are sent to the XLUT. NTSC or PAL comb filter. 11 Adapts to best of two 3 line chroma comb filters in PAL only. YCES Function

0 LPF and HPF error signal, between (0H & 1H) or (1H & 2H) in

NTSC or between (0H & 2H) in PAL,are sent to XLUT

1 LPF error signal, between (0H & 1H) and (1H & 2H) in NTSC or

between (0H & 2H) in PAL, are sent to XLUT YCSEL Function

0 Chroma comb filter

1 Luma comb filter

YC or composite comb ﬁlter architectures

0000 PAL or NTSC 3 line comb

0001 NTSC 3 line comb (0H & 1H)

0010 NTSC 3 line comb (1H & 2H)

0011 NTSC 2 line comb (0H & 1H)

0100 NTSC (2 line) field comb

0101 NTSC or PAL field comb

0110 NTSC (2 line) frame comb

0111 NTSC frame comb

D1 comb ﬁlter architectures 1000 3 line comb 1001 3 line comb (0H & 1H) 1010 3 line comb (1H & 2H) 1011 3 line comb (0H & 2H) 1100 (2 line) field comb 1101 field or 2 line (0H & 1H) comb 1110 (2 line) frame comb 1111 frame comb

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 21 Control Register Deﬁnitions (continued) Comb Filter Control (0D) 76543210 CEST CESG YESG CESTBY XFEN FAST YWBY Reg Bit Name Description 0D 7-6 CEST Chroma error signal transform. 0D 5 CESG Chroma error signal gain. 0D 4 YESG Luma error signal gain. 0D 3 CESTBY Chroma error signal bypass. When HIGH, bypasses chroma error signal. 0D 2 XFEN XLUT filter enable. When HIGH, enables the LPF on the XLUT output. 0D 1 FAST Adaption speed select. When HIGH, the 3 line comb filter selects between comb filter architectures on a pixel by pixel basis. When LOW, the selection is filtered. 0D 0 YWBY Luma weighting bypass. When HIGH bypasses the luma fail weighting. CEST Video Standard Clock Rate (MHz) 00 PAL/NTSC 4*Fsc & 13.5MHz 01 NTSC 12.27MHz 10 PAL 14.75MHz

11 PAL 15MHz

0 Normal chroma fail signal levels

1 Double the chroma error signal levels

0 Normal luma fail signal levels

1 Double the luma error signal levels

TMC22x5yA PRODUCT SPECIFICATION 22 REV. 1.0.0 2/4/03 Control Register Deﬁnitions (continued) Comb Filter Control (0E) 76543210 XIP XSF YMUX CMUX Reg Bit Name Description 0E 7-6 XIP XLUT input select. Selects the comb fail signals presented to the XLUT: 0E 5-4 XSF XLUT special function. 0E 3-2 YMUX Y output select. Output selection of luma 4:1 mux 0E 1-0 CMUX C output select. Output selection of chroma 4:1 mux XIP[1:0] Input to XLUT 00 2 bits of phase error (X[7:6]), 3 bits of chroma (X[5:3]) and luma magnitude error (X[3:0]). 01 4 bits of chroma (X[7:4]) and luma magnitude error (X[3:0]). 10 3 bits of phase error (X[7:5]), 3 bits of chroma magnitude error (X[4:2]), and 2 bits of luma magnitude error (X[1:0]). 11 4 bits of phase error (X[7:4]) and chroma magnitude error (X[3:0]). XSF Luma Chroma

00 Comb Simple

01 Simple Comb

10 Flat with notch Simple

11 Flat with notch Comb

00 Comb

01 Flat - Comb

10 Flat

11 Simple

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 23 Control Register Deﬁnitions (continued) Comb Filter Control (0F) 76543210 Reserved CAT DCES IPCF YCCOMP SYNC Reg Bit Name Description 0F 7 Reserved Reserved, set to zero. 0F 6-5 CAT Adaption threshold. Fixes threshold at which different comb filters are selected. 0F 4 DCES D1 CB C R error signal. When set LOW for D1 chroma comb filters: a) In 3 line comb filter architectures, the magnitude error between the component data for that pixel selects the 3 line comb or adapts to a 2 line comb. On a “C B pixel” the error signal selected on pixel (x+4) is sent to the XLUT with the magnitude difference between “CR pixels” on the same pair of lines, but from pixel (x+3). Likewise on a “CR pixel” the error signal selected on pixel (x+5) is sent to the XLUT with the magnitude difference between “CB pixels” on the same lines but from pixel (x+4). b) In 2 line comb filters the magnitude differences between the same pair of lines is always sent to the XLUT, On a “CB pixel” the error from the preceding “CR pixel” is used and on a “CR pixel” the preceding “CB pixel” would be used. When set HIGH for D1 chroma filters: This is used for 3 line comb filter architecture that are inhibited from adapting to 2 line comb filter architectures. The input to the XLUT is the magnitude error in C R between (0H & 1H) and (1H & 2H) on “CR pixels” and the magnitude error between (0H & 1H) and (1H & 2H) on “CB pixels”. 0F 3-2 IPCF Comb filter input select. Selects primary inputs to the comb filter. 0F 1 YCCOMP YC or Composite input select. Selects YC inputs when HIGH and composite inputs when LOW. 0F 0 SYNC Sync processor select. The syncs are obtained by a LPF when HIGH and by the comb filter when LOW. Sync Pulse Generator (10) 76543210 STS7 STS6 STS5 STS4 STS3 STS2 STS1 STS0 Reg Bit Name Description 10 7-0 STS 7-0 Sync to sync 8 lsbs. Bottom 8 bits of the number of pixels between sync pulses. 5% of max error 15% of max error 25% of max error 50% of max error IPCF Function 0 0 0 1 1 0 1 1 Flat video LPF output HPF output Reserved

TMC22x5yA PRODUCT SPECIFICATION 24 REV. 1.0.0 2/4/03 Control Register Deﬁnitions (continued) Sync Pulse Generator (11) 76543210 STB Reg Bit Name Description 11 7-0 STB Sync to burst. Controls the number of pixels from sync to burst. This signal starts the burst sample and hold. In SC mode, subtract 25 from the desired delay to generate this value. Sync Pulse Generator (12) 76543210 BTV Reg Bit Name Description 12 7-0 BTV Burst to video. Controls the number of pixels from STB to the start of active video. Sync Pulse Generator (13) 76543210 AV7 AV6 AV5 AV4 AV3 AV2 AV1 AV0 Reg Bit Name Description 13 7-0 AV 7-0 Active video line 8 lsbs. Bottom 8 bits of the number of pixels during the active video line. Sync Pulse Generator (14) 76543210 Reserved AV 9 AV8 Reserved STS 10 STS9 STS8 Reg Bit Name Description 14 7-6 Reserved Reserved, set to zero. 14 5-4 AV 9-8 Active video line 2 msbs. Two most significant bits of AV. 14 3 Reserved Reserved, set to zero. 14 2-0 STS 10-8 Sync to sync 3 msbs. Three most significant bits of STS.

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 25 Control Register Deﬁnitions (continued) Sync Pulse Generator (15) 76543210 Reserved VINDO VDIV VDOV Reg Bit Name Description 15 7 Reserved Reserved, set to zero. 15 6-2 VINDO Number of lines in vertical window. The number of lines (0 to 31) after the last EQ pulse that the decoder passes through the Vertical INterval winDOw. 15 1 VDIV Action inside VINDO. The vertical data inside the \VINDO' is passed through a simple decoder when LOW, or is passed unprocessed on the luma channel with the chroma channel set to zero when HIGH. 15 0 VDOV Action outside VINDO. The vertical data after the \VINDO' and before the end of vertical blanking is blanked (YUV = 0) when LOW, or passed through the simple decoder when HIGH. Sync Pulse Generator (16) 76543210 Reserved NFDLY SPGIP MSIP Reg Bit Name Description 16 7-6 Reserved Reserved, set to zero. 16 5-4 NFDLY new field detect delay. NTSC frame detect delay: 16 3-2 SPGIP SPG input select. Selects the input to the Sync Pulse Generator: 16 1 MSIP Mixed sync separator input. Set HIGH for external VIDEOB reference or LOW for output of Low Pass Filter. 16 0 SMO State Machine Offset. Set HIGH for a 1H offset and LOW for a 0H offset. NFDLY Function 00 pixel count = 0 01 pixel count = 1 10 pixel count = 2 11 pixel count = 3 SPGIP Input

00 External HSYNC and VSYNC

01 Digitized sync (subcarrier mode)

10 TRS words embedded in the D1 data stream

11 TRS words embedded in the D2 data stream

TMC22x5yA PRODUCT SPECIFICATION 26 REV. 1.0.0 2/4/03 Control Register Deﬁnitions (continued) Buffered register set 0 (17) Active when BUFFER pin set LOW. 76543210 SG07 SG06 SG05 SG04 SG03 SG02 SG01 SG00 Reg Bit Name Description 17 7-0 SG0 7-0 Msync gain, 8 lsbs. Bottom 8 bits of mixed sync scalar lsb = 1/256 Buffered register set 0 (18) Active when BUFFER pin set LOW. 76543210 YG07 YG06 YG05 YG04 YG03 YG02 YG01 YG00 Reg Bit Name Description 18 7-0 YG0 7-0 Y gain, 8 lsbs. Bottom 8 bits of the luma gain lsb = 1/256 Buffered register set 0 (19) Active when BUFFER pin set LOW. 76543210 UG07 UG06 UG05 UG04 UG03 UG02 UG01 UG00 Reg Bit Name Description 19 7-0 UG0 7-0 U gain, 8 lsbs. Bottom 8 bits of the U gain lsb = 1/256 Buffered register set 0 (1A) Active when BUFFER pin set LOW. 76543210 VG07 VG06 VG05 VG04 VG03 VG02 VG01 VG00 Reg Bit Name Description 1A 7-0 VG0 7-0 V gain, 8 lsbs. Bottom 8 bits of the V gain lsb = 1/256 Buffered register set 0 (1B) Active when BUFFER pin set LOW. 76543210 YG09 YG08 UG010 UG09 UG08 Reserved VG0 9 VG08 Reg Bit Name Description 1B 7-6 YG0 9-8 Y gain, 2 msb. Top 2 bits of the Y gain. msb = 2 1B 5-3 UG0 10-8 U gain, 3 msbs. Top 3 bits of the U gain. msb = 4 1B 2 Reserved Reserved, set to zero. 1B 1-0 VG0 9-8 V gain, 2 msbs. Top 2 bits of the V gain. msb = 2

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 27 Control Register Deﬁnitions (continued) Buffered register set 0 (1C) Active when BUFFER pin set LOW. 76543210 YOFF07 YOFF06 YOFF05 YOFF04 YOFF03 YOFF02 YOFF01 YOFF00 Reg Bit Name Description 1C 7-0 YOFF0 7-0 Y offset, 8 lsbs. Bottom 8 bits of luma or RGB offset Buffered register set 0 (1D) Active when BUFFER pin set LOW. 76543210 Reserved YOFF0 8 SG09 SG08 Reg Bit Name Description 1D 7-3 Reserved Reserved, set to zero. 1D 2 YOFF0 8 Y offset, msb. msb of YOFF 1D 1-0 SG0 9-8 Msync gain, 2 msbs. Top 2 bits of mixed sync scalar. msb = 2 Buffered register set 0 (1E) Active when BUFFER pin set LOW. 76543210 SYSPH06 SYSPH05 SYSPH04 SYSPH03 SYSPH02 SYSPH01 SYSPH00 VAXIS0 Reg Bit Name Description 1E 7-1 SYSPH0 6-0 7 lsbs of phase offset. Bottom 7 bits of the 15 bit system phase offset 1E 0 VAXIS0 V axis flip. Flips the sign of the V axis when HIGH. Buffered register set 0 (1F) Active when BUFFER pin set LOW. 76543210 SYSPH014 SYSPH013 SYSPH012 SYSPH011 SYSPH010 SYSPH09 SYSPH08 SYSPH07 Reg Bit Name Description 1F 7-0 SYSPH0 14-7 8 msbs of phase offset. Top 8 bits of 15 bit system phase offset. Normalized Subcarrier Frequency (20) 76543210 FSC3 FSC2 FSC1 FSC0 Reserved Reg Bit Name Description 20 7-4 FSC 3-0 Bottom 4 bits of fsc. Bottom 4 bits of the 28 bit subcarrier SEED 20 3-0 Reserved Reserved, set to zero.

TMC22x5yA PRODUCT SPECIFICATION 28 REV. 1.0.0 2/4/03 Control Register Deﬁnitions (continued) Normalized Subcarrier Frequency (21) 76543210 FSC11 FSC10 FSC9 FSC8 FSC7 FSC6 FSC5 FSC4 Reg Bit Name Description 21 7-0 FSC 11-4 Lower 8 bits of fsc. Lower 8 bits of the 28 bit subcarrier SEED Normalized Subcarrier Frequency (22) 76543210 FSC19 FSC18 FSC17 FSC16 FSC15 FSC14 FSC13 FSC12 Reg Bit Name Description 22 7-0 FSC 19-12 Middle 8 bits of fsc. Middle 8 bits of the 28 bit subcarrier SEED Normalized Subcarrier Frequency (23) 76543210 FSC27 FSC26 FSC25 FSC24 FSC23 FSC22 FSC21 FSC20 Reg Bit Name Description 23 7-0 FSC 27-20 Top 8 bits of fsc. Top 8 bits of the 28 bit subcarrier SEED

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 29 Control Register Deﬁnitions (continued) Normalized Subcarrier Frequency (24) 76543210 CLMPEN PFLTEN CLPSEL 1-0 CLPBY CLPOF 2-0 Reg Bit Name Description 24 7 DREFSEL Decoder Reference Signal Select. When HIGH, enables a negative going clamp pulse on the DREF pin. The position of the clamp pulse is controlled by register 24. When LOW the DREF pin is HIGH during the active video portion of each line and LOW during the horizontal and vertical blanking intervals. 24 6 PFLTBY Phase error filter bypass. When HIGH, no filtering is done on the phase error signals for the comb filter adapter. When LOW, the filter is enabled. 24 5-4 CLPSEL 1-0 Internal black level clamp selection. 24 3 VCLPEN Vertical clamp filter enable. When LOW, vertical clamp filter is disabled. When HIGH, vertical clamp filter is enabled. 24 2-0 BAND 2-0 Clamp guard band. When an error value between two consecutive lines black level is less than the guard band, it does not effect the filtered black level. Normalized Subcarrier Frequency (25) 76543210 CPDLY7-0 Reg Bit Name Description 25 7-0 CPDLY 7-0 Clamp pulse delay. Controls the number of clock cycles from hsync before the 0.5 µSec clamp pulse is output to the AVOUT pin. This option is only enabled when register 24 bit 7 is set HIGH. CLMP[1:0] Function

00 Clamp disabled, black level set to 240

01 Clamp disabled, black level set to 256

10 Clamp enabled, use Delayed VIDEOB input as

11 Clamp enabled, use LPF as reference

BANDS[2:0] Function

000 No guard band

001 error value < 2 010 error value < 4 011 error value < 6 100 error value < 8 101 error value < 10 110 error value < 12 111 error value < 15

TMC22x5yA PRODUCT SPECIFICATION 30 REV. 1.0.0 2/4/03 Control Register Deﬁnitions (continued) Output Format Control (26) 76543210 Reserved LDVIO OPCKS DPCEN DPC Reg Bit Name Description 26 7-6 Reserved Reserved, set to zero. 26 5 LDVIO LDV clock select. LDV is an output when LOW and an input when HIGH 26 4 OPCKS Output clock select. The output data are clocked by the CLOCK pin when LOW and by the LDV pin when HIGH. 26 3 DPCEN DPC enable. When HIGH on the TMC22153A, the Decoder Product Code is enabled: a value written into DPC determines the decoder product emulated by the TMC22153A. In all other versions of the decoder, DPC is read-only, and returns the code of the particular encoder version installed. 26 2-0 DPC Decoder product code Read/Write in the TMC22153A only. Read-only in all other devices. Buffered register set 1 (27) Active when BUFFER pin set HIGH. 76543210 SG17 SG16 SG15 SG14 SG13 SG12 SG11 SG10 Reg Bit Name Description 27 7-0 SG1 7-0 Msync gain, 8 lsbs. Bottom 8 bits of the mixed sync scalar lsb = 1/256 Buffered register set 1 (28) Active when BUFFER pin set HIGH. 76543210 YG17 YG16 YG15 YG14 YG13 YG12 YG11 YG10 Reg Bit Name Description 28 7-0 YG1 7-0 Y gain, 8 lsbs. Bottom 8 bits of the luma gain lsb = 1/256 DPC Function

000 Reserved

001 TMC22051A

010 TMC22052A

011 TMC22053A

100 Reserved

101 TMC22151A

110 TMC22152A

111 TMC22153A

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 31 Control Register Deﬁnitions (continued) Buffered register set 1 (29) Active when BUFFER pin set HIGH. 76543210 UG17 UG16 UG15 UG14 UG13 UG12 UG11 UG10 Reg Bit Name Description 29 7-0 UG1 7-0 U gain, 8 lsbs. Bottom 8 bits of the U gain lsb = 1/256 Buffered register set 1 (2A) Active when BUFFER pin set HIGH. 76543210 VG17 VG16 VG15 VG14 VG13 VG12 VG11 VG10 Reg Bit Name Description 2A 7-0 VG1 7-0 V gain, 8 lsbs. Bottom 8 bits of the V gain lsb = 1/256 Buffered register set 1 (2B) Active when BUFFER pin set HIGH. 76543210 YG19 YG18 UG110 UG19 UG18 Reserved VG1 9 VG18 Reg Bit Name Description 2B 7-6 YG1 9-8 Y gain, 2 msbs. Top 2 bits of the Y gain msb = 2 2B 5-3 UG1 10-8 U gain, 3 msbs. Top 3 bits of the U gain. msb = 4 2B 2 Reserved reserved, set to zero 2B 1-0 VG1 9-8 V gain, 2 msbs. Top 2 bits of the V gain msb = 2 Buffered register set 1 (2C) Active when BUFFER pin set HIGH. 76543210 YOFF17 YOFF16 YOFF15 YOFF14 YOFF13 YOFF12 YOFF11 YOFF10 Reg Bit Name Description 2C 7-0 YOFF1 7-0 Y offset, 8 lsbs. Bottom 8 bits of luma or RGB offset

TMC22x5yA PRODUCT SPECIFICATION 32 REV. 1.0.0 2/4/03 Control Register Deﬁnitions (continued) Buffered register set 1 (2D) Active when BUFFER pin set HIGH. 76543210 Reserved YOFF1 8 SG19 SG18 Reg Bit Name Description 2D 7-3 Reserved Reserved, set to zero. 2D 2 YOFF1 8 Y offset, msb. msb of YOFF 2D 1-0 SG1 9,8 Msync gain, 2 msbs. Top 2 bits of mixed sync scalar msb = 2 Buffered register set 1 (2E) Active when BUFFER pin set HIGH. 76543210 SYSPH16 SYSPH15 SYSPH14 SYSPH13 SYSPH12 SYSPH11 SYSPH10 VAXISO Reg Bit Name Description 2E 7-1 SYSPH1 6-0 7 lsbs of phase offset. Bottom 7 bits of the 15 bit system phase offset 2E 0 VAXIS1 V axis flip. Flips the sign of the V axis when HIGH. Buffered register set 1 (2F) Active when BUFFER pin set HIGH. 76543210 SYSPH114 SYSPH113 SYSPH112 SYSPH111 SYSPH110 SYSPH19 SYSPH18 SYSPH17 Reg Bit Name Description 2F 7-0 SYSPH1 14-7 8 msbs of phase offset. Top 8 bits of 15 bit system phase offset.

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 33 Control Register Deﬁnitions (continued) Video Measurement (30) 76543210 Reserved LGF LGEN LGEXT RESERVED PGG PGEN PGEXT Reg Bit Name Description 30 7 Reserved Reserved, set to zero. 30 6 LGF Line grab flag. Set HIGH when the decoder has grabbed a line, and must be reset LOW before another line can be grabbed. 30 5 LGEN Line grab enable. When HIGH, the line grabber is used to freeze the contents of the line store, at the programmed line and field count. The phase and frequency of the frozen line are also stored from the DRS, and are continually used to reset the DDS, once per line, until LGF is set LOW. When LGEN is LOW, the line freeze is disabled, the internal loops operate normally, and the line grab signal is used only to gate the pixel grab. 30 4 LGEXT Ext line grab enable. The SET pin is used to produce the line grabber pulse when HIGH and the internal line decode is used when LGEXT is LOW. 30 3 Reserved Reserved, set to zero. 30 2 PGG Pixel grab gate. When HIGH the pixel grab is gated by the field and line grab signals to enable one pixel per four fields in NTSC and 8 field in PAL to be grabbed. This function is disabled if PGEN is set LOW. 30 1 PGEN Pixel grab enable. When HIGH the 10 bit G/Y, B/U, and R/V data, and the mixed sync and luma data after the comb filter, and the demodulated (B-Y) and (R-Y) color difference signals are grabbed once every line at the programmed pixel grab number. When LOW the contents of the pixel grab registers are held and the pixel grab pulse is ignored. 30 0 PGEXT Ext pixel grab enable. The SET pin is used to produce the pixel grab pulse when HIGH and the internal pixel decode is used when PGEXT is LOW. Video Measurement (31) 76543210 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 Reg Bit Name Description 31 7-0 PG 7-0 Pixel grab, 8 lsbs. Bottom 8 bits of the pixel grab. Video Measurement (32) 76543210 LG7 LG6 LG5 LG4 LG3 LG2 LG1 LG0 Reg Bit Name Description 32 7-0 LG 7-0 Line grab, 8 lsbs. Bottom 8 bits of the line grab.

TMC22x5yA PRODUCT SPECIFICATION 34 REV. 1.0.0 2/4/03 Control Register Deﬁnitions (continued) Registers 34-3C are Read-Only Video Measurement (33) 76543210 Reserved FG LG 8 PG10 PG9 PG8 Reg Bit Name Description 33 7 Reserved Reserved. 33 6-4 FG Field grab number. Field grab number 33 3 LG 8 Msb of line grab. msb of line grab 33 2-0 PG 10-8 Pixel grab, 3 msbs. 3 msbs of pixel grab Register (34) 76543210 GY9 GY8 GY7 GY6 GY5 GY4 GY3 GY2 Reg Bit Name Description 34 7-0 GY 9-2 G/Y grab, 8 msbs. Top 8 bits of the "grabbed" G/Y data Register (35) 76543210 BU9 BU8 BU7 BU6 BU5 BU4 BU3 BU2 Reg Bit Name Description 35 7-0 BU 9-2 B/U grab, 8 msbs. Top 8 bits of the "grabbed" B/U data Register (36) 76543210 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 Reg Bit Name Description 36 7-0 RV 9-2 R/V grab, 8 msbs. Top 8 bits of the "grabbed" R/V data Register (37) 76543210 Reserved GY 1 GY0 BU1 BU0 RV1 RV0 Reg Bit Name Description 37 7-6 Reserved Reserved. 37 5-4 GY 1-0 G/Y grab, 2 lsbs. Bottom two bits of G/Y data 37 3-2 BU 1-0 B/U grab, 2 lsbs. Bottom two bits of B/U data 37 1-0 RV 1-0 R/V grab, 2 lsbs. Bottom two bits of R/V data

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 35 Control Register Deﬁnitions (continued) Register (38) 76543210 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Reg Bit Name Description 38 7-0 Y 9-2 Luma grab, 8 msbs. Top 8 bits of the "grabbed" luma data after YPROC Register (39) 76543210 M9 M8 M7 M6 M5 M4 M3 M2 Reg Bit Name Description 39 7-0 M 9-2 Msync grab, 8 msbs. Top 8 bits of the "grabbed" mixed sync data after YPROC Register (3A) 76543210 U9 U8 U7 U6 U5 U4 U3 U2 Reg Bit Name Description 3A 7-0 U 9-2 U grab, 8 msbs. Top 8 bits of the "grabbed" U data Register (3B) 76543210 V9 V8 V7 V6 V5 V4 V3 V2 Reg Bit Name Description 3B 7-0 V 9-2 V grab, 8 msbs. Top 8 bits of the "grabbed" V data Register (3C) 76543210 Y1 Y0 M1 M0 U1 U0 V1 V0 Reg Bit Name Description 3C 7-6 Y 1-0 Luma grab, 2 lsbs. Bottom 2 bits of luma data 3C 5-4 M 1-0 Msync grab, 2 lsbs. Bottom 2 bits of mixed sync data 3C 3-2 U 1-0 U grab, 2 lsbs. Bottom 2 bits of U data 3C 1-0 V 1-0 V grab, 2 lsbs. Bottom 2 bits of V data

TMC22x5yA PRODUCT SPECIFICATION 36 REV. 1.0.0 2/4/03 Control Register Deﬁnitions (continued) Test Control (3D-3E) 76543210 TEST Reg Bit Name Description 3D-3E 7-0 TEST Must be set to zero. Auto increment stops at 3F Test Control (3F) 76543210 VBIT20 PEDDIS CCDEN 5 CCDEN 4 CCDEN 3 CCDEN 2 CCDEN 1 CCDEN 0 Reg Bit Name Description 3F 7 VBIT20 VBIT20 enable. When HIGH the V bit within embedded TRS words is extended through line 20 for NTSC. When LOW, this V bit is HIGH up to line 16 for NTSC. The PAL operation is unaffected by this register bit. 3F 6 PEDDIS Pedestal disable. When HIGH, pedestal is not removed from lines with LID = 00 to 06, lines 0 through 16 3F 5 CCDEN 5 Closed caption data enable 5. When HIGH, enables NTSC line 21 field 0 or PAL line 22 field 0 to be passed ‘FLAT’, through the decoder, on the luminance channel and the pedestal removal will be disabled. 3F 4 CCDEN 4 Closed caption data enable 4. When HIGH, enables NTSC line 22 field 0 or PAL line 23 field 0 to be passed ‘FLAT’, through the decoder, on the luminance channel and the pedestal removal will be disabled. 3F 3 CCDEN 3 Closed caption data enable 3. When HIGH, enables NTSC line 23 field 0 or PAL line 24 field 0 to be passed ‘FLAT’, through the decoder, on the luminance channel and the pedestal removal will be disabled. 3F 2 CCDEN 2 Closed caption data enable 2. When HIGH, enables NTSC line 283 field 1 or PAL line 334 field 1 to be passed ‘FLAT’, through the decoder, on the luminance channel and the pedestal removal will be disabled. 3F 1 CCDEN 1 Closed caption data enable 1. When HIGH, enables NTSC line 284 field 1 or PAL line 335 field 1 to be passed ‘FLAT’, through the decoder, on the luminance channel and the pedestal removal will be disabled. 3F 0 CCDEN 0 Closed caption data enable 0. When HIGH, enables NTSC line 285 field 1 or PAL line 336 field 1 to be passed ‘FLAT’, through the decoder, on the luminance channel and the pedestal removal will be disabled. Status - Read Only (40) 76543210 DDSPH Reg Bit Name Description 40 7-0 DDSPH DDS phase, 8 msbs. The top 8 bits of the sine data generated in the internal DDS.

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 37 Control Register Deﬁnitions (continued) Status - Read Only (41) 76543210 LINEST BGST VACT2 PALODD VFLY FGRAB LGRAB PGRAB Reg Bit Name Description 41 7 LINEST Pixel count reset. Pixel count reset 41 6 BGST Start of burst gate. Start of burst gate 41 5 VACT2 Half line flag. Half line flag 41 4 PALODD PAL Ident. PAL Ident (low on NTSC lines) 41 3 VFLY Vertical count reset. Vertical count reset 41 2 FGRAB Field grab. Field grab 41 1 LGRAB Line grab. Line grab 41 0 PGRAB Pixel grab. Pixel grab Status - Read Only (42) 76543210 FLD VBLK HBLK LID Reg Bit Name Description 42 7 FLD Field ﬂag (F in D1 output). Field flag (F in D1 output) 42 6 VBLK Vertical blanking (V in D1 output). Vertical blanking (V in D1 output) 42 5 HBLK Horizontal blanking (H in D1 output). Horizontal blanking (H in D1 output) 42 4-0 LID Line identification. Line identification Status - Read Only (43) 76543210 YGO YGU UBO UBU VRO VRU Reserved Reg Bit Name Description 43 7 YGO Y/G overflow. Y/G overflow 43 6 YGU Y/G underflow. Y/G underflow 43 5 UBO C B /B overflow. C B/B overflow 43 4 UBU C B /B underflow. C B/B underflow 43 3 VRO C R /R overflow. C R /R overflow 43 2 VRU C R /R underflow. C R /R underflow 43 1-0 Reserved Reserved.

TMC22x5yA PRODUCT SPECIFICATION 38 REV. 1.0.0 2/4/03 Control Register Deﬁnitions (continued) Status - Read Only (44) 76543210 MONO FPERR Reg Bit Name Description 44 7 MONO Color kill flag. High when burst detected and LOW when monochrome signal is detected. 44 6-0 FPERR Frequency/Phase error. Top 7 bits of the modulo two pi frequency or phase error. Reported once per line. Status - Read Only (45) 76543210 DRS Reg Bit Name Description 45 7-0 DRS DRS signal. The 8-bit Decoder Reference Signal. Status - Read Only (46) 76543210 PARTID Reg Bit Name Description 46 7-0 PARTID Part family ID. Reads back the 8-bit part ID number. Read-only. Returns CDh. Status - Read Only (47) 76543210 REVID Reg Bit Name Description 47 7-0 REVID Recoder revision number. REVID TMC22x5y Revision TMC22x5yA Revision 05 F 06 G 10 A 11 B

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 39 Control Register Deﬁnitions (continued) Status - Read Only (48-4A) 76543210 Reserved Status - Read Only (4B) 76543210 PKILL CFSTAT XOP Reg Bit Name Description 4B 7 PKILL Phase kill from comb fail. Phase kill from comb fail. 4B 6-5 CFSTAT Comb ﬁlter status. Comb filter status. 4B 4-0 XOP XLUT output. XLUT output. Status - Read Only (4C-FF) 76543210 Reserved Reg Bit Name Description 4C-FF 7-0 Reserved Reserved. CFSTAT STATUS 00 3 tap comb 01 3 tap [lower] comb 10 3-tap [upper] comb 11 2 tap comb

original composite video frequency spectrum. the high frequency luminance from the chrominance signal.

The FLAT signal is simply a delayed version of the input

will always be equal to the FLAT video input. The TMC22x53A comb ﬁlter architecture has three taps. architectures the pipeline latency is 40 pixels. Figure 10. TMC22x5yA Line Based Comb Filter Architecture

Table 2. Normalized Subcarrier Frequency as a Function of Pixel Data Rates Figure 13. Bandsplit Filter, Full Frequency Response Figure 14. Bandsplit Filter, Passband Response

Figure 15. Block Diagram of Comb Filter Input dependent upon the type of comb ﬁlter being implemented. determined by the SPLIT register bit.

vertically ﬁltered by a ﬁxed 3 line comb ﬁlter. selected 0HL and 0HH are selected. the comb ﬁlter to produce the COMB output. selected as the primary signal. Figure 16. Signal Flow Around the Adaptive Comb Filter.

register bits as shown in Table 3. Table 3. Comb Filter Architecture sent to the XLUT input logic. register bits accordingly, see Table 5.

0 YC or Composite, PAL or NTSC, 3 line

1 YC or Composite, NTSC, 3 line comb (0H

2 YC or Composite, NTSC, 3 line comb (1H

3 YC or Composite, NTSC, 2 line comb (0H

4 YC or Composite, NTSC, (2 line) field

5 YC or Composite, NTSC or PAL, field

6 YC or Composite, NTSC, (2 line) frame

7 YC or Composite, NTSC, frame comb

8 D1, Y or C

9 D1, Y or C BC R , 3 line comb (0H & 1H)

10 D1, Y or C BC R , 3 line comb (1H & 2H)

11 D1, Y or C BC R , 3 line comb (0H & 2H)

12 D1, Y or C BC R , (2 line) field comb

13 D1, Y or C BC R , field or 2 line comb

14 D1, Y or C BC R , (2 line) frame comb

15 D1, Y or C BC R , Frame

Table 4. Simple Example of an Adaptive Comb Filter Architecture

fade between the YCOMB and the SIMPLE bandsplit signals. tinuities that would cause the comb ﬁlter operation to fail. an adaptive comb ﬁlter architecture. comb fails in the comb ﬁlter output. ﬁlter response to their system requirements. Figure 17. Example of a Comb Fail Using a NSTC Two Line Comb Filter

lines, the error signal will go to its maximum value. tains all the high frequency luminance information as well. immaterial and was used only to rectify the chroma signal. signals, to fool the comb fail circuit. signals are limited to ensure no overﬂow occurs. ing the appropriate default using the CEST[1:0] register bits. Figure 18. Generation of Upper and Lower Comb Fail Signals

PAL comb ﬁlter architectures. register bits to a higher percentage threshold. register bits are ignored, and no adaption is implemented. Table 5. Adaption Modes

00 Adapts to the best of 3 types of line

based comb filters in NTSC only. XLUT. NTSC or PAL comb filter.

11 Adapts to best of two 3 line comb filters

Figure 19. Comb Filter Selection

the XLUT input address X[7:0] is also shown. between the weighted comb ﬁlter and the band split ﬁlters. fade to produce a 0 to 32 control signal, as shown in Table 7. the XSF[1:0] register bits, as shown in Table 8. Table 8. XLUT Special Function Definitions ﬁlter, centered at 0.25 of the normalized clock frequency. frequency is adequate for application. externally monitored by reading XOP[4:0] in register 4Bh. Table 6. XLUT Input Selection bits of luma magnitude error (X[1:0]). Table 7. XLUT Output Function. Table 7. XLUT Output Function. (cont.) Figure 20. XLUT Input Selection

nance data, producing the U and V color-difference signals. filter to remove signals at twice the subcarrier frequency. and cosine signals in ROM-based lookup tables. color kill circuit becomes active during the next ﬁeld group. will be set to chroma black. during the next vertical blanking period, the decoder is reset. frame and color frame ﬂags in the FID generator. Table 9. PAL-B,G,H,I Bruch Blanking Sequence

5 No 0 or 2 0 or 4

309 No 0 or 2 0 or 4

6 Y es 0 or 2 1 or 5

309 No 0 or 2 1 or 5

5 Y es 1 or 3 2 or 6

309 Y es 1 or 3 2 or 6

6 No 1 or 3 3 or 7

309 Y es 1 or 3 3 or 7

Figure 21. Block Diagram of Digital Burst Locked Loop

Table 10. PAL-M Bruch Blanking Sequence The PAL color frame bit is the msb of the field count, FID2. given pixel and on a given line. added to the subcarrier oscillator between SAV and EAV. without affecting the burst locked loop. register that can be accessed over the microprocessor port. Figure 22. Gaussian Low Pass Filters Figure 23. Gaussian LPF Passband Detail is controlled by the DMODBY register bit. bypass operation is controlled by the GAUBY register bit. chroma channel (below a programmable threshold) to zero.

7 No 0 or 2 0 or 4

258 Y es 0 or 2 0 or 4

7 No 0 or 2 1 or 5

259 No 0 or 2 1 or 5

7 Y es 1 or 3 2 or 6

258 No 1 or 3 2 or 6

7 Y es 1 or 3 3 or 7

259 Y es 1 or 3 3 or 7

Figure 24. Output Processor Block Diagram Table 11. Blanking Level Selection The blanking level is subtracted from the decoded luma. to the pedestal removal circuit. ated on the back porch or duing the sync tip of a video line. which can produce a visible dot crawl on ﬂat areas of color. Table 12. Adaptive Notch Threshold Control

00 Internal 240 level

01 Internal 256 level

10 External VIDEOB Input

11 Internal LPF Output

Table 13. Matrix Limiters deliberately by using a slightly larger gain than is required. one lsb less than the minimum clip level. bits of registers 17 to 1A and 27 to 2A are forced to zero.

00 RGB output format, limited from 0 to 1023

1023 and CBC R limited to +/- 511.

10 RGB output format, limited from 64 to 940

unaffected by the luma data. inserted into the green data path only. inserted into the luminance data path only. 0.25 of the normalized sample frequency. 27MHz (PXCK) data stream with embedded TRS words. zero, by setting the V_scalar to zero. mode, the output data still needs to be at the PCK clock rate. then the LDV pin becomes an input for an external clock. clocked by the internal or external clock on the LDV pin. Table 14. Output Format

Table 15. NTSC Field and Line Numbering Table 16. PAL B,G,H,I Field and Line Numbering Table 17. PAL M Field and Line Numbering from the falling edge of sync to the burst envelope. d) To remove the syncs on the BLUE and RED outputs. PAL M on line 259 when VACT2 is HIGH and FLD is LOW. The FLD is LOW for field 1 and HIGH for field 2. ating the vertical blanking and burst blanking periods. VACT2 is HIGH during the second half of all active lines. not inhibit the GRABS signal on each line. held HIGH to not inhibit the GRABS signal on each line. is LOW. When GCR 2 is HIGH these signals are three stated.

Signal is available over the microprocessor data bus.

the output of the LSTORE1, i.e. 1HFLAT. the duration of the DHSYNC signal is 64 clock periods. and vertical state machines. Table 18. Vertical Blanking Period Table 19. Vertical Burst Blanking Period ** Signal is available over the microprocessor data bus. Table 20. Table of Line Idents, LID[4:0]

modiﬁed depending upon the mode of operation. Table 21. Timing Offsets burst gate and the nominal start of active video. A V: The number of active pixels in the active video line. tracted from STS provides the nominal front porch. internal state machines to beginning of a ﬁeld (3, 5, or 7). ber of pixels in an active video line. Table 20. Table of Line Idents, LID[4:0] (cont.) Figure 27. Horizontal Timing

Figure 30. PAL-B,G,H,I,N Vertical Interval

Figure 31. PAL-M Vertical Interval

•• 81 6 17 18 258257 259 FIELDS 3 AND 7 -VVUVV -VE EE EE ES SS SS SE EE EE EB UBB UBB UBB UVV UVV 2 6 0 2 6 1 0123456 7 •••
•• 81 6 17 18 258 259 FIELDS 1 AND 5 UVV UVV EE EE EE SS SS SS EE EE EE -BB UBB-BB UBB UVV 2 6 0 2 6 1 2 6 2 012345 678 •••
•• HSYNC HSYNC HSYNC HSYNC VSYNC VSYNC VSYNC VSYNC FLD FLD FLD FLD 258 259 FIELDS 3 AND 7 UVV -VV EE EE EE SS SS SS EE EE EE -BB UBBUBB UBB UVV 2 6 0 2 6 1 2 6 2 012345 678 •••
••

Table 22. PAL VINDO operation PGEN, and PGEXT register bits. any chrominance gain errors in the output matrix. Figure 32. Pixel Grab Locations

Table 23. Pixel Grab Control number equals the programmed ﬁeld count. the bottom 9 bits provide the offset within that quadrant. provides the 0,1,2, or 3 count offset for the last quadrant. pixel in excess of 4*Int(STS/4) is added to 1536. Figure 33. Relationship Between Pixel Count and Pixel Grab Value

NTSC std with STS programmed to 858.

Required pixel 0 < 214 therefore quadrant = 0,
Required pixel 56 < 214 therefore quadrant = 0
Required pixel 250 > 214 therefore quadrant =/= 0
Required pixel 250 < 428 therefore quadrant = 1,
Required pixel 800 > 214 therefore quadrant =/= 0
Required pixel 800 > 428 therefore quadrant =/= 1
Required pixel 800 > 642 therefore quadrant =/= 2
Required pixel 800 < 858 therefore quadrant = 3,
Required pixel 856 > 214 therefore quadrant =/= 0
Required pixel 856 > 428 therefore quadrant =/= 1
Required pixel 856 > 642 therefore quadrant =/= 2
Required pixel 856 < 858 therefore quadrant = 3,
Therefore quadrant = 3, [PG[10:9] = 11]

NTSC or 8 ﬁeld sequence in PAL when LGEN is set HIGH. 2-0 = 110 and LGEXT is set HIGH. DRS SEED and PHASE values at the beginning of each line. input or ﬂywheel if the input has been removed. frozen line to examine individual pixels inside the decoder. will not increment and remain at its maximum value of 3Fh. Table 24. Parallel Port Control

Table 25. Serial Port Addresses that is, bit 7 of the 8-bit sequence. HIGH so the master can generate a stop signal. est be written after the slave address has been established. higher than 3Fh will not produce an ACKnowledge signal.

Start signal
Slave Address byte (R/W bit = LOW)
Block Pointer (00)
Base Address byte
Data byte to base address
Stop signal Write to four consecutive XLUT locations
Start signal
Slave Address byte (R/W bit = LOW)
Block Pointer (01)
Base Address byte
Data byte to base address
Data byte to (base address + 1)
Data byte to (base address + 2)
Data byte to (base address + 3)
Stop signal Read from one XLUT location
Start signal
Slave Address byte (R/W bit = LOW)

Figure 35. Serial Port Read/Write Timing

Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating

only if Operating Conditions are not exceeded.

Applied voltage must be current limited to specified range.
Forcing voltage must be limited to specified range.
Current is specified as conventional current flowing into the device.

Figure 41. Input Timing Parameters

TMC22x5yA output clock, the following block diagram of the TMC22x5yA output stage is provided. Figure 42. Functional Block Diagram of the TMC22x5yA G/Y, B/U, and R/V Output Stage

Figure 43. Output Timing Parameters

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 75 Operating Conditions (continued)

Electrical Characteristics

Notes: 1. Typical IDD with VDD = NOM and TA = NOM, Maximum IDD with VDD = 5.25V and TA = 70°C 2. G/Y[9:0], B/Y[9:0], R/V[9:0] , DVSYNC , DHSYNC , LDV, AVOUT, FID[2:0] Parameter Min. Nom. Max. Units Parallel Microprocessor Interface t PWLCS CS Pulse Width, LOW 2 Pixels tPWHCS CS Pulse Width, HIGH 3 Pixels tSA Address Setup Time 8 ns tHA Address Hold Time 2 ns tSD Data Setup Time (write) 8 ns tHD Data Hold Time (write) 2 ns Serial Microprocessor Interface tDAL SCL Pulse Width , LOW 1.0 µs tDAH SCL Pulse Width, HIGH 0.48 µs tSTAH Hold Time for START or Repeated START 0.48 µs tSTASU Setup Time for START or Repeated START 0.48 µs tSTOSU Setup time for STOP 0.48 µs tBUFF Bus Free Time Betweeen a STOP and a START condition 1.0 µs tDSU Data Setup Time 80 ns Parameter Conditions Min. Typ. Max. Units IDD Power Supply Current1 VDD = Max, fPXCK = 27MHz 225 275 mA IDDQ Power Supply Current, Disabled V DD = Max 50 mA IIH Input Current, HIGH V DD = Max, VIN = VDD ±10 µA IIL Input Current, LOW V DD = Max, VIN = 0V ±10 µA IOZH Hi-Z Output Leakage Current, Output HIGH VDD = Max, VIN = VDD ±10 µA IOZL Hi-Z Output Leakage Current, Output LOW VDD = Max, VIN = 0V ±10 µA IOS Short-Circuit Current -20 -80 mA VOH Output Voltage, HIGH G/Y 9-0, etc2., IOH = MAX 2.4 V VOL Output Voltage, LOW G/Y 9-0, etc2., IOL = MAX 0.4 V SDA, IOL = 3mA 0.4 V SDA, IOL = 6mA 0.6 V C I Digital Input Capacitance 4 10 pF C O Digital Output Capacitance 10 pF

TMC22x5yA PRODUCT SPECIFICATION 76 REV. 1.0.0 2/4/03 Switching Characteristics Note: Timing reference points are at the 50% level, digital output load <40pF. System Performance Characteristics Parameter Conditions Min. Typ. Max. Units tDOZ Output Delay, CS to low-Z 9 ns tHOM Output Hold Time, CS to high-Z 10 ns tDOM Output Delay, CS to Data Valid 30 40 ns Parameter Conditions Min. Typ. Max. Units RES Video Processing Resolution TMC2205xA 8 bits TMC2215xA 10 bits

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 77 Programming Examples Standard: NTSC-M Mode: Line-Locked Input Format: 13.5 Composite Output Format: RGB (0-1023) Sync on Green Decoder: Adaptive 3-Line Chroma Comb Filter Register Map: Standard: NTSC Mode: Line-Locked Input Format: NTSC Composite Output Format: D1 Component Decoder: 3 Line Adaptive Chroma Comb Register Map:

0123456789 ABCDEF

0 D8 01 00 A1 20 28 00 10 40 00 12 00 00 04 24 09

1 5A 56 2E D2 23 00 00 2C 1B 90 13 49 F0 01 00 00 2 40 F8 E0 43 00 00 07 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0 C0 01 00 A1 20 28 00 10 40 00 34 74 80 04 64 08

1 5A 56 2E D2 23 72 00 00 95 0E 51 49 40 00 00 00 2 40 F8 E0 43 24 25 07 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

TMC22x5yA PRODUCT SPECIFICATION 78 REV. 1.0.0 2/4/03 Programming Examples (continued) Standard: NTSC Mode: Line-Locked Input Format: 13.5 MHz Composite Video Output Format: YUV Decoder: Adaptive 3-Line Comb Register Map: Standard: PAL Mode: Line-Locked Input Format: Composite Output Format: YUV Decoder: Adaptive 3-Line Comb Register Map:

0 D8 01 00 A1 20 28 00 10 40 00 34 00 80 04 64 08

1 5A 56 2E D2 23 3C 00 2C 1B 90 13 49 F0 01 00 00 2 40 F8 E0 43 24 25 07 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0 DB 01 00 24 08 00 24 15 40 08 36 00 C0 04 54 09

1 60 53 32 CE 23 01 00 00 00 3E 03 49 00 05 00 00 2 90 15 13 54 24 25 07 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 79 Programming Examples (continued) Standard: PAL Mode: Line-Locked Input Format: PAL-YC Output Format: Y , Cb, Cr (D1 Out) Decoder: Register Map: No Comb Standard: NTSC-M Mode: D1 Mode Input Format: D1, CB YC R [Y] multiplexed data w/embedded TRS words Output Format: D1 Output Decoder: 2 Line Chroma comb of CB C R data Register Map:

0 D3 07 00 00 20 00 00 0C 40 08 24 60 03 00 0B 0A

1 60 53 44 D2 23 00 00 00 88 BF 3C 49 40 00 00 00 2 90 15 13 54 00 00 00 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0 C0 1F 37 E3 20 00 00 0C 40 40 34 60 09 04 F8 02

1 5A 47 35 D2 23 00 0A 00 00 00 00 49 40 00 00 00 2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

TMC22x5yA PRODUCT SPECIFICATION 80 REV. 1.0.0 2/4/03 Programming Examples (continued) Standard: NTSC-M Mode: D1 Mode Input Format: D1, CB YC R [Y] Multiplexed Data w/TRS Output Format: YC B C R , Output DHSync + DVSync Decoder: Simple Transcoder Register Map: Standard: NTSC-M Mode: D1 Mode Input Format: YC B C R Output Format: D1, CB YC R [Y] Multiplexed Data with TRS Decoder: Simple Transcoder Register Map:

0 C0 1F 37 E3 20 00 00 0C 40 40 34 00 09 04 0A 02

1 5A 47 35 D2 23 00 0A 00 00 00 00 49 40 00 00 00 2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0 C0 0F 07 A3 20 00 00 0C 40 00 34 60 09 04 0A 02

1 5A 47 35 D2 23 00 00 00 00 00 00 49 40 00 00 00 2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 81 Programming Worksheet Standard: Mode: Input Format: Output Format: Decoder: Register Map: The DRS appears on the output at the rate. 2 xx xx xx xx xx xx xx xx xx -70 -60 -50 -40 -30 -20 -10 0.00 0.10 0.20 0.30 0.40 0.50 Normalized Frequency Attenuation (dB) 65-22x5y-40 Bandsplit Filter 1 Bandsplit Filter 2 Bandsplit Filter -70 -60 -50 -40 -30 -20 -10 0.00 0.10 0.20 0.30 0.40 0.50 Normalized Frequency Attenuation (dB) 65-22x5y-41 Demodulator Filter 1 Demodulator Filter 2 Demodulation Filter -70 -60 -50 -40 -30 -20 -10 0.00 0.10 0.20 0.30 0.40 0.50 Normalized Frequency Attenuation (dB) 65-22x5y-42 Adaptive Notch Filter 1 Adaptive Notch Filter 2 Adaptive Notch Filter 3 Adaptive Notch Filter -70 -60 -50 -40 -30 -20 -10 0.00 0.10 0.20 0.30 0.40 0.50 Normalized Frequency Attenuation (dB) 65-22x5y-43 Non-Adaptive Notch Filter

TMC22x5yA PRODUCT SPECIFICATION 82 REV. 1.0.0 2/4/03 Notes

PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 83 Mechanical Dimensions – 100 Lead MQFP Package Lead Detail AA 2 B -C- Lead Coplanarity Seating Plane ccc C See Lead Detail E D B e Base Plane R C L α Datum Plane 0° Min. .20 (.008) Min. .13 (.30) .005 (.012) .13 (.005) R Min. 0.063" Ref (1.60mm) A — .134 — 3.40 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .010 — .25 — .015 .38 A2 .100 .120 2.55 3.05 B .009 3, 5 .23 .009 .23C .005 .13 E .667 .687 16.95 17.45 .0256 BSC .65 BSCe L .025 .037 .65 .95 100 100 30 30 N ND 20 20NE α 0° 7° 0° 7° — .004 — .10ccc D .904 .923 22.95 23.45 D1 .783 .791 19.90 20.10 E1 .547 .555 13.90 14.10 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982. Controlling dimension is millimeters. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. "L" is the length of terminal for soldering to a substrate. "B" & "C" includes lead finish thickness.

TMC22x5yA PRODUCT SPECIFICATION 2/4/03 0.0m 001 Stock#DS7022x5yA

Ordering Information

Rang e Decoding Resolution Package Package Marking TMC22051AKHC 0°C to 70°C Simple 8 bit 100-Lead MQFP 22051AKHC TMC22052AKHC 0°C to 70°C 2-Line Comb 8 bit 100-Lead MQFP 22052AKHC TMC22053AKHC 0°C to 70°C 3-Line Comb 8 bit 100-Lead MQFP 22053AKHC TMC22151AKHC 0°C to 70°C Simple 10 bit 100-Lead MQFP 22151AKHC TMC22152AKHC 0°C to 70°C 2-Line Comb 10 bit 100-Lead MQFP 22152AKHC TMC22153AKHC 0°C to 70°C 3-Line Comb 10 bit 100-Lead MQFP 22153AKHC

Product Information

TMC22152AKHC specifications and overview.

Summary

Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit

Description

The TMC22x5yA family of Digital Video Decoders offers unprecedented, broadcast-quality video processing performance in a single chip. It accepts line-locked or subcarrier locked composite, YC, or D1 digital video and produces digital components in a variety of formats.

Source title TMC22152AKHC Datasheet(PDF) - Cadeka Microcircuits LLC.

Related Parts

More parts from the same family.

Browse manufacturer