TMC22091

TMC22091 CADEKA | Alldatasheet

Document overview

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Technical content

Features

• All-digital video encoding
• Internal digital oscillators, no crystals required
• Multiple input formats supported – 24-bit and 15-bit GBR/RGB –Y C B C R 422 or 444 – Color indexed
• 30 overlay colors (TMC22191)
• Fully programmable timing
• Supports input pixel rates of 10 to 15 Mpps
• 256 x 8 x 3 color look-up tables (bypassable on TMC22191)
• 8-bit mask register
• 8-bit composite digital video input
• Hardw are and 24-bit data keying
• Synchronizes with TMC22071 Genlocking V ideo Digitizer
• 8:8:8 video reconstruction
• SMPTE 170M NTSC or CCIR Report 624 PAL compatible
• Supports PAL-M and NTSC without pedestal
• Simultaneous S-VIDEO (Y/C) NTSC/PAL output
• 10-bit D/A conversion (three channels)
• Controlled edge rates
• 3 power-down modes
• Built-in color bars and modulated ramp test signals
• JTA G (IEEE Std 1149.1-1990) test interface
• Single +5V power supply
• 84 lead PLCC package
• 100 lead MQFP package

Description

The TMC22x91 digital video encoders convert digital com- puter image or graphics data (in RGB, YCBCR, or color indexed format) or a CCIR-601 signal into a standard analog baseband television (NTSC or PAL) signal with a modulated color subcarrier. Both composite (single lead) and S-VIDEO (separate chroma and luma) formats are active simultaneously at the three analog output pins, each of which generates a standard video-level signal into doubly-terminated 75W load. The TMC22x91 accepts digitized video from the companion TMC22071 Genlocking V ideo Digitizer. Soft switching between video sources is done under either hardware or programmable data control. The TMC22191 of fers 4-layer keying capability, bypassable CLUT , and 30 Overlay colors. The TMC22x91 is fabricated in a submicron CMOS process and packaged in an 84 Lead Plastic Leadless Chip Carrier, or in a 100 Lead Metric Quad Flat Pack. Performance is guar- anteed from 0°C to 70°C. Logic Symbol PD 23-0 PDC CHROMA LUNA COMPOSITE FRAME BUFFER INTERFACE GENLOCK INTERFACE MICROPROCESSOR INTERFACE VIDEO OUTPUT VHSYNC VVSYNC GHSYNC GVSYNC CS R/W KEY TDI TMS TCK JTAG TEST INTERFACE LDV PXCK CLOCKS TDO VREF COMP R REF ANALOG INTERFACE BYPASS RESET 27008A TMC22x91 DIGITAL VIDEO ENCODER CVBS 7-0 D 7-0 A1-0 OL 4-0 BYPASS and OL 4:0 on TMC22191 only. TMC22091/TMC22191 Digital Video Encoders/Layering Engine Rev. 1.1.0 www .cadeka.com

BYPASS and OL 4:0 on TMC22191 only. mable over a standard microprocessor port. fying the applicable part number. Table 1. Comparing the TMC22x91 Encoder s registers match the incoming data.

PRODUCT SPECIFICATION TMC22091/TMC22191 Mask Register A Mask Register is provided which is logically ANDed with incoming color-index data to facilitate pixel animation and other special graphics effects. The Mask Register is ahead of the Data Key comparators and is enabled only when color- index input is selected. Mask Register programming and operation are similar to that of the 171/176 family of graph- ics RAMD A CS. Color Lookup Table The Color Lookup Table (CLUT) is a 256 x 8 x 3 random- access memory. It provides means for offset, gain, gamma, and color correction in RGB and YC B C R operating modes. It provides a full 24-bit color lookup function for color-index mode. It can be loaded in the same manner as a standard V GA RAMD A C. Colorspace Conversion Matrix and Interpolator The matrix converts RGB data (whether from RGB inputs or color-indexed CLUT data) into Y, B-Y, R-Y format for encoding. In input configurations where the pixel input is already in Y, B-Y, R-Y format, the matrix is bypassed. When pixel data is input in YC B C R 422 format, the interpolation fil- ters produce YC B C R 444 for encoding. Sync Generator The TMC22x91 can operate in Master, Genlock, or Slave modes. In Master and Genlock modes, the encoder internally generates all timing and sync signals, and provides Horizon- tal Sync, Vertical Sync, and Pixel Data Control (PDC) to the external frame buffer circuitry. PDC is independently select- able to function as an input or an output. In Genlock mode, the TMC22x91 timing is controlled by the TMC22071 Gen- locking V ideo Digitizer over the CVBS 7-0 bus, GVSYNC , and GHSYNC . The encoder, in turn, produces VHSYNC , VVSYNC , and PDC for the frame buffer interface. Figure 1a. Pixel Data Format MSB LSB 016 GBR444 MODE 24300A RGB444 YC BC R 444 YC BC R 422 COLOR INDEX GBR15 RGB15 00011000 Format Control Register 00010000 00011100 00011101 0001X011 00011010 00010010 G B R R G B Y C B C R G B R R G B Y C B/C R Pixel G 7 G 0 B7 B0 R 7 R 0 R 7 R 0 G 7 G 0 B7 B0 Y7 Y0 C B7 C B0 R R7 R R0 Y7 Y0 C B7 C R7 C B0 C R0 P7 P0 G 4 R 0 R 4 G 0 R 0 G 4 G 0 R 4 B4 B0 8 7 MSB LSB

TMC22091/TMC22191 PRODUCT SPECIFICATION In Slave mode, VHSYNC , VVSYNC , and PDC (optional) are inputs to the TMC22x91. These inputs determine when new lines, frames, and active picture areas begin. The exter- nal controlling circuitry needs to establish the correct timing for these signals. Horizontal and vertical synchronization signals are digitally generated by the TMC22x91 with controlled rise and fall times on all sync edges, the beginning and end of active video, and the burst envelope. All elements of horizontal sync timing are programmable, as are the frequency, phase, and duration of color burst. Video Input The TMC22x91 accepts genlocked synchronization data and digital composite video signals from the TMC22071 Gen- locking V ideo Digitizer over the 8-bit CVBS bus. The encoder synchronizes its digital subcarrier oscillator to the video input from the TMC22071 with this data. The compos- ite video data output from the TMC22071 is passed to the internal video switch for keying with the encoded pixel data. Chroma Modulator A 32-bit digital subcarrier synthesizer feeds a quadrature modulator, producing a digital chrominance signal. The rela- tive phases of the burst and active video portions of the sub- carrier can be individually adjusted to compensate for external phase errors and to effect a hue control. Interpolation Filters Interpolation filters on the luminance and chrominance sig- nals double the pixel rate in preparation for D/A conversion. This band-limited process greatly simplifies the output filter- ing required following the D/A converters and dramatically reduces sin(x)/x distortion. An interpolation filter on the CVBS data similarly raises the sample rate of the video signal, for mixing with the encoded pixel data. Composite Video Switch The Composite V ideo Switch selects between the composite video input (CVBS) and the composite encoded pixel data on a pixel-by-pixel basis, under the control of a key function. K eying may be managed by hardware or software. The hard- w are key input (KEY pin) directly controls the video switch. The encoder may be programmed to operate with a data key, represented by three 8-bit registers that compare with the 24 input bits. They operate in all input modes and may be indi- vidually enabled or disabled. D/A Converters The analog outputs of the TMC22x91 are the outputs of three 10-bit D/A converters, operating at twice the pixel clock rate. The outputs are capable of driving standard video levels into a doubly-terminated 75W coaxial video cable (37.5W total load). An internal voltage reference is provided which can be used to provide reference current for the three D/A converters. For accurate video levels, an external fixed or variable voltage reference source is recommended. The video signal levels from the TMC22x91 may be adjusted to overcome the insertion loss of analog low-pass output filters. The D/A converters on the TMC22x91 may be powered- down via Control Register 0E bits 5 and 6. The COMPOSITE D/A is controlled by bit 6 and the LUMA and CHR OMA D/A con verters are controlled by bit 5. Figure 1b. Pixel Data Format (TMC22191 when CLUTs are Bypassed) MSB LSB 016 GBR444 MODE RGB444 YC BC R 444 YC BC R 422 COLOR INDEX *CB and CR are loaded on alternate LDV cycles RGB15 GBR15 24393A 01011000 Format Control Register 01010000 0101X000 0101X001 0101X011 01010010 01011010 G B R R G B Y C B C R R G B Y C B* C R * Pixel G 7 G 0 B7 B0 R 7 R 0 R 7 R 0 G 7 G 0 B7 B0 Y7 Y0 C B7 C B0 C R7 C R0 Y7 Y0 C B7 C B0 C R7 C R0 P7 P0PixelP7 P0PixelP7 P0 R 4 B0R 0 G 4 G 0 B4 8 7 MSB LSB G B RG 4 R 0G 0 B4 B0 R 4

PRODUCT SPECIFICATION TMC22091/TMC22191 Microprocessor Interface The microprocessor interface employs a 13 line format. The RESET pin sets all internal state machines to their initialized conditions, disables the analog outputs, sets the internal SRESET bit LOW (reset condition), and places the encoder in a power-down mode. All register and CLUT data are maintained in power-down mode. If the HRESET bit is set HIGH, line 1 field 1 is started when RESET goes HIGH, and SRESET is ignored. If HRESET is LOW , the encoder remains idle after RESET goes HIGH until Control Register bit SRESET is set HIGH, which initiates line 1 field 1. Tw o address lines are provided and decoded for access to the internal Control Registers and CLUT. Control Registers and CLUT are accessed by loading a desired address through the 8-bit D 7-0 port, followed by the desired data read or write for that address. Both the CLUT and the Control Registers are self-indexing, allowing continuous reads or writes to succes- sive addresses. JTAG Test Interface The TMC22x91 includes a standard 4-line JTA G (IEEE Std 1149.1-1990) test interface port, providing access to all digi- tal input/output data pins. This is provided to facilitate com- ponent and board-level testing. Test/Validation Mode The TMC22x91 may be configured to produce standard color bars or a 40 IRE modulated (or unmodulated) video ramp, independent of any pixel or video data input. Color bars are useful as an idle system output signal. The test sig- nals may be used to verify proper operation of the analog video signal chain. TMC22090/TMC22190 Compatibility The TMC22090 and TMC22190 are earlier versions of the TMC22091 and TMC22191, respectively. They lack the fol- lowing features of the newer versions: 1. Selectable Setup (to support NTSC EIA-J video output for Japan) 2. PAL-M format (for South American applications) 3. Extended EH and SL intervals (to support pixel rates above 15 Mpps) 4. Individual D/A power-down (to reduce total dissipation when some outputs are not required) 5. Luminance I/O processing (to reduce flicker in graphics applications) These features are controlled by registers 0E and 0F, and enabled by setting Register OE bit 7 to ONE. If an applica- tion of the TMC22x90 is programmed with this bit set to ZER O (as recommended in the product documentation) then the corresponding TMC22x91 will perform identically. Though the earlier parts continue to be available, it is recom- mended that the newer devices be used in new designs for the additional flexibility. Older designs may be readily converted to the newer versions to take advantage of the added features and lower cost of the later technology.

TMC22091/TMC22191 PRODUCT SPECIFICATION Pin Assignments

84 Lead PLCC

100 Lead MQFP

Note: Pin names in parentheses apply to TMC22091. CVBS2 CVBS1 CVBS0 KEY RESET CS R/W A DGND PDC VHSYNC VVSYNC D TDO TCK TMS TDI D GND VDD BYPASS (TEST) OL 4 (TEST) VREF RREF AGND COMPOSITE A GND LUMA A GND CHROMA A GND COMP V DDA VDDA VDDA Pin Name Pin Name VDDA CVBS7 CVBS6 CVBS5 CVBS4 OL3 (TEST) OL2 (TEST) OL1 (TEST) OL0 (TEST) PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 V DD DGND PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 LDV PXCK D GND VDD GVSYNC GHSYNC CVBS Pin Name Pin Name 65-3751-02 Note: Pin names in parentheses apply to TMC22091. 100 NC COMPOSITE NC AGND LUMA A GND NC CHROMA A GND COMP NC NC V DDA VDDA VDDA VDDA VDDA CVBS7 CVBS6 CVBS5 CVBS4 OL3 (TEST) OL2 (TEST) OL1 (TEST) OL0 (TEST) PD PD22 NC NC NC PD PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 VDD DGND PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 Pin Name Pin Name PD3 NC NC NC NC PD PD1 PD0 LDV PXCK D GND VDD GVSYNC GHSYNC CVBS CVBS2 CVBS1 CVBS0 NC KEY RESET CS R/W A D GND PDC NC NC VHSYNC VVSYNC D TDO TCK TMS TDI D GND VDD BYPASS (TEST) OL4 (TEST) VREF RREF AGND 100 Pin Name Pin Name

PRODUCT SPECIFICATION TMC22091/TMC22191 Pin Descriptions Pin Name Pin Number Value Pin Function Description 84-Lead PLCC 100-Lead MQFP Clocks PXCK 79 60 TTL Master Clock Input. This 20 to 30 MHz clock is internally divided by 2 to generate the internal pixel clock, PCK, which a LOW on RESET forces LOW. PXCK drives the entire TMC22x91, except the asynchronous microprocessor interface and the semi-synchronous LDV data input clock. All internal registers are strobed on the rising edge of PXCK. LDV 78 59 TTL Pixel Data Load Clock. On each rising edge of LDV, data on PD 23-0 are latched into the input preload register, for transfer into the input demultiplexer on the next rising edge of PCK. Frame Buffer Interface PD 23-0 52-63, 66-77 26, 27, 31-40, 43-51, 56-58 TTL Pixel Data Inputs. In YC BC R , GBR, RGB, and color-indexed mode, pixel data enter the TMC22x91 on PD23-0. The specific format is found in Figures 1a and 1b. LDV is the clock that controls the loading of pixel data. VHSYNC 12 80 TTL Horizontal Sync I/O. In Master and Genlock modes, the TMC22x91 outputs horizontal sync on this pin. In Slave modes, the TMC22x91 accepts and locks to horizontal sync input on this pin (with vertical sync on VVSYNC ). VHSYNC and VVSYNC must be coincident since they are clocked into the TMC22x91 on the same rising edge of PXCK. VVSYNC 13 81 TTL Vertical Sync I/O. In separate V and H sync Master and Genlock modes, the TMC22x91 outputs vertical block sync (VVSYNC LOW for the 2.5 (PAL) or 3 (NTSC) lines on which vertical sync pulses occur). In composite sync (H and V sync on same signal) Master and Genlock modes, the TMC22x91 outputs horizontal sync, vertical sync, and equalization over this pin. In Slave mode, the TMC22x91 accepts and locks to vertical sync input on this pin (with horizontal sync on VHSYNC ). VHSYNC and VVSYNC must be coincident such that they are clocked into the TMC22x91 on the same rising edge of PXCK. PDC 11 77 TTL Pixel Data Control. In Master mode, the TMC22x91 forces PDC HIGH when and only when it wants active video from the frame buffer. During blanking (syncs, equalization, burst, and porches), it forces PDC LOW, signaling that it will ignore any data presented over PD 23-0. When PDC is used as an input, forcing it HIGH allows the TMC22x91 to receive PD during the active video state. KEY 4 70 TTL Hardware Key Input. When the HKEN control bit is set HIGH and hardware key pin, KEY, is HIGH, video data entering on CVBS 7-0 are routed to the COMPOSITE output. This control signal is pipelined so the pixel that is presented to the PD port when the KEY signal is invoked is at the midpoint of the soft key transition. When HKEN is LOW, KEY is ignored. Like PD data, KEY is clocked into the TMC22x91 on the rising edge of LDV.

TMC22091/TMC22191 PRODUCT SPECIFICATION OL 4-0 29, 48-5197, 22-25 TTL Overlay Data Inputs (TMC22191 only). 30 of the 256 locations of the CLUT may be reserved for overlay operation. These CLUT locations are directly accessed by five input pins, OL 4-0. OL4-0 are entered into the TMC22191 on a pixel-by- pixel basis and select which of the 30 overlay colors is to be encoded. When all five OL 4-0 inputs are LOW, no overlay occurs. BYPASS 28 96 TTL CLUT Bypass Control (TMC22191 only). When BYPASS is HIGH, the CLUT is in the pixel data path within the TMC22191. When BYPASS is LOW, pixel data bypasses the CLUT. BYPASS is active only for certain modes of the Layering Control Register (LCR) when the Format Control Register bit 6 is HIGH. Genlock Interface GHSYNC 83 64 CMOS Genlock Horizontal Sync. In Genlock mode, the TMC22x91 will start a new horizontal line (blank-to-sync-edge transition) with each falling edge of GHSYNC . In non-genlock modes, the TMC22x91 ignores GHSYNC . The internal pixel clock, PCK, is aligned with the falling edge of VHSYNC or GHSYNC (Genlock mode). GVSYNC 82 63 CMOS Genlock Vertical Sync. In Genlock mode, the TMC22x91 will start a new vertical sync sequence at line 1 field 1 whenever GVSYNC and GHSYNC are coincident such that they are clocked into the TMC22x91 on the same rising edge of PXCK. If GVSYNC falls at any other time, the TMC22x91 will assume that this marks the start of field 2, and will ignore it (in odd-field sync mode) or (in all-field sync mode) respond by generating a single vertical sync pulse, followed by 2 (PAL) or 2.5 (NTSC) lines of vertical sync, keyed to the next falling edge on GHSYNC . See Interface Control Register bit 0 for odd-field and all-field operation. CVBS 7-0 44-47, 84, 1-3 18-21, 65-68 TTL Composite Video Inputs. The encoder receives digitized video, subcarrier phase, and subcarrier frequency over this 8- bit bus at the PCK rate. This data may be provided by the companion TMC22071 Genlocking Video Digitizer. In Genlock mode, the TMC22x91 expects subcarrier phase and frequency data during each line’s horizontal sync interval, as well as video data when keying is engaged, transferred at the PCK rate. Microprocessor Interface D 7-0 14-21 82-89 TTL Data I/O Port. All control parameters are loaded into and read back over this 8-bit port. For digital testing, the five lower bits can also serve as a two-cycle 10-bit data output port. For D/A converter testing, it can be used as a 10-bit two-cycle input port, facilitating, for example, ramp-based D/A converter linearity tests. A 1-0 8-9 74-75 TTL mProc Port Controls. As in a RAMDAC, this control governs whether the microprocessor interface selects a table address or reads/writes table contents. It also governs setting and verification of the TMC22x91’s internal operating modes, also over port D 7-0. Pin Descriptions (continued) Pin Name Pin Number Value Pin Function Description 84-Lead PLCC 100-Lead MQFP

PRODUCT SPECIFICATION TMC22091/TMC22191 CS 6 72 TTL Chip Select. When CS is HIGH, the microprocessor interface port, D7-0, is set to HIGH impedance and ignored. When CS is LOW, the microprocessor can read or write parameters over D 7-0. One additional falling edge of CS is needed to move input data to its assigned working registers. R/W 7 73 TTL Bus Read/Write Control. When R/W and CS are LOW, the microprocessor can write to the control registers or CLUT over D 7-0. When R/W is HIGH and CS is LOW, it can read the contents of any CLUT address or control register over D7-0. RESET 5 71 TTL Master Reset Input. Bringing RESET LOW sets the software reset control bit, SRESET , LOW, forcing the internal state machines to their starting states and disabling all outputs. Bringing RESET HIGH synchronizes the internal pixel clock (PCK = PXCK / 2) to maintain a defined pipeline delay through the TMC22x91. If HRESET is set HIGH, the encoder is enabled when RESET goes HIGH. If HRESET is LOW, the host restarts the TMC22x91 by setting SRESET HIGH. RESET does not affect the CLUT or the control registers, except SRESET . Video Output COMPOSITE 33 2 1 V P-P NTSC/PAL Video. Analog output of composite D/A converter, nominally 1.35 volt peak-to-peak into a 37.5W load. LUMA 35 5 1 V P-P Luminance-only Video. Analog output of luminance D/A converter, nominally 1.35 volt peak-to-peak into a 37.5W load. CHROMA 37 8 1 V P-P Chrominance-only Video. Analog output of chrominance D/A converter, nominally 1.35 volt peak-to-peak into a 37.5W load. Analog Interface V REF 30 98 +1.23 V Voltage Reference Input. External voltage reference input, internal voltage reference output, nominally 1.235 V. COMP 39 10 0.1 mF Compensation Capacitor. Connection point for 0.1mf decoupling capacitor. R REF 31 99 392W Current-setting Resistor. Connection point for external current-setting resistor for D/A converters. The resistor (392W ) is connected between RREF and AGND . Output video levels are inversely proportional to the value of RREF . JTAG Test Interface TDI 25 93 TTL Data Input Port. Boundary scan data input port. TMS 24 92 TTL Scan Select Input. Boundary scan (HIGH)/normal operation (LOW) selector. TCK 23 91 TTL Scan Clock Input. Boundary scan clock. TDO 22 90 TTL Data Output Port. Boundary scan data output port. Power Supply VDD 27, 64, 8141, 62, 95 +5 V Positive digital power supply. VDDA 40-43 13-17 +5 V Positive analog power supply. D GND 10, 26, 65, 42, 61, 76, 0.0 V Digital Ground. AGND 32, 34, 36, 4, 6, 9, 100 0.0 V Analog Ground. Pin Descriptions (continued) Pin Name Pin Number Value Pin Function Description 84-Lead PLCC 100-Lead MQFP

PRODUCT SPECIFICATION TMC22091/TMC22191 Control Registers Test TEST 28, 29, 48-51 22-25, 96-97 0.0 V Factory testing (TMC22091 only). Reserved for factory testing. These pins have no effect on the operation but do function as JTAG registers. They should be grounded directly or pulled down to ground with 1kW or smaller resistors. NC N/A 1, 3, 7, 11-12, 28-30, 52-55, 69, 78-79 No Connect Pin Descriptions (continued) Pin Name Pin Number Value Pin Function Description 84-Lead PLCC 100-Lead MQFP The TMC22x91 is initialized and controlled by a set of regis- ters. The registers are organized into 13 categories: 1. Global Control 2. Format Control 3. Interface Control 4. Test Control 5. K ey Control 6. Misc. Control 7. Standards Control 8. Layering Control (TMC22191) 9. K ey Value 10. Timing 11. Subcarrier 12. Test I/O 13. Mask Register An external controller loads the Control Registers through a standard interface port. It also loads the CLUT and reads its contents or those of the Control Registers. The port is governed by pins CS , R/W , and A 1-0. The Address Register for the CLUT and the Control Register pointer automatically increment to allow successive writes to sequential addresses. In the CLUT, the Address Register has two additional bits which increment in modulo-three to sequentially access the red, green, and blue portions. All three colors must be written when any CLUT address is changed. The control register autoincrement follows the sequence indicated in the Control Register Map. When it reaches address 40, it stops incrementing, allowing multiple reads or writes of test data from/to the TESTD AT register. To exit the test mode, reset the Control Register pointer by setting A 1-0, D 7-0, and R/W LOW and then bring CS LOW . Address 1F is a read-only status register. It is addressed by the autoincre- ment sequencer. An y data may be written into this port at that time but it will not be stored. When address 50 is accessed, no autoincrement takes place, allowing multiple writes to the Mask Register.

Table 2. Microprocessor Port Control Table 3. Control Register Map Table 3. Control Register Map (continued)

1. Functions are listed in the order used for reading and
2. For each register listed above, all bits not listed are
3. The meaning of Register 04 (Key Control Register/Layer-

PRODUCT SPECIFICATION TMC22091/TMC22191 Control Register Definitions Global Control Register (00) 7 6 5 4 3 2 1 0 Reserved SRESET PAL LUMDIS CHRDIS HRESET Reg Bit Name Function 00 7-5 Reserved. 00 4 SRESET Software reset. When LOW, resets and holds internal state machines and disables outputs. When HIGH (normal), starts and runs state machines and enables outputs. 00 3 PAL Video standard select. When LOW, the NTSC standard is generated with 7.5 IRE pedestal. When HIGH, PAL standard video is generated. This bit is ignored if Register 0E bit 7 is HIGH, enabling the 0E and 0F registers. 00 2 LUMDIS Luminance input disable. When LOW (normal), luminance (Y) data from external frame buffer is enabled. When HIGH, luminance (Y) data into the TMC22x91 is forced to 0 IRE but sync pulses continue from the LUMA output. 00 1 CHRDIS Chrominance input disable. When LOW (normal), burst and frame buffer data into the TMC22x91 are enabled. when HIGH, burst and frame buffer data are suppressed, enabling monochrome operation. 00 0 HRESET Software reset enable. SRESET is forced LOW when the RESET pin is taken LOW. State machines are reset and held. When HRESET is LOW, RESET may be taken HIGH at any time. The TMC22x91 is enabled and a new frame is begun with line 1, field 1 on the next PXCK after SRESET is set HIGH. The D/A converters are powered down while RESET is LOW. When HRESET is HIGH, a new frame is begun with line 1, field 1 on the next PXCK after RESET is taken HIGH. SRESET is ignored. The D/A converters remain active during the reset sequence.

TMC22091/TMC22191 PRODUCT SPECIFICATION Control Register Definitions (continued) Format Control Register (01) 7 6 5 4 3 2 1 0 Reserved LCREN RAMPEN CB FORMAT INMODE Reg Bit Name Function 01 7 Reserved. 01 6 LCREN (TMC22191) Layering Control Register enable. When LOW, the Layering Control Register is not available and Key Control Register functions are enabled. In this mode, the TMC22191 functions like the TMC22091. When HIGH, the Layering Control Register takes the place of the Key Control Register and enables the layering functions. Data loaded into the Key or Layering Control Registers will remain but have a different meaning if this bit is changed. 01 5 RAMPEN Modulated ramp test. When LOW (normal), the TMC22x91 encodes and outputs video corresponding to input data. When RAMPEN and CB are both HIGH, an internally generated 40 IRE modulated ramp is produced, preempting input data. 01 4 CB Color bar test. When HIGH (normal), the TMC22x91 encodes and outputs video corresponding to input data. When CB , RAMPEN, and Format Control Register bit 0 are LOW, internally generated color bars are produced, preempting input data. 01 3-2 FORMAT PD 23-0 input format select. Two bits select RGB, GBR, or YCBC R input data. When bits 3 and 2 are: 0 0 the CLUT output is interpreted as RGB and is converted to YCBC R . 0 1 is reserved. Bits 3 and 2 must be 00 or 10 when the Layering Control Register is enabled (TMC22191). 1 0 the CLUT output is interpreted as GBR, and is converted to YCBC R . 1 1 the CLUT output is interpreted as YCBC R . 01 1-0 INMODE PD 23-0 input mode select. These two bits set up the TMC22x91 for either 444, 422, 15-bit, or 8-bit input modes. 0 0 24-bit/pixel GBR, RGB, or YCBC R 444 data enters from PD23-0 0 1 YC BC R 422 data enters from PD23-8; CR and CB alternate from PD15-8 1 0 15-bit/pixel GBR or RGB data from PD14-0 1 1 8-bit/pixel color indexed data enters from PD7-0. Bits 1 and 0 must be 00, 01, or 11 when the Layering Control Register is enabled (TMC22191).

PRODUCT SPECIFICATION TMC22091/TMC22191 Control Register Definitions (continued) Interface Control Register (02) 7 6 5 4 3 2 1 0 VITSEN SHCY TBASE SOUT FBDIS PDCDIR FLDLK Reg Bit Name Function 02 7 VITSEN VITS lines enable. When LOW, all UBB lines in the vertical interval are black burst regardless of input data. When HIGH, all UBB lines in the vertical interval become UVV active video and are dependent upon input data. 02 6 SHCY Short-cycle test mode. When LOW, normal operation is enabled. when HIGH, EH (equalization pulse HIGH length) and SL (vertical sync LOW length) are shortened by 256. 02 5-4 TBASE Time-base source select. These two bits set up the TMC22x91 for either genlock or frame buffer control of timing. When bits 5 and 4 are: 0 0 the encoder counts out its own time-base from input clock PXCK. 0 1 the encoder locks to synchronizing signals from external genlock. 1 0 the encoder locks to synchronizing signals from frame buffer controller. 02 3 SOUT Sync output mode select. When LOW, VHSYNC and VVSYNC output separate horizontal and vertical sync pulses. When HIGH, composite sync (H and V) is output on VVSYNC while horizontal sync is output on VHSYNC . 02 2 FBDIS Frame buffer signals enable. When LOW, VVSYNC and VHSYNC outputs to frame buffer are enabled. When HIGH, VVSYNC and VHSYNC outputs to frame buffer are disabled. 02 1 PDCDIR PDC master/slave select. When LOW, PDC is an output where the encoder is requesting data from the frame buffer. When HIGH, PDC is an input, and directs the encoder to accept data from the frame buffer. 02 0 FLDLK Field lock select. When LOW, (in Slave mode) the encoder locks to each new field. When HIGH, the encoder locks to field 1 only.

TMC22091/TMC22191 PRODUCT SPECIFICATION Control Register Definitions (continued) Test Control Register (03) 7 6 5 4 3 2 1 0 Reserved LIMEN TESTEN HOLDEN TSTMSB LUMTST 8FSUBR CHRTST Reg Bit Name Function 03 7 Reserved. 03 6 LIMEN Luminance limiter enable. When LOW, all luminance values are passed to modulator. when HIGH, luminance values are limited to 101 IRE. 03 5 TESTEN Test enable. When LOW, normal operation is enabled. When HIGH, TESTDAT 7-0 (Register 40) is connected to the composite output (READ) and D/A converters (WRITE) for test. 03 4 HOLDEN MSBs/LSBs hold select. When LOW, alternates MSBs and LSBs in test, at PXCK rate. When HIGH, reads/writes only MSBS or LSBS in test (per TSTMSB, bit 3) 03 3 TSTMSB LSBS,MSBS hold select. When LOW, connects 2 LSBs to TESTDAT 1-0 for testing when TESTEN is HIGH. When HIGH, connects 8 MSBs to TESTDAT 7-0 for testing when TESTEN is HIGH. 03 2 LUMTST LUMA channel test. When LOW (normal), the luminance D/A converter is driven from luminance channel. When HIGH, the luminance D/A converter is driven from TESTDAT for testing when TESTEN is HIGH. 03 1 8FSUBR 8-field subcarrier reset enable. When LOW, the internal subcarrier generator is reset with frequency and phase data from FREQ, SYSPH, and BURPH registers every eight fields. When HIGH, the internal subcarrier generator free- runs on the basis of frequency and phase data from the last time it was reset. When RESET goes LOW, the subcarrier frequency and phase will be reset from FREQ, SYSPH, and BURPH after field 8. 03 0 CHRTST CHROMA channel test. When LOW (normal), the chrominance D/A converter is driven from chrominance channel. When HIGH, the chrominance D/A converter is driven from TESTDAT when TESTEN is HIGH.

PRODUCT SPECIFICATION TMC22091/TMC22191 Control Register Definitions (continued) K ey Control Register (04) 7 6 5 4 3 2 1 0 Reserved HKEN BUKEN SKEXT DKDIS EKDIS FKDIS SKEN Reg Bit Name Function 04 7 Reserved. 04 6 HKEN Hardware key enable. When LOW, the KEY input pin ignored. When HIGH, the KEY input pin is enabled. 04 5 BUKEN Burst key enable. When LOW, output video burst is generated on TMC22x91. When HIGH, output burst is taken from genlock input data. 04 4 SKEXT Data key operation select. When LOW, data keying is allowed only during active video. When HIGH, keying is allowed during active video and blanking. 04 3 DKDIS Green/red/Y data key disable. When LOW, green/red/Y input data is enabled for data keying. When HIGH, green/red/Y input data is ignored for data keying. This function is enabled when Layering Control Register is enabled (TMC22191). 04 2 EKDIS Blue/green/C B data key disable. When LOW, Blue/green/CB input data is enabled for data keying. When HIGH, Blue/green/CB input data is ignored for data keying. This function is enabled when Layering Control Register is enabled (TMC22191). 04 1 FKDIS Red/blue/C R data key disable. When LOW, red/blue/CR input data is enabled for data keying. When HIGH, red/blue/CR input data is ignored for data keying. This function is enabled when Layering Control Register is enabled (TMC22191). 04 0 SKEN Data key enable. When LOW, data keying is disabled. When HIGH, data keying is enabled.

TMC22091/TMC22191 PRODUCT SPECIFICATION Control Register Definitions (continued) Layering Control Register (04) (TMC22191) 7 6 5 4 3 2 1 0 LAYMODE HKEN BUKEN SKEXT LAYMODE SKEN Reg Bit Name Function 04 7 LAYMODE MSB of Layer Assignments select. 04 6 HKEN Hardware key enable. When LOW, the KEY input pin ignored. When HIGH, the KEY input pin is enabled. 04 5 BUKEN Burst key enable. When LOW, output video burst is generated on TMC22191. When HIGH, output burst is taken from genlock input data. 04 4 SKEXT Data key operation select. When LOW, data keying is allowed only during active video. When HIGH, data keying is allowed during active video and blanking. 04 3-1 LAYMODE Three LSBs of Layer Assignments select. 04 0 SKEN Data key enable. When LOW, data keying is disabled. When HIGH, data keying is enabled. K ey Value Registers (05-07) Reg Bit Name Function 05 7-0 DKEY Green/red/Y data key value. Eight bits hold the match value which triggers keying on red/Y. 06 7-0 EKEY Blue/green/U data key value. Eight bits hold the match value which triggers keying on green/U. 07 7-0 FKEY Red/blue/V key value. Eight bits hold the match value which triggers keying on blue/V.

PRODUCT SPECIFICATION TMC22091/TMC22191 Control Register Definitions (continued) Miscellaneous Control Register (0E) 7 6 5 4 3 2 1 0 EFEN COMPD/A SVIDD/A FKREN RATIO TFLK T512 CB100 Reg Bit Name Function 0E 7 EFEN Register 0E and 0F enable. When LOW, the functions of Register 0E and 0F are disabled. When HIGH, Registers 0E and 0F are active. When Registers 0E and 0F are enabled, Register 00 bit 3 is ignored. Register 0E bit 7 will read back whatever value was written. 0E 6 COMPD/A COMPOSITE D/A disable. When HIGH, the COMPOSITE D/A converter is powered-down. When LOW, the D/A is enabled. 0E 5 SVIDD/A LUMA/CHROMA D/A disable. When HIGH, the LUMA and CHROMA D/A converters are powered-down. When LOW, they are enabled. 0E 4 FKREN Luminance processing enable. When FKREN is HIGH, the KEY input defines the function of CVBS input data. When the KEY input is HIGH, CVBS data is keyed over PD input data. When KEY is LOW, CVBS data is assumed to be luminance data delayed by one When FKREN is LOW, the KEY input operates normally, switching between CVBS and PD data. 0E 3 RATIO Luminance ratio control bit. When LOW, 1/2 of current luminance and 1/2 of field delayed luminance from the CVBS input are added to yield a new combined luminance value. When RATIO is HIGH, 3/4 of current luminance is added to 1/4 of the delayed luminance to produce a new luminance value. 0E 2 TFLK Luminance-pass threshold. The difference between current luminance and delayed luminance (from the CVBS inputs) is compared against a preset threshold set by TFLK. When TFLK is LOW, the high threshold must be exceeded to trigger the combining of current and delayed luminance (according to RATIO). If the higher threshold is not exceeded, current luminance is passed without modification. When TFLK is HIGH, a lower threshold is used to trigger the combining of current and delayed luminance. 0E 1 T512 EH/SL offset control bit. When LOW, the true value of EH and SL is offset by 256. When HIGH, the true value for EH and SL is offset by 512. 0E 0 CB100 NTSC/PAL color bars select. When HIGH, color bars with 100% white level are selected. When LOW, color bars will have 75% white level.

TMC22091/TMC22191 PRODUCT SPECIFICATION Control Register Definitions (continued) Standards Control Register (0F) 7 6 5 4 3 2 1 0 EFEN SIX25 PALID SETUP YGAIN CGAIN Reg Bit Name Function 0F 7 EFEN Same as Register 0E bit 7, but read-only. 0F 6 SIX25 Select 625 lines per frame. When HIGH, the encoder assumes 625 line per frame. When LOW, 525 lines per frame are assumed. 0F 5 PALID PAL select. When HIGH, Phase alternate line (PAL) operation is selected. When LOW, operation conforms to NTSC standards. 0F 4 SETUP Setup enable. When HIGH, a 7.5 IRE Pedestal is added to the output video. when LOW, no pedestal is added. 0F 3-2 YGAIN Luminance gain settings are adjusted to conform to the following NTSC and PAL standards: 0 0 NTSC without SETUP 0 1 NTSC-A and PAL-M 1 0 PAL-I and PAL-N 1 1 Reserved 0F 1-0 CGAIN Chrominance gain settings are adjusted to conform to the following NTSC and PAL standards: 0 0 NTSC without SETUP 0 1 NTSC-A and PAL-M 1 0 PAL-I and PAL-N 1 1 Reserved Timing Registers (10-17) Reg Bit Name Function 10 7-0 SY Horizontal sync tip length. This 8-bit register holds a value extending from 0 to 255 PCK cycles. 11 7-0 BR Breezeway length. This 8-bit register holds a value extending from 0 to 255 PCK cycles. 12 7-0 BU Burst length. This 8-bit register holds a value extending from 0 to 255 PCK cycles. 13 7-0 CBP Color back porch length. This 8-bit register holds a value extending from 0 to 255 PCK cycles. 14 7-0 XBP Extended color back porch 8 LSBs. This 8-bit register holds the LSBs of a 10-bit value extending from 0 to 1023 PCK cycles. The two MSBs are located in control register 18. 15 7-0 VA Active video 8 LSBs. This 8-bit register holds the LSBs of a 10-bit value extending from 0 to 1023 PCK cycles. The two MSBs are located in control register 18. 16 7-0 VC Active video start 8 LSBs. This 8-bit register holds the LSBs of a 10-bit value which is the initial half active video length extending from 0 to 1023 PCK cycles. The two MSBs are located in control register 18. 17 7-0 VB Active video end 8 LSBs This 8-bit register holds the LSBs of a 10-bit value which is the end half active video length extending from 0 to 1023 PCK cycles. The two MSBs are located in control register 18.

PRODUCT SPECIFICATION TMC22091/TMC22191 Control Register Definitions (continued) Timing Register (18) 7 6 5 4 3 2 1 0 XBP VA VC VB Reg Bit Name Function 18 7-6 XBP Extended color back porch 2 MSBs. These two bits hold the MSBs of a 10-bit value extending from 0 to 1023 PCK cycles. The LSBs are located in control register 14. 18 5-4 VA Active video 2 MSB. These two bits hold the MSBs of a 10-bit value extending from 0 to 1023 PCK cycles. The LSBs are located in control register 15. 18 3-2 VC Active video start 2 MSBs. These two bits hold the MSBs of a 10-bit value which is the initial half active video length extending from 0 to 1023 PCK cycles. The LSBs are located in control register 16. 18 1-0 VB Active video end 2 MSBs. These two bits hold the MSBs of a 10-bit value which is the end half active video length extending from 0 to 1023 PCK cycles. The LSBs are located in control register 17. Timing Registers (19-1E) Reg Bit Name Function 19 7-0 FP Front porch length. This 8-bit register holds a value extending from 0 to 255 PCK cycles. 1A 7-0 EL Equalization pulse LOW length. This 8-bit register holds a value from 0 to 255 PCK cycles. 1B 7-0 EH Equalization pulse HIGH length. This 8-bit register holds a value extending from 0 to 255 PCK cycles. This value, when added to 256 (or 512), determines the final pulse length in the range of 256 to 511 (or 767) PCK cycles. 1C 7-0 SL Vertical sync LOW length. This 8-bit register holds a value from 0 to 255 PCK cycles. This value, when added to 256 (or 512), determines the final pulse length in the range of 256 to 511 (or 767) PCK cycles. 1D 7-0 SH Vertical sync HIGH length. This 8-bit register holds a value extending from 0 to 255 PCK cycles. 1E 7-0 CBL Color bar length. This 8-bit register holds a value which is the length of each color bar displayed extending from 0 to 255 PCK cycles. Timing Register (1F) 7 6 5 4 3 2 1 0 FIELD LTYPE Reg Bit Name Function 1F 7-5 FIELD Field identification (read only). These three bits are updated 12 PXCK periods after each VHSYNC . They allow the user to determine field type on a continuous basis. 1F 4-0 LTYPE Line type identification (read only). These five bits are updates 5 PXCK periods after each VHSYNC . They allow the user to determine line type on a continuous basis.

TMC22091/TMC22191 PRODUCT SPECIFICATION Control Register Definitions (continued) Subcarrier Registers (20-27) Reg Bit Name Function 20 7-0 FREQL Subcarrier frequency 4th byte (LSBs). This 8-bit register holds the LSB (bits 7-0) of the 32-bit subcarrier frequency value (non-genlock modes). The next eight most significant bits are held in Register 21. 21 7-0 FREQ3 Subcarrier frequency 3rd byte. This 8-bit register holds bits 15:8 of the subcarrier frequency value (non-genlock modes). The next eight most significant bits are held in Register 22. 22 7-0 FREQ2 Subcarrier frequency 2nd byte. This 8-bit register holds bits 23-16 of the subcarrier frequency value (non-genlock modes). The eight MSBs are held in Register 23. 23 7-0 FREQM Subcarrier frequency 1st byte (MSBs). This 8-bit register holds the MSBs (bits 31-24) of the 32-bit subcarrier frequency value (non-genlock modes). 24 7-0 SYSPHL Video phase offset LSBs. This 8-bit register holds the 8 LSBs of color subcarrier phase offset during active video. 25 7-0 SYSPHM Video phase offset MSBs. This 8-bit register holds the 8 MSBs of color subcarrier phase offset during active video. 26 7-0 BURPHL Burst phase offset LSBs. This 8-bit register holds the 8 LSBs of burst phase offset for color adjustment. 27 7-0 BURPHM Burst phase offset MSBs. This 8-bit register holds the 8 MSBs of burst phase for color adjustment. Test I/O Register (40) Reg Bit Name Function 40 7-0 TESTDAT Test data input/output. This 8-bit register holds MSBs or LSBs, as determined by the Test Control Register. This control address does not auto-increment during read or write operations. To exit the test mode, reset the Control Register pointer by setting A 1-0 and R/W LOW and then bring CS LOW. Mask Register (50) Reg Bit Name Function 50 7-0 MASK Mask register. This 8-bit register holds an 8-bit word that is logically ANDed with the incoming data presented to the three CLUTs in color-index mode. This register is a write-only register. Y-Component Register (60) Reg Bit Name Function 60 7-0 Y Y-component register. This register holds the contents of the luminance value before the Sync and Blank Insert circuitry of the encoder. Loading the Control Register pointer with 60 h brings 8-bit Y values out on the D7-0 port.

the data format and source presented to the PD port. V GA colors in the encoded video environment. gain (CLUT data = CLUT address) for PAL and NTSC. functions. The CLUT is loaded in Y-CB -CR sequence. CLUT locations must be in RGB format. Table 4. CLUT Transfer Functions for NTSC and PAL

Table 5. CLUT Locations Addressed by

00 No Overlay

10 No Overlay

output data to color-difference values. Table 6. Pixel Input Operation for Format Control Register bit 6 = HIGH (TMC22191) Figure 2. Pixel Data (PD23-0) Sequence for YCB C R 422

play (phosphor nonlinearity in converting current into light). where a typical Gamma is 2.2 for NTSC, 2.8 for PAL. play monitor. Each R, G, and B channel is treated as linear. 601 signal, Gamma should have already been applied. determined from 24 registers that are loaded by a controller.

10 MHz and 15 MHz can be accommodated, and any desired

val with timing register identification. ister, and PCK is the pixel clock period. izontal line comprises the sum of appropriate elements. periods to the calculated value for VA. Table 7. Horizontal Timing Specifications video timing may be produced. ister, and PCK is the pixel clock period. based upon H, the Horizontal line time. and the Extended Color Back Porch, XBP = VA + CBP –VB. Table 8. Vertical Timing Specifications

Table 9. NTSC Field/Line Sequence and Identification

1 EE 00 264 EE 00 1 EE 00 264 EE 00

2 EE 00 265 EE 00 2 EE 00 265 EE 00

3 EE 00 266 ES 01 3 EE 00 266 ES 01

4 SS 03 267 SS 03 4 SS 03 267 SS 03

5 SS 03 268 SS 03 5 SS 03 268 SS 03

6 SS 03 269 SE 02 6 SS 03 269 SE 02

7 EE 00 270 EE 00 7 EE 00 270 EE 00

8 EE 00 271 EE 00 8 EE 00 271 EE 00

9 EE 00 272 EB 10 9 EE 00 272 EB 10

10 UBB 0D 273 UBB 0D 10 UBB 0D 273 UBB 0D

20 UBB 0D 282 UBB 0D 20 UBB 0D 282 UBB 0D

21 UVV 0F 283 UBV 0E 21 UVV 0F 283 UBV 0E

22 UVV 0F 284 UVV 0F 22 UVV 0F 284 UVV 0F

263 UVE 0C 525 UVV 0F 263 UVE 0C 525 UVV 0F

pulse is specified under Operating Conditions.

Figure 6. PAL Vertical Interval

Table 10. PAL Field/Line Sequence and Identification pulse, color burst suppressed.

1 SS 03 313 ES 01 626 SS 03 938 ES 01

2 SS 03 314 SS 03 627 SS 03 939 SS 03

3 SE 02 315 SS 03 628 SE 02 940 SS 03

4 EE 00 316 EE 00 629 EE 00 941 EE 00

5 EE 00 317 EE 00 630 EE 00 942 EE 00

7 UBB 0D 319 UBB 0D 632 UBB 0D 944 -BB 05

8 UBB 0D 320 UBB 0D 633 UBB 0D 945 UBB 0D

22 UBB 0D 335 UBB 0D 647 UBB 0D 960 UBB 0D

24 UVV 0F 337 UVV 0F 649 UVV 0F 962 UVV 0F

308 UVV 0F 621 UVV 0F 933 UVV 0F 1246 UVV 0F

309 UVV 0F 622 -VV 07 934 UVV 0F 1247 UVV 0F

311 EE 00 624 EE 00 936 EE 00 1249 EE 00

312 EE 00 625 EE 00 937 EE 00 1250 EE 00

Figure 7. PAL-M Vertical Interval

Table 11. PAL-M Field/Line Sequence and Identification pulse, color burst suppressed.

1 SS 03 263 ES 01 1 SS 03 263 ES 01

2 SS 03 264 SS 03 2 SS 03 264 SS 03

3 SS 03 265 SS 03 3 SS 03 265 SS 03

4 EE 00 266 SE 02 4 EE 00 266 SE 02

5 EE 00 267 EE 00 5 EE 00 267 EE 00

6 EE 00 268 EE 00 6 EE 00 268 EE 00

17 UBB 0D 279 UBB 0D 18 UVV 0F 279 UBB 0D

261 EE 00 522 -VV 07 261 EE 00 522 UVV 0F

524 EE 00 524 EE 00

525 EE 00 525 EE 00

video waveform. The TMC22x91 does this automatically.

1. H and V Sync leading and trailing edges.
2. Active video leading and trailing edges.

ting external delay compensation and color adjustment. Register bit 1 for the subcarrier reset function. Table 12. Standard Timing Parameters

1. XBP, VA, VC, and VB are 10-bit values. The 2 MSBs for these four variables are in Timing Register 18. See Table 3.
2. EH and SL are 9-bit values. A most significant "1" is forced by the TMC22x91 since EH and SL must range from 256 to 511.

EH and SL may be extended to 767. Only the eight LSBs are stored in Timing Registers 1B and 1C.

1. Every calculated timing parameter has a minimum value of 5 except EH and SL which have minimum values of 256.

between the internal synthesizer and the chroma modulator. The nominal value for SYSPH is zero. split into two 8-bit registers, SYSPHM and SYSPHL. ber 8,192 advances the burst phase by 45°. Table 13. Standard Subcarrier Parameters

SCH error between the two sources. corrected with SYSPH and BURPH of fsets of AAA h. controlled by the Format Control Register. The percentage color saturation is selectable via Misc. green, magenta, red, blue, and black. component is varied from black to white. Figure 8. 100% Color Bars With 100% and 75% Chrominance Saturation

PXCK period. This uncertainty does not apply to tDOZ . 8-bit luminance pixels synchronous with respect to PXCK. To halt the pixel flow from D7-0, bring CS HIGH.

1. Master mode. The encoder independently produces all
2. Slave mode. The encoder accepts horizontal and vertical
3. Genlock mode. The encoder accepts horizontal and ver-

data input from the external pixel source. Figure 12. Reset Timing – PCK Synchronization 12, PCK is denoted by odd PXCK counts. following this RESET rising edge is designated as PXCK 1. pixel data and LDV which also operates at the rate of PCK. and LDV as well as LDV and PCK as shown in Figure 13.

source image (i.e. variable matte color from CVBS data). Table 14. Layer Assignments, Image Sources, and Keying Controls (TMC22191)

1. For LAYMODE = 0 to 7, Pixel Data always passes through the CLUTs. FORMAT, INMODE, and the BYPASS pin selects the

input format for PD23-0 according to Table 6.

1. For LAYMODE = 8 to F and BYPASS = HIGH, Data Key is disabled.
2. Asserting the signal listed under "Keying Control:" enables the corresponding "Signal Source:". Signals with " " are asserted

0 PD(YC BC R , RGB, CI) CVBS KEY or

1 PD(YC BC R , RGB, CI) CVBS KEY or

2 PD(YC BC R , RGB, CI) CVBS KEY PD(YC BC R , RGB, CI)Data Key OVERLA Y OL 4-0

3 PD(YC BC R , RGB, CI) CVBS KEY PD(YC BC R , RGB, CI)Data Key OVERLA Y OL 4-0

4 CVBS O VERLA Y OL 4-0 PD(YC BC R , RGB, CI) KEY or

5 CVBS PD(YC BC R , RGB, CI) KEY or

6 PD(YC BC R , RGB, CI) CVBS KEY O VERLA Y OL 4-0 PD(YC BC R , RGB, CI) Data Key

7 PD(YC BC R , RGB, CI) CVBS KEY O VERLA Y OL 4-0 PD(YC BC R , RGB, CI) Data Key

8 PD(YC BC R , CI) CVBS KEY or

9 PD(RGB) PD(YC BC R , CI) BYPASS CVBS KEY or

PD port data when CVBS is active.

1. Normally, keying is only effective during the Active V ideo

alw ays active, and may be exercised at will. input at the same time as the KEY signal. depending on the input mode selected as shown in Table 16. Figure 22. Hardware Keying Control Register OE bit 4 is HIGH (TMC22191). values are not identical, no key will be generated. Table 16. Table D, E, F Contents

of the TMC22091 function as JTA G registers. The JTA G port is a 4-line interface, following IEEE Std. (TDO) is referred to the falling edge of TCK. Table 16. JTAG Interface Connections

Figure 34. Transition Levels for Three-State Measurements

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating

conditions. Functional operation under any of these conditions is NOT implied.

1. Applied voltage must be current limited to specified range, and measured with respect to GND.
2. Forcing voltage must be limited to specified range.
3. Current is specified as conventional current, flowing into the device.

PRODUCT SPECIFICATION TMC22091/TMC22191 Operating Conditions Parameter Min. Nom. Max. Units VDD Power Supply Voltage 4.75 5.0 5.25 V VIH Input Voltage, Logic HIGH TTL Compatible Inputs, all but TCK 2.0 VDD V TTL Compatible Input TCK 2.5 VDD V CMOS Compatible Inputs (2/3)VDD VDD V VIL Input Voltage, Logic LOW TTL Compatible Inputs GND 0.8 V CMOS Compatible Inputs GND (1/3)VDD V IOH Output Current, Logic HIGH -2.0 mA IOL Output Current, Logic LOW 4.0 mA VREF External Reference Voltage 1.235 V IREF D/A Converter Reference Current, VREF = Nom. 2.1 3.15 4.4 mA (IREF = VREF / RREF , flowing out of the RREF pin) R REF Reference Resistor, VREF = Nom. 281 392 588 W R OUT Total Output Load Resistance 37.5 W TA Ambient Temperature, Still Air 0 70 °C Pixel Interface f PXL Pixel Rate 12.27 15 Mpps fPXCK Master Clock Rate, 2x pixel rate 24.54 30 MHz tPWHPX PXCK Pulse Width, HIGH 10 ns tPWLPX PXCK Pulse Width, LOW 10 ns For PD, VVSYNC , VHSYNC , PDC, KEY tSP Setup Time 12 ns tHP Hold Time, PD and KEY 0 ns tHP Hold Time, PDC, VHSYNC , VVSYNC 5 ns tXL Delay Time, LDV 10 ns tPWHLDV LDV Pulse Width, HIGH 15 ns tPWLLDV LDV Pulse Width, LOW 10 ns tPWLVH VHSYNC Pulse Width, LOW 6 15 PXCK periods tPWHVV VVSYNC Pulse Width, LOW 0.5 3 H Genlock Interface tSGI Setup Time, GHSYNC , GVSYNC , CVBS 10 ns tHGI Hold Time, GHSYNC , GVSYNC , CVBS 0 ns Microprocessor Interface t PWLCS CS Pulse Width, LOW 55 ns tPWHCS CS Pulse Width, HIGH 30 ns tSA Address Setup Time 10 ns tHA Address Hold Time 0 ns tSD Data Setup Time (write) 15 ns tHD Data Hold Time (write) 0 ns

TMC22091/TMC22191 PRODUCT SPECIFICATION Note: 1. Timing reference points are at the 50% level.

Electrical Characteristics

Note: 1. Typical IDD with VDD = +5.0 Volts and TA = 25°C, Maximum IDD with VDD = +5.25 Volts and TA = 0°C. tSR Reset Setup Time 24 ns tHR Reset Hold Time 2 ns JTAG Interface f TCK Test Clock (TCK) Rate 20 MHz tPWLTCK TCK Pulse Width, LOW 10 ns tPWHTCK TCK Pulse Width, HIGH 25 ns tSTP Test Port Setup Time, TDI, TMS 10 ns tHTP Test Port Hold Time, TDI, TMS 3 ns Parameter Conditions Min. Typ. Max. Units IDD Power Supply Current1 VDD = Max, fPXCK = 30MHz 250 300 mA IDDQ Power Supply Current1 (D/A disabled) VDD = Max, fPXCK = 30MHz 60 mA VRO Voltage Reference Output 0.988 1.235 1.482 V IBR Input Bias Current, VREF VREF = Nom 100 mA IIH Input Current, Logic HIGH VDD = Max, VIN = VDD 10 mA IIL Input Current, Logic LOW VDD = Max, VIN = 0V -10 mA VOH Output Voltage, Logic HIGH IOH = Max 2.4 V VOL Output Voltage, Logic LOW IOL = Max 0.4 V IOZH Hi-Z Leakage current, HIGH VDD = Max, VIN = VDD 10 mA IOZL Hi-Z Leakage current, LOW VDD = Max, VIN = GND -10 mA C I Digital Input Capacitance TA = 25°C, f = 1MHz 4 10 pF C O Digital Output Capacitance TA = 25°C, f = 1MHz 10 pF VOC Video Output Compliance Voltage -0.3 2.0 V R OUT Video Output Resistance 15 kW C OUT Video Output Capacitance IOUT = 0 mA, f = 1 MHz 15 25 pF Operating Conditions (continued) Parameter Min. Nom. Max. Units

PRODUCT SPECIFICATION TMC22091/TMC22191 Switching Characteristics Notes: 1. Timing reference points are at the 50% level. 2. Analog CLOAD < 10 pF, D7-0 load < 40 pF. 3. Pipeline delay, with respect to PXCK, is a function of the phase relationship between the internally generated PCK (PXCK/2) and PXCK, as established by the hardware reset. 4. tDOM = 1 PXCK + 54 ns = 100 ns worst-case at PXCK = 24.54 MHz. System Performance Characteristics Notes: 1. TTL input levels are 0.0 and 3.0 Volts, 10%-90% rise and fall times <3 ns. 2. Analog CLOAD < 10 pF, D7-0 load < 40 pF. 3. NTSC Parameter Conditions Min. Typ. Max. Units PIPES Pipeline Delay3 PD to Analog Out 44 44 44 PXCK periods tDOZ Output Delay, CS to low-Z 6 23 ns tDOM Output Delay, CS to Data Valid4 100 ns tHOM Output Hold Time, CS to hi-Z 10 ns tDOTP Output Delay, TCK to TDO Valid 30 ns tHOTP Output Hold Time, TCK to TDO Valid 5 ns tDOS Output Delay PXCK to VHSYNC , VVSYNC , PDC 25 ns tR D/A Output Current Risetime 10% to 90% of full-scale 2 ns tF D/A Output Current Falltime 90% to 10% of full-scale 2 ns tDOV Analog Output Delay 20 ns Parameter Conditions Min. Typ. Max. Units RES D/A Converter Resolution 10 10 10 Bits ELI Integral Linearity Error 0.25 % ELD Differential Linearity Error 0.20 % EG Gain Error –10 % FS dp Differential Phase PXCK = 24.54 MHz,

40 IRE Ramp3

0.5 degree dg Differential Gain PXCK = 24.54 MHz, 0.9 % SKEW CHROMA to LUMA Output Skew 0 2 ns PSRR Power Supply Rejection Ratio CCOMP = 0.1 mF, f = 1kHz 0.5 %/ %VDD

Figure 37. TMC22x91-to-TMC22071 Interface Circuit performance is strongly influenced by the board layout.

• K eep analog traces (COMP, V REF , RREF ) as short and as far from all digital signals as possible.
• The power plane for the TMC22x91 should be separate from that which supplies other digital circuitry. A single power plane should be used for all of the V DD pins. If the power supply for the TMC22x91 is the same for the system’s digital circuitry, power to the TMC22x91 should be filtered with ferrite beads and 0.1mF capacitors to reduce noise.
• The ground plane should be solid, not cross-hatched. Connections to the ground plane should be very short.
• Decoupling capacitors should be applied liberally to V DD pins. For best results, use 0.1mF capacitor in parallel with 47mF capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice.
• The PXCK should be handled carefully. Jitter and noise on this clock or its ground reference will translate to noise on the video outputs. Terminate the clock line carefully to eliminate overshoot and ringing. Microprocessor I/O Operations Various CLUT Read/Write operations are shown in Table 17. Each step in the table requires a CS pulse (falling edge fol- lowed by a rising edge) to execute. For Write operations, R/W and A 1-0 must conform to setup and hold timing with respect to the falling edge of CS . D7-0 must meet setup and hold timing with respect to the rising edge of CS . These timing relationships are illustrated in Fig- ure 10. When writing data into an internal register (i.e. CLUT Address Register) an extra CS falling edge is required to transfer the input data to that register. This requirement is usually accomplished by executing the next step in the sequence. If there is no planned next step in the sequence, executing a Control Register Read step will meet the require- ment and terminate the sequence. For Read operations, R/W and A 1-0 must conform to setup and hold timing with respect to the falling edge of CS . Read data on D7-0 is initiated by the falling edge of CS\\ and termi- nated by the rising edge of CS as shown in Figure 11. When reading Control Registers, valid data appears tDOM after the falling edge of CS . When reading CLUT locations, an extra CLUT Read step is needed to set up the CLUT Read sequence. This is accomplished in the table by executing an extra CLUT Read step just before the CLUT Read sequence which returns successive d, e, and f data. CLUT Read sequences must be terminated an extra CS falling edge. This requirement is usually accomplished by executing the next I/O step. If there is no planned next step in the sequence, executing a Control Register Read step will meet the require- ment and terminate the sequence.

Table 17. CLUT Read/Write Sequences 1 0 01 00 Write 00 into CLUT Address Register. 1 0 01 00 Write 00 into CLUT Address Register. 2 0 11 d1 d1 written into D, CLUT address 00. 3 0 11 e1 e1 written into E, CLUT address 00. 4 0 11 f1 f1 written into F, CLUT address 00. 767 0 11 d256 d256 written into D, CLUT address FF. 768 0 11 e256 e256 written into E, CLUT address FF. 769 0 11 f256 f256 written into F, CLUT address FF. 770 1 00 xx Sequence termination. 1 0 01 addr Write addr into the CLUT Address Register. 2 0 11 d1 d1 written into D, CLUT address addr. 3 0 11 e1 e1 written into E, CLUT address addr. 4 0 11 f1 f1 written into F, CLUT address addr. 5 1 00 xx Sequence termination. 1 0 01 addr Write addr into the CLUT Address Register. 2 1 11 xx Set up for CLUT Read sequence. 3 1 11 d1 d1 read from D, CLUT address addr. 4 1 11 e1 e1 read from E, CLUT address addr. 5 1 11 f1 f1 read from F, CLUT address addr. 6 1 00 xx Sequence termination. 1 1 01 addr Read CLUT Address Register. 2 0 11 d1 d1 written into D, CLUT address addr. 3 0 11 e1 e1 written into E, CLUT address addr. 4 0 11 f1 f1 written into F, CLUT address addr. 6 0 11 d2 d2 written into D, CLUT address addr+1. 7 0 11 e2 e2 written into E, CLUT address addr+1. 8 0 11 f2 f2 written into F, CLUT address addr+1. 9 1 00 xx Sequence termination.

PRODUCT SPECIFICATION TMC22091/TMC22191

Related Products

• TMC22071 Genlocking V ideo Digitizer
• TMC2242/2243/2246 V ideo Filters
• TMC2249 V ideo Mixer
• TMC2255 Con volver
• TMC2272 Colorspace Converter
• TMC2302 Image Manipulation Sequencer Read/Modify/Write CLUT Location address 1 0 01 addr Write addr into the CLUT Address Register. 2 1 11 xx Set up for CLUT Read. 3 1 11 d1 d1 read from D, CLUT address addr. 4 1 11 e1 e1 read from E, CLUT address addr. 5 1 11 f1 f1 read from F, CLUT address addr.
• •• ••• ••• ••• System Modifies d1, e1, f1 to d1', e1', f1'. 6 0 01 addr Write addr into the CLUT Address Register. (terminates Read sequence) 7 0 11 d1’ d1' written into D, CLUT address addr. 8 0 11 e1’ e1' written into E, CLUT address addr. 9 0 11 f1’ f1' written into F, CLUT address addr. 10 1 00 xx Sequence termination.

Table 17. CLUT Read/Write Sequences (continued)

TMC22091/TMC22191 PRODUCT SPECIFICATION Notes:

PRODUCT SPECIFICATION TMC22091/TMC22191 Notes:

TMC22091/TMC22191 PRODUCT SPECIFICATION Mec hanical Dimensions – 84-Lead PLCC Package A .165 .200 4.19 5.08 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .090 .130 2.29 3.30 — —A2 .020 .51 B .013 .021 .33 .53 D/E 1.185 1.195 30.10 30.35 D1/E1 1.150 1.158 29.21 29.41 D3/E3 1.000 BSC 25.40 BSC .050 BSC 1.27 BSCe J .042 .056 1.07 1.42 2 ND/NE 21 21 84 84N ccc .004 0.10— — B1 .026 .032 .66 .81 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982. Corner and edge chamfer = 45°. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm). -C- A2 B LEAD COPLANARITY ccc C D E J A D3/E3 e JB1

PRODUCT SPECIFICATION TMC22091/TMC22191 Mec hanical Dimensions 100 Lead MQFP Package – 3.2mm Footprint Lead Detail A A2 B -C- Lead Coplanarity Seating Plane ccc C See Lead Detail E D B Pin 1 Indentifier e Base Plane R C L α Datum Plane 0° Min. .20 (.008) Min. .13 (.30) .005 (.012) .13 (.005) R Min. 0.076" (1.95mm) Ref A — .134 — 3.40 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .010 — .25 — .015 .38 A2 .100 .120 2.55 3.05 B .008 3, 5 .22 .009 .23C .005 .13 E .667 .687 16.95 17.45 .0256 BSC .65 BSCe L .028 .040 .73 1.03 100 100 30 30 N ND 20 20NE α 0° 7° 0° 7° — .004 — .12ccc D .904 .923 22.95 23.45 D1 .783 .791 19.90 20.10 E1 .547 .555 13.90 14.10 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982. Controlling dimension is millimeters. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. "L" is the length of terminal for soldering to a substrate. "B" & "C" includes lead finish thickness.

TMC22091/TMC22191 PRODUCT SPECIFICATION 6/12/98 0.0m 002 Stock# DS70022091

Ordering Information

Product Number Temperature Range Screening Package Package Marking TMC22091KHC TA = 0°C to 70°C Commercial 100-Lead MQFP 22091KHC TMC22091R0C TA = 0°C to 70°C Commercial 84-Lead PLCC 22091R0C TMC22191KHC TA = 0°C to 70°C Commercial 100-Lead MQFP 22191KHC TMC22191R0C TA = 0°C to 70°C Commercial 84-Lead PLCC 22191R0C