TMC22071AR1C

TMC22071A CADEKA | Alldatasheet

Document overview

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Technical content

Features

• Fully integrated acquisition
• 3-channel video input multiplexer
• Tw o-stage video clamp
• Automatic gain adjustment
• Sync detection and separation
• Pixel and subpixel adjustment of HSYNC-to-Video timing
• Genlock to NTSC or PAL inputs
• Clock generation
• 8-bit video A/D converter
• Microprocessor interface
• Line-locked pixel rates - 12.27 MHz NTSC - 13.5 MHz NTSC or PA L
• Direct interface to TMC22x9x encoders
• Built-in circuitry for crystal oscillator
• No tuning or external voltage reference required
• 68 Lead PLCC or 100 Lead MQFP package

Applications

• Frame grabber
• Digital VCR/VTR
• Desktop video

Description

The TMC22071A Genlocking V ideo Digitizer converts stan- dard baseband composite NTSC or PAL video into 8-bit dig- ital composite video data. It extracts horizontal and vertical sync signals and generates a pixel clock for the on-board 8-bit A/D converter and a 2x clock for the transfer of data to subsequent video processing decoding or encoding with the TMC22x5y V ideo Decoder or TMC22x9x Digital V ideo Encoder family. It also measures the color subcarrier phase and frequency and provides this data to the Encoder (for gen- locked color NTSC or PAL encoding), or a frame buffer (for frame capture) over the digital composite video port. The TMC22071A includes a three-channel video input mul- tiplexer, analog clamp, variable gain amplifier, and digital back porch clamp. The on-board oscillator circuitry gener- ates the clock from a 20 MHz crystal or the clock source may be an external oscillator. It is programmable over a micro- processor interface for NTSC or PAL operation. No external component changes and no production tuning or service adjustments are ever required. The TMC22071A is fabricated in an advanced CMOS process, and is packaged in a 68 Lead PLCC or 100 Lead MQFP . Its performance is guaranteed from 0°C to 70°C. Block Diagram VIN1 ANALOG CLAMP GAIN D/A GVSYNC GHSYNC PXCK 65-22071-01 LDV VALID CVBS 7-0 BACK PORCH CLAMP DATA SELECTOR SUBCARRIER PHASE-LOCKED LOOP SYNC SEPARATOR HORIZONTAL PHASE-LOCKED LOOP DIRECT DIGITAL SYNTHESIZER LOWPASS FILTER D/A +1.2V RESET D 0 CS R/W INT COMP CLK IN CLK OUT DDS OUT PFD IN PXCK SEL EXT PXCK C BYP VREF R B R T CONTROL MICROPROCESSOR INTERFACE ANALOG INTERFACE DDS/PIXEL CLOCK INTERFACE MUX VIN2 VIN3 A/D TMC22071A Genlocking Video Digitizer Rev. 1.0.5 www .cadeka.com

TMC22071A PRODUCT SPECIFICATION Functional Description The TMC22071A is a fully-integrated genlocking video A/D converter which digitizes NTSC or PAL baseband composite video under program control. It accepts video on three selectable input channels, adjusts gain, clamps to the back porch, and digitizes the video at a multiple of the horizontal line frequency. It extracts horizontal and vertical sync, mea- sures the subcarrier frequency and phase (relative to the sam- pling clock), and provides the data along with digital composite video data over an 8-bit digital video port. Two sync outputs (GHSYNC and GVSYNC ) are also provided. It generates 1x (LDV) and 2x (PXCK) pixel clocks for data transfer. PXCK also serves as a master clock for the compan- ion TMC22x9x Encoders and TMC22x5y decoders. Operating parameters are set up via a serial microprocessor port. Internal or external voltage reference operation is avail- able Timing The TMC22071A operates from an internally-synthesized clock, PXCK, which runs at twice the pixel data rate. The nominal pixel rates may be set to 12.27 Mpps for NTSC and 13.5 Mpps for NTSC and PAL. Customers requiring 14.75 or 15 Mpps PAL operation should consult factory. Video Input Three high-impedance video inputs are selected by an inter- nal multiplexer under host processor control. The device accepts industry-standard video levels of 1.23 V olts (sync tip to peak color = 1 volt sync tip to reference white). Good channel-to-channel isolation allows active video on all three inputs simultaneously. Antialiasing filtering (if used) and line termination resistors must be provided externally. The input selection is controlled by two bits in the Control Regis- ter. Analog Clamp The front-end analog clamp ensures that the input video falls within the active range of the A/D converter. The digitized composite video output can be clamped to the back porch by a secondary digital clamp. Automatic Gain Adjustment Since video signals may vary substantially from nominal lev- els, the TMC22071A performs an automatic level setting routine to establish correct signal amplitudes for digitizing. The TMC22071A relies upon the presence of the sync tip-to-back porch voltage to determine the gain required for the input video signal. Sync tip compression or clipping is often affected by APL (Average Picture Level) variation. Rather than tracking minor variations in sync tip amplitude and constantly adjust- ing video gain, the TMC22071A establishes proper signal amplitudes during initial genlock acquisition, and then (optionally) holds the gain constant. This results in a stable picture under variable signal conditions. Improperly terminated or weak video signals are handled in the TMC22071A by a selectable gain of +1.0 or +1.5. The higher gain can amplify a doubly-terminated signal which is reduced in amplitude by 2/3. If the input signal levels are well controlled, the automatic gain adjustment can be disabled and the gain held at its nom- inal value (unity or 1.5X). Analog-to-Digital Converter The TMC22071A contains a high-performance 8-bit A/D converter. Its gain and offset are automatically set as a part of the automatic gain adjustment process during initial signal acquisition, and require no user attention. The reference voltages to the A/D converter are set up by internal D/A converters under automatic control during gen- lock acquisition. These voltages determine the gain and off- set of the A/D converter with respect to the video level presented at its input. Low-Pass Filter The digitized composite video stream is digitally low-pass filtered to remove chrominance components from the sync separator. Filtering provides robust operation by optimizing the signal-to-noise ratio of the synchronizing/blanking por- tion of the video, improving the accuracy of the back porch blanking level detector. A digital sync separator provides the output sync signals, GHSYNC and GVSYNC , and times internal operations. Horizontal Phase-Locked Loop A phase-locked loop generates PXCK, at twice the pixel rate. The reference signal for the horizontal phase-locked loop is generated by the Direct Digital Synthesizer (DDS). The DDS output is constructed with an internal D/A con- verter and is output from the TMC22071A via the DDS OUT pin. This signal is passed through an external LC filter and input to the horizontal phase-comparator. The frequency of the DDS output is one ninth of that of PXCK. A 20 MHz clock is required to drive the DDS. Preferably, this may be input to the TMC22071A via CMOS levels on the CLK IN pin. Alternately, a 20 MHz crystal may be directly connected between CLK IN and CLK OUT with tuning capacitors to activate the internal crystal oscillator cir- cuitry. If incoming video is lost or disconnected after the TMC22071A has acquired and locked, PXCK, GHSYNC

PRODUCT SPECIFICATION TMC22071A GVSYNC and GRS data will continue. The GRS data will be the initial subcarrier frequency and phase values selected by the Format select bits of the Control Register. The TMC22071A will acquire and lock to incoming video within two frames after video is restored. Subcarrier Phase-Locked Loop A fully-digital phase-locked loop is used to extract the phase and frequency of the incoming color burst. These frequency and phase values are output over the CVBS bus during the horizontal sync period. Fairchild’s video decoder and gen- lockable encoder chips will accept these data directly. Back Porch Digital Clamp A digital back-porch clamp is employed to ensure a constant blanking level. It digitally offsets the data from the A/D con- verter to set the back porch level to precisely 3C h for NTSC and 40h for PAL. When the digital clamp is enabled, the CVBS video output data is determined from the A/D conver- sion result minus the back porch level + 3C h (40h for PAL). Digitized Video Output The digitized 8-bit video output is provided over an 8-bit wide CVBS data port, synchronous with PXCK and LDV . Subcarrier frequency, subcarrier phase, and Field ID data (GRS) are transmitted in 4-bit nibbles over CVBS 3-0 during the horizontal sync tip period at the PXCK rate. Microprocessor Interface Since microprocessor buses are notoriously noisy from a wide-band analog point of view, the microprocessor inter- face bus is only one bit wide, rather than the more customary eight. The operation of this bus is similar to other bus- controlled devices except that the TMC22071A internal Control Register is accessed one bit at a time. A sequence of 47 bits is written to or read from the LSB of a standard microprocessor port. Writing to or reading from the secondary address results in the transfer of data to or from the internal shift register. The RESET input, when LOW, sets all internal state machines to their initialized conditions. Returning the RESET pin HIGH starts the signal acquisition sequence which lasts until locking with the gain-adjusted and clamped video signal is achieved. Pin Assignments 65-22071-02 VDD CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 VDD DGND CVBS5 CVBS6 CVBS7 GHSYNC GVSYNC VALID D GND DGND LDV V DD PXCK DGND DGND VDD VDDA AGND VDDA VDDA AGND RB VIN3 VDDA VIN2 AGND VDDA VIN1 Pin Name Pin Name AGND RT AGND VREF AGND VDDA AGND CBYP PFD IN A GND DDS OUT PXCK SEL V DDA COMP A GND DGND CLK IN V DD CLK OUT EXT PXCK D GND DGND DGND VDD VDD R/W CS V DD RESET D GND INT D GND Pin Name Pin Name

TMC22071A PRODUCT SPECIFICATION Pin Assignments (continued) 65-22071-02B NC NC R/W CS V DD RESET D GND NC NC NC NC NC NC D GND INT V DD NC NC CVBS CVBS1 CVBS2 CVBS3 CVBS4 16* 13 0 5180 100 V DD DGND CVBS5 CVBS6 CVBS7 NC GHSYNC GVSYNC VALID NC NC NC D GND DGND LDV D GND VDD NC V DD PXCK D GND DGND VDD VDDA AGND 41* 42* Pin Name Pin Name VDDA VDDA NC NC A GND NC R B VIN3 NC V DDA VIN2 NC A GND VDDA VIN1 NC A GND RT AGND VREF NC A GND VDDA AGND CBYP NC PFD IN NC NC NC A GND DDS OUT NC NC NC PXCK SEL V DDA COMP A GND DGND CLK IN V DD CLK OUT EXT PXCK D GND DGND DGND VDD NC V DD 100 Pin Name Pin Name Notes: 1. NC = Do Not Connect. * These pins are not connected in the TMC22071A. However, you should connect these pins as shown for compatibility with future genlock ICs. Pin Definitions Pin Name Pin Number Pin Type Function 68 pin PLCC 100 pin MQFP Video Input V IN1-3 34, 31, 65, 61, 1.23Vp-p Composite Video Input. Video inputs,1.25 Volts peak-to-peak, sync tip to peak color Clocks CLK IN 51 91 CMOS 20 MHz DDS clock input. 20 MHz CMOS clock input to DDS. This pin may also be used along with CLK OUT for directly connecting crystals. CLK OUT 53 93 CMOS Inverted clock output. Inverted DDS clock output. This pin may also be used along with CLK IN for directly connecting a crystal. PXCK 19 45 CMOS 2x Pixel clock output. 2x oversampled line-locked clock output. LDV 17 40 CMOS Pixel clock output. Delayed pixel clock output. LDV runs at 1/2 the rate of PXCK and its rising edge is useful for transferring CVBS digital video from the TMC22071A to the TMC22x9x Digital Video Encoders. EXT PXCK 54 94 CMOS External PXCK input. Input for external PXCK clock source. PXCK SEL 46 86 CMOS PXCK source select. Select input for internal or external PXCK. When HIGH, the internally generated line-locked PXCK is selected. When LOW, the external PXCK source is enabled.

TMC22071A PRODUCT SPECIFICATION Digital Video GHSYNC 12 32 CMOS Horizontal sync output. When the TMC22071A is locked to incoming video, the GHSYNC pin provides a negative-going pulse after the falling edge of the horizontal sync pulse. There is a fixed number of PXCK clock cycles between adjacent falling edges of GHSYNC , except following a VCR headswitch. GVSYNC 13 33 CMOS Vertical sync output. When the TMC22071A is locked to incoming video, the GVSYNC pin provides a negative-going edge after the start of the first vertical sync pulse of a vertical blanking interval. CVBS 7-0 11-9, 6- 30-28, 25-21 CMOS Composite output bus. 8-bit composite video data is output on this bus at 1/2 the PXCK rate. During horizontal sync, field ID, subcarrier frequency, and subcarrier phase are available on this bus. mP l/O D 0 66 9 TTL Data l/O port. Microprocessor data port. All control parameters are loaded into and read back from the Control Register over this 1-bit bus. A 0 60 1 TTL mP port control. Microprocessor address bus. A LOW on this input loads the l/O Port Shift Register with data from D0 and CS. A HIGH transfers the l/O Port Shift Register contents into the Control Register on the last falling edge of CS CS 62 5 TTL Chip select. When CS is HIGH, D0 is in a high-impedance state and ignored. When CS is LOW, the microprocessor can read or write D0 data into the Control Register. RESET 64 7 TTL Master reset input. Bringing RESET LOW forces the internal state machines to their starting states, loads the Control Register with default values, and disables outputs. Bringing RESET HIGH restarts the TMC22071A in its default mode. R/W 61 4 TTL Bus read/write control. When R/W and A0 are LOW, the microprocessor can write to the Control Register over D0. When R/W is HIGH and A0 is LOW, the contents of the Status Register are read over D0. INT 67 17 TTL Interrupt output. This output is LOW if the internal horizontal phase lock loop is unlocked with respect to incoming video for 128 or more lines per field. After lock is established, INT goes HIGH. VALID 14 34 TTL HSYNC locked flag. This output, when HIGH indicates that incoming horizontal sync has been detected within the ±16 pixel window in time established by previous sync pulses. When LOW, it indicates that incoming horizontal sync has not been found within the expected time frame. VALID will toggle if the time stability of incoming video is such that sync positioning varies more than ±16 pixels or if occasional horizontal sync pulses are missing. Pin Definitions (continued) Pin Name Pin Number Pin Type Function 68 pin PLCC 100 pin MQFP

PRODUCT SPECIFICATION TMC22071A Analog Interface VREF 38 70 +1.23 V VREF input/output. +1.23 Volt reference. When the internal voltage reference is used, this pin should be decoupled to AGND with a 0.1 mF capacitor. An external +1.2 Volt reference may be connected here, overriding the internal reference source. COMP 48 88 0.1 mF Compensation capacitor. Compensation for DDS D/A converter circuitry. This pin should be decoupled to VDDA with a 0.1 mF capacitor. R T,RB 36, 28 68 0.1 mF A/D VREF decoupling. Decoupling points for A/D converter voltage references. These pins should be decoupled to AGND with a 0.1 mF capacitor. PLL Filter DDS OUT 45 82 Internal DDS output. Analog output from the internal Direct Digital Synthesizer D/A converter, at 1/9 the PXCK frequency. PFD IN 43 77 Horizontal PLL input. Analog input to the Phase/Frequency Detector of the horizontal phase-locked loop. C BYP 42 75 1 mF Comparator bypass. Decoupling point for the internal comparator reference of the Phase/Frequency Detector. This pin should be decoupled to A GND with a 0.1 mF capacitor. Power Supply V DDA 23, 25, 26, 30, 33, 40, 49, 51, 52, 60, 64, 73, +5 V Analog power supply. Positive power supply to analog section. V DD 1, 7,18, 22, 52, 58,59,63 6, 18, 26, 42, 44, 48, 92, 98, 100 +5 V Digital power supply. Positive power supply to digital section. Ground A GND 24, 27, 32, 35, 37, 39, 41, 44, 49, 50, 55, 63, 67, 69, 72, 74, 81, 0.0 V Analog ground. Ground for analog section. D GND 8, 15, 16, 20, 21, 50, 55-57, 65, 68 8, 16, 27, 38, 39, 41, 46, 47, 90, 95- 0.0 V Digital ground. Ground for digital section. Pin Definitions (continued) Pin Name Pin Number Pin Type Function 68 pin PLCC 100 pin MQFP

Figure 4. Control Register Map SRESET starts and runs state machines, PXCK, and enables outputs. 1-3 FORMAT Input signal format select. 4-6 TEST Factory test control bits. These should be set LOW. 7,8 SOURCE Video source select. Bit 8 is the MSB.

01 VIN2

9 VGAIN Video gain. When LOW, gain is set to unity. When HIGH, gain is set to 1.5X. 10-11 TEST Factory test control bits. These should be set LOW. 1/4 pixel. A value of 08h advances HSYNC 1/4 pixel.

PRODUCT SPECIFICATION TMC22071A 25 AGC AGC operation control. After H and V sync acquisition, the A/D converter references are adjusted to encompass the full video range. The system can initiate an A/D adjustment sequence at any time by bringing this bit HIGH. The control bit will reset to 0 following AGC adjustment. 26 FRERUN When HIGH, a free-running PXCK is generated, independent of incoming video. When LOW, PXCK is locked to incoming video. 27-29 TEST Factory test control bits. These should be set LOW. 30 VCR/TV Block sync enable. When HIGH the TMC22071A accepts both normal and block sync. (In block sync, the incoming signal is at the sync tip level for 2.5 (PAL) or 3 (NTSC) consecutive lines. Equalization pulses may be absent.) When LOW, only normal sync may be input. For most applications, whether using a VCR or a studio video input source, best performance will be found when this bit is HIGH. 31 CVBSEN CVBS bus enable. When LOW, the CVBS 7-0, GHSYNC , and GVSYNC outputs are in a high-impedance state. When HIGH, they are enabled. 32 TEST Factory test control bit. This should be set LOW.

33 BPFOUT

Burst phase / frequency output control. When HIGH, GRS is disabled. When LOW, burst phase and frequency information is output on CVBS3-0. 34 DCLAMP Digital clamp enable. The digital clamp is enabled when DCLAMP is HIGH and disabled when LOW. 35-39 TEST Factory test control bits. These should be set LOW. 40-43 STVAL Sync tip value. When DCLAMP is HIGH and STVAL is set to its default value 3 h the output sync level is 3h for NTSC and 7h for PAL. Bit 43 is the MSB. 44 VCR VCR lock control. Setting this bit LOW improves the TMC22071A’s locking to VCR signals. When only clean video input signals are used, the user may set this bit HIGH for compatibility with existing TMC22071 firmware. 45 TEST Factory test control bit. This should be set LOW. 46 GRSONLY When the horizontal phase lock loop becomes unlocked (i.e. after video input is disconnected) and this Control Bit is HIGH, all CVBS data is forced LOW except subcarrier frequency and phase data (GRS). GHSYNC , GVSYNC , and PXCK continue with default GRS data until video is required. The presence of GRS also depends upon bit 33. If the GRSONLY bit is LOW, GHSYNC , GVSYNC , and PXCK continue with default GRS data continue but video pixel data is random. Status Bits (Read Only) 47 COLOR Burst present status bit. This bit is HIGH when burst is present on the input video. It is LOW, when burst is not present. 48-55 BLKAMP Blanking amplitude status bit. These eight bits report the actual blanking level.

56 LOCK

H-lock loop status bit. When HIGH, the TMC22071A is not locked to an input signal. When LOW, lock has been achieved. 57-58 TEST These are read-only bits for testing puposes only. Control Register Bit Functions (continued) Bit Name Function

TMC22071A PRODUCT SPECIFICATION Absolute Maximum Ratings (beyond which the device may be damaged)1 Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range, and measured with respect to GND. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device. Operating Conditions (for standard temperature range) Note: 1. Timing reference points are at the 50% level. Parameter Min. Max. Unit. Power Supply Voltage -0.5 7.0 V Input Voltage -0.5 V DD + 0.5 V Digital Outputs Applied Voltage 2 -0.5 V DD + 0.5 V Forced Current3,4 -6.0 6.0 mA Short Circuit Duration (single output in HIGH state to GND) 1 sec Temperature Operating, Case -60 130 °C Operating, Junction 150 °C Lead Soldering (10 seconds) 300 °C Vapor Phase Soldering (1 minute) 220 °C Storage -65 150 °C Parameter Min. Nom. Max. Units V DD Power Supply Voltage 4.75 5.0 5.25 V VIH Input Voltage, Logic HIGH TTL Inputs 2.0 V DD V CMOS Inputs 2/3V DD VDD V VIL Input Voltage, Logic LOW TTL Inputs D GND 0.8 V CMOS Inputs D GND 1/3 VDD V IOH Output Current, Logic HIGH -2.0 mA lOL Output Current, Logic LOW 4.0 mA VIN Video Input Signal Level, Sync Tip to Peak White 1.0 V VREF External Reference Voltage 1.235 V TA Ambient Temperature, Still Air 0 70 °C Microprocessor Interface t PWHCS CS Pulse Width, LOW 50 ns tPWHCS CS Pulse Width, HIGH 50 ns tSA Address Setup Time 0 ns tHA Address Hold Time 16 ns tSD Data Setup Time 20 ns tHD Data Hold Time 0 ns

PRODUCT SPECIFICATION TMC22071A Electrical Characteristics (for standard temperature range) Note: 1. Typical IDD with VDD = +5.0 Volts and TA = 25°C, Maximum IDD with VDD = +5.25 Volts and TA = 0°C. Switching Characteristics (for standard temperature range) Parameter Conditions Min Typ Max Units IDD Power Supply Current1 Total Current VDD = Max, fPXCK = 30MHz 190 230 mA IREF Reference Inputcurrent V REF = +1.235V 100 mA IIH Input Current, Logic HIGH V DD = Max, VIN = 4.0V ±10 mA IIL Input Current, Logic LOW V DD = Max, VIN = 0.4V ±10 mA VOH Output Voltage, Logic HIGH I OH = -2.0 mA 2.4 V VOL Output Voltage, Logic LOW I OL = 4.0 mA 0.4 V IOZH Hi-Z Output Leakage current, HIGH V DD = Max, VIN = VDD ±10 mA IOZL Hi-Z Output Leakage current, LOW V DD = Max, VIN =GND ±10 mA C l Digital Input Capacitance T A = 25°C, f = 1 Mhz 4 15 pF C O Digital Output Capacitance T A - 25°C, f = 1 Mhz 10 pF C V Input Capacitance, VIN1-3 TA = 25°C, f = 3.58 Mhz 15 pF R V Input Resistance, VIN1-3 50 k W Parameter Conditlons Min Typ Max Units tDO Output Delay Time C LOAD = 35 pF 2 15 ns tHO Output Hold Time 3 8 ns fPCK Pixel Rate 12 15.3 MHz fPXCK Master Clock Rate 24 30.6 MHz tPWHPX PXCK Pulse Width, LOW 12 ns tPWHPX PXCK Pulse Width, HIGH 12 ns tDH Horizontal Sync to GHSYNC 14 pixels tVD Vertical Sync to GVSYNC 14 pixels tXL PXCK LOW to LDV HIGH 8 ns tXV PXCK LOW to LDV LOW 8 ns tDOM D 0 enable time 20 ns tHOM D 0 disable time 10 15 ns tDOZ CS LOW to D0 output driven 5 ns

1. NTSC/PAL compliant black burst at nominal input level ±10%, frequencies nominal ±10 ppm.

Figure 17. Typical Interface Circuit

20 MHz, TTL

The TMC22071A is a complex mixed-signal VLSI circuit. Figure 18. Simple Anti-aliasing Filter

Figure 19. Group Delay Equalizer Filter crystal must be a 20 MHz “fundamental” type, not overtone. connections are shown in Figure 20. Table 4. Crystal Parameters Figure 20. Direct Crystal Connections

20 MHz

pins; DGND and AGND are digital and analog ground pins). tal supplies via a ferrite bead inductor on the analog lead. come from the same power source. processor are shared by the TMC22x9x and TMC22071A. Figure 21. TMC22x9x Interface Circuit

TMC22071A PRODUCT SPECIFICATION Printed Circuit Board Layout Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Wire-wrap is not an option. Overall system performance is strongly influ- enced by the board layout. Capacitive coupling from digital to analog circuits may result in poor picture quality. Con- sider the following suggestions when doing the layout: 1. Keep the critical analog traces (COMP,V REF , RT, RB , DDS OUT, PFD IN, CBYP , and VIN1-3) as short as pos- sible and as far as possible from all digital signals. The TMC22071A should be located near the board edge, close to the analog output connectors. 2. The digital power plane for the TMC22071A should be that which supplies the rest of the digital circuitry. A sin- gle power plane should be used for all of the V DD pins. If the analog power supply for the TMC22071A is the same as that of the system’s digital circuitry, power to the TMC22071A V DDA pins should be decoupled with ferrite beads and 0.1 mF capacitors to reduce noise. 3. The ground plane should be solid, nor cross-hatched. Connections to the ground plane should have very short leads. 4. Decoupling capacitors should be applied liberally to V DD pins. Remember that not all power supply pins are created equal. They typically supply adjacent circuits on the device, which generate varying amounts of noise. For best results, use 0.1mF capacitors in parallel with 10mF capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice. 5. If the digital power supply has a dedicated power plane layer, it should not overlap the TMC22071A, the voltage reference or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the TMC22071A and its related analog circuitry can degrade performance. 6. CLK should be handled carefully. Jitter and noise on this clock or its ground reference may degrade perfor- mance. Terminate the clock line carefully to eliminate overshoot and ringing.

Related Products

• TMC22x9x Digital Video Encoders
• TMC2242/TMC2243/TMC2246 Video Filters
• TMC2081 Digital Video Mixer
• TMC22x5y Digital Decoders
• TMC2302 Image Manipulation Sequencer

PRODUCT SPECIFICATION TMC22071A Notes:

TMC22071A PRODUCT SPECIFICATION Notes:

PRODUCT SPECIFICATION TMC22071A Notes:

TMC22071A PRODUCT SPECIFICATION Mechanical Dimensions

68 Lead PLCC Package

-C-B LEAD COPLANARITY ccc C D D1 E J A D3/E3 e J A .165 .200 4.19 5.08 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .090 .130 2.29 3.30 ——A2 .020 .51 B .013 .021 .33 .53 D/E .985 .995 25.02 25.27 D1/E1 .950 .958 24.13 24.33 D3/E3 .800 BSC 20.32 BSC .050 BSC 1.27 BSCe J .042 .056 1.07 1.42 2 ND/NE 17 17 68 68N ccc .004 0.10—— B1 .026 .032 .66 .81 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982 Corner and edge chamfer (J) = 45¡ Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)

PRODUCT SPECIFICATION TMC22071A Mechanical Dimensions (continued) 100 Lead MQFP Package – 3.2mm Footprint Lead Detail AA 2 B -C- Lead Coplanarity Seating Plane ccc C See Lead Detail E D B Pin 1 Indentifier e Base Plane R C L a Datum Plane 0¡ Min. .20 (.008) Min. .13 (.30) .005 (.012) .13 (.005) R Min. 0.076" (1.95mm) Ref A — .134 — 3.40 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .010 — .25 — .015 .38 A2 .100 .120 2.55 3.05 B .008 3, 5 .22 .009 .23C .005 .13 E .667 .687 16.95 17.45 .0256 BSC .65 BSCe L .028 .040 .73 1.03 100 100 30 30 N ND 20 20NE a 0¡ 7¡ 0¡ 7¡ — .004 — .12ccc D .904 .923 22.95 23.45 D1 .783 .791 19.90 20.10 E1 .547 .555 13.90 14.10 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982. Controlling dimension is millimeters. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. "L" is the length of terminal for soldering to a substrate. "B" & "C" includes lead finish thickness.

TMC22071A PRODUCT SPECIFICATION 7/24/98 0.0m 002 Stock#DS7022071A

Ordering Information

Note: 1. 100 Lead MQFP is strongly recommended for all new board designs. Product Number Temperature Range Screening Package Package Marking TMC22071AR1C TA = 0°C to 70°C Commercial 68-Lead PLCC 22071AR1C TMC22071AKHC 1 TA = 0°C to 70°C Commercial 100-Lead MQFP 22071AKHC