TMC2192

TMC2192 CADEKA | Alldatasheet

Document overview

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Technical content

Features

• Multiple input formats – 20 bit CCIR601 – 10 bit CCIR656 – 10 bit Digital Composite
• Synchronization modes – Master – Slave – Genlock – CCIR656
• Subcarrier modes – Free-run – Subcarrier reset – Genlock – DRS-lock
• Ancillary Data Control (ANC)
• Pixel rates from 10 MHz to 15 MHz
• Programmable horizontal timing
• Programmable vertical blanking interval (VBI)
• Line-by-line pedestal enable
• Programmable pedestal height from -20 IRE to 20 IRE
• Programmable burst amplitude and phase
• Controlled edge rates for – Sync – Burst – Active video
• Programmable color space matrix
• 8:8:8 video reconstruction
• Three 10 bit D/A’s with independent trim
• Individual power down modes for each D/A
• Multiple output formats – S-video – Composite – Digital composite output
• Pin-driven and data-driven, window keying
• Closed Caption waveform generation (13.5 MHz only)
• Sin(X)/X compensation filter
• 5 bit VBI line counter
• 3 bit field counter
• Internal test pattern generation – 100% Color Bars – 75% Color Bars – Modulated Ramp

Applications

• Broadcast Television
• Nonlinear Video Processing TMC2192

10 Bit Encoder

PD[23:0] OL[4:0] CVBS[9:0] Gain Adjustment KEY FVHGEN PXCK HSIN VSIN DCVEN\\ HSOUT VSOUT LINE[4:0] FLD[2:0] PDCIN/PDCOUT MPU RESET SERB D[7:0] A[1:0]/SA[1:0] CS/SCL R/W\\/SDA VREF C BYPCOMP CBYPLUMA CBYPLUMA DAC REF. U V Y OVERLAY MIXER LUMA CHROMA COMPOSITE RREF COMP RREFCHROMA RREF LUMA Chroma Modulator CC 2194001a INTERP. INTERP. INTERP. y cb cr www.cadeka.com

TMC2192 PRODUCT SPECIFICATION 2 REV. 1.0.0 8/13/03 Table of Contents Serial Interface Read/Write Examples . . . . 31 System Performance Characteristics . . .63

TMC2192 PRODUCT SPECIFICATION 4 REV. 1.0.0 8/13/03 Pin Assignments Pin Definitions Pin Name Pin Number Value Description CLOCK, SYNC, & CONTROL INPUTS (6 pins) DCVEN 57 TTL Digital CVBS Output Enable. When DCVEN is LOW, the Comp2 output prior to the D/A is routed to D7-0, FLD2-1 providing a digital composite output. When DCVEN is HIGH, D7-0 and FLD2-1 operate in their normal mode. HSIN 56 TTL Horizontal Sync Input. When operating in slave, Genlock, or DRS-Lock the TMC2192 will start a new horizontal line with each falling edge of HSIN KEY 20 TTL Hard Key selection. When the control register bit HKEN is set HIGH and the hardware KEY pin is high, the video data considered to be the foreground. is routed to the COMP2 output. This control signal is data aligned so that the pixel that is present on the PD port when KEY signal is latched is at the midpoint of the key transition. When HKEN is LOW, Key is ignored. PD1 PD0 DGND VDD VSIN HSIN DCVEN SER CS\\/SCL R/W\\/SDA A1/SA1 A0/SA0 D DGND VDD PDC HSOUT VSOUT LINE4 LINE3 LINE2 LINE1 LINE0 V DDA COMP C BYPCOMP AGND CHROMA C BYPCHROM VDDA RREFCHROM AGND LUMA C BYPLUMA VDDA RREFLUMA AGND AGND VDDA VDDA AGND AGND KEY OL OL3 OL2 OL1 OL0 DGND PD23 PD22 PD21 PD20 31 50 65-6294-14 100 81 Pin Function Pin Function PD PD18 PD17 PD16 PD15 PD14 PD13 PD12 VDD DGND PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 Pin Function Pin 100 Function FLD2 FLD1 FLD0 CVBS9 CVBS8 CVBS7 CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1 CVBS0 RESET PXCK V DD DGND VREF RREFCOMP AGND

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 5 PXCK 95 TTL Pixel Clock Input. PXCK is a clock signal that period is twice the sample rate of the pixel data. The operating range is 20 to 30 MHz. The clock is internally divided by 2 to generate the internal pixel clock, PCK. PXCK drives the entire TMC2192 except the asynchronous microprocessor interface. RESET 94 TTL Master Chip Reset. When LOW, All outputs are tri-stated and the internal state machines and control registers are reset. At rising edge of RESET , all outputs are active, the preset values will be loaded into the control registers and the internal states machines start to operate. VSIN 55 TTL Vertical Sync Input. When operating in slave, Genlock, or DRS-Lock the TMC2192 will start a new vertical field with each falling edge of VSIN that is coincident with HSIN. SYNC & CONTROL OUTPUTS (11 pins) FLD[2:0] 81 –83 TTL Field Identifier. Field Identifier outputs the current field number. For all video standards the field identifier will cycle through the eight counts. HSOUT 74 TTL Horizontal Sync Output. The alignment of HSOUT to the pixel data port or DCVBS port is controlled by control register TSOUT. LINE[4:0] 76 –80 TTL Vertical Blanking Interval Line Identifier. LINE identifies the current line number for the first 31 lines. If the line count is greater than 31 then LINE is 11111b. The first line with a vertical serration is considered to be line 0. PDC 73 TTL Pixel Data Control. When PDCDIR = LOW: At a rising edge, The next pixel starts a controlled ramp of the PD data. At a falling edge, the pixel prior is the last PD used in the ramp. The rising edge is determined by the PDCCNT control register, the falling edge of PDC is determined by the horizontal timing registers. When PDCDIR = HIGH: PDCIN is used to override the internal PDC. When HIGH, the internal PDC controls the blank and unblank window. When LOW, the video remains blanked regardless of the internal PDC. All edges have the same ramp control as the internal PDC. VSOUT 75 TTL Vertical Sync Output. The alignment of VSOUT to the pixel data port or DCVBS port is controlled by control register TSOUT. DATA INPUTS (39 pins) CVBS[9:0] 84 –93 TTL Composite Data Input OL[4:0] 21 –25 TTL Overlay Control PD[23:0] 27 –38, 41–52 TTL Component Data Input ANALOG INTERFACE – Video Out (5 pins) LUMA 10 1.35Vp-p Luma CHROMA 5 1.35Vp-p Chroma COMP 2 1.35Vp-p Composite D/A with optional keying Pin Definitions (continued) Pin Name Pin Number Value Description

TMC2192 PRODUCT SPECIFICATION 6 REV. 1.0.0 8/13/03 ANALOG INTERFACE – Support (9 pins) CBYPLUMA 11 0.1 µF Reference Bypass Capacitor for LUMA DAC. Connection point for 0.1 µF Capacitor. CBYPCHROM 6 0.1 µF Reference Bypass Capacitor for CHROMA DAC. Connection point for 0.1 µF Capacitor. CBYPCOMP 3 0.1 µF Reference Bypass Capacitor for COMPOSITE DAC. Connection point for 0.1 µF Capacitor. RREFLUMA 13 1210 Ohm Current Setting Resistor. Connection point for external current setting resistor for LUMA DAC. The resistor is connected between R REFLUMA and GND. Output video levels are inversely proportional to the value of RREF2. RREFCHROM 8 1210 Ohm Current Setting Resistor. Connection point for external current setting resistor for CHROMA DAC. The resistor is connected between R REFCHROM and GND. Output video levels are inversely proportional to the value of RREFCHROM. RREFCOMP 99 1210 Ohm Current Setting Resistor. Connection point for external current setting resistor for COMPOSITE DAC. The resistor is connected between R REFCOMP and GND. Output video levels are inversely proportional to the value of RREFCOMP. VREF 98 1.235 V Voltage Reference Input. External voltage reference input, internal voltage reference output, nominally 1.235V. MPU INTERFACE (13 pins) A[1:0]/S A[1:0] 61, 62 TTL When SER (HIGH), OLUT/control/pointer address. When SER (LOW), SA[1:0] of serial chip address SA[6:0]. CS/SCL 59 TTL/R-BUS When SER (HIGH), microprocessor port clock. When SER (LOW), serial bus clock. D[7:0] 63 –70 TTL Bi-directional Data Bus. RW/SDA 60 TTL/R-BUS When SER (HIGH), read/write control. When SER (LOW), serial bus bi-directional data. SER 58 TTL Microprocessor Select. When LOW, the serial interface is enabled. When HIGH, the parallel interface is enabled. POWER & GROUND (17 pins) A GND 4, 9, 14, 15, 18, 19, 100 0.0V Analog ground DGND 26, 40, 53, 71, 97 0.0V Digital ground VDD 39, 54, 72, 96 +5.0V Digital positive power supply VDDA 1, 7, 12, 16, 17 +5.0V Analog positive power supply Pin Definitions (continued) Pin Name Pin Number Value Description

Figure 1. Input Formats Figure 2. 24 Bit Input Format

0 Y909

1. INMODE = 01, PD[23:14] = YC BCR running at 27MHz.

point in the multiplexed CB, Y , CR Y , D1 data stream.

cients, Table 1 summarizes the gain for each coefficient. processing block and prior to the sync and pedestal insertion. The blank, pedestal, and sync values are given as a reference. Table 4 gives the default coefficients values for the CSM. Table 1. CSM Coefficient Range MCF2 0 to 1 11 bit coefficient. MCF3 0 to 1 11 bit coefficient. Table 2. Expected Output Values for the CSM with YCBCR Inputs

these are master, slave, genlock, 656 mode, and DRS-Lock. embedded into the data stream. sync mode or in a MPEG style field toggle mode. either the CBVS port or the pixel data port. Figure 7. Propagation Delay through the Encoder

start of the first vertical serration. spective of the corresponding values of VBIENF. will occur on the next four pixels following the toggle point. video region and are controlled by PDRM control register. Table 3. PDC Edge Control

00 The following four pixels have the weighting of

01 The fifth pixel is sampled and scaled 1/8, 1/2,

10 MHz and 15 MHz can be accommodated, and any desired

register, and PCK is the pixel clock period. Table 4. Horizontal Line Equations

1. XBP, VA, VC, and VB are 10 bit values. The 2 MSBs for these four variables are in Timing Register 2D.
2. EH and SL are 9 bit values. A most significant "1" is forced by the TMC2192 since EH and SL must range from 256 to 511.

EH and SL may be extended to 767. Only the eight LSBs are stored in Timing Registers 29 and 2A.

1. Every calculated timing parameter has a minimum value of 5 except EH and SL which have minimum values of 256.

register, which dictates the field and line sequence. Figure 12. NTSC Vertical Interval Table 7. Default Horizontal Timing Parameters

• ••
• •• 282 283 284 285 HSOUT VSOUT (TOUT = 1) 65-6294-15 VSOUT (TOUT = 0) HSOUT VSOUT (TOUT = 1) VSOUT (TOUT = 0)

Table 8. NTSC Field/Line Sequence and Identification

4 SS 03 266 ES 01 4 SS 03 266 ES 01

5 SS 03 267 SS 03 5 SS 03 267 SS 03

6 SS 03 268 SS 03 6 SS 03 268 SS 03

7 EE 00 269 SE 02 7 EE 00 269 SE 02

8 EE 00 270 EE 00 8 EE 00 270 EE 00

9 EE 00 271 EE 00 9 EE 00 271 EE 00

10 UBB 0D 272 EB 10 10 UBB 0D 272 EB 10

19 UBB 0D … UBB 0D 19 UBB 0D … UBB 0D

20 UBB 0D 282 UBB 0D 20 UBB 0D 282 UBB 0D

21 UVV 0F 283 UBV 0E 21 UVV 0F 283 UBV 0E

22 UVV 0F 284 UVV 0F 22 UVV 0F 284 UVV 0F

263 UVE 0C 525 UVV 0F 263 UVE 0C 525 UVV 0F

264 EE 00 1 EE 00 264 EE 00 1 EE 00

265 EE 00 2 EE 00 265 EE 00 2 EE 00

Figure 13. PAL Vertical Interval

-VE Half-line video, half-line equalization pulse, color burst suppressed. Table 9. PAL Field/Line Sequence and Identification

1 SS 03 313 ES 01 1 SS 03 313 ES 01

2 SS 03 314 SS 03 2 SS 03 314 SS 03

3 SE 02 315 SS 03 3 SE 02 315 SS 03

4 EE 00 316 EE 00 4 EE 00 316 EE 00

5 EE 00 317 EE 00 5 EE 00 317 EE 00

7 UBB 0D 319 UBB 0D 7 UBB 0D 319 -BB 05

22 UBB 0D … UBB 0D 22 UBB 0D … UBB 0D

23 UBV 0E 334 UBB 0D 23 UBV 0E 334 UBB 0D

25 UVV 0F 336 UVV 0F 25 UVV 0F 336 UVV 0F

26 UVV 0F 337 UVV 0F 26 UVV 0F 337 UVV 0F

309 UVV 0F 622 -VV 07 309 UVV 0F 622 UVV 0F

311 EE 00 624 EE 00 311 EE 00 624 EE 00

312 EE 00 625 EE 00 312 EE 00 625 EE 00

Figure 14. PAL-M Vertical Interval

• •• 271 279 280 281 259258 260 FIELDS 4 AND 8 -VVU V V - V E E EE EE SS SS SS EE EE EE B UBB UBB UBB UBV UVV 261 262 263 264 265 266 267 268 269 270 •••
• •• 271 279 280 281 521 522 FIELDS 1 AND 5 UVV UVV EE EE EE SS SS SS EE EE EE -BB UBB-BB UBB UVV 5 2 3 5 2 4 5 2 5 123456 789 •••
• •• 521 522 FIELDS 3 AND 7 U V V - V V E EE EE ES SS SS SE EE EE E -BB UBBUBB UBB UVV 5 2 3 5 2 4 5 2 5 123456 789 •••
• •• HSOUT VSOUT (TOUT = 1) VSOUT (TOUT = 0) HSOUT VSOUT (TOUT = 1) VSOUT (TOUT = 0) HSOUT VSOUT (TOUT = 1) VSOUT (TOUT = 0) HSOUT VSOUT (TOUT = 1) VSOUT (TOUT = 0)

-VE Half-line video, half-line equalization pulse, color burst suppressed. Table 10. PAL-M Field/Line Sequence and Identification

1 SS 03 263 ES 01 1 SS 03 263 ES 01

2 SS 03 264 SS 03 2 SS 03 264 SS 03

3 SS 03 265 SS 03 3 SS 03 265 SS 03

4 EE 00 266 SE 02 4 EE 00 266 SE 02

5 EE 00 267 EE 00 5 EE 00 267 EE 00

6 EE 00 268 EE 00 6 EE 00 268 EE 00

9 UBB 0D 271 UBB 1D 9 UBB 0D 271 UBB 1D

17 UBB 0D 279 UBB 0D 17 UBB 0D 279 UBB 0D

261 EE 00 522 -VV 07 260 -VE 04 522 UVV 0F

524 EE 00 262 EE 00 524 EE 00

525 EE 00 525 EE 00

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 21 Chrominance Processor Control registers for this section: Subcarrier Programming The color subcarrier is produced by an internal 32 bit digital frequency synthesizer which is completely programmable in frequency and phase. Separate registers, FREQx, SYSPHx, BSTPHx, are provided for phase adjustment of the color burst and of the active video, permitting external delay com- pensation, color adjustment, etc. FREQx is the subcarrier phase step per pixel and SYSPHx is phase offset at field 1, line 1 (line 4 for NTSC), pixel 1. NTSC Subcarrier For NTSC encoding, the subcarrier synthesizer frequency has a simple relationship to the pixel clock period, repeating over 2 lines: The decimal value for the subcarrier phase step is: Where the number of pixels/line is: This value must be converted to binary and split into four 8 bit registers, FREQM, FREQ2, FREQ3, and FREQL. PAL Subcarrier The PAL relationship is more complex, repeating only once in 8 fields (the well-known 25 Hz offset): This value must be converted to binary and split as described previously for NTSC. The number of pixels/line is found as in NTSC. PAL-M Subcarrier SYSPHx establishes the appropriate phase relationship between the internal synthesizer and the chroma modulator. The nominal value for SYSPHx is zero. Other values for SYSPHx must be converted to binary and split into two 8 bit registers, SYSPHM and SYSPHL. Burst Phase (BURPHx) sets up the correct relative NTSC modulation angle. The value for BURPH is: BURPHx = SYSPHx This value must be converted to binary and split into two 8 bit registers, BURPHM and BURPHL. Address Bit(s) Name 0x06 7-6 FORMAT 0x06 5-3 MODE 0x07 5 DDSRST 0x11 7 DRSSEL 0x18 6 GLKCTL1 0x18 5 GLKCTL0 0x3F 3 GAUSS_BYP 0x40 7-0 FREQL 0x41 7-0 FREQ3 0x42 7-0 FREQ2 0x43 7-0 FREQM 0x44 7-4 SYSPHL 0x45 3-0 SYSPHM 0x46 7-4 BURPHL 0x47 3-0 BURPHM 0x48 7-4 BRSTFULL 0x49 3-0 BRST1 0x4A 7-4 BRST2 FREQx 455 2⁄ pixels line⁄ PXCK Frequency FREQ 909 4⁄

Ancillary Data Control (ANC).

• Freerun At the rising edge of RESET the DDS starts to generate the subcarrier reference and will continue to freerun the subcar- rier. When setting the control register DDSRST is HIGH, the TMC2192 will reset the DDS to the SYSPH value on the next field 1, line 1 (line 4 for NTSC), pixel 1 occurrence and will reset this bit to be LOW. This allows the encoder to start with the correct SCH relationship. The phase of the subcar- rier reference will drift over time since a 32 bit accumulator has a error of ±0.5 Hz when generating the subcarrier refer- ence for NTSC 13.5 MHz.
• Subcarrier Reset At the rising edge of RESET the DDS starts to generate the subcarrier reference and will reset the DDS to the SYSPH value every field 1, line 1 (line 4 for NTSC), pixel 1 occur- rence. This enables the encoder to maintain the proper SCH relationship.
• Genlock The Genlock mode allows the TMC2192 to lock to a com- posite reference when used in conjunction with the TMC22071A Genlocking Video Digitizer. The TMC22071A produces a genlock reference signal (GRS) which contains field identification, PALODD status, relative phase and rela- tive frequency of the composite reference. The GRS is sam- pled on the CVBS bus 60 PXCK’s after the falling edge of HSIN . The phase and frequency values are used to update the DDS on a line to line basis, thus synchronizing the sub- carrier to an external composite reference.
• DRS-Lock The DRS-Lock mode allows the TMC2192 to lock its com- posite output to the decoded composite or S-video input of the TMC22x5y. The TMC22x5y produces a decoder refer- ence signal (DRS) which contains field identification, PAL- ODD status, relative phase and relative frequency of the composite or S-video input. The DRS is sampled on either the CVBS bus or the PD port, depending on DRSSEL, 60 PXCK’s after the falling edge of HSIN . The phase and fre- quency values are used to update the DDS on a line to line basis, thus synchronizing the subcarrier to an external com- posite reference.
• Ancillary Data Control (ANC) Subcarrier synchronization in ANC mode is covered in the Ancillary Data Control section of this data sheet. SCH Phase Error Correction SCH refers to the timing relationship between the 50% point of the leading edge of horizontal sync and the positive or negative zero-crossing of the color burst subcarrier refer- ence. SCH error is usually expressed in degrees of subcarrier phase. In PAL, SCH is defined for line 1 of field 1, but since there is no color burst on line 1, SCH is usually measured at line 7 of field 1. The need to specify SCH relative to a partic- ular line in PAL is due to the 25 Hz offset of PAL subcarrier frequency. Since NTSC has no such 25 Hz offset, SCH applies to all lines. The SCH relationship is important in the TMC2192 when two video sources are being combined or if the composite video output is externally combined with another video source. In these cases, improper SCH phasing will result in a noticeable horizontal jump of one image with respect to another and/or a change in hue proportional to the SCH error between the two sources. SCH phasing can be adjusted by modifying BURPH and SYSPH values by equal amounts. SCH is advanced/delayed by one degree by increasing/decreasing the value of BURPH and SYSPH by approximately B6 h. An SCH error of 15o is corrected with SYSPH and BURPH offsets of AAAh.

Table 11. Standard Subcarrier Parameters

288 enables it for the remainder of field 2. and fall times in all video standards. The TMC2192 includes a flexible closed-caption processor. is in a 13.5 MHz pixel rate. the offset shown in Table 16 to specify the line. may be automatically generated by setting CCPAR HIGH. ing that the CCDx registers are ready to accept data. The CC data is transmitted during the specified line. Table 13. Closed Caption Line Selection

274 EVEN 274-289

328 EVEN 328-343

1. P = odd parity bit, x = reserved bit will be ignored

bit 0 (B0, LSB) is odd parity for B7-1. TMC2192 ignores ancillary data. packet indicate the number of words in ancillary data. the TMC2192 assumes PHV = LOW. Table 14. Ancillary Data Format

present, the TMC2192 assumes FRV = LOW.

1. The F bit is part of the EAV timing reference code and tracks the F0 bit.

) and the ANCTREN bit in the control register. counter will continue to count as it does in basic mode. sending field data only once. Table 15. Ancillary Data Control – Phase Table 16. Ancillary Data Control Frequency Table 17. Field Identification and Subcarrier Reset Modes

and layering features is shown in Figure 21. Figure 20. Layering Engine super blacks in the overlay palette. half the luminance magnitude and chrominance magnitude. shadow boxes around overlaid text. Table 18. Layering and Keying Modes

0 PD OVERLAY OL4-0 CVBS KEY or Data Key

1 PD CVBS KEY or Data Key OVERLAY OL4-0

2 CVBS OVERLAY OL4-0 PD KEY or Data Key

3 CVBS PD KEY or Data Key OVERLAY OL4-0

each device having a unique address. SDA need to be pulled HIGH by external pull-up resistors. action as a start or stop sequence.

• Start signal
• Slave address byte
• Block Pointer
• Offset Pointer
• Data byte to read or write
• Stop signal When the serial interface is inactive (SCL and SDA are HIGH) communications are initiated by sending a start sig- nal. The start signal is a HIGH-to-LOW transition on SDA while SCL is HIGH. This signal alerts all slaved devices that a data transfer sequence is coming. The first eight bits of data transferred after a start signal com- prise a seven bit slave address and a single R/W bit. The R/W bit indicates the direction of data transfer, read from or write to the slave device. If the transmitted slave address matches the address of the device (set by the state of the SA1-0 input pins in Table 24), the TMC2192 acknowledges by bringing SDA LOW on the 9th SCL pulse. If the addresses do not match, the TMC2192 will not acknowledge. Data Transfer via Serial Interface For each byte of data read or written, the MSB is the first bit of the sequence. If the TMC2192 does not acknowledge the master device during a write sequence, the SDA remains HIGH so the mas- ter can generate a stop signal. If the master device does not acknowledge the TMC2192 during a read sequence, the encoder interprets this as “end of data”. Writing data to specific control registers of the TMC2192 requires that the 8 bit address of the control register of inter- est be written after the slave address has been established. This control register address is the base address for subse- quent write operations. The base address auto increments by one for each byte of data written after the data byte intended for the base address.

Figure 25. Serial Port Read/Write Timing Table 21. Serial Port Addresses

• Start signal
• Slave Address byte (R/W bit = LOW)
• Block Pointer (00)
• Offset Pointer
• Stop signal
• Start signal
• Slave Address byte (R/W bit = HIGH)
• Data byte from base address
• Data byte from (base address + 1)
• Data byte from (base address + 2)
• Data byte from (base address + 3)
• N O A C K Control Register Map

Table 22. Control Register Map Table 22. Control Register Map (continued)

1. For each register listed above, all bits not specified are

TMC2192 PRODUCT SPECIFICATION 36 REV. 1.0.0 8/13/03 Control Register Definitions (continued) Part Identification Register (0x02) 76543210 PARTID0 Reg Bit Name Description 02 7-0 PARTID0 (Read Only) 0x92 Revision Identification Register (0x03) 76543210 REVID0 Reg Bit Name Description 03 7-0 REVID0 Reads back the revision number of the part. Gamma Filters Register (0x04) 76543210 RESERVED RESERVED RESERVED RESERVED SRESET SKEN PDRM Reg Bit Name Description 04 7-4 RESERVED Set to Low 04 3 SRESET Software RESET. When LOW, resets internal state machines and disables outputs. When HIGH, state machines are active and outputs are enabled. 04 2 SKEN Data KEY Enable. When SKEN is LOW, Data keying is disabled. When SKEN is HIGH, Data keying is enabled. 04 1-0 PDRM Pixel Data Ramping Mode. Pixel Data weighting for the rising edge of active video. NTSC: 0 0 1/8 1/2 7/8 1 1 PAL: 0 1/8 3/8 5/8 7/8 1 1 00 Pixels are weighted on the edge.

01 Sample and hold the 5th pixel for the slope weighting

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 37 Control Register Definitions (continued) Input Format Register (0x05) 76543210 D10FF INMODE OMIX SOURCE Reg Bit Name Description 05 7 D1OFF YCBCR Input Formatting. When D1OFF is HIGH, 64 is subtracted from Y data path of the PD port. When D1OFF is LOW, pixel data is passed through. 05 6 Reserved Program Low 05 5-4 INMODE Input Mode Select. 00 24 bit YC BCR (4:4:4) PD[7:0] = Y PD[23:16] = C B PD[15:8] = CR 01 10 bit D1 (YC BCR) PD[23:14] = YC BCR at 27MHz 10 20 bit YC BCR (4:4:4) PD[9:0] = Y PD[23:14] = C BCR (at 27MHz) 11 20 bit YC BCR (4:2:2) PD[9:0] = Y PD[23:14] = C BCR 05 3-2 OMIX Overlay Mixer Select.

00 No mix – PD data is always passed

01 Hard mix – mixer performs a hard switch between PD and Overlay

10 Set1 mix – the pixel data has the following weighting on the

transition; 0, 1/2, 1

11 Set2 mix – the pixel data has the following weighting on the

transition; 0, 1/8, 1/2, 7/8, 1 05 1-0 SOURCE Video Input Select. Chooses from internal test patterns or pixel data port.

00 PD PORT

01 Modulated Ramp

10 INTERNAL COLOR BAR (75%)

11 INTERNAL COLOR BAR (100%)

TMC2192 PRODUCT SPECIFICATION 38 REV. 1.0.0 8/13/03 Control Register Definitions (continued) General Control Register (0x06) 76543210 FORMAT MODE PDCDIR TOUT TSOUT Reg Bit Name Description 06 7-6 FORMAT Video Format.

00 NTSC

01 PAL – B,G,H,I,N

10 PAL – M

11 Reserved

06 5-3 MODE Video Mode.

000 MASTER with free-running subcarrier

001 SLAVE with free-running subcarrier

010 CCIR656 with free-running subcarrier

011 GENLOCK with subcarrier phase and frequency locked to the GRS

information.

100 MASTER with subcarrier phase reset every 8 fields

101 SLAVE with subcarrier phase reset every 8 fields

110 CCIR656 with subcarrier phase reset every 8 fields.

111 DRS-Lock with subcarrier phase and frequency locked to the DRS

information. 06 2 PDCDIR PDC Directional Control. When PDC is LOW, the PDC pin is an output. When PDCDIR is HIGH, the PDC pin is an input that can override the internally generated PDC and blank the active video of a line. 06 1 TOUT External Sync Output Control. When TOUT = LOW, a MPEG style field toggle is the output on pin VSOUT When TOUT = HIGH, a traditional vertical sync is the output on pin VSOUT. 06 0 TSOUT External Sync Delay Control. When the TSOUT is LOW, HSOUT, VSOUT are delayed to match propagation delay through the chip. When TSOUT is HIGH, HSOUT, VSOUT are aligned with the incoming data on the PD port.

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 39 Control Register Definitions (continued) Horizontal Ancillary Data Control Register (0x07) 76543210 LDFID SKFLIP DDSRST RESERVED ANCFREN ANCPHEN ANCTREN Reg Bit Name Description 07 7 LDFID Field Lock Select. When LDFID is HIGH, the FLD[2:0] pins are used as inputs to lock the field the that the TMC2192 is encoding. 5 PXCK’s after the falling edge of HSIN the FLD[2:0] pins are sampled. When LDFID is LOW, the FLD[2:0] pins output the current field that is being encoded. 07 6 SKFLIP Soft Key Inversion. When SKFLP is LOW, the key generated by the data keying is a normal state. When SKFLP is HIGH, the key generated by the data keying is a inverted state. 07 5 DDSRST DDS Reset. By inserting a logic HIGH into this register the DDS accumulator is reset to SYSPH value at the start of the next field 1 and DDSRST is reset LOW. This enables the DDS to be reset when the encoder is operating with a free running subcarrier. 07 4-3 RESERVED 07 2 ANCFREN Ancillary Frequency Enable. When HIGH, the encoder gets subcarrier frequency data (FREQ3-0) from incoming ancillary data (in accordance with FRV bit). When LOW, FREQ3-0 registers contain the subcarrier frequency data. 07 1 ANCPHEN Ancillary Phase Enable. When HIGH, the encoder gets subcarrier phase offset data (SCHPHL and SCHPHM) from incoming ancillary data (in accordance with PHV bit). When LOW, a default value of 0000h is used for subcarrier phase. 07 0 ANCTREN Ancillary Timing Enable. When HIGH, the encoder decodes incoming ancillary data to determine video timing (FIELD and SVF). When LOW, the ancillary timing reference data is ignored. Ancillary Data ID Register (0x08) 76543210 ANCID Reg Bit Name Description 08 7-0 ANCID Ancillary Data Identification. Bits 7-0 determine the ancillary data identification. Bit 0 is an odd parity bit. The value in this register must match that of the incoming ancillary data.

TMC2192 PRODUCT SPECIFICATION 40 REV. 1.0.0 8/13/03 Control Register Definitions (continued) Keying/Overlay Engine Register (0x09) 76543210 HKEN BUKEN SKEXT DKDIS EKDIS FKDIS LAYMODE Reg Bit Name Description 09 7 HKEN Hardware KEY Enable. When LOW, the KEY pin is ignored. When HIGH, the KEY pin is enabled. 09 6 BUKEN Burst KEY Enable. When LOW, the output video burst is generated internally. When HIGH, the output video burst is taken from the CVBS port. 09 5 SKEXT Data KEY Operation Select. When LOW, data keying is allowed only during active video window. When HIGH, data keying is allowed during frame. 09 4 DKDIS Y Data KEY Disable. When LOW, Y input data is enabled for data keying. When HIGH, Y input data is ignored for data keying. 09 3 EKDIS C B Data KEY Disable. When LOW, CB input data is enabled for data keying. When HIGH, CB input data is ignored for data keying. 09 2 FKDIS CR Data KEY Disable. When LOW, CR input data is enabled for data keying. When HIGH, CR input data is ignored for data keying. 09 1-0 LAYMODE Layer Assignment Select. Mode BACKGND Source MIDGND Source Key FOREGND Source Key

0 PD OVERLAY 0L4-0 CVBS KEY

1 PD CVBS KEY OVERLAY OL4-0

2 CVBS OVERLAY OL4-0 PD KEY

3 CVBS PD KEY OVERLAY OL4-0

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 41 Control Register Definitions (continued) Key Value Register (0x0A) 76543210 DKEYMAX Reg Bit Name Description 0A 7-0 DKEYMAX Y Maximum Data Key Value. DKEYMAX is compared against the 8 MSB’s of Y channel. If DKEYMAX is greater or equal to Y and DKEYMIN less than Y then a match is signaled. Key Value Register (0x0B) 76543210 DKEYMIN Reg Bit Name Description 0B 7-0 DKEYMIN Y Minimum Data Key Value. DKEYMIN is compared against the 8 MSB’s of Y channel. If DKEYMAX is greater or equal to Y and DKEYMIN less than Y then a match is signaled. Key Value Register (0x0C) 76543210 EKEYMAX Reg Bit Name Description 0C 7-0 EKEYMAX CB Maximum Data Key Value. EKEYMAX is compared against the 8 MSB’s of CB channel. If EKEYMAX is greater or equal to CB and EKEYMIN less than CB then a match is signaled. Key Value Register (0x0D) 76543210 EKEYMIN Reg Bit Name Description 0D 7-0 DKEYMIN CB Minimum Data Key Value. EKEYMIN is compared against the 8 MSB’s of CB channel. If EKEYMAX is greater or equal to CB and EKEYMIN less than CB then a match is signaled

TMC2192 PRODUCT SPECIFICATION 42 REV. 1.0.0 8/13/03 Control Register Definitions (continued) Key Value Register (0x0E) 76543210 FKEYMAX Reg Bit Name Description 0E 7-0 FKEYMAX CR Maximum Data Key Value. FKEYMAX is compared against the 8 MSB’s of CR channel. If FKEYMAX is greater or equal to CR and FKEYMIN less than CR then a match is signaled. Key Value Register (0x0F) 76543210 FKEYMIN Reg Bit Name Description 0F 7-0 FKEYMIN CR Minimum Data Key Value. FKEYMIN is compared against the 8 MSB’s of CR channel. If FKEYMAX is greater or equal to CR and FKEYMIN less than CR then a match is signaled.

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 43 Control Register Definitions (continued) DAC Control Register (0x10) 76543210 COMPDIS CHROMADIS LUMADIS RESERVED RESERVED OLUTDIS RESERVED Reg Bit Name Description 10 7 COMPDIS Composite D/A Disable. When COMPDIS is LOW, the COMPOSITE D/A is enabled. When COMPDIS is HIGH, the COMPOSITE D/A is disabled. 10 6 CHROMADIS Chroma D/A Disable. When CHROMADIS is LOW, the CHROMA D/A is enabled. When CHROMADIS is HIGH, the CHROMA D/A is disabled. 10 5 LUMADIS LUMA D/A Disable. When LUMADIS is LOW, the LUMA D/A is enabled. When LUMADIS is HIGH, the LUMA D/A is disabled. 10 4-3 RESERVED Set to 0. 10 2 OLUTDIS Overlay LUT Disable. When OLUTDIS is LOW, the olut is enabled. When OLUTDIS is HIGH, the olut is disabled. 10 1-0 RESERVED Program Low

TMC2192 PRODUCT SPECIFICATION 44 REV. 1.0.0 8/13/03 Control Register Definitions (continued) DAC Control Register (0x11) 76543210 DRSSEL RESERVED COMP2DB SINEN REFSEL LUMDIS CHRMDIS BURSTDIS Reg Bit Name Description 11 7 DRSSEL DRS Selection. When DRSSEL is HIGH, PD[7:0] is routed to the DRS detection block. When DRSSEL is LOW, CVBS[9:2] is routed to the DRS detection block. 11 6 RESERVED Program Low 11 5 COMP2DB. Composite 2 Overflow Control. When COMP2DB is HIGH, the digital range of the composite sumer is 0 to 2047 with half the digital resolution. When COMP2DB is LOW, the digital output of the composite summer is 0 to 1023, all values exceeding 1023 or below 0 are clipped. 11 4 SINEN X/Sine(X) Filter Enable. When SINEN is LOW, the X/Sin(X) filter is bypassed. When SINEN is HIGH, the X/Sin(X) filter is used to compensate for the DAC roll-off at high frequencies. 11 3 RESERVED Program Low 11 2 LUMDIS Luma Disable. When LUMDIS is LOW, the luminance data on the composite data path is enabled. When LUMDIS is HIGH, the luminance data on the composite data path is disabled. 11 1 CHRMDIS Chroma Disable. When CHRMDIS is LOW, the chrominance data on the composite data path is enabled. When CHRMDIS is HIGH, the chrominance data on the composite data path is disabled. 11 0 BURSTDIS Burst Disable. When BURSTDIS is LOW, the burst is enabled. When BURSTDIS is HIGH, the burst is disabled.

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 45 Control Register Definitions (continued) VBI Ped Enable Register (0x14) 76543210 VBIPEDEM Reg Bit Name Description 14 7-0 VBIPEDEM VBI Pedestal Enable, Even Fields. VBIPEDEM is the bits 15-8 of VBIPEDE[15:0]. VBIPEDE controls the addition of pedestal on a line by line basis from line 10 in NTSC (VBIPEDE[0] = HIGH) to line 24 (VBIPEDE[14] = HIGH) in the EVEN field of NTSC. VBIPEDE[15] controls the pedestal from line 25 to line 263 inclusive. VBI Ped Enable Register (0x15) 76543210 VBIPEDEL Reg Bit Name Description 15 7-0 VBIPEDEL VBI Pedestal Enable, Even Fields. VBIPEDEL is the bits 7-0 of VBIPEDE[15:0]. VBIPEDE controls the addition of pedestal on a line by line basis from line 10 in NTSC (VBIPEDE[0] = HIGH) to line 24 (VBIPEDE[14] = HIGH) in the EVEN field of NTSC. VBIPEDE[15] controls the pedestal from line 25 to line 263 inclusive. VBI Ped Enable Register (0x16) 76543210 VBIPEDOM Reg Bit Name Description 16 7-0 VBIPEDOM VBI Pedestal Enable, Odd Fields. VBIPEDOM is the bits 14-7 of VBIPEDO[14:0]. VBIPEDO controls the addition of pedestal on a line by line basis from line 273 (VBIPEDE[0] = HIGH) to line 286 (VBIPEDE[13] = HIGH) in the ODD field of NTSC. VBIPEDO[14] controls the pedestal from line 287 to line 525 inclusive.

TMC2192 PRODUCT SPECIFICATION 46 REV. 1.0.0 8/13/03 Control Register Definitions (continued) VBI Ped Enable Register (0x17) 76543210 VBIPEDOL HVA Reg Bit Name Description 17 7-1 VBIPEDOM VBI Pedestal Enable, Odd Fields. VBIPEDOL is the bits 6-0 of VBIPEDO[14:0]. VBIPEDO controls the addition of pedestal on a line by line basis from line 273 (VBIPEDE[0] = HIGH) to line 286 (VBIPEDE[13] = HIGH) in the ODD field of NTSC. VBIPEDO[14] controls the pedestal from line 287 to line 525 inclusive. 17 0 HVA Horizontal and Vertical Sync Alignment. When HVA is LOW, the falling edge of HSIN and VSIN must occur just prior to the rising edge of PXCK to start an field 1. When HVA is HIGH, VSIN is allowed to vary from HSIN by ±32 pixels. Vertical Blanking Interval Enable Register (0x18) 76543210 Reserved GLKCTL1 GLKCTL0 VBIENF1 Reg Bit Name Description 18 7 Reserved 18 6 GLKCTL1 Genlock Control Register 1. When GLKCTL1 is LOW, the PALODD bit of the GRS stream is ignored. When GLKCTL1 is HIGH, the PALODD bit of the GRS stream controls the PALODD flip of the subcarrier. 18 5 GLKCTL0 Genlock Control Register 0. When GLKCTL0 is LOW, the Color Frame bit of the GRS stream is ignored. When GLKCTL0 is HIGH, the Color Frame bit of the GRS stream controls the field sequence in the FVHGEN. 18 4-0 VBIENF VBI Active Video Enable, Field 1. The value of VBIENF1 determines which line blanking stops and active line for EVEN fields in NTSC starting from line 4 to line 35 or an ODD fields for PAL starting from line 1 to line 32.

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 47 Control Register Definitions (continued) Vertical Blanking Interval Enable Register (0x19) 76543210 SHORT T512 HALFEN VBIENF2 Reg Bit Name Description 19 7 SHORT Test Register. Program LOW. 19 6 T512 EH/SL Offset Control Bit. When LOW, the true value of EH and SL is offset by 256. When HIGH, the true value of EH and SL is offset by 512. 19 5 HALFEN Half Line Enable. When LOW, half-line blanking occurs on line 283 (NTSC) or line 23 (PAL). When HIGH, line 283 (NTSC) or line 23 (PAL) is treated as a full line of active video. 19 4-0 VBIENF2 VBI Active Video Enable, Field 2. The value of VBIENF2 determines which line blanking stops and active line for ODD fields in NTSC starting from line 4 to line 35 or an EVEN fields for PAL starting from line 1 to line 32. Pedestal Height Register (0x1A) 76543210 Reserved PEDHGT1 Reg Bit Name Description 1A 7 Reserved 1A 6-0 PEDHGT1 Composite Pedestal Height. PEDHGT1 is a 2’s comp value producing a pedestal height from -22.1 IRE to 21.7 IRE with .345 IRE steps on the composite data path. The default 7.5 IRE pedestal for NTSC-M results from a hex code of 0010110b. Closed Caption Register (0x1C) 76543210 CCD1 Reg Bit Name Description 1C 7-0 CCD1 First Byte of CC Data. Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity Bit if CCPAR is HIGH.

TMC2192 PRODUCT SPECIFICATION 48 REV. 1.0.0 8/13/03 Control Register Definitions (continued) Closed Caption Register (0x1D) 76543210 CCD2 Reg Bit Name Description 1D 7-0 CCD2 Second Byte of CC Data. Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity Bit if CCPAR is HIGH Closed Caption Register (0x1E) 76543210 CCON CCRTS CCPAR CCFLD CCLINE Reg Bit Name Description 1E 7 CCON Enable CC Data Packet. Command the CC data generator to send either CC data or a NULL byte whenever the specified line is transmitted. 1E 6 CCRTS Request To Send Data. This bit is set HIGH by the user when bytes 0x1C and 0x1D have been loaded with the next two bytes to be sent. When the encoder’s line count reaches preceding the line specified in bits 4-0 of this register the data will be transferred from registers 0x1C and 0x1D, and RTS will be RESET LOW. A new pair of bytes may then be loaded into registers 0x1C and 0x1D. If CCON = 1 and CCRTS = 0 when the CC line is to be sent, NULL bytes will be sent. 1E 5 CCPAR Auto Parity Generation. When set HIGH, the encoder replaces the MSB of bytes 0x1C and 0x1D with a calculated ODD parity. When set LOW, the CC processor transmits the 16 bits exactly as loaded into registers 0x1C and 0x1D. 1E 4 CCFLD CC Field Select. When LOW, CC data is transmitted on the selected line of ODD fields. When HIGH, it is sent on EVEN fields. 1E 3-0 CCLINE CC Line Select. Defines (with an offset) the line on which CC data are transmitted. Timing Register (0x1F) 76543210 PDCNT Reg Bit Name Description 1F 7-0 PDCNT Pixel Data Control Start. PDCNT determines the number of pixels (PCK’s) from the midpoint of the falling edge of horizontal sync to the rising edge of PDC on active video lines.

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 49 Control Register Definitions (continued) Timing Register (0x20) 76543210 SY Reg Bit Name Description 20 7-0 SY Horizontal Sync Tip Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles. Timing Register (0x21) 76543210 BR Reg Bit Name Description 21 7-0 BR Breezeway Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles. Timing Register (0x22) 76543210 BU Reg Bit Name Description 22 7-0 BU Burst Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles. Timing Register (0x23) 76543210 CBP Reg Bit Name Description 23 7-0 CBP Color Back Porch Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles. Timing Register (0x24) 76543210 XBP Reg Bit Name Description 24 7-0 CBP Extended Color Back Porch Duration. This 8 bit register holds the LSB’s of a 10 bit value extending from 0 to 1023 PCK cycles.

TMC2192 PRODUCT SPECIFICATION 50 REV. 1.0.0 8/13/03 Control Register Definitions (continued) Timing Register (0x25) 76543210 VA Reg Bit Name Description 25 7-0 VA Active Video Region Duration. This 8 bit register holds the LSB’s of a 10 bit value extending from 0 to 1023 PCK cycles. Timing Register (0x26) 76543210 VC Reg Bit Name Description 26 7-0 VC Active Video Region 2nd Half Line Duration. This 8 bit register holds the LSB’s of a 10 bit value extending from 0 to 1023 PCK cycles. Timing Register (0x27) 76543210 VB Reg Bit Name Description 27 7-0 VB Active Video Region 1st Half Line Duration. This 8 bit register holds the LSB’s of a 10 bit value extending from 0 to 1023 PCK cycles. Timing Register (0x28) 76543210 VB Reg Bit Name Description 28 7-0 EL Equalization Pulse Low Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles.

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 51 Control Register Definitions (continued) Timing Register (0x29) 76543210 EH Reg Bit Name Description 29 7-0 EH Equalization Pulse High Duration. This 8 bit register holds 8 LSB’s of EH, The addition of 256 or 512 is controlled by T512. The range is either 256 to 511 PCK cycles or 512 to 767 PCK cycles. Timing Register (0x2A) 76543210 SL Reg Bit Name Description 2A 7-0 SL Vertical Sync Pulse Low Duration. This 8 bit register holds 8 LSB’s of SL, The addition of 256 or 512 is controlled by T512. The range is either 256 to 511 PCK cycles or 512 to 767 PCK cycles. Timing Register (0x2B) 76543210 SH Reg Bit Name Description 2B 7-0 SH Vertical Sync Pulse High Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles. Timing Register (0x2C) 76543210 FP Reg Bit Name Description 2C 7-0 FP Front Porch Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles.

TMC2192 PRODUCT SPECIFICATION 52 REV. 1.0.0 8/13/03 Control Register Definitions (continued) Timing Register (0x2D) 76543210 XBP VA VB VC Reg Bit Name Description 2D 7-6 XBP Extended Color Back Porch Duration. 2 MSB’s of the 10 bit XBP, extending from 0 to 1023 PCK cycles. 2D 5-4 VA Active Video Duration. 2 MSB’s of the 10 bit VA, extending from 0 to 1023 PCK cycles. 2D 3-2 VB Active Video Region 1st Half Line Duration. 2 MSB’s of a 10 bit VB, extending from 0 to 1023 PCK cycles. 2D 1-0 VC Active Video Region 2nd Half Line Duration. 2 MSB’s of a 10 bit VC, extending from 0 to 1023 PCK cycles. Timing Register (0x2E) 76543210 FIELD LTYPE Reg Bit Name Description 2E 7-5 FIELD Field Identification. (READ ONLY) These three bits are updated 12 PXCK periods after each vertical sync. They allow the user to determine field type on a continuous basis 2E 4-0 LTYPE LineType Identification (READ ONLY) These three bits are updated 5 PXCK periods after each horizontal sync. They allow the user to determine line type on a continuous basis. Timing Register (0x2F) 76543210 CBL Reg Bit Name Description 2F 7-0 CBL Color Bar Duration. This 8 bit register holds a value extending from 0 to 255 PCK cycles. Color Space Matrix Register (0x30) 76543210 MCF1L Reg Bit Name Description 30 7-0 MCF1L Matrix Coefficient #1. Bits 7-0 of MCF1.

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 53 Control Register Definitions (continued) Color Space Matrix Register (0x31) 76543210 RESERVED Reg Bit Name Description 31 7-0 RESERVED Program Low Color Space Matrix Register (0x32) 76543210 RESERVED Reg Bit Name Description 32 7-0 RESERVED Program Low Color Space Matrix Register (0x33) 76543210 MCF2L Reg Bit Name Description 33 7-0 MCF2L Matrix Coefficient #2. Bits 7-0 of MCF4. Color Space Matrix Register (0x34) 76543210 RESERVED Reg Bit Name Description 34 7-0 RESERVED Program Low Color Space Matrix Register (0x35) 76543210 MCF3L Reg Bit Name Description 35 7-0 MCF3L Matrix Coefficient #3. Bits 7-0 of MCF6.

TMC2192 PRODUCT SPECIFICATION 54 REV. 1.0.0 8/13/03 Control Register Definitions (continued) Color Space Matrix Register (0x36) 76543210 RESERVED Reg Bit Name Description 36 7-0 RESERVED Program Low Color Space Matrix Register (0x37) 76543210 RESERVED Reg Bit Name Description 37 7-0 RESERVED Program Low Color Space Matrix Register (0x38) 76543210 RESERVED Reg Bit Name Description 38 7-0 RESERVED Program Low Color Space Matrix Register (0x39) 76543210 RESERVED Reg Bit Name Description 39 7-0 RESERVED Program Low Color Space Matrix Register (0x3A) 76543210 MCF1M MCF2M Reg Bit Name Description 3A 7-4 MCF1M Matrix Coefficient #1. Bits 11-8 of MCF1. 3A 3-0 RESERVED Program Low

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 55 Control Register Definitions (continued) Color Space Matrix Register (0x3B) 76543210 MCF3M RESERVED MCF4M Reg Bit Name Description 3B 7-3 RESERVED Set to 0. 3B 2-0 MCF4M Matrix Coefficient #4. Bits 10-8 of MCF4. Color Space Matrix Register (0x3C) 76543210 MCF5M RESERVED MCF6M Reg Bit Name Description 3C 7-3 RESERVED Set to 0. 3C 2-0 MCF6M Matrix Coefficient #6. Bits 10-8 of MCF6. Color Space Matrix Register (0x3D) 76543210 RESERVED RESERVED Reg Bit Name Description 3D 7-4 RESERVED Program Low 3D 3-0 RESERVED Program Low Color Space Matrix Register (0x3E) 76543210 RESERVED RESERVED Reg Bit Name Description 3E 7-4 RESERVED Program Low 3E 3-0 RESERVED Program Low

TMC2192 PRODUCT SPECIFICATION 56 REV. 1.0.0 8/13/03 Control Register Definitions (continued) Color Space Matrix Register (0x3F) 76543210 SEL_CLK RESERVED GAUSS_BYP SEL_PIX C2DB_OFF NMEH CSMFMT Reg Bit Name Description 3F 7 SEL_PIX DCVBS Output Selection. When SEL_PIX is HIGH, the interpolated pixel data is selected as the output for the DCVBS port. When SEL_PIX is LOW, the non-interpolated pixel data is selected as the output for the DCVBS port. 3F 6 RESERVED Program Low 3F 5 GAUSS_BYP Gaussian Bypass Select. When GAUSS_BYP is LOW, the gaussian filter is enabled. When GAUSS_BYP is HIGH, the gaussian filter is bypassed. 3F 4 SEL_CLK DCVBS Clock Select. When SEL_CLK is LOW, the DCVBS output is clocked at the PXCK. When SEL_CLK is HIGH, the DCVBS output is clocked at the PCK. 3F 3 C2DB_OFF COMP2DB Offset Selection. When C2DB_OFF is HIGH an offset of 256 is added to the COMP2 output allowing the chrominance data that extends below the sync level to be passed through the outputs. 3F 2-0 RESERVED Program Low Subcarrier Register (0x40) 76543210 FREQL Reg Bit Name Description 40 7-0 FREQL Subcarrier Frequency. Bits 7-0 of the subcarrier frequency FREQL[31:0].

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 57 Control Register Definitions (continued) Subcarrier Register (0x41) 76543210 FREQ3 Reg Bit Name Description 41 7-0 FREQ3 Subcarrier Frequency. Bits 15-8 of the subcarrier frequency FREQL[31:0]. Subcarrier Register (0x42) 76543210 FREQ2 Reg Bit Name Description 42 7-0 FREQ2 Subcarrier Frequency. Bits 23-16 of the subcarrier frequency FREQL[31:0]. Subcarrier Register (0x43) 76543210 FREQM Reg Bit Name Description 43 7-0 FREQM Subcarrier Frequency. Bits 31-24 of the subcarrier frequency FREQL[31:0]. Subcarrier Register (0x44) 76543210 SYSPHL Reg Bit Name Description 44 7-0 SYSPHL System Phase. Bits 7-0 of the video phase offset SYSPH[15:0]. Subcarrier Register (0x45) 76543210 SYSPHM Reg Bit Name Description 45 7-0 SYSPHM System Phase. Bits 15-8 of the video phase offset SYSPH[15:0].

TMC2192 PRODUCT SPECIFICATION 58 REV. 1.0.0 8/13/03 Control Register Definitions (continued) Subcarrier Register (0x46) 76543210 BURPHL Reg Bit Name Description 46 7-0 BURPHL Burst Phase. Bits 7-0 of the burst phase offset BURPH[15:0]. Subcarrier Register (0x47) 76543210 BURPHM Reg Bit Name Description 47 7-0 BURPHM Burst Phase. Bits 15-8 of the burst phase offset BURPH[15:0]. Burst Height Register (0x48) 76543210 BRSTFULL Reg Bit Name Description 48 7-0 BRSTFULL Burst Height – Maximum Amplitude. The 8 bit value assigned to U burst component in NTSC and to the U and V components in PAL for the maximum burst amplitude. The burst envelopes midpoint is derived from BRSTFULL. The value programmed into BRSTFULL needs to be .707 of the magnitude of the burst vector. Burst Height Register (0x49) 76543210 BRST1 Reg Bit Name Description 49 7-0 BRST1 Burst Height – 1st Intermediate Value. The 8 bit value assigned to U burst component in NTSC and to the U and V components in PAL for the first intermediate value of the burst envelope. The value programmed into BRST1 needs to be .707 of the magnitude of the burst vector.

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 59 Control Register Definitions (continued) Subcarrier Register (0x4A) 76543210 BRST2 Reg Bit Name Description 4A 7-0 BRST2 Burst Height – 2nd Intermediate Value. The 8 bit value assigned to U burst component in NTSC and to the U and V components in PAL for the second intermediate value of the burst envelope. The value programmed into BRST2 needs to be .707 of the magnitude of the burst vector.

TMC2192 PRODUCT SPECIFICATION 60 REV. 1.0.0 8/13/03 Absolute Maximum Ratings (beyond which the device may be damaged) Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range, and measured with respect to GND. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device. Parameter Min. Max. Unit Power Supply Voltage -0.5 7.0 V Digital Inputs Applied Voltage 2 -0.5 V DD + 0.5 V Forced Current3,4 -20.0 20.0 mA Digital Outputs Applied Voltage 2 -0.5 V DD + 0.5 V Forced Current3,4 -20.0 20.0 mA Short Circuit Duration (Single Output in HIGH state to GND) 1 second Analog Output Short Circuit Duration (Single output to GND) In finite Temperature Operating, Ambient -20 +110 °C Operating, Junction, Plastic package +150 °C Lead, Soldering (10 seconds) +300 °C Vapor Phase Soldering (1 minute) +220 °C Storage -65 +150 °C Operating Conditions Parameter Min. Nom. Max. Units VDD Power Supply Voltage 4.75 5.0 5.25 V VIH Input Voltage, Logic HIGH TTL Compatible Inputs 2.0 V DD V CMOS Compatible Inputs 0.7V DD VDD V VIL Input Voltage, Logic LOW TTL Compatible Inputs GND 0.8 V CMOS Compatible Inputs GND 0.3V DD V IOH Output Current, Logic HIGH -2.0 mA IOL Output Current, Logic LOW 4.0 mA VREF External Reference Voltage 1.235 V IREF D/A Converter Reference Current (IREF = VREF / RREF, flowing out of the RREF pin) 1.020 mA RREF Reference Resistor, VREF = Nom. 1210 Ω ROUT Total Output Load Resistance 37.5 Ω TA Ambient Temperature, Still Air 0 70 °C Pixel Interface f PXL Pixel Rate 10 15 Mpps fPXCK Master Clock Rate, 2x pixel rate 20 30 MHz tPWHPX PXCK Pulse Width, HIGH 15 ns tPWLPX PXCK Pulse Width, LOW 17.5 ns

PRODUCT SPECIFICATION TMC2192 REV. 1.0.0 8/13/03 61 tSP Setup Time 16 ns tHP Hold Time 0 ns Parallel Microprocessor Interface t PWLCS CS Pulse Width, LOW 4 PXCK tPWHCS CS Pulse Width, HIGH 6 PXCK tSA Address Setup Time 17 ns tHA Address Hold Time 0 ns tSD Data Setup Time (write) 16 ns tHD Data Hold Time (write) 0 ns tSR RESET Setup Time 12 ns tHR RESET Hold Time 2 ns Serial Interface t DAL SCL Pulse Width, LOW 1.3 µs tDAH SCL Pulse Width, HIGH 0.6 µs tSTAH SDA Start Hold Time 0.6 µs tSTASU SCL to SDA Setup Time (Stop) 0.6 µs tSTOSU SCL to SDA Setup Time (Start) 0.6 µs tBUFF SDA Stop Hold Time Setup 1.3 µs tDSU SDA to SCL Data Setup Time 300 ns tDHO SDA to SCL Data Hold Time 300 ns Operating Conditions (continued) Parameter Min. Nom. Max. Units

TMC2192 PRODUCT SPECIFICATION 62 REV. 1.0.0 8/13/03

Electrical Characteristics

Notes: 1. Typical I DD with VDD = +5.0 Volts and TA = 25°C. 2. Timing reference points are at the 50% level. Switching Characteristics Notes: 1. Timing reference points are at the 50% level. 2. Analog C LOAD <10 pF, D7-0 load <40 pF. 3. Pipeline delay, with respect to PXCK, is a function of the phase relationship between the internally generated PCK (PXCK/2) and PXCK, as established by the hardware RESET. Symbol Parameter Conditions Min. Typ. Max. Units IDD Power Supply Current V DD = Max., fPXCK = 27MHz 335 375 mA IDDQ Power Supply Current (D/A disabled) VDD = Max., fPXCK = 27MHz 15 25 mA VRO Voltage Reference Output 1.235 V IBR Input Bias Current, VREF VREF = Nom. 50 µA IIH Input Current, Logic HIGH V DD = Max., VIN = VDD 10 µA IIL Input Current, Logic LOW V DD = Max., VIN = GND -10 µA VOH Output Voltage, Logic HIGH I OH = Max. 2.4 V VOL Output Voltage, Logic LOW I OL = Max. 0.4 V IOZH Hi-Z Leakage current, HIGH V DD = Max., VIN = VDD 10 µA IOZL Hi-Z Leakage current, LOW V DD = Max., VIN = GND -10 µA CI Digital Input Capacitance T A = 25°C, f = 1MHz 4 10 pF CO Digital Output Capacitance T A = 25°C, f = 1MHz 10 pF VOC Video Output Compliance Voltage -0.3 2.0 V ROUT Video Output Resistance 15 k Ω COUT Video Output Capacitance I OUT = 0 mA, f = 1 MHz 15 25 pF Parameter Conditions Min. Typ. Max. Units PIPES Pipeline Delay PD to Analog Out PD to DCVBS PXCK Periods tDOZ Output Delay, CS to low-Z 4 15 ns tDOM Output Delay, CS to Data Valid 15 ns tHOM Output Hold Time, CS to hi-Z 10 ns tDO Output Delay PXCK to HSOUT, VSOUT, PDC, LINE, FLD 15 ns tR D/A Output Current Risetime 10% to 90% of full-scale 2 ns tF D/A Output Current Falltime 90% to 10% of full-scale 2 ns tDOV Analog Output Delay 10 ns

TMC2192 PRODUCT SPECIFICATION 64 REV. 1.0.0 8/13/03 Layout Considerations Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Wire-wrap is not an option. Overall system performance is strongly influ- enced by the board layout. Capacitive coupling from digital to analog circuits may result in poor picture quality. Con- sider the following suggestions when doing the layout:

• Keep analog traces (C BYPx, VREF, RREF, DACx) as short and far from all digital signals as possible. The TMC2192 should be located near the board edge, close to the analog output connectors.
• The power plane for the TMC2192 should be separate from that which supplies other digital circuitry. A single power plane should be used for all of the V DD pins. If the power supply for the TMC2192 is the same for the system's digital circuitry, power to the TMC2192 should be filtered with ferrite beads and 0.1µF capacitors to reduce noise.
• The ground plane should be solid, not cross-hatched. Connections to the ground plane should be very short.
• Decoupling capacitors should be applied liberally to pins. For best results, use 0.1µF capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice.
• If there is dedicated digital power plane, it should not overlap the TMC2192 footprint, the voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the TMC2192 and its related analog circuitry can have an adverse effect on performance.
• The PXCK should be handled carefully. Jitter and noise on this clock or its ground reference will translate to noise on the video outputs. Terminate the clock line carefully to eliminate overshoot and ringing.
• Connect all unused inputs to the TMC2192 to either ground or V DD. Do not leave them unconnected.

Figure 30. Typical Layout

Figure 31. ST-163E Layout

TMC2192 PRODUCT SPECIFICATION 68 REV. 1.0.0 8/13/03 Mechanical Dimensions 100-Lead MQFP Lead Detail AA 2 B -C- Lead Coplanarity Seating Plane ccc C See Lead Detail E D B Pin 1 Indentifier e Base Plane R C L α Datum Plane 0° Min. .20 (.008) Min. .13 (.30) .005 (.012) .13 (.005) R Min. 0.076" (1.95mm) Ref A — .134 — 3.40 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .010 — .25 — .015 .38 A2 .100 .120 2.55 3.05 B .008 3, 5 .22 .009 .23C .005 .13 E .667 .687 16.95 17.45 .0256 BSC .65 BSCe L .028 .040 .73 1.03 100 100 30 30 N ND 20 20NE α 0° 7° 0° 7° — .004 — .12ccc D .904 .923 22.95 23.45 D1 .783 .791 19.90 20.10 E1 .547 .555 13.90 14.10 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982. Controlling dimension is millimeters. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. "L" is the length of terminal for soldering to a substrate. "B" & "C" includes lead finish thickness.

TMC2192 PRODUCT SPECIFICATION 8/13/03 0.0m 002 Stock#DS30002192

Ordering Information

Product Number Temperature Range Screening Package Package Marking TMC2192KHC TA = 0°C to 70°C Commercial 100-pin MQFP TMC2192KHC