TMC2081 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

  • Mixes 24//16-bit GBR/YC B C R 444//YC B C R 422 and 8-bit color-index sources
  • 24//16-bit GBR/YC B C R 444//YC B C R 422 output
  • 255-step proportional mixing via a 7-0 inputs
  • 256-step mixing with a 8-0 for a =100h unity gain
  • 256 x 8-bit look-up table on a channel
  • Lap-dissolve and fade effects a and crosspoint controls for soft and color-border wipe generation
  • Mask register and three 256 x 8 bypassable CLUTs with overlay on A-channel
  • Analog preview output with sync on Green/Y
  • D/A power-down modes
  • Single +5 volt power supply operation
  • Pin compatible with TMC22080 Digital Mixer

Applications

  • Mixing computer graphics and live video
  • Lap-dissolve between video sources
  • Fade to black or to user-selectable fill color
  • Window/wipe processing

Description

The TMC2081 is a Digital Video Mixer that performs M = ( a V + ( 1- a V (for 0 a cross-fading at speeds faster than 40 Mpps proportionally controlled by a 9-bit a -channel input. Variable rate dissolves and fades may be implementedwith unity gain at the a end- points. With the a -Look-Up Table ( a LUT), mixing may be controlled by a single bit of the a -channel input. Setup is via a microprocessor interface. Supported video formats are 24-bit GBR, YC B C R 444, and 16-bit YC B C R 422 component video. Dissimilar pixel for- mats may be mixed using on-chip interpolation and decima- tion filters and GBR/YC B C R and YC B C R /GBR color-space conversion matrices. An additional format accepted by the A-channel is 8-bit color-indexed pixel data which addresses three bypassable 256 x 8 color look-up tables (CLUTs). A 15 color overlay palette and a 24-bit fill register are also included. Digital and Analog outputs may be programmed to view either mixer inputs, V or V or mixer output, M. Packaged in a 128-lead plastic metric quad flat-pack (MQFP), the TMC2081 is fabricated with a sub-micron CMOS process. Performance is guaranteed over the com- mercial, 0 C to 70 C temperature range. TMC2081 Digital Video Mixer Rev. 1.3.0 Logic Symbol PDA 23-0 PDB 23-0 OL 3-0 M 23-0 D 7-0 D 2-0 SMX 2-0 SYNC BLANK AV DATA INPUTS VIDEO OUTPUTANALOG OUTPUTS D/A SETUP TIMING INPUTSOVERLAY & CONTROL ANALOG TIMING MICRO- PROCESSOR INTERFFACE PASSEN a8-0 SIG0 65-2081-01 CLK TMC2081 DIGITAL VIDEO MIXER SIG14 AVOUT G/Y COMP B/CB VREF R REF R/CR PASS14 CS R/W

TMC2081 PRODUCT SPECIFICATION Block Diagram Register a Register Delay Delay Delay Unity Gain Switch A Register/ Formatter 256x8x3 CLUT Source Select Fill Register Crosspoint Switch Triple Dual Input 9-bit a-Mixer 444 422 Formatter 65-2081-02 M 23-0 B/CB R/CR G/Y SIG14 SYNC BLANK CLK SMX 2-0 D 7-0 A2-0 CS R/W PDA 23-0 PDB 23-0 OL 3-0 a8-0 SIG0 PASS14PASSEN AVOUTAV RGB YCbC r Matrix YC bC r RGB Matrix YC bC r RGB Matrix DAC Formatter 2's OSB M M A B A B F D/A D/A D/A REF A B 444 422 Decimator/ Filter 422 444 Interpolator/ Filter Mask Register B Register/ Formatter Delay (2/15 clock) Microprocessor Interface 15x8x3 Overlay Table a LUT VREF RREF COMP

format combinations are shown in Table 1.

  1. The B-channel path includes circuits that
  2. Prior to mixing, incoming pixel data streams

B channel control registers. by the control bits programmed into the internal registers. may be accessed through a microprocessor interface. sections of the TMC2081 via internal Control Registers. locations are not accessible. Table 1. Input and Output Data Format Examples Table 2. GBR Mixing Example (9-bit

444 Bypass Bypass Bypass Bypass Bypass Low YC

422 Bypass Bypass Bypass Enable Bypass Low YC

422 Bypass Bypass Enable Bypass Bypass High YC

422 Bypass Bypass Bypass Bypass Bypass High YC

000 BB CC AA EE FF DD EE FF DD

040 BB CC AA EE FF DD E1 F2 D0

080 BB CC AA EE FF DD D5 E6 C4

100 BB CC AA EE FF DD BB CC AA

Table 3. YCB C R 422 Mixing Example (CB and CR in 2’s Complement) Table 4. YCB C R 422-to-YCB C R 444 Mixing Example

  1. 8-bit color-index mapped to a palette of 256x256x256

Formats with the expected data ranges are shown in Table 5. Table 5. YCB C R and GBR Data Types and Figure 1. Pixel Data Formats

(from offset binary to 2’s complement) by MSB inversion. passing incoming pixel data directly to subsequent circuits. and V2 mixer input formats must match CLUT formats. sponding color which is selected at the RGB/YCB C R matrix. OL 3-0 may be changed on a pixel-by-pixel basis. Table 6. A-Channel GBR-to-YCB C R Mapping format matches that of the A-channel prior to mixing. of the A and B-channels are matched. 0.06 dB. Minimum stopband rejection is 41 dB. 7-0 address a 256 x 8-bit lookup table (aLUT). register 0. For 8-bit a mixing, set a8 = 0. the D7-0 microprocessor port. Table 7. B-Channel YCB C R -GBR Mapping for

Table 8. Alpha Channel Gains Three registers, 03, 04, and 05, store a solid fill color, F. at the input to the crosspoint switch. 1 and V2 inputs of the a-Mixer. Rate of dissolve is controlled directly through the a-channel. selected by the crosspoint switch. tion becomes evident at the output, M. to 256/256 and B-channel gain is set to 0/256. shadow effects can be implemented. latencies of the a-, A- and B-channels are matched. phase and frequency data from upstream video processors. The 444-to-422 formatter may be bypassed for 24-bit output. mat, the formatter needs to be enabled.

  • Y C B C R 444
  • Y C B C R 422
  • GBR

Table 10. GBR DAC Transfer Characteristic Sample outputs are listed in Table 11 and Table 12. Table 11. YCrCb DAC Transfer Characteristic Table 12. YCrCb DAC Transfer Characteristic remain partially executed by keeping a-values constant. 422 format and outputting data in 422 or 444 format. B C R or GBR pixel pair at the input of the mixer. The YCB C R 444 output is mixed at the full a rate. the even values that are synchronous with CR data. with mixing at the M23-0 outputs tracking both Y and CB C R . Table 13. Microprocessor Port Address Map

000 RAM Address Register for CLUT, aLUT, and

001 Directs RAM R/W operations selected by the

010 Reserved

011 RAM Address Register for CLUT, aLUT, and

100 Reserved

101 Directs Control Register R/W operations

110 Mask Register (Default: Load with FF)

111 Control Address Register

Table 14. Control Address Register Bit

7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

00 A-channel CLUT

01 A-channel Overlay palette

10 Reserved

  1. To read the a-LUT, Control Register 06h, bit 5 must be
  2. To read the CLUT and Overlay Table, Control Register
  3. Data may be written to the CLUT or aLUT with Control

Register bits set to enable or bypass.

  1. When writing to the a-LUT, the address pre-increments.
  2. Load mask register to pass PDA data.

The TMC2081 operates from a single +5 V olt power supply. Table 15. Control Register Read/Write Sequences

Table 16. CLUT Read/Write Sequences 1 0 111 0x Selects A-CLUT for write. 2 0 000 00 Presets RAM Address Register to 00. 4 0 001 g0 g0 written into green (G/Y) CLUT address 00. 768 0 001 r255 r255 written into red (R/C R ) CLUT address FF. 769 0 001 g255 g255 written into green (G/Y) CLUT address FF. 1 0 111 4x Select A-channel Overlay. n Write an into RAM Address Register. 3 0 001 r n rn written into red (R/CR ) CLUT address. 4 0 001 g n gn written into green (G/Y) CLUT address. 5 0 001 b n bn written into blue (B/CB) CLUT address. 3 0 001 aa Write aa to aLUT location 00. 258 0 001 zz Write zz, to aLUT location FF. 1 0 111 C6 Select aLUT and Register 06 in Address Control Register. 2 1 101 aa Read Control Register 06. bb = (aa OR 20h) to set bit 5. 3 0 101 bb Restores aa with aLUT enabled. 4 0 011 00 Write 00 into RAM Address Register (sets address to 00). 5 1 001 cc Read contents of aLUT, cc, from location 00. 260 1 001 zz Read contents of aLUT, zz, from last location FF.

PRODUCT SPECIFICATION TMC2081 Pin Assignments

128 Pin Plastic Quad Flat Pack (PQFP) Package

A SIG0 PASSEN AV OL VDD D GND OL 2 OL 1 OL 0 PDA 23 PDA 22 PDA 21 PDA 20 PDA 19 PDA 18 PDA 17 PDA 16 PDA 15 PDA 14 PDA 13 PDA 12 128 97 34 64 PDA 11 PDA 10 PDA 9 PDA 8 PDA 7 PDA 6 PDA 5 PDA 4 PDA 3 PDA 2 PDA 1 PDA 0 VDD D GND SMX 2 SMX 1 SMX 0 CLK BLANK SYNC VREF R REF AGND 65-2081-06 Pin Name Pin Name R/CR B/CB AGND G/Y COMP VDDA VDDA PDB 23 PDB 22 PDB21 PDB20 PDB19 PDB18 PDB17 PDB16 PDB15 PDB14 PDB13 PDB12 PDB11 PDB10 PDB9 PDB8 PDB7 PDB6 PDB5 PDB4 PDB3 PDB2 PDB1 PDB0 M23 M 22 M 21 M 20 M 19 M 18 M 17 M 16 D GND VDD M 15 M 14 M 13 M 12 M 11 M 10 M 9 M 8 M 7 M 6 M 5 M 4 M 3 M 2 M 1 M 0 AVOUT PASS14 SIG14 D GND VDD D 7 D 6 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Pin Name Pin Name

TMC2081 PRODUCT SPECIFICATION Pin Descriptions Name Pin Number Value Pin Function Description Clock CLK 59 TTL Clock Input. TTL-compatible clock. All pixel data is registered on the rising edge of CLK. CLK synchronizes the flow of pixel data through the TMC2081 and the operation of the a-input. Pixel I/O PDA 23-0 21-44 TTL A-Channel Pixel Inputs. A-channel pixel inputs are registered on the rising edge of CLK and specify which of the CLUT locations are addressed after masking. The CLUT in the A-Channel may be bypassed. PDA 7-0 are applied to all three CLUT sections when color- index pixel data is used. PDB 23-0 72-95 TTL B-Channel Pixel Inputs. B-channel pixel inputs are registered on the rising edge of CLK and are applied to the mixer after color-space conversion, and interpolation, if selected. a 8-0 45,46,49-55 TTL a-Channel Inputs. The a-channel inputs are registered on the rising edge of CLK and control proportional mixing at pixel rates up to 40 Mpps. a 8 acts as a key input, switching A- and B-channel pixel data on a pixel-by-pixel basis. a0 is the LSB. SMX 2-0 56-58 TTL ABF Crosspoint Mux Control. When enabled by setting the SMX Control Register bits to 111, these inputs control the ABF Crosspoint Switch which directs the A- or B-channel pixels or the fill color register values to the V 1 or V2 inputs to the mixer. SMX2-0 input pins are ignored when the SMX Control Register bits are not 111. SMX2-0 are registered on the rising edge of CLK. ABF Crosspoint Switch control is according to the following: OL 3-0 15,18-20 TTL Overlay Inputs. Overlay inputs select one of 15 overlay colors from the PDA overlay palette. OL3-0 are registered on the rising edge of CLK. When PDA or overlay is enabled and OL3-0 > 0, the contents of the addressed palette are selected in place of the pixel data. Overlay is inactive when OL 3-0 = 0h or when disabled via the Control Registers. OL 0 is the LSB. M 23-0 96-103, 106-121 TTL Mixed Pixel Outputs. Mixer output or digital preview of the V1 and V2 Crosspoint Switch outputs are synchronized to the rising edge of CLK. M 23-0 date is passed on for further processing (mixing, encoding, etc.). Pipeline latency is 14 clock cycles. SMX 2-0 V1 V2

000 A B

001 A F

010 B A

011 B F

100 F A

101 F B

PRODUCT SPECIFICATION TMC2081 Video Controls PASSEN 13 TTL Pass Enable Input. Data selected by A/BPASS is enabled by PASSEN . SIG0 12 TTL Signal 0 Input. Input to a 14 CLK delay. Output is at SIG14. PASS14 123 TTL Pass Enable Output (14 Clock Delay). PASSEN delayed by 14 CLK cycles to match the pipeline latency of pixels SIG14 124 TTL Signal 0 Output (14 Clock Delay). SIG0 delayed to match the 14 CLK cycles pipeline latency of pixels AV 14 TTL Active Video Input. When HIGH, AV enables data from the PDA and PDB ports. When LOW, at the M23-0 output, GBR data is set to zero and YCBC R data is set to 10h 80h 80h in the offset binary format and 10h 00h 00h in 2’s complement format. In the 422 mode, AV transitioning HIGH defines the next pixel to be the first CB pixel. AVOUT 122 TTL Delayed AV Output. AV delayed by either 12 or 14 clock cycles. A 14 clock cycle delay matches the pipeline delay of the A and B channels. A 12 clock cycle delay is useful for interfacing with Fairchild Encoders. SYNC 61 TTL Sync Enable for G/Y D/A. D/A Converter sync enable. SYNC= LOW, disables a current source at the G/Y output, forcing the sync tip to zero volts. SYNC = HIGH, activates the sync current at the G/Y output. SYNC is delayed either 2 or 15 clock cycles according to the status of the DACDLY bit. To disable sync on G/Y, ground SYNC. BLANK 60 TTL Blanking Control for D/As. D/A Converter blanking input. BLANK = LOW disables the data and pedestal output currents. If BLANK = HIGH, data and pedestal currents are added to the SYNC current. BLANK is delayed either 2 or 15 clock cycles according to the status of the DACDLY bit. For blank levels, see Tables 9, 10, 11, and 12. Microprocessor I/O R/W 8 TTL Read/Write Control. Read-Write control input. R/W controls the direction of the D7-0 port. If R/W = HIGH and CS is LOW, registers or CLUTs may be read. If R/W = LOW and CS = LOW, data may be written to control registers or CLUTs via the D7-0 port. R/W is latched on the falling edge of CS. CS 7 TTL Chip Select. Chip Select Input. If CS = HIGH, port, D7-0, is set to high- impedance. If CS = LOW, port D7-0 is enabled. Read data (R/W = HIGH) is enabled on the falling edge of CS. Write data is latched into the TMC2081 on the rising edge of the CS. CLUT, aLUT, or overlay read/write operations require CS to be HIGH for at least 4 CLK cycles after CS = LOW. A2-0 11-9 TTL Register Select Controls. Address bits input. A2-0 select registers or tables to be accessed (see Table 13) via D7-0. A2-0 are latched on the falling edge of CS. D 7-0 127,128, 1-6 TTL Data I/O Port. Bi-directional data port. D0 is the LSB. Control Registers, CLUT, aLUT and Overlay locations are accessed via D7-0. Video Output G/Y 68 1 V P-P Green/Luminance Video. The green/luminance analog video output. Sync pulses are included on this output. B/C B 66 0.7 V P-P Blue/CB Video. Blue/CB analog video output. R/CR 65 0.7 V P-P Red/CR Video. Red/CR analog video output. Pin Descriptions (continued) Name Pin Number Value Pin Function Description

TMC2081 PRODUCT SPECIFICATION Reference VREF 62 +1.23 V Voltage Reference Input/Output. An internal voltage source of +1.2 Volts (nominal) is applied to the VREF terminal. This is the reference for all three D/A converters of the TMC2081. Decoupling VREF to AGND with a 0.1mF ceramic capacitor is recommended. This pin may also be used as an input for an external voltage reference source. R REF 63 681 W Current-Setting Resistor. Full-scale output current of the TMC2081 is determined by the value of the resistor connected between RREF and AGND . Varying this resistor will vary the “white” output level for all three D/A converters. The TMC2081 is not designed for operation with an external current reference. COMP 69 0.1 mF Compensation Capacitor. A 0.1 mF ceramic capacitor is connected between the COMP and V DDA at pin 70 or 71. Power, Ground V DDA 70,71 +5 V Analog Power Supply. The TMC2081 operates from a single +5V supply. All power pins must be connected. VDDA and VDD must be derived from a common power supply. VDD 16,47,105,126 +5 V Digital Power Supply. The TMC2081 operates from a single +5V supply. All power pins must be connected. VDDA and VDD must be derived from a common power supply. AGND 64,67 0.0 V Analog Ground. All ground pins must be connected. D GND 17,48,104,125 0.0 V Digital Ground. All ground pins must be connected. Pin Descriptions (continued) Name Pin Number Value Pin Function Description

PRODUCT SPECIFICATION TMC2081 Control Register Map Reg Bit Name Function A-Channel Control Register 00 7 AOVLEN A-channel Overlay enable/disable 00 6 ADEC Decimator bypass/enable 00 5 AMAT A-channel GBR-to-YC BC R bypass/enable 00 4 CLUT Bypass/enable CLUT (power down) 00 3 AMSB Inverts C B/CR MSB 00 2 aGAIN Alpha Channel 9-/8-bit gain 00 1-0 AFORMAT A Pixel data path setup (4 formats) B-Channel/Mixer Control Register 01 7 Reserved 01 6-5 MSOURCE M 23-0 pixel source 01 4 BMAT Bypass/enable the B- channel YCBC R -to-GBR 01 3 BINT Bypass/enable Interpolator 01 2 BMSB Inverts C B/CR MSB 01 1-0 BFORMAT B Pixel data path setup (4 formats) Mixer Control Register 02 7 MIXFMT Mixer format select 02 6-5 DSOURCE Selects data source for the internal D/A converters 02 4-2 SMX Chooses video source to be directed to the mixer imputs, V 1 and V2 02 1-0 MIXTFN Used to alter the mixer transfer function Fill Color Registers 03 7-0 REDVAL Value for Red/C R 04 7-0 GRNVAL Value for Green/Y 05 7-0 BLEVAL Value for Blue/C B Control Register Definitions Output Control Register 06 7 AVPIPE Sets pipeline latency of AV 06 6 Reserved 06 5 aLUTEN aLUTEN power down enable 06 4 PASSON Sets pixel activity subject to mixer transfer function 06 3 A/BPASS Selects A or B data in PASSON mode 06 2 MOUT Bits M 23-0 enable 06 1 MMSB Inverts C B, CR MSBs 06 0 MFORMAT Sets output data format D/A Control Register 07 7-6 Reserved 07 5 DACDLY Selects SYNC and BLANK pipe delay 07 4 DACFMT C B/CR translate from 2’s complement to offset binary 07 3 AWAKE D/A converters enable/ disable 07 2 SETUP Sets IRE blanking levels 07 1 Reserved 07 0 DMAT D/A converter input data YC BC R /GBR conversion Identification (read-only) 08 7-0 REVID Chip revision ID 09 7-0 CHIPID Chip type ID = 2F Reg Bit Name Function

TMC2081 PRODUCT SPECIFICATION Control Register Definitions (continued) A-Channel Control Register (00) 76543210 AOVLEN ADEC AMAT CLUT AMSB aGAIN AFORMAT Reg Bit Name Description 00 7 AOVLEN When HIGH, the Overlay palette in the PDA pixel path is enabled and controlled by the OL3-0 inputs. When LOW, the PDA Overlay palette is disabled. 00 6 ADEC When HIGH, this bit causes A-channel pixel data to be decimated from YC BC R 444 to YCBC R 422 format. When LOW, no decimation takes place and the data is passed through. 00 5 AMAT When HIGH, the A-channel pixel data is converted from GBR to YC BC R format. When LOW, no conversion takes place and the data is passed through. 00 4 CLUT When HIGH, the A-channel CLUT is enabled and addressed by pixel data. When LOW the CLUT is bypassed. 00 3 AMSB When LOW,the MSBs of the A-channel C B and CR (PDA15 and PDA7) are passed though. When HIGH, the MSBs of the CB and CR are inverted. 00 2 aGAIN a-channel gain. LOW selects 9-bit unity gain. HIGH selects 8-bit gain. For 8-bit a mixing, set a8 = 0. 00 1-0 AFORMAT These two bits set up the A channel data path to accommodate four different formats: 0 0 YC BC R 444 0 1 YCBC R 422 1 0 8-bit color index 1 1 24-bit GBR B-Channel Control Register (01) 76543210 Reserved MSOURCE BMAT BINT BMSB BFORMAT Reg Bit Name Description 01 7 Reserved. 01 6-5 MSOURCE Source of pixels to be connected to port M 23-0. 0 0 Mixer Pixels 0 1 A pixels 1 0 B pixels 1 1 Reserved 01 4 BMAT When HIGH, the B-channel pixel data is converted from YC BC R to GBR format. When LOW, no conversion takes place and the data is passed through. 01 3 BINT When HIGH, B-channel pixel data is interpolated from the YC BC R 422 to the YC BC R 444 format. When LOW, no interpolation takes place and the data is passed through. 01 2 BMSB When LOW, the MSBs of the B-channel C B and CR bytes (PDB15 and PDB7) are passed through. When HIGH, the MSBs of the CB and CR bytes are inverted. 01 1-0 BFORMAT B-channel pixel data format select bits. 0 0 YCBC R 444 0 1 YCBC R 422 1 0 Reserved 1 1 24-bit GBR

PRODUCT SPECIFICATION TMC2081 Control Register Definitions (continued) Fill Color Registers (03–05) Mixer Control Register (02) 76543210 MIXFMT DSOURCE SMX MIXFTN Reg Bit Name Description 02 7 MIXFMT When LOW, the mixer is set for YC BC R format. When HIGH, the mixer expects GBR format. 02 6-5 DSOURCE The data source for the internal D/A converters is selected by two control bits. 0 0 A-pixels 0 1 B-pixels 1 0 Mixed pixels 1 1 Reserved 02 4-2 SMX These three control bits determine which video sources (A-pixels, B-pixels, fill color registers) are directed to the two mixer inputs, V 1 and V2, through the ABF Crosspoint Mux: 0 0 0 A to V 1, B to V2 0 0 1 A to V1, F to V2 0 1 0 B to V1, A to V2 0 1 1 B to V1, F to V2 1 0 0 F to V1, A to V2 1 0 1 F to V1, B to V2 1 1 0 Reserved 1 1 1 Enables SMX 2-0 inputs for external source select 02 1-0 MIXTFN These two bits are used to alter the mixer transfer function: 0 0 (V1 – V2)a + V2 0 1 (V1) a + V2 1 0 (V1) a 1 1 Reserved Reg Bit Name Description 03 7-0 REDVAL Value for Red/C R 04 7-0 GRNVAL Value for Green/Y 05 7-0 BLUVAL Value for Blue/C B

TMC2081 PRODUCT SPECIFICATION Control Register Definitions (continued) Output Control Register (06) 76543210 AVPIPE Reserved aLUTEN PASSON A/BPASS MOUT MMSB MFORMAT Reg Bit Name Description 06 7 AVPIPE When LOW the pipeline latency from AV, to AVOUT is 14 CLK cycles. When HIGH, the pipeline latency is 12 CLK cycles. 06 6 Reserved. 06 5 aLUTEN When LOW (write only), the aLUTEN is powered down. Data from a 8-0 bypasses the aLUT to control the mixer directly. When HIGH, a7-0 addresses the aLUT which controls the mixer. 06 4 PASSON When HIGH, either PDA or PDB data may be selected to pass through the mixer without modification. When LOW the mixer transfer function is enabled if the PASSEN input is HIGH. The PASSON feature allows Genlock or Decoder reference signals to be passed downstream for subsequent processing. 06 3 A/BPASS Selects A or B data in PASSON mode. LOW allows all pixels from PDA 23-0 during PASSEN = LOW to pass to M23-0. HIGH allows all pixels from PDB23-0 during PASSEN = LOW to pass to M23-0. 06 2 MOUT Digital outputs M 23-0 are enabled when this bit is HIGH. These outputs are in a high-impedance state when MOUT is LOW. 06 1 MMSB When LOW, the MSBs of the C B and CR M23-0 output positions (M15 and M7) are not inverted. When HIGH, the MSBs of the CB and CR output positions are inverted. 06 0 MFORMAT When LOW, 24-bit GBR or YC BC R 444 output data formats are enabled. When HIGH, the multiplexer in the M23-0 path is enabled producing 16-bit YCBC R 422. D/A Control Register (07) 76543210 Reserved DACDLY DACFMT AWAKE SETUP DOVLEN DMAT Reg Bit Name Description 07 7-6 Reserved. 07 5 DACDLY Selects SYNC and BLANK pipe delay. LOW = 15 clocks, HIGH = 2 clocks. 07 4 DACFMT Translates C B/CR format from 2’s complement to CB/CR offset binary. LOW passes CB/CR unchanged. HIGH inverts CB/CR MSB. 07 3 AWAKE D/A converters are enabled when HIGH. The D/A converters are powered-down when AWAKE is LOW. 07 2 SETUP When LOW, 0 IRE blanking levels are present on the D/A converter outputs. When HIGH, blanking levels are 7.5 IRE units. 07 1 Reserved. 07 0 DMAT When HIGH, D/A converter input data is converted from YC BC R to GBR format. When LOW, no conversion takes place and the data is passed through.

PRODUCT SPECIFICATION TMC2081 Control Register Definitions (continued) Absolute Maximum Ratings (beyond which the device may be damaged)1 Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. Identification Registers (08-09) Reg Bit Name Description 08 7-0 REVID Chip revision identification. 09 7-0 PARTID Chip type identification = 2F. Parameter Min. Max. Unit Power Supply Voltage -0.5 +7.0 V Input Voltage -0.5 (V DD + 0.5) V Digital Inputs Applied voltage2 -0.5 (V DD + 0.5) V Externally forced current 3, 4 -20.0 20.0 mA Digital Outputs Applied voltage2 -0.5 (V DD + 0. 5) V Externally forced current3, 4 -20.0 20.0 mA Short Circuit Duration (Single output in HIGH state to GND) 1 second Analog Output Short Circuit Duration (Single output to GND) infinite Temperature Operating, case -60 +130 °C Operating, Junction, Plastic package +150 °C Lead, soldering (10 seconds) 300 °C Vapor phase soldering (1 minute) +220 °C Storage -65 150 °C

TMC2081 PRODUCT SPECIFICATION Operating Conditions

Electrical Characteristics

Note: 1. Typical IDD measured at VDD = +5.0 Volts and TA = 25°C, Maximum IDD measured at VDD = + 5.25 Volts and TA = 0°C. Parameter Min. Nom Max. Units VDD Power Supply Voltage 4.75 5.0 5.25 V VIH Input Voltage, Logic HIGH TTL Inputs, all but CLK, CE

2.0 V DD V

CLK, CE 2.4 V DD V VIL Input Voltage, Logic LOW TTL Inputs GND 0.8 V I OH Output Current, Logic HIGH -2.0 mA IOL Output Current, Logic LOW 4.0 mA VREF External Reference Voltage 1.235 V IREF D/A Converter Reference Current 1.8 mA REF = VREF / RREF , sourced from RREF pin) R REF Reference Resistor @ VREF = Nom. 681 W R OUT Total Output Load Resistance 37.5 W TA Ambient Temperature, Still Air 0 70 °C Parameter Conditions Min. Typ. Max. Units IDD Power Supply Current1 fCLK = 25MHz, DAC, CLUT and aLUT enabled 300 360 mA IDDQ Power Supply Current1 fCLK = 0 DAC, CLUT and aLUT enabled 260 330 mA IDAC DAC Supply Current f CLK = 25MHz 80 100 mA ICLUT CLUT Supply Current 85 100 mA IaLUT aLUT Supply Current 30 45 mA IDDSE Power Supply Current Sleep Mode (D/A, CLUT, aLUT, and D/A overlay disabled) 51 5 m A VRO Voltage Reference Output 0.98 1.2 1.48 V IBR Input Bias Current, VREF VREF = Nom -100 40 mA IIH Input Current, Logic HIGH V DD = Max, VIN = 4.0V -5 5 mA IIL Input Current, Logic LOW V DD = Max, VIN = 0.4V -5 5 mA VOH Output Voltage, Logic HIGH I OH = Max 2.4 V VOL Output Voltage, Logic LOW I OL = Max 0.4 V IOZH High-Z Leakage Current, HIGH V DD = Max, VIN = VDD -5 5 mA IOZL High-Z Leakage Current, LOW V DD = Max, VIN = GND -5 5 mA C I Digital Input Capacitance T A = 25°C, f = 1MHz 15 pF C O Digital Output Capacitance T A = 25°C, f = 1MHz 15 pF VOC Video Output Compliance Voltage -0.4 2.0 V R OUT Video Output Resistance 15 K W C OUT Video Output Capacitance I OUT = 0mA, f = 1MHz 15 25 pF

PRODUCT SPECIFICATION TMC2081 Switching Characteristics Notes: 1. Timing reference points are at the 50% level. 2. Analog and digital C LOAD = 15pF. 3. TTL input levels are 0.0 and 3.0 Volts, 10% - 90% rise and fall times < ns. System Performance Characteristics Parameter Min. Nom. Max. Units Microprocessor Interface t PWLCS CS Pulse Width, LOW 95 ns tPWHCS CS Pulse Width, HIGH 4/f PXL ns tSA Address Setup Time 0 ns tHA Address Hold Time 4 ns tSD Data Setup Time (write) 6 ns tHD Data Hold Time (write) 3 ns tDOZ Output Delay, CS to low-Z 16 ns tDOM Output Delay, CS to Data Valid 110 ns tHOM Output Hold Time, CS to High-Z 7 ns Pixel Interface f PXL Pixel Rate 40 Mpps tCYPX Pixel Cycle Period 25 ns tPWH CLK Pulse Width, HIGH 6 ns tPWL CLK Pulse Width, LOW 6 ns For PDA, PDB, a, SMX, OL, PASSEN , SIG0, AV inputs: tSP Setup Time 6 ns tHP Hold Time 2 ns tHO Output Hold Time, CLK to data disabled 6 ns tDO Output Delay, CLK to data valid 17 ns Analog Outputs PIPES Pipeline Delay 15 CLKs t R D/A Output Current Risetime (10% - 90%) 6 ns tF D/A Output Current Falltime (10% - 90%) 3 ns tDOV Analog Output Delay 20 ns SKEW D/A to D/A Output Skew 1 ns Parameter Conditions Min. Typ. Max. Units VVID Video Amplitude with 37.5 W load 0.7 Volt VSYNC Sync Amplitude with 37.5 W load 0.3 Volt RES D/A Converter Resolution 8 Bits E LI D/A Integral Linearity Error 0.75 LSB ELD D/A Differential Linearity Error 0.75 LSB EG D/A Gain Error ±11 % FS

Figure 7. Pixel/Alpha Data Timing – 444/444 Mode Figure 8. Pixel/Alpha Data Timing – 422/422 Mode

14 Clock Pipeline Delay

Figure 9. Pixel/Alpha Data Timing – 422/444 Mode Figure 10. PASSON Timing – 444 Mode

TMC2081 PRODUCT SPECIFICATION Application Notes (continued) Figure 21. Recommended TMC2081 Connections

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  • TMC22053 Decoder PDA0 PDA1 PDA2 PDA3 PDA4 PDA5 PDA6 PDA7 PDA8 PDA9 PDA10 PDA11 PDA12 PDA13 PDA14 PDA15 PDA16 PDA17 PDA18 PDA19 PDA20 PDA21 PDA22 PDA23 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 G/Y B/CB R/CR VREF COMP RREF SYNC BLANK AVOUT PASS14 SIG14 R/W CS PDB0 PDB1 PDB2 PDB3 PDB4 PDB5 PDB6 PDB7 PDB8 PDB9 PDB10 PDB11 PDB12 PDB13 PDB14 PDB15 PDB16 PDB17 PDB18 PDB19 PDB20 PDB21 PDB22 PDB23 OL0 OL1 OL2 OL3 ALPHA0 ALPHA1 ALPHA2 ALPHA3 ALPHA4 ALPHA5 ALPHA6 ALPHA7 ALPHA8 SMX0 SMX1 SMX2 AV PASSEN SIG0 CLK 128 127 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 103 102 101 100 122 123 124 VDDA 0.1 681 0.1 0.1 0.1 0.1 0.1 0.1 65-3701-13 Use single ground plane for analog and digital power. Isolate analog lands from digital lands. 75 ohm external load expected for correct output voltages Total expected load is 37.5 ohms. BEAD SYNC* BLANK* MICROBUS CLOCK SIG0 PASSON ENABLE ACTIVE VIDEO SMX ALPHA OL PDB PDA VDDA TMC2081KB VDD LM185-1.2 MIXER OUTPUT G/Y OUT AV+14 CLKS PASS_EN+14 CLKS SIG0+14 CLKS B/CB OUT R/CR OUT

PRODUCT SPECIFICATION TMC2081 Mechanical Dimensions – 128-Lead MQFP Package D E e PIN 1 IDENTIFIER A A1 B Base Plane Seating Plane See Lead Detail -C- ccc C LEAD COPLANARITY Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982. Controlling dimension is millimeters. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. "L" is the length of terminal for soldering to a substrate. "B" & "C" includes lead finish thickness. A — .160 — 4.07 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .010 — .25 — .018 .45B .012 .30 D1/E1 1.098 1.106 27.90 28.10 .0315 BSC .80 BSCe L .029 .041 .73 1.03 128 128 32 32 3, 5 .009 .23C .005 .13 5 N ND D/E 1.219 1.238 30.95 31.45 ccc — .004 — 0.10 a 0¡ 7¡ 0¡ 7¡ a C 0¡ Min. R 0.063" Ref (1.60mm) Datum Plane Lead Detail L .20 (.008) Min. .13 (.005) R Min. .13/.30 .005/.012

TMC2081 PRODUCT SPECIFICATION Notes:

PRODUCT SPECIFICATION TMC2081 Notes:

TMC2081 PRODUCT SPECIFICATION 5/20/98 0.0m 001 Stock# DS70002081 Ó 1998 Fairchild Semiconductor Corporation LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com O rdering Information Product Number Temperature Range Screening Package Package Marking TMC2081KBC TA = 0°C to 70°C Commercial 128-Lead MQFP 2081KBC