TMC2072KHC

TMC2072 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

• Fully integrated acquisition
• 3-channel video input multiplexer
• Two-stage (analog and digital) video clamp
• Automatic gain adjustment
• Sync detection and separation
• Pixel and subpixel adjustment of video-to-sync output timing
• Genlock to any NTSC or PAL format, including PAL-M and PAL-N
• Pixel clock generation
• 8-bit video A/D conversion
• Standard R-bus serial microprocessor interface
• User-selectable line-locked pixel rates include: – 12.27 MHz NTSC & PAL-M – 13.5 MHz NTSC & all PAL – 14.75 MHz PAL (non-M) TMC2072-1 only – 15.0 MHz PAL (non-M) TMC2072-1 only
• Direct interface to Fairchild Semiconductor video encoders and decoders
• Built-in circuitry for crystal oscillator
• No tuning or external voltage reference required
• Space-saving 100-lead MQFP package

Applications

• Frame grabber
• Digital videotape recorders
• Desktop video

Description

The TMC2072 Genlocking Video Digitizer samples and quantizes standard analog baseband composite NTSC or PAL video into its 8-bit digital equivalent. It extracts horizontal and vertical sync signals, from which an on-chip PLL generates a line-locked pixel clock for the on-chip 8-bit A/D converter and a double-speed register clock to transfer data to a subsequent video processing subsystem. A second PLL generates a chroma subcarrier locked to the incoming chroma burst. The chip reports each line’s color burst phase and frequency during the next horizontal sync pulse. The TMC2072 includes a three-channel video input multi- plexer, analog clamp, variable gain amplifier, and digital back porch clamp. The user may provide either an external 20MHz clock or a 20MHz crystal. No external component changes or tuning are required for PAL or NTSC operation at either D1 or square pixel VGA pixel rates. The TMC2072 is fabricated in a submicron CMOS process and is packaged in a 100-lead MQFP. Its performance is guaranteed from 0 to 70°C. Block Diagram VIN1 ANALOG CLAMP GAIN D/A GVSYNC GHSYNC PXCK 65-2072-01 LDV VALID CVBS7-0 BACK PORCH CLAMP DATA SELECTOR SUBCARRIER PHASE-LOCKED LOOP SYNC SEPARATOR HORIZONTAL PHASE-LOCKED LOOP DIRECT DIGITAL SYNTHESIZER LOWPASS FILTER D/A +1.2V RESET SDA SCL SA2-0 INT COMP CLK IN CLK OUT DDS OUT PFD IN PXCK SEL EXT PXCK CBYP VREF RB RT CONTROL MICROPROCESSOR INTERFACE ANALOG INTERFACE DDS/PIXEL CLOCK INTERFACE MUX VIN2 VIN3 A/D TMC2072 Genlocking Video Digitizer

TMC2072 PRODUCT SPECIFICATION 2 REV. 1.0.4 6/19/01 Functional Description The TMC2072, a fully integrated self-genlocking video A/D converter, digitizes NTSC or PAL baseband composite sig- nals. It accepts video on one of three input channels, adjusts the gain, clamps to the back porch and digitizes the video at a user-selectable multiple of the horizontal line frequency. It extracts horizontal and vertical sync, measures the subcar- rier frequency and phase, and provides these data with the digitized composite data over an 8-bit digital video port. Horizontal and vertical sync outputs are provided, along with pixel clock (LDV) and twice pixel clock (PXCK). Operating parameters are set up via a standard two-wire microprocessor port. The chip can work with either an inter- nal or an external voltage reference. Fabricated in an advanced CMOS process, the TMC2072 is housed in a 100 lead metric quad flat package. Its perfor- mance is guaranteed from 0 to 70°C and from 4.75 to 5.25 supply volts. Timing The TMC2072’s A/D converter and digital signal path operate from alternate cycles of an internally-synthesized clock, PXCK. This 24.5 to 30 MHz clock is derived from the incoming 20 MHz reference clock and phase-locked to the horizontal sync tips of the incoming analog video stream. The frequency of PXCK may be set as 1560 (NTSC VGA square pixel), 1716 (NTSC D1), 1732 (PAL D1), or 1888 or 1920 (PAL VGA) times the incoming video line rate. Timing of the serial microprocessor interface bus is indepen- dent of the pixel clock and is described under the Micropro- cessor Interface section that follows Functional Description. Video Input Via the microprocessor interface, the user can enable one of the chip’s three analog video input ports. Although each port normally anticipates a standard video signal level with 286 to 300 mV between sync tip and blank, another control register bit allows it to be used with half-power (approxi- mately 70% amplitude) signals. Good crosstalk isolation accommodates active video on all three inputs simulta- neously. The user must provide antialias filtering and proper line termination externally. Analog Clamp The front-end analog clamp ensures that the input video falls within the active range of the A/D converter. The digitized composite video output can be clamped to the back porch by a secondary digital clamp. Automatic Gain Adjustment To accommodate approximately a ±15% range in video signal amplitudes, the TMC2072’s on-chip AGC circuit engages for one video frame following either: 1) initial lock after reset; 2) loss and recovery of lock while operating; or 3) setting of control bit AGCEN high by the host micropro- cessor. The AGC operation adjusts the A/D converter’s on- chip reference voltages until video blank causes it to output approximately 1/4 of its full range. The chip then holds this gain adjustment constant until a new AGC sequence is initi- ated by AGCEN going high or by loss and recovery of video lock. The one-frame timeout prevents the gain control from riding gain and trying to track noise or minor variations in signal strength. To handle doubly-terminated and other weak video signals, the user should set the VGAIN control bit high, thereby boosting video gain 50% above nominal. Analog-to-Digital Converter The TMC2072 contains a high-performance 8-bit A/D converter. Its gain and offset are automatically set as a part of the automatic gain adjustment process during initial signal acquisition, and require no user attention. The reference voltages to the A/D converter are set up by internal D/A converters under automatic control during genlock acquisition. These voltages determine the gain and offset of the A/D converter with respect to the video level presented at its input. Low-Pass Filter The digitized composite video stream is digitally low-pass filtered to remove chrominance components from the sync separator. Filtering provides robust operation by optimizing the signal-to-noise ratio of the synchronizing/blanking por- tion of the video, improving the accuracy of the back porch blanking level detector. A digital sync separator provides the output sync signals, GHSYNC and GVSYNC, and times internal operations. Horizontal Phase-Locked Loop A phase-locked loop generates PXCK, at twice the pixel rate. The reference signal for the horizontal phase-locked loop is generated by the Direct Digital Synthesizer (DDS). The DDS output is constructed with an internal D/A con- verter and is output from the TMC2072 via the DDS OUT pin. This signal is passed through an external LC filter and input to the horizontal phase-comparator. The frequency of the DDS output is one ninth of that of PXCK. A 20MHz clock is required to drive the DDS. Preferably, this may be input to the TMC2072 via CMOS levels on the CLK IN pin. Alternately, a 20MHz crystal may be directly connected between CLK IN and CLK OUT with tuning capacitors to activate the internal crystal oscillator circuitry.

within two frames after it is restored. lockable encoder chips will accept these data directly. subtle line-to-line variations. wide CVBS data port, synchronous with PXCK and LDV. the horizontal sync tip period at the PXCK rate. serial interface with each device having a unique address. for receiving and transmitting data over the serial interface. SCL and SDA are pulled HIGH by external pull-up resistors. action as a start or stop sequence.

• Start signal
• Slave address byte
• Base register address byte
• Data byte to read or write
• Stop signal When the serial interface is inactive (SCL and SDA are HIGH) communications are initiated by sending a start sig- nal. The start signal is a HIGH-to-LOW transition on SDA while SCL is HIGH. This signal alerts all slaved devices that a data transfer sequence is coming. The first eight bits of data transferred after a start signal com- prise a seven bit slave address and a single R/W bit. The R/W bit indicates the direction of data transfer, read from or write to the slave device. If the transmitted slave address matches the address of the device (set by the state of the SA2:0 input pins.), the TMC2072 acknowledges by bringing SDA LOW on the 9th SCL pulse. If the addresses do not match, the TMC2072 does not acknowledge.

Table 1. Serial Port Addresses The address is 1000 SA2 SA1 SA0. Figure 1. Microprocessor Parallel Port – Read Timing

PRODUCT SPECIFICATION TMC2072 REV. 1.0.4 6/19/01 5 ↓ Stop signal ↓ Start signal ↓ Slave Address byte (R/W bit = HIGH) ↓ Data byte from base address ↓ Stop signal Read from four consecutive control registers ↓ Start signal ↓ Slave Address byte (R/W bit = LOW) ↓ Base Address byte ↓ Stop signal ↓ Start signal ↓ Slave Address byte (R/W bit = HIGH) ↓ Data byte from base address ↓ Data byte from (base address + 1) ↓ Data byte from (base address + 2) ↓ Data byte from (base address + 3) ↓ Stop signal Pin Assignments Pin Definitions Pin Name Pin Number Pin Type Function Video Input V IN1-3 65, 61, 58 1.23Vp-p Composite Video Input. Video inputs,1.235 Volts peak-to-peak, sync tip to peak color Clocks CLK IN 91 CMOS 20 MHz DDS clock input. 20 MHz CMOS clock input to DDS. This pin may also be used along with CLK OUT for directly connecting crystals. CLK OUT 93 CMOS Inverted clock output. Inverted DDS clock output. This pin may also be used along with CLK IN for directly connecting a crystal. PXCK 45 CMOS 2x Pixel clock output. 2x oversampled line-locked clock output. 65-2072-05 SA0 SA1 SA2 SDA SCL V DD RESET D GND NC NC NC NC NC NC NC D GND INT V DD NC NC CVBS CVBS1 CVBS2 CVBS3 CVBS4 13 0 5180 100 V DD DGND CVBS5 CVBS6 CVBS7 BURL GHSYNC GVSYNC VALID FID0 FID1 NC D GND DGND LDV D GND VDD NC V DD PXCK D GND DGND VDD VDDA AGND Pin Name Pin Name VDDA VDDA NC NC A GND NC R B VIN3 NC V DDA VIN2 NC A GND VDDA VIN1 NC A GND RT AGND VREF NC A GND VDDA AGND CBYP NC PFD IN NC NC NC A GND DDS OUT NC NC NC PXCK SEL V DDA COMP A GND DGND CLK IN V DD CLK OUT EXT PXCK D GND DGND DGND VDD NC V DD 100 Pin Name Pin Name Note: 1. NC = No internal connection between package and IC. Fairchild Semiconductor recommends leaving these pins open to simplify board upgrades to potential future genlock chips.

TMC2072 PRODUCT SPECIFICATION 6 REV. 1.0.4 6/19/01 LDV 40 CMOS Pixel clock output. Delayed pixel clock output. LDV runs at 1/2 the rate of PXCK and its rising edge is useful for transferring CVBS digital video from the TMC2072 to the TMC22x9x Digital Video Encoders. EXT PXCK 94 CMOS External PXCK input. Input for external PXCK clock source. PXCK SEL 86 CMOS PXCK source select. Select input for internal or external PXCK. When HIGH, the internally generated line-locked PXCK is selected. When LOW, the external PXCK source is enabled. Digital Video GHSYNC 32 CMOS Horizontal sync output. When the TMC2072 is locked to incoming video, the GHSYNC pin provides a negative-going pulse after the falling edge of each horizontal sync pulse. When the device is locked to a stable video signal, there is a fixed number of PXCK clock cycles between adjacent falling edges of GHSYNC . If no video signal is present and LEADLAG is less than 4A(hex), the TMC2072 will output normal, evenly-spaced horizontal pulses. If no video signal is present and LEADLAG exceeds 88(hex), the TMC2072 will omit every eighth Hsync pulse. As LEADLAG is increased from 49h to 89h, seven out of every eight Hsyncs will be unaffected, but the eighth will shrink by one clock cycle per LSB step, until it disappears entirely at 89h. GVSYNC 33 CMOS Vertical sync output. When the TMC2072 is locked to incoming video, the GVSYNC pin provides a negative-going edge after the start of the first vertical sync pulse of a vertical blanking interval. If no video signal is present on the selected input pin, GVSYNC will remain continuously at logic high, until a signal is selected and lock is reestablished. A system designer requiring a free-running vertical sync may wish to provide this with an external pixel counter. CVBS 7-0 30-28, 25-21 CMOS Composite output bus. 8-bit composite video data are output on this bus at 1/2 the PXCK rate. During horizontal sync, field ID, subcarrier frequency, and subcarrier phase are available on this bus. FID[0] 35 CMOS Odd/even ( “top/bottom”) field flag. LOW denotes the first field of a video frame; HIGH, the second. FID[1] 36 CMOS Bruch blanking flag. In PAL, LOW denotes a frame with burst blanked on line 310, whereas HIGH denotes burst detected on line 310. FID[1] is valid only in PAL and only when FID[0] is high and should be interpreted as follows: µP l/O SA[2:0] 3-1 R-bus chip address, 3 LSBs. Full 7-bit address = {1, 0, 0, 0, SA[2], SA[1], SA[0]} SDA 4 R-bus R-bus bidirectional data line. SCL 5 R-bus R-bus clock line (input/slave only) Pin Definitions (continued) Pin Name Pin Number Pin Type Function FID[1:0] PAL Field Number

01 II or VI

11 IV or VIII

PRODUCT SPECIFICATION TMC2072 REV. 1.0.4 6/19/01 7 RESET 7 TTL Master reset input. Bringing RESET LOW forces the internal state machines to their starting states, loads the Control Register with default values, and disables outputs. Bringing RESET HIGH restarts the TMC2072 in its default mode. INT 17 TTL Interrupt output. This output is LOW if the internal horizontal phase lock loop is unlocked with respect to incoming video for 128 or more lines per field. After lock is established, INT goes HIGH. VALID 34 TTL HSYNC locked flag. Hsync locked flag. When high, this output indicates that the most recent incoming horizontal sync has been detected within ±16 pixels of its expected position. It goes low if no sync is encountered during this ±16-pixel window, as during a typical VCR headswitch line. Once the chip has locked to a clean video source, this flag should remain high continuously. If the chip has locked to a VCR, this flag will typically go low for one (or sometimes two) lines at the bottom of each field. BURL 31 TTL/ CMOS Burst lock flag. When high, this output indicates that the chip’s internal subcarrier synthesizer is phase-aligned with the current line’s incoming chroma burst. The flag goes low when the internal and external phases diverge. Analog Interface V REF 70 +1.23 V VREF input/output. +1.23 Volt reference. When the internal voltage reference is used, this pin should be decoupled to AGND with a 0.1 µF capacitor. An external +1.2 Volt reference may be connected here, overriding the internal reference source. COMP 88 0.1 µF Compensation capacitor. Compensation for DDS D/A converter circuitry. This pin should be decoupled to VDDA with a 0.1 µF capacitor. RB, RT 57, 68 0.1 µF A/D VREF decoupling. Decoupling points for A/D converter voltage references. These pins should be decoupled to AGND with a 0.1 µF capacitor. PLL Filter DDS OUT 82 Internal DDS output. Analog output from the internal Direct Digital Synthesizer D/A converter, at 1/9 the PXCK frequency. PFD IN 77 Horizontal PLL input. Analog input to the Phase/Frequency Detector of the horizontal phase-locked loop. C BYP 75 1 µF Comparator bypass. Decoupling point for the internal comparator reference of the Phase/Frequency Detector. This pin should be decoupled to A GND with a 0.1 µF capacitor. Power Supply V DDA 49, 51, 52, 60, 64, 73, 87 +5 V Analog power supply. Positive power supply to analog section. All pins must be connected. VDD 6, 18, 26, 42, 44, 48, 92, 98, 100 +5 V Digital power supply. Positive power supply to digital section. All pins must be connected. Ground A GND 50, 55, 63, 67, 69, 72, 74, 81, 89 0.0 V Analog ground. Ground for analog section. All pins must be connected. DGND 8, 16, 27, 38, 39, 41, 46, 47, 90, 95-97 0.0 V Digital ground. Ground for digital section. All pins must be connected. Pin Definitions (continued) Pin Name Pin Number Pin Type Function

TMC2072 PRODUCT SPECIFICATION 8 REV. 1.0.4 6/19/01 Control and Status Register Bit Functions Summary Register Function Reg 00 97h (year of revision) read only Reg 01 20h (part #) read only Reg 02 72h (part #) read only Reg 03 01h (silicon revision #) read only Reg 04 Reserved Reg 05 Lock flags; sync tip read only Reg 06 Blank level read only Reg 07 Reserved Reg 08 Format; clock rate; freerun; clamp; reset Reg 09 HSync lead/lag Reg 0A Gain; loop filter bandwidth; subpixel sync & clk position Reg 0B Video source select Reg 0C Vsync delay Reg 0D Sync tip set Reg 0E Output timing, tristate Reg 0F Reserved Details Bit Name Function Reg 00 97h (year of revision) Read Only Reg 01 20h (part #) Read Only Reg 02 72h (part #) Read Only Reg 03 01h (silicon revision #) Read Only Reg 04 Reserved Reg 05 Lock Flags & Sync Height Read Only

7 BURST_DET Each time a high-frequency signal is detected during a video line ’s normal

expected burst interval, this flag goes high until the next line’s expected burst period. If no high-frequency signal is present during the expected burst interval, this flag goes low. With a standard color television signal input, this flag will be low during vertical field groups and, in PAL, Bruch-blanked lines. [TMC22071A bit 47.] 6 BURST LOCK If the subcarrier loop is unlocked on the current video line, i.e., the subcarrier phase error measured during burst exceeds the lock threshold, this flag goes low until the next burst interval. If the phase error is less than the threshold, the flag is reset high. This flag is meaningful only if HLOCK is low.

5 HLOCK During each video field, if most horizontal sync pulses arrive more than 15 pixels

before or after their expected positions, this flag will go high. If most of the field’s incoming horizontal syncs fall within 15 pixels of their expected positions, this flag will go low. [TMC22071A bit 56.] 4:0 ST These bits report the each line ’s average sync tip level out of the A/D converter (as observed over CVBS). For a clean signal, the reported value will match the sync tip set in Reg 0D, below.

PRODUCT SPECIFICATION TMC2072 REV. 1.0.4 6/19/01 9 Reg 06 Blank level Read Only 7:0 BP Blank level, as measured at the low-pass-filtered A/D output during each line ’s color back porch. For a standard video input, its decimal value will be approximately 60 (NTSC) or 64 (PAL). [TMC22071A bits 55:48.] Reg 07 Reserved Reg 08 Standard and Clock Rate Select 7:6 V_STD Video Standard. These two control bits select the incoming video standard, viz:

00 NTSC, NTSC-EIAJ (power-on default)

01 PALM (Brazil)

10 PALB,G,H,I

11 PALN (Argentina)

[With bits 5:4, these bits cover all functions of TMC22071A bits 3:1.] 5:4 CK_RATE Pixel Clock/Sample Rate. Pixel (sample) rate selector, as follows: 00 12.27 MHz (power-on default; 525-line VGA) 01 13.5 MHz (D1 television rate) 10 14.75 MHz (625-line square-pixel VGA) TMC2072-1 only 11 15.0 MHz TMC2072-1 only Note: The 12.27 MHz pixel rate is reserved for 525-line television standards (NTSC, PAL-M), whereas the 14.75 and 15.0 MHz rates are for 625-line standards (all other PAL) only. Bit combinations 0x1x and 1x00 may yield stable composite data samples, sync pulses, and pixel clock, but no useful color subcarrier information. 3 FREERUN Freerun vs. Genlock Operation. LOW (power-on default): Standard genlock mode, in which the PXCK, GHSYNC , and GVSYNC lock to the incoming video’s observed sync pattern. HIGH: GHSYNC is counted down from a free-running PXCK, which is unrelated to the incoming video. [TMC22071A bit 26.] 2 BPFOUT Genlock Reference Signal Enable. LOW (power-on default): Loop-predicted subcarrier phase and frequency data (GRS) are sent over CVBS during each horizontal sync pulse. HIGH: GRS data suppressed, such that the CVBS datastream is just the digitized incoming video signal. [TMC22071A bit 33.] 1 DC_CLAMP HIGH (power-on default): vertically low-pass filtered digital porch clamp enabled. LOW: digital clamp disabled [TMC22071A bit 34, except that the TMC22071A clamp has no vertical filter.] 0 S_RESET Master Software Reset Control. HIGH (power-on default & self-reset state): normal operation. LOW: Bringing this “one-shot” control low resets all internal state machines and registers except the microprocessor control bits themselves. The bit then sets itself high, permitting normal operation. (Because it automatically returns to the high state, this bit will always appear as a 1 when read through the microprocessor port.) [TMC22071A bit 0.] Reg 09 Lead-Lag 7:0 LEAD_LAG Hsync Lead/lag Control (in one-pixel = two-PXCK increments). Power-on default = 80 Hex. To advance (delay) GHSYNC and GVSYNC relative to the video input, decrease (increase) the value. Program code 79h, with sub pixel control = 0.5 will align the GHSYNC output with the falling sync edge of the input video. [TMC22071A bits 24:17.] Details (continued) Bit Name Function

TMC2072 PRODUCT SPECIFICATION 10 REV. 1.0.4 6/19/01 Reg 0A Gain, loop filter, subpixel adjust 7 V_GAIN Analog Gain into A/D Converter. LOW (power-on default): unity gain, suitable for nominal 1-volt (sync tip to reference white) video signals. HIGH: 1.5 X gain, for over-terminated video signals with approximately 200mV sync tips. [TMC22071A bit 9.]

6 DDS_TEST Reserved, test bit for DDSDAC; reset low (power-on default)

5 HFILT Horizontal Phase-Locked Loop Filter Bandwidth. LOW (power-on default): narrow H loop filter to minimize jitter with clean video sources. HIGH: wide filter bandwidth, to better accommodate jittery or noisy sources. 4:0 SUBPIX Sample Clock (and Sync Signal) Subpixel Offset Timing Control. Format is fractional two’s complement, i.e., 0.SFFFF, where bit 4, the signed most significant bit (S), represents 1 PXCK or 1/2 pixel. Thus, the programming range is 01111 = +15/32 pixel to 10000 = -16/32 pixel. A value of 01000 will advance the sample clock and syncs by 1/4 pixel relative to the incoming video, whereas a value of 11000 will retard them the same amount. The power-on default value of 0 nominally aligns the sample clock with the center of the incoming signal’s falling sync edges. [TMC22071A bits 16:12.] Reg 0B Input select

7 Reserved, reset low (power-on default)

6 NCOMP Reserved, test bit: noise comparator disable; reset low (power-on default)

5:4 SOURCE These two bits determine which of the three analog input lines is active, as follows:

00 VIN1 (power-on default)

01 VIN2

1X VIN3. [TMC22071A bits 8:7.]

3 SCALE Reset low (power-on default) to compensate burst PLL for line-by-line changes in

sampling rate. Set high to disable compensation (test purpose only). 2:0 ANTEST Reserved, analog circuit test bits; reset low (power-on default) Reg 0C Field and Vsync reporting

6 FID FREE LOW (power-on default): The color frame identifier (FID[1] in NTSC) toggles

smoothly, but with no guaranteed relationship to the incoming color burst phase. HIGH freezes FID[1] in NTSC mode, if a two-field (odd/even only) sequence is desired. 5:3 Reserved, reset low (power-on default) 2 DLYRPTF Delay Field i.d. Update. LOW (power-on default): FID will increment at the start of each incoming vertical sync pulse group. (NTSC lines 4 and 266.) HIGH: FID will increment at the start of the next line after the start each incoming vertical sync. 1 DLYRPT Delay GVSYNC Output. LOW (power-on default): TMC2072 will generate a GVSYNC falling edge as it predicts the start of a new vertical sync series. This is recommended for laser disk or higher quality video signals, for which the chip can easily predict video field timing. HIGH: TMC2072 will generate a GVSYNC falling edge on the line after it detects the start of a vertical sync series. This is recommended for jittery input signals, if a one-line upward image displacement is acceptable. Details (continued) Bit Name Function

PRODUCT SPECIFICATION TMC2072 REV. 1.0.4 6/19/01 11 0 ENAGC Re-Enable Automatic Gain Control. HIGH (self-resetting one-shot): Initiates a new, self-terminating one-frame AGC sequence, independent of sync lock status. LOW (power-on default and self-reset): AGC is enabled for one frame when video sync is initially acquired, and each time sync is lost and reacquired. [TMC22071A bit 25]. Reg 0D Sync Tip Set 7:4 Reserved 3:0 ST[3:0] Programmable Sync Tip Value. Power-on default = 0. Recommended setting = 3. When the chip has achieved stable lock, this will be the average value output over CVBS during sync tips and equalization pulses. [TMC22071A bit 43:40.] Reg 0E 7 FLIPPX LOW (power-on default): Phase of PXCK output matches that of the TMC22071A. HIGH: Phase of PXCK output is inverted, relative to that of the TMC22071A. 6 FLIPLDV LOW (power-on default): Phase of LDV output matches that of the TMC22071A. HIGH: Phase of LDV output is inverted, relative to that of the TMC22071A. 5 XDLY LOW (power-on default): PXCK output timing matches that of TMC22071A. HIGH: PXCK output is delayed approximately 5-10ns, to simplify interface timing in some systems. 4 VDLY LOW (power-on default): LDV output timing matches that of TMC22071A. HIGH: LDV output is delayed approximately 5-10ns, to simplify interface timing in some systems.

3 ENVHCVBS LOW (power-on default): Digital outputs CVBS0-7, FID(2:0) and GV/GHSYNC

are tristated, to avoid bus contentions elsewhere on the system. HIGH: These pins are enabled, for normal operation.

2 FORCEZERO LOW (power-on default): If the Hloop loses lock (Hlock\\ goes high), the CVBS

port will output the default subcarrier frequency and cumulative phase keyed to each GHSYNC falling edge, and the raw output of the A/D converter at all other times. In this case, since the incoming video and internal state machine are asynchronous, GRS data may appear anywhere along each digitized video line. HIGH: If the Hloop loses lock, the CVBS data port will yield only the default subcarrier phase and frequency data, and zero at all other times. 1:0 Reserved, reset low (power-on default) Reg 0F 7:0 Reserved, reset low (power-on default) Details (continued) Bit Name Function

TMC2072 PRODUCT SPECIFICATION 16 REV. 1.0.4 6/19/01 Operating Conditions (for standard temperature range) Note: 1. Timing reference points are at the 50% level. Electrical Characteristics (for standard temperature range) Note: 1. Typical I DD with VDD = +5.0 Volts and TA = 25°C, Maximum IDD with VDD = +5.25 Volts and TA = 0°C. Parameter Min. Nom. Max. Unit VDD Power Supply Voltage 4.75 5.0 5.25 V VIH Input Voltage, Logic HIGH TTL Inputs 2.0 V DD V CMOS Inputs 2/3V DD VDD V VIL Input Voltage, Logic LOW TTL Inputs D GND 0.8 V CMOS Inputs D GND 1/3 VDD V IOH Output Current, Logic HIGH -2.0 mA lOL Output Current, Logic LOW 4.0 mA VIN Video Input Signal Level, Sync Tip to Peak White 0.9 1.0 1.1 V VREF External Reference Voltage 1.235 V TA Ambient Temperature, Still Air 0 70 °C Serial Microprocessor Interface t DAL SCL Pulse Width, LOW 1.3 µs tDAH SCL Pulse Width, HIGH 0.6 µs tSTAH SDA Start Hold Time 0.6 µs tSTASU SCL to SDA Setup Time (START) 0.6 µs tSTOSU SCL to SDA Setup Time (STOP) 0.6 ns tBUFF SDA Stop to SDA Start Hold Time 1.3 µs tDSU SDA to SCL Data Setup Time 300 ns tDHO SCL to SDA Hold Time 300 ns Parameter Conditions Min. Typ. Max. Unit IDD Power Supply Current1 Total Current VDD = Max, fPXCK = 30MHz 190 230 mA IREF Reference Input Current V REF = +1.235V 100 µA IIH Input Current, Logic HIGH V DD = Max, VIN = 4.0V ±10 µA IIL Input Current, Logic LOW V DD = Max, VIN = 0.4V ±10 µA VOH Output Voltage, Logic HIGH I OH = -2.0 mA 2.4 V VOL Output Voltage, Logic LOW I OL = 4.0 mA 0.4 V IOZH Hi-Z Output Leakage current, HIGH V DD = Max, VIN = VDD ±10 µA IOZL Hi-Z Output Leakage current, LOW V DD = Max, VIN =GND ±10 µA Cl Digital Input Capacitance T A = 25°C, f = 1 Mhz 4 15 pF CO Digital Output Capacitance T A - 25°C, f = 1 Mhz 10 pF CV Input Capacitance, VIN1-3 TA = 25°C, f = 3.58 Mhz 15 pF RV Input Resistance, VIN1-3 50 k Ω

1. NTSC/PAL compliant black burst at nominal input level ±10%, frequencies nominal ±10 ppm.

Figure 16. Typical Interface Circuit

20 MHz, TTL

The internal VREF source is adequate for most applications. 6.7MHz and a group delay of 140 nanoseconds at 5MHz. Figure 17. Simple Anti-aliasing Filter Figure 18. Group Delay Equalizer Filter crystal must be a 20 MHz “fundamental” type, not overtone. connections are shown in Figure 19. Table 4. Crystal Parameters Figure 19. Direct Crystal Connections pins; DGND and AGND are digital and analog ground pins). tal supplies via a ferrite bead inductor on the analog lead. trostatic discharge, and DC biased to approximately 1.9V.

20 MHz

PRODUCT SPECIFICATION TMC2072 REV. 1.0.4 6/19/01 19 Printed Circuit Board Layout Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Wire-wrap is not an option. Overall system performance is strongly influ- enced by the board layout. Capacitive coupling from digital to analog circuits may result in poor picture quality. Con- sider the following suggestions when doing the layout: 1. Keep the critical analog traces (COMP,V REF, RT, RB, DDS OUT, PFD IN, CBYP, and VIN1-3) as short as pos- sible and as far as possible from all digital signals. The TMC2072 should be located near the board edge, close to the analog output connectors. 2. The digital power plane for the TMC2072 should be that which supplies the rest of the digital circuitry. A single power plane should be used for all of the V DD pins. If the analog power supply for the TMC2072 is the same as that of the system’s digital circuitry, power to the TMC2072 V DDA pins should be decoupled with ferrite beads and 0.1 µF capacitors to reduce noise. 3. The ground plane should be solid, nor cross-hatched. Connections to the ground plane should have very short leads. 4. Decoupling capacitors should be applied liberally to V DD pins. Remember that not all power supply pins are created equal. They typically supply adjacent circuits on the device, which generate varying amounts of noise. For best results, use 0.1µF capacitors in parallel with 10µF capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice. 5. If the digital power supply has a dedicated power plane layer, it should not overlap the TMC2072, the voltage reference or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the TMC2072 and its related analog circuitry can degrade performance. 6. CLK should be handled carefully. Jitter and noise on this clock or its ground reference may degrade perfor- mance. Terminate the clock line carefully to eliminate overshoot and ringing.

Related Products

• TMC22x9x Digital Video Encoders
• TMC2242/TMC2243/TMC2246 Video Filters
• TMC2081 Digital Video Mixer
• TMC22x5y Digital Decoders
• TMC2302 Image Manipulation Sequencer Interface to the TMC22x5y Decoder The TMC22x5y Digital Video Decoders have been designed to directly interface to the TMC2072 Digital Video Genlock. The TMC2072 is the source for TMC22x9x input signals CVBS 7-0, GHSYNC, GVSYNC, LDV, and PXCK as shown in Figure 20. These signals directly connect to the TMC22x5y. The serial microprocessor interfaces for TMC22x5y and TMC2072 are identical. The SDA and SCL bus signals from the host microprocessor are shared by the TMC22x5y and TMC2072. Only SA[2:0], VALID, and INT signals are separate from the microprocessor bus.

Figure 20. TMC22x5y Interface Circuit

8 CVBS7:0

PRODUCT SPECIFICATION TMC2072 REV. 1.0.4 6/19/01 20 Mechanical Dimensions 100 Lead MQFP Package – 3.2mm Footprint Lead Detail AA 2 B -C- Lead Coplanarity Seating Plane ccc C See Lead Detail E D B Pin 1 Indentifier e Base Plane R C L α Datum Plane 0° Min. .20 (.008) Min. .13 (.30) .005 (.012) .13 (.005) R Min. 0.076" (1.95mm) Ref A — .134 — 3.40 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .010 — .25 — .015 .38 A2 .100 .120 2.55 3.05 B .008 3, 5 .22 .009 .23C .005 .13 E .667 .687 16.95 17.45 .0256 BSC .65 BSCe L .028 .040 .73 1.03 100 100 30 30 N ND 20 20NE α 0° 7° 0° 7° — .004 — .12ccc D .904 .923 22.95 23.45 D1 .783 .791 19.90 20.10 E1 .547 .555 13.90 14.10 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982. Controlling dimension is millimeters. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. "L" is the length of terminal for soldering to a substrate. "B" & "C" includes lead finish thickness.

TMC2072 PRODUCT SPECIFICATION 6/19/01 0.0m 003 Stock#DS30002072  2001 Fairchild Semiconductor Corporation www.fairchildsemi.com DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Ordering Information

Product Number Temperature Range Screening Package Package Marking TMC2072KHC T A = 0°C to 70°C Commercial 100-Lead MQFP 2072KHC