TMC2069P7C FAIRCHILD | Alldatasheet
Document overview
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- PDF pages: 12
Technical content
Features
- Parallel TTL Compatible Inputs
- Component and VGA Outputs
- Fairchild demo board compatibility
Applications
- Evaluation of TMC3003 DAC
- Output for TMC2068P7C Decoder demo board
- Output for Genesis 10-bit Line doubler board
- System Breadboarding
Description
The TMC2069P7C DAC demonstration board provides a flexible base for evaluating the performance of the TMC3003 triple 10 bit DAC. The board can output analog component video or VGA. There are high quality Hybrid filters (601-003) on the output. Block Diagram +5V TMC3003 Analog RGB VGA Output Analog Outputs for the TMC22153 Digital Decoder Analog RGB/YPbPr Video Output
96 Way
(female) Digital Inputs: 10 bit G/Y 10 bit B/U 10 bit R/V DAC Clock SYNC/CR BLANK High Quality LPF High Quality LPF High Quality LPF -5V0V TMC2069P7C Demonstration Board for the TMC3003 DAC Rev. 0.9.1
0 MHz 6 MHz
especially suited for video and graphics applications. grades are available: 30, 50, and 80 Msps. to the TMC2068P7C decoder demonstration board.
- To set up the output levels on the triple dac, place a digi-
digital level 824 and blanking at 240.
- The output analog levels should be 286 mV sync tip to
- Apply either the unmodulated digital ramp used in step
- Adjust RV2, to adjust the RED, and RV3, to adjust the
voltage levels to the values on the green channel. Pr peak to peak should be 525 mV . Figure 2. Unmodulated Ramp Waveform Figure 1. Output Low Pass Filters
PRODUCT SPECIFICATION TMC2069P7C Preliminary Information Power Supply Requirements The TMC2069P7C board requires 1.5 Amps from the +5 V olt power supply and 0.5 Amps from the -5 V olt power sup- ply. The -5 V olt power supply powers the SMA filters. The +5 V olt power supply not only drives TTL logic devices but it also provides the power and voltage references to the TMC3003. Therefore, it is recommended that a bench power supply be used with the cable lengths kept to a minimum. Output Low-Pass Filters The 601-003 filters are high end broadcast quality filters. They are Virtual 601 post filters with a bandwidth of 5.75MHz. 5-pole, sharp cutoff, Elliptic response, with 3 sections of group delay equalization. These filters were designed for SinX/X compensated CCIR 601 luminance applications and make an excellent post-filter following a D/A converter. The response at 5.0MHz typically varies< 0.25dB with supplies of 5V to 8V . When operating in the 0dB gain mode, pin 6 must be well isolated from ground planes. When operating in the +6dB gain mode, pin 6 must have a low resistance path to ground. For more information please contact Microelectronic Module Corporation (MMC) at 414-785-6506.
Figure 3. TMC2069P7C (10 Bit Triple DAC)
Figure 4. TMC3003, Passive Filters
Figure 5. TMC2069P7C
Figure 6. IPCONN
Figure 7. Power
Table 1. TMC2069P7C Parts List
TMC2069P7C PRODUCT SPECIFICATION Preliminary Information INPUT 96 Way Connector (Female) Row A Row B Row C 32 +5V 32 GND 32 +5v
31 D1 or R/V [bit 0] 31 +5V 31 GND
30 D1 or R/V [bit 1] 30 +5V 30 PXCK
29 D1 or R/V [bit 2] 29 +5V 29 GND
28 D1 or R/V [bit 3] 28 GND 28 PCK
27 D1 or R/V [bit 4] 27 Analog Composite/luma 27 GND
26 D1 or R/V [bit 5] 26 GND 26 CREF
25 D1 or R/V [bit 6] 25 Analog chroma 25 GND
24 D1 or R/V [bit 7] 24 XEN 24 VSYNC
23 D1 or R/V [bit 8] 23 GND 23 HSYNC
22 D1 or R/V [bit 9] 22 XDIR 22 HREF
21 Comp, G/Y, or Luma [bit 0] 21 XHSYNC
21 VREF
20 Comp, G/Y, or Luma [bit 1] 20 XVSYNC 20 ODD IN
19 Comp, G/Y, or Luma [bit 2] 19 XPXCK 19 GND
18 Comp, G/Y, or Luma [bit 3] 18 XRS [bit 3] 18 NTSC/PAL
17 Comp, G/Y, or Luma [bit 4] 17 XRS [bit 2] 17 CLAMP pulse
16 Comp, G/Y, or Luma [bit 5] 16 XRS [bit 1] 16 RGB
15 Comp, G/Y, or Luma [bit 6] 15 XRS [bit 0] 15
14 Comp, G/Y, or Luma [bit 7] 14 GND 14
13 Comp, G/Y, or Luma [bit 8] 13 -5V 13
12 Comp, G/Y, or Luma [bit 9] 12 -5V 12 LOCK
11 Chroma or B/U [bit 0] 11 -5V 11 D1
10 Chroma or B/U [bit 1] 10 GND 10 RESET
9 Chroma or B/U [bit 2] 9 PGM_IN 9 SCL
8 Chroma or B/U [bit 3] 8 -12V 8 GND
7 Chroma or B/U [bit 4] 7 -12V 7 SDA
6 Chroma or B/U [bit 5] 6 IE (input enable) 6 OE (output enable)
5 Chroma or B/U [bit 6] 5 GND 5 BLANK
(DAC)
4 Chroma or B/U [bit 7] 4 4
3 Chroma or B/U [bit 8] 3 3
2 Chroma or B/U [bit 9] 2 +12V 2 +12V
1 GND 1 GND 1 GND
TMC2069P7C PRODUCT SPECIFICATION Preliminary Information Input Edge Connector Design Notes Figure 8. Y/Composite LPF and Clamp Circuit TMC2242 Signal Flow FORWARD Signal Flow BACKWARD TMC2072 TMC3003 EPROM High Quality LPF Low Quality LPF Low Quality LPF Low Quality LPF+5V to -5V 2:1 Mux High Quality LPF High Quality LPF FPGA D.C. Supply SW1 TMC22153Decoder Input Logic 10 bit ADCs Digital LPFs SW1 SW2 TMC1185TMC1185 TMC2242 Chrominance BPF and Clamp Circuit Important: Boards with different revision letters may not be compat- ible. Damage may occur if they are connected together!
- XPXCK is a two times pixel clock fed BACKW ARD.
- XHSYNC and XVSYNC are timing reference signals fed BACKW ARD.
- The MASTER/SLA VE signal states if a board is a MASTER or a SLA VE board. This signal is fed FORW ARD. A MASTER board produces the PXCK, HSYNC, and VSYNC signals, and a SLA VE board expects to receive XPXCK, XHSYNC, XVSYNC, etc .
- XDIR is fed FORW ARD and controls in which direction the XRS[3:0] data flows.
- PGM_IN is a negative going pulse, logically ANDed with the onboard program start pulse, for initiating the programming sequence for components on that board. Care must be taken to ensure that multiple devices do not try to drive the RBUS at any given time. Minimum width of PGM_IN is 1uS.
- The RESET pin on the input edge connector should be connected directly to the RESET pin on the output connector. A link should be used to connect any pulse to the RESET line.
- The MASTER/SLA VE, XDIR, PGM_IN and RESET pins on the input edge connector should be connected to +5V through a 10k pull up resistor.
- The CLAMP signal is fed BACKW ARD from a MASTER to a SLA VE board. The CLAMP signal should not be fed FORW ARD.
Related Products
- TMC2068P7C Decoder demonstration board
- TMC2067P7C ADC demonstration board
- Raydemo software
- TMC2070P7C R-bus interface board
TMC2069P7C PRODUCT SPECIFICATION Preliminary Information 5/20/98 0.0m 001 Stock# DS7002069P Ó
1998 Fairchild Semiconductor Corporation
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com O rdering Information Notes: 1. Setup for use with Genesis 10-bit line doubler and comes with OVER-21 filters instead of 601-003 filters. For information call MMC at 414-785-6516. sales@mmccorp.com A schematic database is available in OrCAD ä format. Contact the factory. The TMC2069P7C Demonstration Board, design documentation, and software are provided as a design example for the customers of Fairchild. Fairchild makes no warranties, express, statutory, or implied regarding merchantability or fitness for a particular purpose. FCC Compliance This device has not been approved by the Federal Communications Commission (FCC). This board is intended for the evalua- tion of Fairchild products only. This device is not and may not be offered for sale or lease or sold or leased until the approval of the FCC has been obtained. Product Number Temperature Range Speed Grade Screening Package Package Marking TMC2069P7C 25 C 80 MHz Commercial 4” by 5” Printed Circuit Board TMC2069P7C TMC2069P7CG C 80 MHz Commercial 4” by 5” Printed Circuit Board TMC2069P7CG