TMC1175A FAIRCHILD | Alldatasheet
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Technical content
$e ICOM tor Division ; Video A/D Converter 8 bit, 40 Msps Features Applications = * 8-mit resolution * Video digitizing” E ‘+ 40 Msps conversion rate + VGA and CCD digitizing = + Low power: 100mW @ 20 Msps. + LCD projection panels * Integral track/hold + Image scanners * Integral and differential linearity error 0.5 LSB + Personal computer video boards * Single +5V power supply * Multimedia systems * Differential phase 0.5 degree * Low cost, high speed data conversion * Differential gain 1.5% + Three-state TTLICMOS-compatible outputs * Low cost Description . - : The TMC1175A/1275 analog-to-digital (A/D) converter ing or eliminating input driving amplifiers. All digital employs a two-step architecture to convert analog signals three-state outputs are TTL- and CMOS-compatible. into 8-bit digital words at sample rates of up to 40 Msps ; ; (Megasamples per second). An integral Track/Hold circuit The TMCL175A and TMC1275 share their core achitec- delivers excellent performance on signals with full-scale fre- tures; the TMC1275 adds two overrange outputs that indicate quency components up to 12 MHz. The innovative architec- When the analog input signal is beyond the conversion range. ture and submicron CMOS technology limit typical power ; . dissipation to 100 mW. ‘The TMC1175A/1275 is available in 24-pin plastic DIP, 24-Iead plastic SOIC, and 28-lead J-lead PLCC packages. The TMC1175A/1275 operates from a single +5 Volt power Performance specifications are guaranteed from -20°C to supply and has internal voltage reference resistors for 75°C. self-bias operation. Input capacitance is very low, simplify- Block Diagram . ch Coarse ‘ => A VR+ 4 ror D; Fe [| Matre Corrector ine VR- 4 ORN* Fine dL “T1275 Only cONV - ~ ; auisan Rev. 1.0.2 2.397 ;
Figure 1. Reference Resistors The A/D converter input range is very flexible and extends , . mance. Similarly, increasing the range can improve differen. V' ransfer function to vary with temperature. ‘Two reference pull-up and pull-down resistors connected to ‘Progress during a reference change is invalid. divided by the on-chip resistors to bias the RT and RB points.
‘TMC1175A/TMC1275 PRODUCT SPECIFICATION . Table 1. Output Codins ‘Whenever the analog input signal is sampled and found to be
- LSB = (Rr~ Re) /255 AGND and DGND pins of the TMC1175A/1275 be con-
- TMCI27s Only nected to the system analog ground plane.
ORN XK N-3 Xk Data N-2 Data N-1 MX DataN . Figure 2. Conversion Timing
Figure 3. Internal Timing
TMCI176ATMC1275 PRODUCT SPECIFICATION Pin Assignments ee < SSz¢98r¢e cE 1 24 Dend <e525c5 Denn 2 23 Rg ASRNSRS . Dp 3 22 VR ns D4 21 Agno vR- 26 q p 18 ORNMppaz 02 6 20 AGno Pe 27 q p 17 ORPMoDAz — Dy 6 19 Vin Denn 28 4 f 16 Vpop Dy 7 18 Vppa we 1g h 15 wc = Ds 8 17 Ry CE 2g h 14 CONV E De 9 16 vRe Deno 34 h 13 Vopo E Dy 10 15 ORNV;ppa2 Do 4q H 12 07 = Vooo 11 14 ORPMippa2 Serer CONV 12 18 Vooo oem onna 1TMCI275 Pin Descriptions ta name [ee PLCC Pin Function Description VIN RT- Rp | Analog Input. The input voltage conversion range lies between the voltages applied to the AT and RB pins. RT 17 2.6V | Reference Voltage Top Input. RT is the top input to the reference resistor ladder. A DC voltage applied to RT defines the positive end of the Vin conversion range. 23 27 | 0.6V | Reference Voltage Bottom Input. Ra is the bottom input to the . reference resistor ladder. A DC voltage applied to Rp defines the negative end of the Vin conversion range. VR Reference Voltage Top Source. VR+ is the internal pull-up reference resistor for self-bias operations. Reference Voltage Bottom Source. VR- is the intemal pull-down. reference resistor for self-bias operations. CMOS | Output Enable. (CMOS-compatible) When LOW, D7-0 are enabled. When HIGH, D7-0 are in a high-impedance state. - CONV 14 | CMOS | Convert (Clock) Input. (CMOS-compatible) Vin is sampled on the falling edge of CONV. D7-0 10-3 12-9, | CMOS/ | Data Outputs (D7 = MSB). Eight-bit CMOS- and TTL-compatible 7-4 | TTL _| digital outputs. Data is output following the rising edge of CONV. 14) 17 CMOS/ | OverRange Positive Output. When HIGH, ORP indicates that the TTL | analog input voltage is at least one LSB higher than the voltage that produces output code FFh. ORP is synchronous with D7-9. CMOS/ | OverRange Negative Output. When HIGH, ORN indicates that the TTL | analog input voltage is at least one LSB lower than the voltage that produces output code 00h. ORN is synchronous with D7-0. " - 2-401
PRODUCT SPECIFICATION ‘TMC1175A/TMC1275 Pin Descriptions (continued) [en name | DIP__| PLCC |PinType| Pin Function Description VoDA 14%, 16, 17%, 18%] +5V | Analog Supply Voltage. These should originate from a common 18 21 +5V source and be decoupled to AGND. Vopp 11,13 | 13,16 | +5V | Digital Supply Voltage. +5 Volt power inputs. These should originate from a common +5V power source and be decoupled to . AGND. [Acno | 20,21 | 24,25 | o.ov | Analog Ground. Connect to the system analog ground plane. - . [Deno | 2,24 [| 3,28 | 0.0v_| Digital Ground. Connect to the system analog ground plane. No Connect Notes: 1. TMC1275 Only. 2. TMC1175A Only. Specification Notes or 62,8V/uis. With an 8-bit A/D converter, q (the quantization step size) = 2V/255 = 7.8mV. The input signal will slew one Bandwidth TSR in 124ps. To limit the error (and noise) contribution due The specification for bandwidth of an A/D converters some- {0 4Pertue fects to VALSB, the aperture must be shorter what different from the normal frequency-response specifi- ian 62ps. cation used in amplifiers and filters. An understanding of the This is the primary reason that the signal to noise ratio drops differences will help in selecting converters properly for par Fras full scale frequency increases. Note, also, that the slew ticular applications. rate is directly proportional to signal amplitude, A. A/Ds will AID conversion comprises two distinct processes: sampling handle lower-amplitude signals of higher bandwidth. aga ard ete ta epastane The an All this is of particular interest in applications such as digi- np ‘ g it ste uzing. The quan- tizing analog VGA RGB signals, or the output of aCCD. y al valoe, Whil ing is a bah frequency pro- is a period of rapid slewing from one pixel value to another, a i antiaine Operates ona de sign igh-f id ready ty th followed by a relatively stable dc level before the signal ess, quantizing operates on a de signal, held steady by the glews to the next pixel value. The goal is, of course, to sam- jold circuit. Therefore, the sampllng, Process 1s Wi ple on these pixel values, not on the slewing between pixels. relates to the dynamic characteristics of the converter, During the aperture time, the A/D sees essentially a dc sig- Sampling involves an aperture time, the time during which __‘#h and classic bandwidth considerations are not important. the track/hold is trying to capture the input signal and settle _AS long asthe input crcl can slew and eile the nett on ade value to hold. Itis analogous to the shutter speed of a Yaiyr in le Prescribed period, an accurale conversion willbe camera: the shorter the aperture (or faster the shutter) the less made. the signal wil be blurred andthe less uncertainty there will The TMIC1175A/127S is capable of slewing a full 2V and in the quantized value, settling between samples taken as little as 25ns apart, mak- For example, 10 MHz sinewave with a1V peak amplitude _iR8it deal for digitizing analog VGA and CCD outputs. (2Vp-p) has a maximum slew rate of 2nfA at zero crossing, 2-402
PRODUCT SPECIFICATION TMCHI7SA/TMC1275 Absolute Maximum Ratings (beyond which the device may be damaged)’ fl [Paranieter | Gondltions Sd in] Wy [Woe] Oni] [Vous MensuredtoAcwo SOS COV Less Heard bone [3 | [of © © [Nppq MeasuredtoVooo | OS PY [Acno | MeasuredtoDeno——SC~d~C | Yo [Forced curen™ TP tO 0m [Applied Votage” | MeasuedtoAcno ———+(| 8 | [Vobaro5] V_| [Forced Gunenf® P| Pt] [Output | Applied Voltage | MeasuredtoDenn | 08 | [Vp +05] Vv [Forced Curent? | ma | Short Circuit Duration | Single outputin HIGH state to ground | ||| S00 | Operating, ambient Pte [dunetion 80] [Storage Pes 80 [Lead Soldering | 40seconds_ | TT 800 [Vapor Phase Soldering [tminute TTT 20S Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if ‘Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 8. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. Operating Conditions [Parameter Min [Nom [Max [Unite | [Vooo | Bigial Power Supphvotese[——=S~C S| 80 | 828 |__| AGND Analog Ground {Measured to Vv Nr [sooremrnre | ee Conversion Rate [ tmcii7eata7s20 | [| 20 | Msps_| [Twcr7sanz7ss0 [| [| 80 | Maps | |Tmori7sariz7s40 [|| 40 | Mps | tewi | CONV Pulsewidth, HIGH [ tMort7eaiz7e20 [1s [Tons | ee ements [| —-—T| | wwortrsaia7s40 [2 J | Ts | (2-404
TMC1175A/TMC1275, PRODUCT ‘SPECIFICATION ee. PRODUCT SPECIFICATION Operating Conditions (continued) [Parameter CS‘ | Nom | Max] Unite | Tew [CONV Pusewiaih, LOW —_[tucrrrearave20_ [as | |_| ne | [aworrrsararss0 [2 [|__| ae _| [Tuctirsarars40 [12 | rs _| [Var [Reference Votage,Top [| 2086 | Vow] vv] — [Vas [Reference votage, otom | ———SSiYo| o8 | a0 | oe [Wer | RotrenesVtage Oren [ "ie [so pr [eee tere fa [me VppD VIL Input Voltage, Logic LOW 0.3x Vv VppD [Ton | Output Current, Logic HIGH | Le ee re ee [ta___[Ambiont Temperature, ar J | 20 fds fe
Electrical Characteristics
[Parameter onions tiny ta [Un Power Supply Curent” ['Voop=Vooa=Max,Cloap=aeF[ | tt ——*d a 15= S0Meps a 1S = 40s [0 [40 [ima J Quiescent [cows tow ae] [Conv= Wee 1020 [ma | Total Power Dissipation | Vooo = Vooa=Max, GLoap=a55F| t_| |_| a [1s=S0Meps as 05m | [1s = 40Msps 8021 | [Convene [Rw [pat Resistance P8000 [18 [input Curent analog a a | | 200 [270 | e40 [2] [1 [Input Curent HIGH | Vooo= Wax Vv=Vooo—_| |_| 8 an] [. _[ ovat Curent, Low | Vooo= wax vin=ov [| a un | [Jozi | Wrz Outpt Leakage | Vooo = Max, Vin=Voo0 |_| | a5 | 4a | [toa [Wrz OuiputLeatage | Vooo=MaxVin=OV | Sd as | [tos | Ster-cireut ourent fe] 2-405
PRODUCT SPECIFICATION ‘TMC1175A/TMC1275 Electrical Characteristics (continued) [Parameter Tomtom Tin] Typ | Max [Unita] VoH | Output Voltage, HIGH ToH = -100nA_ Voopo-03{ | | VC [lon=-2sma fs TT [lon=Max Te Voi | OutputVoltage, LOW | tor=Max | Tf | Goi | Digital input Capactance [ SSSCSCSC~wSSCSC~irC HO | Digtal Ouput Capactance [SSS | Note: 1. Typical values with Vopp = VpDa = Nom and Ta = Nom, Minimum/Maximum values with Vopp = VODA = Max and Ta = Min. Switching Characteristics [Parameter ~~~ ~—Coetvone ‘Tin | yp | Max | Unite | Samping Tine Osa a Output Hold Time CipAd = 18oF Det] | too _ | Output Delay Time CLOAD = 15pF [| of 20 | ns | Output Enable Time 2 [ios [ouiputoisabiotime ———s| CC |r | System Performance Characteristics [Parameter TC i in | THF] Max [Unit] ELI | Integral Linearity Error, | VaT- VAB >= 2.0V 20.75] LSB Independent Differential Linearity Error_| Vat - VRB >= 2.0V |_| 40.3 | 40.5 | LSB | BW | Bandwidth’ TMC1175A/1275-20 10 TMC1175A/1275-30 12 TMC1175A/1275-40 12 [Ear | Aperture Error a Offset Voltage, Top RT — ViN for most positive code transition | -8 | -25 | -42 | mv | | Eos | Offset Voltage, Bottom Re ~ Vin for most negative code transition | 30 | 40 | 50 | mv | Differential Gain fg = 14.3Msps | 27 NTSC 40 IRE Mod Ramp VppA = +5.0V, Ta=25°C Vat — VRB = 2.0V Differential Phase 1S = 14.3Msps deg NTSC 40 IRE Mod Ramp VpDA = +5.0V, TA=25°C. Vat - VrB = 2.0V Notes: 1. Values shown in Typ column are typical for Vopp = VoDA = +5V and Ta = 25°C. 2. ‘Bandwidth is the frequency up to which a full-scale sinewave can be digitized without spurious codes. 2-406
‘TMCII75ATMC1275 PRODUCT SPECIFICATION System Performance Characteristics [Parameter orcs ina ‘Signal-to-Noise Ratio fs = 20Msps, Vin = 2V p-p fiN = 1.24MHz 44 48 dB fiN = 2.48MHz 43 47 4B fiN = 6.98MHz cal 45 dB fin = 10.0MHz 37 42 Ca | =— fg = 30Msps, Vin = 2V p-p E fiN = 1.24MHz 42 47 a | ee fiN = 2.48MHz 40 45 dB fiN = 6.98MHz 38 43 dB fiN = 10.0MHz 33 39 dB fiN = 12.0MHz 30 37 dB - 1g = 40Msps, Vin = 2V p-p fiN = 1.24MHz 40 45 4B fin = 2.48MHz 38 43 dB fiN = 6.98MHz 36 a aB fiN = 10.0MHz 34 38 dB fin = 12.0MHz 32 36 dB SFDR | Spurious-Free Dynamic Range | fs = 20Msps, VIN = 2V p-p fiIN = 1.24MHz 46 62 dB fiN = 2.48MHz 44 51 dB fin = 6.98MHz 4 45 4B fin = 10.0MHz 38 43 dB . fs = 30Msps, VIN = 2V p-p fi = 1.24MHz 42 49 dB fin = 2.48MHz 40 45 aB fiN = 6.98MHz 37 4 dB fIN = 10.0MHz 35 40 dB . fiN = 12.0MHz 34 39 aB fs = 40Msps, VIN = 2V p-p fIN = 1.24MHz 40 44 dB fiN = 2.48MHz 39 43 dB fiN = 6.98MHz 38 4 dB fIN = 10.0MHz 36 40 dB fIN = 12.0MHz 36 39 dB Notes: 1. SNR values do not include the harmonics of the fundamental frequency. 2, SFDRis the ratio in dB of fundamental amplitude to the harmonic with the highest amplitude. 3. Values shown in Typ column are typical for VoDD = VDDA =+8V and Ta = 25°C. 2-407
Figure 8. Typical tpp vs fs Figure 9. Typical SFDR vs fin and fs
10 Taig = 40 Maps to is 59 Mops
Figure 10. Typical SNR vs fin and fs. Figure 11. Typical SNR vs Full Scale Input Range TMC1175A/1275 as well as a bias voltage to offset the R+, provides the bias current for the band-gap reference. is also shown for varying the mid-range voltage level. input range.
PRODUCT SPECIFICATION TMC1175A/TMC1275, 6. CONV should be handled carefully. Jitter and noise on _ing system applications and circuit variations. An on-board this clock may degrade performance. Terminate the D/A converter is provided to reconstruct the digitized signal clock line carefully to eliminate overshoot and ringing. and to evaluate converter performance. Evaluation Board _ Contact your sales representative for information. ‘An eyaluation board is available that implements good inter- face practices and provide a convenient testbed for develop-
Ordering Information
. [ase | ampere ange |_seewne | exe | Wong Product Number Rate | Temperature Range | Screening Package Marking [TMCri7saMrc2o | 20 Maps| Ta=-20°Ct0 75°C _| Commercial | PrLeed SOIC | TH7saM7cz0 | TMCTT7SAM7CI0 | _9OMsPS _[Ta=-20°Ct076°C | Commercial | 2¢Lead SOIC | TI76AM7CS0 | [Twct7eAi7c<0 | 40Mepe | Ta= 20°C 1076°C | Commercial | Aiclaad SOIC | T175AMTOA0 | [TMCTi7sANoCa0 | 20 Maps [Ta=-20°C 10750 | Commercial | atLeed PDIP | T176AN@020 | [rac 75AN20s0 [imcrirsanacoo | s0Maps [Ta=-20°Ct0 790 | Commer | 28:Land PLCC | TY7EARSCSO | [TMGTT7éARGG«) | 40Meps | Ta=-20°C1075°C_| Commercial | 28-Lead BLOC | 1176ARSCA0 | [rmciz7sw7c20 | 20 Maps| Ta=-20°G1075°0 | Commercial | @tLead SOIG | 1275M7G20 2écLead SOIC | Y27647C20 [Tuctarswrcao | 40 Maps| Ta=-20°0t0 76°0_| Commercial | 24-Leed SOIC | e7eM7G30_| [ TucraveNace0 | s0Meps | Ta=-20°Ct0 70 | Commercial | 24-Lead PDIP | T276N2080_| TMCTa7ENae«0 | _40Maps_[Ta=-20GI0 75°C _| Commercial | atLead POIP | T276NeG40_| TMCr27=RaCio a 2-410