TMC1203KLC20

TMC1203 CADEKA | Alldatasheet

Document overview

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Technical content

Features

• 8-bit resolution
• 50 Msps conversion rate
• Low power: 100mW per channel @ 20 Msps
• Integral track/hold
• Independent clock inputs
• Integral and differential linearity error 0.5 LSB
• Differential phase 0.7 degree
• Differential gain 1.8%
• Single +5V power supply
• Three-state TTL/CMOS-compatible outputs
• Low cost

Applications

• V ideo digitizing (composite and Y-C)
• V GA and CCD digitizing
• LCD projection panels
• Image scanners
• Personal computer video boards
• Multimedia systems
• Low cost, high speed data conversion
• Digital communications

Description

Incorporated into the TMC1203 are three analog-to-digital (A/D) converters, each with independent clocks and refer- ence voltages. Analog signals are converted to Triple 8-bit digital words at sample rates up to 50 Msps (Megasamples per second) per channel. Integral Track/Hold circuits deliver excellent performance on signals with full-scale spectral components up to 12 MHz. Innovative two-step architecture conversion architecture and submicron CMOS technology reduce typi- cal power dissipation to 100 mW per converter. Power is derived from a single +5 Volt power supply. Out- puts are three-state outputs and TTL/CMOS-compatible. TMC1203 package is a 80-lead Metric Quad Flat Pack (MQFP). Performance specifications are guaranteed from 0°C to 70°C. Block Diagram 8-bit A/D Converter R TA DA 7-0 OE A CLK A VINA R BA 8-bit A/D Converter R TB DB 7-0 OE B CLK B 65-3720-01 VINB R BB 8-bit A/D Converter R TC DA 7-0 OE C CLK C VINC R BC TMC1203 Triple Video A/D Converter 8-Bit, 50Msps Rev. 1.2.0 www .cadeka.com

clock where ‘X’ is equivalent to A, B or C. part will function with a full-scale range from 1.0V to 5.0V . and some reduced differential linearity performance. of the applied reference voltages. progress during a reference change is invalid. at 00h or FFh, as appropriate. Table 1. A/D Output Coding

1 LSB = (R

the A/D outputs in a high-impedance state when HIGH. The TMC1203 operates from a single +5 V olt power supply.

PRODUCT SPECIFICATION TMC1203 Pin Assignments NC DA 5 DA 6 DA 7 OE A VDD VDD NC CLK A NC VDDA VINA AGND R TA R BA DGND DGND DGND DGND /CR DGND DGND DGND NC NC DGND DGND VDD VDD VDD VDD NC DGND DGND DC 0 DC 1 DC 2 DC 3 DC 4 DC 5 DC 6 Pin Name Pin Name DC 7 OE C VDD VDD CLK C NC VDDA VINC AGND R TC R BC R BB R TB AGND VINB VDDA NC CLK B NC VDD VDD OE B DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 DGND DGND NC DGND DGND DA 0 DA 1 DA 2 DA 3 DA 4 Pin Name Pin Name 12 4 65-3720-08 4164

PRODUCT SPECIFICATION TMC1203 Pin Descriptions Pin Name Pin Number Value Pin Function Description A/D Converters V INA , V INB V INC 12, 55, 48 R TX to R BX Analog Inputs. The input voltage conversion range lies between the voltage applied to the R TX and R BX pins. R TX , R BX R TA , R TB , R TC 14, 53, 50 2.6V Reference Voltage, Top Inputs. DC voltages applied to R TA , R TB and R TC define highest value of V INX R BA , R BB , R BC 15, 52, 51 0.6V Reference Voltage, Bottom Inputs. DC voltages applied to R BA R BB and R BC define highest value of V INX CLK A , CLK B CLK C 9, 58, 45 CMOS Convert (Clock) Inputs. A/D converter clock inputs. CMOS- compatible. V INX is sampled on the falling edge of CLK X . Clock inputs are separate for the three converters. DA 7-0 4, 3, 2, 80, 79, 78, 77, 76 CMOS/ TTL Data outputs, Converter A (D = MSB). Eight-bit CMOS- and TTL-compatible digital outputs. Valid data is output on the rising edge of CLK X DB 7-0 63, 64, 65, 66, 67, 68, 69, 70 CMOS/ TTL Data outputs, Converter B (D = MSB). Eight-bit CMOS- and TTL-compatible digital outputs. Valid data is output on the rising edge of CLK X DC 7-0 41, 40, 39, 38, 37, 36, 35, 34 CMOS/ TTL Data outputs, Converter C (D = MSB). Eight-bit CMOS- and TTL-compatible digital outputs. Valid data is output on the rising edge of CLK X OE A , OE B , OE C 5, 62, 42 CMOS Output Enable Inputs. CMOS-compatible. When LOW, the A/D output is enabled. When HIGH, the output is in a high-impedance state. Output Enables are separate for the three converters. Power V DDA 11, 47, 56 +5V Analog Supply Voltage. +5 Volt power inputs. These should come from the same power source and be decoupled to A GND V DD 6, 7, 27, 28, 29, 30, 43, 44, 60, +5V Digital Supply Voltage. +5 Volt power inputs. These should come from the same power source and be decoupled to A GND A GND 13, 49, 54 0.0V Analog Ground. Ground connections. These pins should be connected to the system analog ground plane. D GND 16, 17, 18, 19, 20, 21, 22, 25, 26, 32, 33, 71, 72, 74, 75 0.0V Digital Ground. Ground connections. These pins should be connected to the system analog ground plane. No Connect 31, 46, 57, 59, open Not Connected.

other distortion effects will be worsened. dc signal, and bandwidth considerations are less important. for digitizing analog VGA and CCD outputs. Figure 1. Timing

PRODUCT SPECIFICATION TMC1203 Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. 5. EIAJ test method. Operating Conditions Analog Inputs Applied Voltage Measured to A GND 2 -0.5 V DDA +0.5 V Forced current 3, 4 -10.0 +10.0 mA Digital Outputs Applied voltage Measured to D GND2 -0.5 V DD + 0.5 V Forced current 3, 4 -6.0 +6.0 mA Short circuit duration Single output in HIGH state to ground) 1 second Temperature Operating, ambient -20 110 °C Junction +150 °C Lead, soldering 10 seconds +300 °C Vapor Phase soldering 1 minute +220 °C Storage -65 +150 °C Electrostatic Discharge5 ±150 V Parameter Min. Nom Max. Units VDD , VDDA , VDDP Power Supply Voltage 4.75 5.0 5.25 V AGND Analog Ground (Measured to DGND ) -0.1 0 0.1 V VRTX Reference Voltage, Top 2.6 V DDA V VRBX Reference Voltage, Bottom 0 0.6 V VRTX -VRBX Reference Voltage Differential 1.0 2.0 5.0 V VINX Analog Input Range V RB VRT V VIH Input Voltage, Logic HIGH 0.7 V DD VDD V VIL Input Voltage, Logic LOW GND 0.3 V DD V IOH Output Current, Logic HIGH -4.0 mA IOL Output Current, Logic LOW 4.0 mA TA Ambient Temperature, Still Air 0 70 °C Absolute Maximum Ratings (continued) (beyond which the device may be damaged)1 Parameter Condition Min Typ Max Unit

TMC1203 PRODUCT SPECIFICATION

Electrical Characteristics

Note: 1. Typical values with VDD = VDDA = Nom and TA = Nom, Minimum/Maximum values with VDD = VDDA = Max. and TA = Min.. Parameter Conditions Min. Typ 1 Max. Units IDD Power Supply Current1 VDD = VDDA = VDDP = Max., CLOAD = 35pF, fCK = fS (3 A/Ds) fS = 20 Msps 70 90 mA fS = 40 Msps 94 120 mA fS = 50 Msps 105 135 mA IDDQ Power Supply Current, Quiescent VDD = VDDA = Max. CLK X = LOW 29 55 mA CLK X = HIGH 45 65 mA PD Total Power Dissipation V DD = VDDA = VDDP = Max., CLOAD = 35pF, fCK = fS (3 A/Ds) fS = 20 Msps 300 470 mW fS = 40 Msps 425 630 mW fS = 50 Msps 490 710 mW C AI Input Capacitance, Analog CLK X = LOW 4 pF CLK X = HIGH 12 pF R IN Input Resistance 500 k W R REF Reference Resistance 200 270 340 W ICB Input Current, Analog ±1 mA IIH Input Current, HIGH V DD = Max., VIN = VDD ±5 mA IIL Input Current, LOW V DD = Max., VIN = 0V ±5 mA IOZH Hi-Z Output Leakage Current, Output HIGH VDD = Max., VIN = VDD ±5 mA IOZL Hi-Z Output Leakage Current, Output LOW VDD = Max., VIN = VDD ±5 mA IOS Short-Circuit Current -35 mA VOH Output Voltage, HIGH I OH = -100mA V DD -0.3 V IOH = -2.5mA 3.5 V IOH = Max. 2.4 V VOL Output Voltage, LOW I OL = Max. 0.4 V C DI Digital Input Capacitance 4 10 pF C DO Digital Output Capacitance 10 pF

PRODUCT SPECIFICATION TMC1203 Switching Characteristics Parameter Conditions Min. Typ. Max. Units fS Conversion Rate TMC1203-20 20 Msps TMC1203-40 40 Msps TMC1203-50 50 Msps t PWH CLKX Pulsewidth, HIGH TMC1203-20 14 ns TMC1203-40 14 ns TMC1203-50 12 ns t PWL CLKX Pulsewidth, LOW TMC1203-20 8 ns TMC1203-40 8 ns TMC1203-50 7 ns E AP Aperture Error 30 ps tSTO Sampling Time Offset 1 2 5 ns tSTS Sampling Time Skew 150 400 ps tHO Output Hold Time CLOAD = 15pF 9 ns tDO Output Delay Time 14 ns tENA Output Enable Time 27 ns tDIS Output Disable Time 42 ns System Performance Characteristics Parameter Conditions Min. 2 Typ1 Max.2 Units ELI Integral Linearity Error, Independent VRT = 2.6V ±0.5 LSB ELD Differential Linearity Error V RB = 0.6V ±0.5 LSB BW Bandwidth 1 TMC1203-20 10 MHz TMC1203-40 12 MHz TMC1203-50 12 MHz E OT Offset Voltage, Top (RT - VIN for most positive code transition) VRT = 2.6V, VRB = 0.6V -40 80 mV EOB Offset Voltage, Bottom (RB - VIN for most negative code transition) VRT = 2.6V, VRB = 0.6V -95 -30 mV dg Differential Gain f S = 14.3Msps NTSC 40 IRE Mod Ramp V DDA = +5.0V, TA=25°C VRT = 2.6V, VRB = 0.6V 1.8 % dp Differential Phase f S = 14.3Msps NTSC 40 IRE Mod Ramp V DDA = +5.0V, TA=25°C VRT = 2.6V, VRB = 0.6V 0.7 deg XTALK Channel Crosstalk f N = 5.0 MHz 45 dB

TMC1203 PRODUCT SPECIFICATION Notes: 1. Values shown in Typ. column are typical for VDD = VDDA =+5V and TA = 25°C. 2. Values shown in Min. and Max. columns are for VDD = VDDA and TA over entire range specified under Operating Conditions. 3. SNR values do not include the harmonics of the fundamental frequency. 4. SFDR is the ratio in dB of fundamental amplitude to the harmonic with the highest amplitude. 5. Characteristics specified for V RT = 2.6V, VRB = 0.6V. 6. Bandwidth is the frequency up to which a full-scale sinewave can be digitized without spurious codes. SNR 3 Signal-to-Noise Ratio f S = 20Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz 46 dB fN = 2.48MHz 46 dB fN = 6.98MHz 45 dB fN = 10.0MHz 45 dB fS = 40Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz 42 dB fN = 6.98MHz 41 dB fN = 12.0MHz 40 dB fN = 20.0MHz 38 dB fS = 50Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz 40 dB fN = 6.98MHz 40 dB fN = 12.0MHz 40 dB SFDR 4 Spurious-Free Dynamic Range f S = 20Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz 53 dB fN = 2.48MHz 48 dB fN = 6.98MHz 44 dB fN = 10.0MHz 40 dB fS = 40Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz 49 dB fN = 6.98MHz 44 dB fN = 12.0MHz 38 dB fS = 50Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz 46 dB fN = 6.98MHz 40 dB fN = 12.0MHz 37 dB System Performance Characteristics (continued) Parameter Conditions Min. 2 Typ1 Max.2 Units

Figure 10. Typical Interface Circuit - High Performance circuitry is a standard 741-type. analog input voltage at VINX to the safe operating range. referred to the system digital ground plane. performance is strongly influenced by the board layout.

1. Keep the critical analog traces (V

as possible and as far as possible from all digital signals.

PRODUCT SPECIFICATION TMC1203 2. Segregate traces:

• A/D analog
• D/A analog
• Clocks
• Digital Treat analog inputs as transmission lines. Cleanly route traces over the ground plane bearing in mind that the return currents will flow through the ground plane beneath the traces. Do not route digital traces nearby. A few inches of digital trace less than a few line widths from an analog trace will cross-couple noise into adjacent analog circuits. 3. The power plane for the TMC1203 should be separate from that which supplies the rest of the digital circuitry. A single power plane should be used for all of the V DD pins. If the power supply for the TMC1203 is the same as that of the system's digital circuitry, power to the TMC1203 should be decoupled with ferrite beads and 0.1mF capacitors to reduce noise. 4. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. 5. Decoupling capacitors should be applied liberally to V DD pins. Remember that not all power supply pins are created equal. They supply different circuits on the inte- grated circuit, each of which generate varying amounts and types of noise. For best results, use 0.1mF ceramic capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice. 6. If the digital power supply has a dedicated power plane layer, it should not be placed under the TMC1203, the voltage reference, or the analog inputs. Capacitive cou- pling of digital power supply noise from this layer to the TMC1203 and its related analog circuitry can have an adverse effect on performance. 7. CLK X should be handled carefully. Jitter and noise on this clock may degrade performance. Terminate the clock line, if needed, to eliminate overshoot and ringing.

Related Products

• TMC1175A, TMC1275 8-Bit Video A/D Converters
• TMC1173A, TMC1273 3V , Low-Power 8-Bit Video A/D Converters
• TMC1103 Triple 8-bit A/D with Clamps and PLL
• TMC3003/TMC3503 Triple Video D/A Converters
• TMC2242B/TMC2243/TMC2246A Digital Filters

TMC1203 PRODUCT SPECIFICATION Notes:

PRODUCT SPECIFICATION TMC1203 Mechanical Dimensions – 80-Lead MQFP Package -C- LEAD COPLANARITY Seating Plane ccc C See Lead Detail Base PlaneA A2 E D Pin 1 Identifier B e Lead Detail R C L a Datum Plane 0¡ Min. .20 (.008) Min. .13 (.30) .005 (.012) 0.063" Ref (1.60mm) A — .134 — 3.40 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .010 — .25 — .018 .45 A2 .100 .120 2.55 3.05 B .012 3, 5 .30 .009 .23C .005 .13 E .667 .687 16.95 17.45 .0315 BSC .80 BSCe L .025 .041 .65 1.03 80 80 24 24 N ND 16 16NE a 0¡ 7¡ 0¡ 7¡ — .004 — 0.10ccc D .904 .923 22.95 23.45 D1 .783 .791 19.90 20.10 E1 .547 .555 13.90 14.10 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982. Controlling dimension is millimeters. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. "L" is the length of terminal for soldering to a substrate. "B" & "C" includes lead finish thickness. .13 (.005) R Min.

TMC1203 PRODUCT SPECIFICATION 5/20/98 0.0m 001 Stock# DS70001203 O rdering Information Product Number Co nversion Rate (Msps) Temperature Range Screening Package Package Marking TMC1203KLC20 20 Msps TA = 0°C to 70°C Commercial 80-Lead MQFP 1203KLC20 TMC1203KLC40 40 Msps TA = 0°C to 70°C Commercial 80-Lead MQFP 1203KLC40 TMC1203KLC50 50 Msps TA = 0°C to 70°C Commercial 80-Lead MQFP 1203KLC50