TMC1175AM7C30

TMC1175A CADEKA | Alldatasheet

Document overview

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Technical content

Features

• 8-Bit resolution
• 40 Msps conversion rate
• Low power: 100mW at 20 Msps
• Integral track/hold
• Integral and differential linearity error 0.5 LSB
• Single or dual +5 Volt supplies
• Differential phase 0.5 degree
• Differential gain 1.5%
• Three-state TTL/CMOS-compatible outputs
• Low cost

Applications

• Video digitizing
• VGA and CCD digitizing
• LCD projection panels
• Image scanners
• Personal computer video boards
• Multimedia systems
• Low cost, high speed data conversion

Description

The TMC1175A analog-to-digital (A/D) converter employs a two-step flash architecture to convert analog signals into 8-bit digital words at sample rates of up to 40 Msps (Megasamples per second). An integral Track/Hold circuit delivers excellent performance on signals with full-scale fre- quency components up to 12 MHz. Innovative architecture and submicron CMOS technology limit typical power dissi- pation to 100 mW. Power may be derived from either single or dual +5V supplies. Internal voltage reference resistors allow self-bias operation. Input capacitance is very low, simplifying or eliminating input driving amplifiers. All digital three-state outputs are TTL- and CMOS-compatible. The TMC1175A is available in 24-lead plastic SOIC, and 28-lead J-lead PLCC packages. Performance specifications are guaranteed from -20°C to 75°C. Block Diagram Reference Matrix D7-0 VIN VR+ RT RB VR– Track/ Hold OE CONV 24453A Coarse Quantizer Digital Error- Corrector Fine Quantizer www.cadeka.com

damaged by signals within the range AGND to VDDA. part will function with a full-scale range from 1.0V to 5.0V . on the input signal conditioning circuitry. bility of the applied reference voltages. divided by the on-chip resistors to bias the RT and RB points. Figure 1. Reference Resistors verter transfer function to vary with temperature. end up on the conversion data output. progress during a reference change is invalid.

Table 1. Output Coding puts are enabled when OE is LOW. may be connected to a separate regulated +5 volt supply. sequence is immaterial. Latch-up will not occur. analog input sections of the TMC1175A. Figure 2. Conversion Timing

Figure 3. Internal Timing

PRODUCT SPECIFICATION TMC1175A REV. 1.3.3 2/28/02 5 Pin Descriptions Pin Name Pin Number Pin Type Pin Function DescriptionM7 R3 Inputs VIN 19 23 R T – RB Analog Input. The input voltage conversion range lies between the voltages applied to the RT and RB pins. RT 17 20 2.6V Reference Voltage Top Input. RT is the top input to the reference resistor ladder. A DC voltage applied to RT defines the positive end of the VIN conversion range. RB 23 27 0.6V Reference Voltage Bottom Input. RB is the bottom input to the reference resistor ladder. A DC voltage applied to RB defines the negative end of the VIN conversion range. VR+ 16 19 Reference Voltage Top Source. VR+ is the internal pull-up reference resistor for self-bias operations. VR– 22 26 Reference Voltage Bottom Source. VR- is the internal pull-down reference resistor for self-bias operations. OE 1 2 CMOS Output Enable. (CMOS-compatible) When LOW, D7-0 are enabled. When HIGH, D7-0 are in a high-impedance state. CONV 12 14 CMOS Convert (Clock) Input. (CMOS-compatible) VIN is sampled on the falling edge of CONV. Outputs D 7-0 10–3 12–9, 7–4 CMOS/ TTL Data Outputs (D7 = MSB). Eight-bit CMOS- and TTL-compatible digital outputs. Data is output following the rising edge of CONV. Power V DDA 14, 15, 18 17, 18, +5V Analog Supply Voltage. Independent +5 volt power connection to analog comparator circuits. VDDD 11, 13 13, 16 +5V Digital Supply Voltage. Independent +5 volt power connection to digital error correction and output drivers. AGND 20, 21 24, 25 0.0V Analog Ground. Connect to the system analog ground plane. DGND 2, 24 3, 28 0.0V Digital Ground. Connect to the system analog ground plane. No Connect N/C 1, 8, 15, open Not Connected. Bandwidth Specification Notes The specification for bandwidth of an A/D converter is some- what different from the normal frequency-response specifi- cation used in amplifiers and filters. An understanding of the differences will help in selecting converters properly for par- ticular applications. A/D conversion comprises two distinct processes: sampling and quantizing. Sampling is “grabbing” a snapshot of the input signal and holding it steady for quantizing. The quan- tizing process is approximating the analog input, which may be any value within the conversion range, with its nearest numerical value. While sampling is a high-frequency pro- cess, quantizing operates on a dc signal, held steady by the track/hold circuit. Therefore, the sampling process is what relates to the dynamic characteristics of the converter. Sampling involves an aperture time, the time during which the track/hold is trying to capture the input signal and settle on a dc value to hold. It is analogous to the shutter speed of a camera: the shorter the aperture (or faster the shutter) the less the signal will be blurred, and the less uncertainty there will be in the quantized value. For example, a 10 MHz sinewave with a 1V peak amplitude (2Vp-p) has a maximum slew rate of 2πfA at zero crossing, or 62.8V/µs. With an 8-bit A/D converter, q (the quantization step size) = 2V/255 = 7.8mV . The input signal will slew one LSB in 124ps. To limit the error (and noise) contribution due to aperture effects to 1/2LSB, the aperture must be shorter than 62ps.

PRODUCT SPECIFICATION TMC1175A REV. 1.3.3 2/28/02 7 Absolute Maximum Ratings (beyond which the device may be damaged)1 Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if operating conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device Parameter Conditions Min Typ Max Unit Power Supply Voltages VDDA Measured to AGND -0.5 7.0 V VDDD Measured to DGND -0.5 7.0 VDDA Measured to VDDD -0.5 0.5 V AGND Measured to DGND -0.5 0.5 Digital Inputs Applied Voltage 2 Measured to DGND -0.5 VDDD + 0.5 V Forced Current3,4 -10.0 10.0 mA Analog Inputs Applied Voltage 2 Measured to AGND -0.5 VDDA + 0.5 V Forced Current3,4 -10.0 10.0 mA Outputs Applied Voltage 2 Measured to DGND -0.5 VDDD + 0.5 V Forced Current3,4 -6.0 6.0 mA Short Circuit Duration Single output in HIGH state to ground 1 sec Temperature Operating, Ambient -20 110 °C Junction 150 °C Storage -65 150 °C Lead Soldering 10 seconds 300 °C Vapor Phase Soldering 1 minute 220 °C

TMC1175A PRODUCT SPECIFICATION 8 REV. 1.3.3 2/28/02 Operating Conditions Parameter Min Nom Max Units VDDD Digital Power Supply Voltage 4.75 5.0 5.25 V VDDA Analog Power Supply Voltage 4.75 5.0 5.25 V AGND Analog Ground (Measured to DGND) -0.1 0 0.1 V fS Conversion Rate TMC1175A-20 20 Msps TMC1175A-30 30 Msps TMC1175A-40 40 Msps tPWH CONV Pulsewidth, HIGH TMC1175A-20 15 ns TMC1175A-30 13 ns TMC1175A-40 12 ns tPWL CONV Pulsewidth, LOW TMC1175A-20 15 ns TMC1175A-30 12 ns TMC1175A-40 12 ns VRT Reference Voltage, Top 2.0 2.6 V DDA V VRB Reference Voltage, Bottom 0 0.6 3.0 V VRT-VRB Reference Voltage Differential 1.0 5.0 V VIN Analog Input Range VRB VRT V VIH Input Voltage, Logic HIGH 0.7 x VDDD VDDD V VIL Input Voltage, Logic LOW GND 0.3 x VDDD V IOH Output Current, Logic HIGH -4.0 mA IOL Output Current, Logic LOW 4.0 mA TA Ambient Temperature, Still Air -20 75 °C

Electrical Characteristics

Parameter Conditions Min Typ 1 Max Units IDD Power Supply Current1 VDDD = VDDA = Max, CLOAD = 35pF fS = 20Msps 20 30 mA fS = 30Msps 25 35 mA fS = 40Msps 30 40 mA IDDQ Power Supply Current, Quiescent V DDD = VDDA = Max CONV = LOW 7 18 mA CONV = HIGH 10 20 mA PD Total Power Dissipation V DDD = VDDA = Max, CLOAD = 35pF fS = 20Msps 100 160 mW fS = 30Msps 125 185 mW fS = 40Msps 150 210 mW CAI Input Capacitance, Analog CONV = LOW 4 pF CONV = HIGH 12 pF RIN Input Resistance 500 1000 kΩ

PRODUCT SPECIFICATION TMC1175A REV. 1.3.3 2/28/02 9 Note: 1. Typical values with VDDD = VDDA = Nom and TA = Nom, Minimum/Maximum values with VDDD = VDDA = Max and TA = Min. Switching Characteristics ICB Input Current, Analog ±1 µA RREF Reference Resistance 200 270 340 Ω IIH Input Current, HIGH V DDD = Max, VIN = VDDD ±5 µA IIL Input Current, LOW VDDD = Max, VIN = 0V ±5 µA IOZH Hi-Z Output Leakage V DDD = Max, VIN = VDDD ±5 µA IOZL Hi-Z Output Leakage V DDD = Max, VIN = 0V ±5 µA IOS Short-Circuit Current -30 mA VOH Output Voltage, HIGH I OH = -100µA VDDD-0.3 V IOH = -2.5mA 3.5 V IOH = Max 2.4 V VOL Output Voltage, LOW I OL = Max 0.4 V CDI Digital Input Capacitance 4 10 pF CDO Digital Output Capacitance 10 pF Parameter Conditions Min Typ Max Units tSTO Sampling Time Offset 2 5 8 ns tHO Output Hold Time CLOAD = 15pF 5 ns tDO Output Delay Time CLOAD = 15pF 20 ns tENA Output Enable Time 27 ns tDIS Output Disable Time 42 ns Electrical Characteristics (continued) Parameter Conditions Min Typ 1 Max Units

TMC1175A PRODUCT SPECIFICATION 10 REV. 1.3.3 2/28/02 System Performance Characteristics Parameter Conditions Min Typ 1 Max Units ELI Integral Linearity Error, Independent VRT = 2.6V VRB = 0.6V ±0.5 ±1 LSB ELD Differential Linearity Error V RT = 2.6V VRB = 0.6V ±0.3 ±1 LSB BW Bandwidth 2 TMC1175A-20 TMC1175A-30 TMC1175A-40 MHz MHz MHz E AP Aperture Error 30 ps EOT Offset Voltage, Top R T – VIN for most positive code transition -8 -25 -42 mV EOB Offset Voltage, Bottom R B – VIN for most negative code transition 30 40 60 mV dg Differential Gain fS = 14.3Msps NTSC 40 IRE Mod Ramp V DDA = +5.0V, TA=25°C VRT = 2.6V, VRB = 0.6V 1.5 2.7 % dp Differential Phase f S = 14.3Msps NTSC 40 IRE Mod Ramp V DDA = +5.0V, TA=25°C VRT = 2.6V, VRB = 0.6V 0.5 1.0 deg SNR3 Signal-to-Noise Ratio f S = 20Msps, VRT = 2.6V, VRB = 0.6V fIN = 1.24MHz 44 48 dB fIN = 2.48MHz 43 47 dB fIN = 6.98MHz 41 45 dB fIN = 10.0MHz 37 42 dB fS = 30Msps, VRT = 2.6V, VRB = 0.6V fIN = 1.24MHz 42 47 dB fIN = 2.48MHz 40 45 dB fIN = 6.98MHz 38 43 dB fIN = 10.0MHz 33 39 dB fIN = 12.0MHz 30 37 dB fS = 40Msps, VRT = 2.6V, VRB = 0.6V fIN = 1.24MHz 40 45 dB fIN = 2.48MHz 38 43 dB fIN = 6.98MHz 36 41 dB fIN = 10.0MHz 34 38 dB fIN = 12.0MHz 32 36 dB

PRODUCT SPECIFICATION TMC1175A REV. 1.3.3 2/28/02 11 Notes: 1. Values shown in Typ column are typical for V DDD = VDDA = +5V and TA = 25°C. 2. Bandwidth is the frequency up to which a full-scale sinewave can be digitized without spurious codes. 3. SNR values do not include the harmonics of the fundamental frequency. 4. SFDR is the ratio in dB of fundamental amplitude to the harmonic with the highest amplitude. SFDR4 Spurious-Free Dynamic Range fS = 20Msps, VRT = 2.6V, VRB = 0.6V fIN = 1.24MHz 46 52 dB fIN = 2.48MHz 44 51 dB fIN = 6.98MHz 41 45 dB fIN = 10.0MHz 38 43 dB fS = 30Msps, VRT = 2.6V, VRB = 0.6V fIN = 1.24MHz 42 49 dB fIN = 2.48MHz 40 45 dB fIN = 6.98MHz 37 41 dB fIN = 10.0MHz 35 40 dB fIN = 12.0MHz 34 39 dB fS = 40Msps, VRT = 2.6V, VRB = 0.6V fIN = 1.24MHz 40 44 dB fIN = 2.48MHz 39 43 dB fIN = 6.98MHz 38 41 dB fIN = 10.0MHz 36 40 dB fIN = 12.0MHz 36 39 dB System Performance Characteristics (continued) Parameter Conditions Min Typ 1 Max Units

TMC1175A PRODUCT SPECIFICATION 14 REV. 1.3.3 2/28/02 4. Decoupling capacitors should be applied liberally to VDD pins. Remember that not all power supply pins are created equal. They supply different circuits on the inte- grated circuit, each of which generate varying amounts and types of noise. For best results, use 0.1µF ceramic capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice. 5. If the digital power supply has a dedicated power plane layer, it should not be placed under the TMC1175A, the voltage reference, or the analog inputs. Capacitive cou- pling of digital power supply noise from this layer to the TMC1175A and its related analog circuitry can have an adverse effect on performance. 6. CONV should be handled carefully. Jitter and noise on this clock may degrade performance. Terminate the clock line at the CONV input, if required, to eliminate overshoot and ringing. Evaluation Board An evaluation board is available that implements good inter- face practices and provide a convenient testbed for develop- ing system applications and circuit variations. An on-board D/A converter is provided to reconstruct the digitized signal and to evaluate converter performance. Contact your sales representative for information.

PRODUCT SPECIFICATION TMC1175A REV. 1.3.3 2/28/02 15 Mechanical Dimensions 24 Lead SOIC (5.4 mm) Package 0.51 0.31 0.30 15.50 5.60 8.10 0.10

1.27 BSC

1.90 .050 BSC .020 .004 .012 .012 .610 .220 .319 N ccc e C E D B .014 .004 .006 .587 .205 .295 A .067 .075 0.36 0.10 1.70 0.15 14.90 5.20 7.50 LEAD COPLANARITY ccc -C- C 1 12 E α h x 45° C L D A Be SEATING PLANE 8α° 0 8 0 0.50 1.27 h L .010 .016 .020 .050 0.25 0.41 Symbol Inches Min. Max. Min. Max. Millimeters Notes

TMC1175A PRODUCT SPECIFICATION 16 REV. 1.3.3 2/28/02 Mechanical Dimensions (continued)

28 Lead PLCC Package

D e E A .165 .180 4.19 4.57 Symbol Inches Min. Max. Min. Max. Millimeters Notes E1 J A A2 B D3/E3 J – C – ccc C LEAD COPLANARITY A1 .090 .120 2.29 3.05 A2 .020 .51— — B .013 .021 .33 .53 D/E .485 .495 12.32 12.57 D1/E1 .450 .456 11.43 11.58 D3/E3 .300 BSC 7.62 BSC e .050 BSC 1.27 BSC J .042 .048 1.07 1.22 2 ND/NE 7 7 N 28 28 ccc .004 0.10— — B1 .026 .032 .66 .81 Notes: All dimensions and tolerances conform to ANSI Y14.5M-1982 Corner and edge chamfer (J) = 45° Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)

TMC1175A PRODUCT SPECIFICATION 2/28/02 0.0m 002 Stock#DS7001175A

Ordering Information

Rate Temperature Range Screening Package Package Marking TMC1175AM7C20 20 Msps TA = -20°C to 75°C Commercial 24-Lead SOIC 1175AM7C20 TMC1175AM7C30 30 Msps TA = -20°C to 75°C Commercial 24-Lead SOIC 1175AM7C30 TMC1175AM7C40 40 Msps TA = -20°C to 75°C Commercial 24-Lead SOIC 1175AM7C40 TMC1175AR3C20 20 Msps TA = -20°C to 75°C Commercial 28-Lead PLCC 1175AR3C20 TMC1175AR3C30 30 Msps TA = -20°C to 75°C Commercial 28-Lead PLCC 1175AR3C30 TMC1175AR3C40 40 Msps TA = -20°C to 75°C Commercial 28-Lead PLCC 1175AR3C40

For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2009 by CADEKA Microcircuits LLC. All rights reserved. CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) Ampl ify t he H uman Ex per ience TMC1175AW7C20 20 Msps TA = -20°C to 75°C Commercial 24-Lead SOIC (0.300 wide body SOIC) 1175AW7C20 24 Lead SOIC, 0.300 Wide Body Package 3142 211 A .093 .104 2.35 2.65 Symbol Inches Min. Max. Min. Max. Millimeters Notes A1 .004 .012 0.10 0.30 .020 0.51B .013 0.33 C .009 .013 0.23 0.32 E .290 .299 7.36 7.60 e .394 .419 10.00 10.65 .010 .020 0.25 0.51 H .050 BSC 1.27 BSC h L .016 .050 0.40 1.27 0° 8° 0° 8° N 24 24 α ccc .004 0.10— — D .599 .614 15.20 15.60 Notes: Dimensioning and tolerancing per ANSI Y14.5M-1982. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). "L" is the length of terminal for soldering to a substrate. Terminal numbers are shown for reference only. "C" dimension does not include solder finish thickness. Symbol "N" is the maximum number of terminals. HE A D e B – C – ccc C LEAD COPLANARITY SEATING PLANE α h x 45° L C Addendum 03/03/09 CADEKA Adds New Package Option