TMB2193MS100 FAIRCHILD | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 24
Technical content
Features
- 10-bit or 20-bit Parallel YCbCr input
- 24-bit RGB input
- D1, Genlock and Master mode operation
- Composite, S-video and component analog outputs
- Digital Composite output
- Fairchild demo board compatibility
Applications
- Evaluation of TMC2193 DENC
- Evaluation of TMC2072 Genlock interface
- Output for TMC2068P7C Decoder demo board
- System Breadboarding
Description
The TMB2193MS100 demonstration board provides a flexi- ble base for evaluating the performance of the TMC2193 Digital Video Encoder (DENC). The demonstration board can be driven by either a D1 or Genlock signal, or it can sup- ply the synchronization signals needed to drive a framestore or any MPEG Decoder. Both YCbCr, in either 4:2:2, D1, or 4:4:4 formats, and RGB inputs are supported. The board provides high quality analog composite video, analog S-video, analog component video and digital composite video outputs. Block Diagram
96 Way
(female) RBUS Connector 65-B2193-01 Digital Inputs: 10 bit D1 24 bit RGB 20 bit YCbCr PXCK Analog Outputs: Composite S-Video RGB YPbPr Sync Digital Outputs (Optional): 10 bit DCVBS HSYNC VSYNC PXCK Digital Outputs: HSYNC VSYNC MPXCK TMC2193 FPGA TMC2072 MCU +5V 0V -5V Analog LPF TMB2193MS100 Demonstration Board for the TMC2193 Rev. 0.9.0
a video framestore with no additional glue logic. which map to load from the PROG[3-0] (Px) dip switches. Table 1. Default Control Register Maps
Table 2. FPGA Control 1 Table 3. FPGA Control 2
1 REFSEL CVBS Input
0 B[5:2] bus
1 GENLOCK
0 SYNCSEL HSIN, VSIN Input
0 IXH and IXV
1 GH and GV
Table 4. Switch, Button, and Jumper Description boards connected to the TMB2193MS100 are driven by MRST. the reset line on all boards connected to the TMB2193MS100 are driven by MRST. CASC INT Cascade Programming Enable. When CASC INT is open, the AT89C55 automatically initializes the devices after reset. before initializing the devices on the TMB2193MS100. RBUSEN When RBUSEN is open, the RBUS port is disabled. When RBUSEN is closed, the RBUS port is enabled.
clock oscillator as the clock source.
- Set P3-0 to 0h, P3 is ON (down), P2 is ON (down), P1 is
ON (down), and P0 is ON (down).
- Plug in power supply connector and apply power. The
- Reset board by pressing the MRST button.
- Connect a scope probe to TP25 and adjust R39 until the
sync to blank amplitude is 286 mV .
- Connect a scope probe to TP19 and adjust R36 until the
sync to blank amplitude is 286 mV .
- Connect a scope probe to TP21 and adjust R37 until the
sync to blank amplitude is 286 mV .
- Connect a scope probe to TP23 and adjust R38 until the
When JPx is open, the output video is a single 75Ohm termination. When JPx is closed, the output video is a double 75Ohm termination. Selects either the PXCK from the TMC2072 or the onboard TTL clock oscillator. is the PXCK from the input header. E3 Output Header Clock Selection. (down), ESAx is in a LOW state. When SAx is OFF (up), ESAx is in a HIGH state. GSA1 is in a LOW state. When CAS is OFF (up), GSA1 is in a HIGH state. GSA0 is in a LOW state. When ERS is OFF (up), GSA0 is in a HIGH state. P3-0 Control Register Programming. Default Control Register Maps for a description. Table 4. Switch, Button, and Jumper Description (continued)
PRODUCT SPECIFICATION TMB2193MS100 Preliminary Information Figure 1. TMB2193 0.9.0 TOP Raytheon Electronics - Semiconductor Division 5580 Morehouse Dr. San Diego, CA 92121 B 11 2Thursday, September 04, 1997 Title Size Document Number Rev Date: Sheet of CKDRIVE CKDRIVE MPXCK EPXCK FPXCK OPXCK GPXCK IXPXCK 675MCLK 135MCLK HEADERIN HEADERIN IXHSYNC IXVSYNC IXPXCK MPXCK SDA SCL HSOUT VSOUT PGM_IN A_DEL[0..9] B[0..9] C[0..9] RESET FRESET A[0..9] FPGA FPGA A_DEL[0..9] B[0..9] C[0..9] CVBS[0..7] GHSYNC GVSYNC IXHSYNC IXVSYNC PD[0..23] ECVBS[0..9] HSIN VSIN OLENG[0..5] FMCU[0..7] IXPXCK FPXCK 675MCLK A[0..9] GENLOCK GENLOCK CVBS[0..7] SDA SCL GHSYNC GVSYNC GPXCK GMCU[0..6] MCU MCU EMCU[0..3] GMCU[0..6] SDA PGM_OUT FMCU[0..7] PGM_IN SCL FRESET 135MCLK RESET VSOUT HEADEROUT HEADEROUT HSOUT VSOUT DCVBS[0..9] SDA SCL RESET OPXCK PGM_OUT TMC2193 TMC2193 PD[0..23] ECVBS[0..9] EPXCK HSIN VSIN DCVBS[0..9] HSOUT VSOUT SDA SCL OLENGI[0..5] EMCU[0..3] POWER {Schematic} A_DEL[0..9] B[0..9] C[0..9] CVBS[0..7] IXHSYNC\\ IXVSYNC\\ GHSYNC GVSYNC GPXCK IXPXCK IXPXCK FPXCK MPXCK PD[0..23] ECVBS[0..9] OLENG[0..5] DCVBS[0..9] HSIN OPXCK GMCU[0..6] FMCU[0..7] PGM_IN RESET\\ PGM_OUT FRESET\\ VSIN HSOUT SDA VSOUT EMCU[0..3] EPXCK SCL A[0..9] 675MCLK 135MCLK 65-B2193-02
TMB2193MS100 PRODUCT SPECIFICATION Preliminary Information Figure 2. Friday, February 07, 1997 TMB2193 0.9.0 CKDRIVE.SCH Raytheon Electronics - Semiconductor Division
5580 Morehouse Drive
San Diego, CA 92121 (619) 457-1000 B 91 2 Title Size Document Number Rev Date: Sheet of VCCVCC VCC PLACE COMPONENTS ON THIS PAGE CLOSE TO THE GENLOCK. GPXCK MPXCK IXPXCK PASS MPXCK FPCXK EPXCK OPXCK 0.1µF U2A 74F14 U1A 74F240 A12 A24 A36 A48 Y1 18 Y2 16 Y3 14 Y4 12 U1B 74F240 A111 A213 A315 A417 G19 Y1 9 Y2 7 Y3 5 Y4 3 SELECT 27MHz OUT 5 SELECT U10A 74F74 CLK3 Q 5 Q 6 PR 4CL1 U10B 74F74 D12 CLK11 Q 9 Q 8 PR 10CL13 MPXCK EPXCK FPXCK OPXCK GPXCK IXPXCK 135MCLK 675MCLK VCC 0.1µF 0.1µF 65-B2193-03
PRODUCT SPECIFICATION TMB2193MS100 Preliminary Information Figure 3. TMB2193 0.9.0 FPGA.SCH Raytheon Electronics - Semiconductor Division 65-B2193-04 5580 Morehouse Dr. San Diego, CA 92121 B 31 2Thursday, September 04, 1997 Title Size Document Number Rev Date: Sheet of VCC VCC BYTE BLASTER GHSYNC GVSYNC IXHSYNC\\ IXVSYNC\\ VSIN HSIN IXPXCK FPXCK CVBS5 CVBS3 CVBS6 PD22 PD20 PD21 PD4 PD2 OLENG5 PD20 PD12 PD7 PD18 CVBS7 ECVBS2 A_DEL6 OLENG4 A_DEL7 PD19 PD14 FMCU7 PD9 PD8 FMCU0 GHSYNC PD9 PD23 FMCU1 PD6 PD5 PD23 PD7 PD4 VSIN ECVBS6 IXHSYNC\\ GVSYNC PD16 PD22 PD21 PD3 PD1 FMCU1 PD2 ECVBS7 ECVBS8 ECVBS9 ECVBS4 HSIN IXVSYNC\\ OLENG3 A_DEL4 FMCU2 CVBS7 ECVBS5 FPXCK OLENG1 OLENG2 CVBS6 CVBS0 FMCU5 PD10 OLENG0 CVBS1 FMCU3 PD0 PD11 PD17 CVBS4 PD10 A_DEL9 A_DEL5 A_DEL3 A_DEL8 A_DEL0 A_DEL1 FMCU3 B6A7 CVBS2 CVBS0 FMCU4 CVBS1 FMCU6 FMCU5 FMCU2 CVBS2 FMCU7 PD19 CVBS5 PD16 PD17 PD15 PD18 PD8 FMCU4 FMCU6 PD13 FMCU0 PD14 PD11 PD12 ECVBS3 PD1 PD5 PD15 CVBS3 CVBS4 PD3 PD0 PD13 PD6 OLENG1 OLENG5 OLENG2 OLENG0 OLENG4 OLENG3 A_DEL5 A_DEL7 A_DEL9 A_DEL0 A_DEL4 A_DEL1 A_DEL8 A_DEL3 A_DEL2 A_DEL6 ECVBS9 ECVBS5 ECVBS4 ECVBS7 ECVBS0 ECVBS2 ECVBS6 ECVBS3 ECVBS8 ECVBS1 A_DEL2 EPC1PC8 DATA 1 DCLK2 OE3 nCS4 nCASC 6 C10 0.1µF U11 EPF10K10TC144 MSEL077 MSEL176 nSTATUS35 nCONFIG74 DCLK107 CONF_DONE2 INIT_DONE14 nCE106 nCEO3 nWS142 nRS141 nCS144 CS143 RDYnBSY11 CLKUSR7 DATA7116 DATA6114 DATA0108 DATA1109 DATA2110 DATA3111 DATA4112 DATA5113 TDI105 TDO4 TCLK1 TMS34 DEDIN54 DEDIN56 DEDIN124 DEDIN126 GCLK0125 GCLK155 DEV_CLRn122 DEV_OE128 1010 1212 1313 1818 1919 2020 2121 2222 2323 2626 2727 2828 2929 3030 3131 3232 33 3336 3637 3738 3839 3941 4142 4243 4344 4446 4647 4748 4849 4951 5159 5960 6062 6263 6364 6465 6567 6768 6869 6970 7072 7273 7378 7879 7980 8081 8182 8283 8386 8687 8788 8889 8990 9091 9192 9295 9596 9697 9798 9899 99100 100101 101102 102117 117118 118119 119120 120121 121130 130131 131132 132133 133135 135136 136137 137138 138140 140 1717 JP1 HEADER 5X2 910 B[0..9] C[0..9] CVBS[0..7] GHSYNC GVSYNC IXHSYNC\\ IXVSYNC\\ PD[0..23] ECVBS[0..9] HSIN VSIN FMCU[0..7] IXPXCK FPXCK OLENG[0..5] A_DEL[0..9] A[0..9] 675MCLK VCC C19 0.1µF 1K C11 0.1µF C12 0.1µF C13 0.1µF C14 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
TMB2193MS100 PRODUCT SPECIFICATION Preliminary Information Figure 4. Monday, January 20, 1997 TMB2193 0.9.0 GENLOCK.SCH Raytheon Electronics - Semiconductor Division San Diego, CA 92121 (619) 457-1000 B 21 2 Title Size Document Number Rev 65-B2193-05 Date: Sheet of VCC VCC VCC VCC VCC STUFF EITHER C36 OR CR1 STUFF: A for TMC2072 B for TMC22071A SDA GD0 GCS GSA0 GRW\\ GVSYNC GSA1 GRESET\\ GHSYNC GHSYNC GVSYNC GPXCK GPXCK CVBS6 CVBS3 CVBS7 CVBS[0..7] DGND CVBS0 GND CVBS4 CVBS1 CVBS5 AGND CVBS2 GSA1GMCU5 GD0GMCU4 GRW\\GMCU3 GSA0GMCU6 GA0GMCU2 GCSGMCU1 GRESET\\GMCU0 GA0 20MCLK C29 22µF/6.3V C30 22µF/6.3V R16 R10 220 TMC22071AKHC(2072KHC)_2 VIN165 VIN261 VIN358 D09 NC12 (SA2)3 CS (SCL)5 EXT PXCK94 LDV 40 NC 85 NC19 NC20 CVBS0 21 CVBS1 22 CVBS5 28 CVBS7 30 GHSYNC 32 GVSYNC 33 VALID 34 NC13 NC76 VREF 70COMP 88 RT 68 RB 57 NC 83 CBYP 75 PFD IN 77 NC10 NC14 CVBS4 25 NC66 NC43 CLK IN91 CVBS2 23 PXCK 45 CLK OUT93 NC 99 A0 (SA0)1 (SA1)2 RESET7 NC11 NC15 INT 17 CVBS3 24 CVBS6 29 (BURL) 31 NC71 NC53 NC54 NC 56NC 59NC 62(FID2) 37(FID1) 36(FID0) 35 NC 78NC 79NC 80 DDS OUT 82 NC 84 PXCK SEL86 R/W (SDA)4 R15 10µH H11 TP1 VID_IN R11 3.3K R14 4.75K R13 4.75K R12 4.75K H3 1 C33 6.8pF C40 390pF C36 0.1uF C39 150pF C37 0.1µF C35 0.1uF C34 0.1uF C38 0.1µF C31 0.1uF C23 0.1µF C24 0.1µF C25 0.1µF C26 0.1µF C27 0.1µF C28 0.1µF C22 0.1µF C21 0.1µF C20 0.1µF JP3 A JP4 A JP5 A JP6 B JP7 B JP8 B H21 TP2 GH TP3 GV TP4 GPXCK BNC CR1 1.235V 20MHz OUT 5 PTH 1 PTH1 PTH1 PTH1 CVBS[0..7] SDA SCL GHSYNC GVSYNC GPXCK GMCU[0..6] VCC C32 0.1µF
PRODUCT SPECIFICATION TMB2193MS100 Preliminary Information Figure 5. TMB2193 0.9.0 65-B2193-06 B 41 2Thursday, September 04, 1997 Title Size Document Number Rev Date: Sheet of VCC
10 BIT FRAMESTORE
A[0..9] A_DEL[0..9] A_DEL9 A_DEL5 A_DEL4 A_DEL2 A_DEL8 A_DEL0 A_DEL6 A_DEL7 A_DEL1 A_DEL3 SIMM72 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 GND1 VDD 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 GND19 28 28 29 29 VDD 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 GND39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 VDD 48 49 49 50 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 58 58 VDD 59 60 60 61 61 62 62 63 63 64 64 65 65 66 66 67 67 68 68 69 69 70 70 71 71 GND72 IXHSYNC\\ IXVSYNC\\ A[0..9] SCL IXPXCK FRESET\\ VSOUT HSOUT MPXCK SDA A_DEL[0..9]
TMB2193MS100 PRODUCT SPECIFICATION Preliminary Information Figure 6. TMB2193 0.9.0 65-B2193-07 HEADERIN.SCH Raytheon Semiconductor - La Jolla San Diego, CA92121 (619) 457-1000 B 10 12Thursday, September 04, 1997 Date: Sheet of FS_CONN {Value} IXHSYNC IXVSYNC A[0..9] SCL IXPXCK FRESET VSOUT HSOUT MPXCK SDA A_DEL[0..9] +12V VCC -12V -5V -5V MPXCK VSOUT HSOUT IMASTER/SLAVE IXVSYNC\\ IXHSYNC\\ RESET\\ SCL SDA PGM_IN IXPXCK IXVSYNC\\ IXHSYNC\\ IXPXCK MPXCK RESET\\ SCL SDA HSOUT VSOUT PGM_IN A[0..9] SCL SDA IXHSYNC\\ IXVSYNC\\ IXPXCK HSOUT VSOUT MPXCK P2A EURO96F 1 12 23 34 45 56 67 78 89 910 1011 1112 1213 1314 1415 1516 1617 1718 1819 1920 2021 2122 2223 2324 2425 2526 2627 2728 2829 2930 3031 3132 32 P2B EURO96F 1 332 343 354 365 376 387 398 409 4110 4211 4312 4413 4514 4615 4716 4817 4918 5019 5120 5221 5322 5423 5524 5625 5726 5827 5928 6029 6130 6231 6332 64 P2C EURO96F 1 652 663 674 685 696 707 718 729 7310 7411 7512 7613 7714 7815 7916 8017 8118 8219 8320 8421 8522 8623 8724 8825 8926 9027 9128 9229 9330 9431 9532 96 R17 10K IXHSYNC\\ IXVSYNC\\ IXPXCK MPXCK SDA SCL HSOUT VSOUT PGM_IN A_DEL[0..9] B[0..9] C[0..9] RESET\\ FRESET\\ A[0..9]
PRODUCT SPECIFICATION TMB2193MS100 Preliminary Information Figure 7. Wednesday, January 22, 1997 TMB2193 0.9.0 65-B2193-08 HEADEROUT.SCH Raytheon Electronics - Semiconductor Division San Diego, CA92121 (619) 457-1000 B 61 2 Title Size Document Number Rev Date: Sheet of +12V VCC -5V -12V
96 WAY EDGE CONNECTIONS FROM THE TMC2193 BOARD
PXCK\\ PXCK HSOUT VSOUT SDA SCL RESET\\ PXCK4 PXCK4 VSOUT HSOUT SCL SDA DCVBS0 DCVBS1 DCVBS2 DCVBS3 DCVBS4 DCVBS5 DCVBS6 DCVBS7 DCVBS8 DCVBS9 DCVS[0..9] PGM_OUT PGM_OUT RESET\\ P3A EURO96M 1010 1111 1212 1313 1414 1515 1616 1717 1818 1919 2020 2121 2222 2323 2424 2525 2626 2727 2828 2929 3030 3131 3232 P3B EURO96M 133 234 335 436 537 638 739 840 941 1042 1143 1244 1345 1446 1547 1648 1749 1850 1951 2052 2153 2254 2355 2456 2557 2658 2759 2860 2961 3062 3163 3264 P3C EURO96M 165 266 367 468 569 670 771 872 973 1074 1175 1276 1377 1478 1579 1680 1781 1882 1983 2084 2185 2286 2387 2488 2589 2690 2791 2892 2993 3094 3195 3296 U2B 74F14 3 4 SELECT HSOUT VSOUT DCVBS[0..9] SDA SCL RESET\\ OPXCK PGM_OUT
TMB2193MS100 PRODUCT SPECIFICATION Preliminary Information Figure 8. TMB2193 0.9.0 65-B2193-09 LPF .SCH Raytheon Electronics - Semiconductor Division 5580 Morehouse Dr. San Diego, CA 92121 A 11 12Thursday, September 04, 1997 Title Size Document Number Rev Date: Sheet of VDD R18
75 Ohm
A_IN A_OUT
PRODUCT SPECIFICATION TMB2193MS100 Preliminary Information Figure 9. TMB2193 0.9.0 65-B2193-10 MCU.SCH Raytheon Electronics - Semiconductor Division 5580 Morehouse Dr. San Diego, CA 92121 B 81 2Friday, September 19, 1997 Title Size Document Number Rev Date: Sheet of VCC VCC VCC VCC VCCVCC VCC VCC VCC UART PLACE NEAR STANDOFF SA1 SA0 CAS ERS EMCU0 ERESET\\ EMCU1 EDCVBSEN\\ EMCU2 ESA1 EMCU3 ESA0 RESET\\ MRESET\\ MRESET\\ RXD TXD RXD TXD SCL SDA GD0 GRW\\ GAO GCS FMCU0 FMCU1 FMCU2 FMCU3 FMCU4 FMCU5 FMCU6 FMCU7 FMCU[0..7] SCL SDA SCL SDA PROG0 PROG1 PROG2 PROG3 PGM_OUT PGM_OUT PGM_IN ERESET\\ EDCVBSEN\\ GRESET\\ FRESET\\ PGM_IN CAS_PROGEN CAS_PROGEN FRESET\\ 135MCLK 135MCLK RESET\\ ESA0 ESA1 PROG1 PROG3 VSOUT VSOUT GSA1 GCSGMCU1 GSA1GMCU5 GRW\\GMCU3 GA0GMCU2 GD0GMCU4 GSA0 PROG0 GRESET\\GMCU0 GSA0GMCU6 PROG2 R21 10K R20 4K7 MRST JP10 UART
4 R23
P0.043 P0.142 P0.241 P0.340 P0.439 P0.538 P0.637 P0.736 P1.02 P1.13 P1.24 P1.35 P1.46 P1.57 P1.68 P1.79 P2.0 24 P2.1 25 P2.2 26 P2.3 27 P2.4 28 P2.5 29 P2.6 30 P2.7 31 P3.0 11 P3.1 13 P3.2 14 P3.3 15 P3.4 16 P3.5 17 P3.6 18 P3.7 19 XTAL220 XTAL121 RST10 EA/VPP 35 ALE/PROG 33 PSEN 32 NC1 NC12 NC23 NC34 C41 10.0µF/16V R22 4K7 R19 1OHM, 1/4W C JP11 CASCADE INIT JP9 RBUSEN C42 0.1µF U2C 74F14 5 6 U2D 74F14 9 8 SCL +5V SDA GND 15-83-0064 GREEN 2 1 135MCLK1 R49 10K SW DIP-8 R50 10K R51 10K R52 10K R53 10K R54 10K R55 10K R56 10K FB3 F BEAD 1H10 1 H111 H121 C43 0.1µF EMCU[0..3] GMCU[0..6] SDA PGM_OUT FMCU[0..7] PGM_IN FRESET\\ 135MCLK SCL RESET\\ VSOUT
TMB2193MS100 PRODUCT SPECIFICATION Preliminary Information Figure 10. Thursday, January 23, 1997 TMB2193 0.9.0 POWER.SCH Raytheon Electronics - Semiconductor Division San Diego, CA92121 (619) 457-1000 B 12 12 Title Size Document Number Rev Date: Sheet of VDD VDDA VCC +5V -5V DGND AGND VEE Ground Test Points P5V GND N5V C47 0.01µF 50V C46 0.1µF 50VC50 0.1µF 50V C51 0.01µF 50V TP11 GND TP12 GND TP13 GND TP14 GND TP15 GND FB1 F BEAD FB2 F BEAD + C44 22µF 35V + C45 0.47µF 35V + C48 22µF 35V + C49 0.47µF 35V TP9 +5V TP10 -5V CR3 1N4004 2 1 CR4 1N4004 2 1 CR2 RED LED CR5 ORANGE LED JP12 POWER3
PRODUCT SPECIFICATION TMB2193MS100 Preliminary Information Figure 11. TMB2193 0.9.0 65-B2193-12 MMC A 71 2Thursday, September 04, 1997 Title Size Document Number Rev Date: Sheet of VCC D IS150 OHM (1%) DO NOT STUFF A2XEN B2XEN C2XEN D2XEN NC1EN NC2EN ALL 1% R41 D R42 D R43 D R44 D JP14 JUMPER JP15 JUMPER JP16 JUMPER JP17 JUMPER JP18 JUMPER JP19 JUMPER JP20 JUMPER R45 R46 R47 R48 JP21 JUMPER JP22 JUMPER JP23 JUMPER ST-163E AIN1 BIN12 CIN13 DIN24 A2X4 C2X16 B2X9 D2X21 AOUT 5 BOUT 8 COUT 17 DOUT 20 NC17 NC218 R57 10K R58 10K R59 10K R60 10K R61 10K R62 10K AOUTAIN CIN COUT BOUT DOUT BIN DIN
TMB2193MS100 PRODUCT SPECIFICATION Preliminary Information Figure 12. TMB2193 0.9.0 65-B2193-13 TMC2193.SCH Raytheon Electronics - Semiconductor Division 5580 Morehouse Dr. San Diego, CA 92121 B 51 2Thursday, September 04, 1997 Title Size Document Number Rev Date: Sheet of LPF {Schematic} A_IN A_OUT MMC {Schematic} AOUT DOUT BOUT COUTCIN BIN DIN AIN VDD VCC VCC VDD VDD CONNECT Cx TO VDDA PIN AND CBYPy PIN DIRECTLY STUFF EITHER C54 OR D4 PD[0..23] OLENG[0..5] DCVBS3 PD2 PD14 PD18 DCVBS1 DCVBS4 DCVBS6 HSOUT ECVBS1 PD19 OLENG3 ECVBS9 PD22 PD23 DCVBS5 PD20 PD11 ECVBS[0..9] PD13 ECVBS0 PD4 PD12 DCVBS2 SCL PD7 PD8 PD3 PD5 PD16 OLENG2 VSOUT ECVBS4 ECVBS3 ECVBS2 DCVBS9 PD21 ECVBS8 SDA PD6 OLENG4 DCVBS0 DCVBS7 ECVBS6 ECVBS5 DCVBS[0..9] PD0 PD9 DCVBS8 ECVBS7 PD17 PD1 PD15 OLENG0 OLENG1 OLENG5 PD10 EMCU[0..3] ESA0EMCU3 EDCVBSEN\\EMCU1 ESA1EMCU2 EMCU0 ERESET\\ R32 8.25K Ohm R33 8.25K Ohm R35 8.25K Ohm R31 10K Ohm R28 10K Ohm R29 10K Ohm R40 4K7 TP27 VSOUT TP28 HSOUT TP26 PXCK TP29 HSIN TP30 VSIN JP13 C58 0.1uF C57 0.1uF C56 0.1uF TP16 RDA TP18 DA1 TP20 DA2 TP22 DA3 TP24 DA4 TP17 ORDA TP19 ODA1 TP21 ODA2 TP23 ODA3 TP25 ODA4 RDAC DAC1 DAC2 DAC3 DAC4 C55 0.1uF C67 0.1uF C63 0.1uF C62 0.1uF C66 0.1uF C65 0.1uF C61 0.1uF C64 0.1uF C68 0.1uF TMC2193KHC V_REF 98 VDDA 1 COMP2 2 C_BYB4 3 AGND 4 CH/R/P_R 5 C_BYB3 6 VDDA 7 R_REF3 8 AGND 9 Y/B/P_B 10 C_BYB2 11 VDDA 12 R_REF2 13 AGND14 COMP/G/Y 15 C_BYB1 16 VDDA 17 R_REF1 18 REFDAC 19 KEY20 OL421 OL322 OL223 OL124 OL025 DGND 26 PD2327 PD2228 PD2129 PD2030 PD1931 PD1832 PD1733 PD1634 PD1535 PD1436 PD1337 PD1238 VDD39 DGND 40 PD1141 PD1042 PD943 PD844 PD745 PD646 PD547 PD448 PD349 PD250 PD052 PD151 VDD54 VSIN55 HSIN56 SER58 CS/SCL59 R/W/SDA60 A1/SA161 A0/SA062 D7 63 CVBS093 CVBS192 CVBS291 CVBS390 CVBS489 CVBS588 CVBS687 CVBS786 CVBS885 CVBS984 PXCK95 PDC73 HSOUT74 VSOUT75 DCVEN57 RESET94 D0 70 DGND 71 VDD72 LINE4 76LINE3 77 D6 64D5 65D4 66D3 67D2 68D1 69 FLD0 83 FLD1 82 FLD2 81 LINE0 80 LINE1 79 LINE2 78 R_REF4 99 AGND 100 VDD96 DGND 53 DGND 97 R37 10K Pot 1 3 R36 10K Pot 1 3 R39 10K Pot 1 3 R34 8.25K Ohm R30 10K OhmR38 10K Pot 1 3 C54 0.1uF 1.235V R27 3.3K Ohm PD[0..23] ECVBS[0..9] EPXCK HSIN VSIN DCVBS[0..9] HSOUT VSOUT SDA SCL OLENGI[0..5] EMCU[0..3]
Table 5. TMB2193MS100 Parts List
Table 5. TMB2193MS100 Parts List (continued)
Table 6. INPUT 96 Way Connector (Female)
31 D1 or R/V [bit 0] 31 +5V 31 GND
30 D1 or R/V [bit 1] 30 +5V 30 PXCK
29 D1 or R/V [bit 2] 29 +5V 29 GND
28 D1 or R/V [bit 3] 28 GND 28 PCK
27 D1 or R/V [bit 4] 27 Analog Composite/luma 27 GND
26 D1 or R/V [bit 5] 26 GND 26 CREF
25 D1 or R/V [bit 6] 25 Analog chroma 25 GND
24 D1 or R/V [bit 7] 24 XEN 24 VSYNC
23 D1 or R/V [bit 8] 23 GND 23 HSYNC
22 D1 or R/V [bit 9] 22 XDIR 22 HREF
21 Comp, G/Y, or Luma [bit 0] 21 XHSYNC 21 VREF
20 Comp, G/Y, or Luma [bit 1] 20 XVSYNC 20 ODD IN
19 Comp, G/Y, or Luma [bit 2] 19 XPXCK 19 GND
18 Comp, G/Y, or Luma [bit 3] 18 XRS [bit 3] 18 NTSC/PAL
17 Comp, G/Y, or Luma [bit 4] 17 XRS [bit 2] 17 CLAMP pulse
16 Comp, G/Y, or Luma [bit 5] 16 XRS [bit 1] 16 RGB
15 Comp, G/Y, or Luma [bit 6] 15 XRS [bit 0] 15
14 Comp, G/Y, or Luma [bit 7] 14 GND 14
13 Comp, G/Y, or Luma [bit 8] 13 -5V 13
12 Comp, G/Y, or Luma [bit 9] 12 -5V 12 LOCK
11 Chroma or B/U [bit 0] 11 -5V 11 D1
10 Chroma or B/U [bit 1] 10 GND 10 RESET
9 Chroma or B/U [bit 2] 9 PGM_IN 9 SCL
8 Chroma or B/U [bit 3] 8 -12V 8 GND
7 Chroma or B/U [bit 4] 7 -12V 7 SDA
6 Chroma or B/U [bit 5] 6 IE (input enable) 6 OE (output enable)
5 Chroma or B/U [bit 6] 5 GND 5 BLANK
4 Chroma or B/U [bit 7] 4 4
3 Chroma or B/U [bit 8] 3 3
2 Chroma or B/U [bit 9] 2 +12V 2 +12V
1 GND 1 GND 1 GND
TMB2193MS100 PRODUCT SPECIFICATION Preliminary Information Input Edge Connector Design Notes 1. Boards with different revision letters may not be compatible. Damage may occur if they are con- nected together! 2. XPXCK is a two times pixel clock fed BACKW ARD. 3. XHSYNC and XVSYNC are timing reference signals fed BACKW ARD. 4. The MASTER/SLA VE signal states if a board is a MASTER or a SLA VE board. This signal is fed FORW ARD. A MASTER board produces the PXCK, HSYNC, and VSYNC signals, and a SLA VE board expects to receive XPXCK, XHSYNC, XVSYNC, etc. 5. XDIR is fed FORW ARD and controls in which direction the XRS[3:0] data flows. 6. PGM_IN is a negative going pulse, logically ANDed with the onboard program start pulse, for initiating the programming sequence for components on that board. Care must be taken to ensure that multiple devices do not try to drive the RBUS at any given time. Minimum width of PGM_IN is 1uS. 7. The RESET pin on the input edge connector should be connected directly to the RESET pin on the output con- nector. A link should be used to connect any pulse to the RESET line. 8. The MASTER/SLA VE, XDIR, PGM_IN and RESET pins on the input edge connector should be connected to +5V through a 10k pull up resistor. 9. The CLAMP signal is fed BACKW ARD from a MASTER to a SLA VE board. The CLAMP signal should not be fed FORW ARD. Y/Composite LPF and Clamp Circuit Chrominance BPF and Clamp Circuit TMC1185 TMC1185 SW1 SW1 +5V 0V -5V 2:1 MUX 65-B2193-14 10 bit ADCs Digital LPFs TMC2242 EPROM FPGA Signal Flow FORWARD TMC2072 TMC3003 Low Quality LPF Low Quality LPF Low Quality LPF High Quality LPF High Quality LPF High Quality LPF TMC22153 DC Supply Decoder Input Logic TMC2242 SW2 Signal Flow BACKWARD
Table 7. OUTPUT 96 Way Connector (Male)
2 D1 or R/V [bit 0] 2 +5V 2 GND
3 D1 or R/V [bit 1] 3 +5V 3 PXCK
4 D1 or R/V [bit 2] 4 +5V 4 GND
5 D1 or R/V [bit 3] 5 GND 5 PCK
6 D1 or R/V [bit 4] 6 Analog Composite/luma 6 GND
7 D1 or R/V [bit 5] 7 GND 7 CREF
8 D1 or R/V [bit 6] 8 Analog chroma 8 GND
9 D1 or R/V [bit 7] 9 XEN 9 VSYNC
10 D1 or R/V [bit 8] 10 GND 10 HSYNC
11 D1 or R/V [bit 9] 11 XDIR 11 HREF
12 Comp, G/Y, or Luma [bit 0] 12 XHSYNC 12 VREF
13 Comp, G/Y, or Luma [bit 1] 13 XVSYNC 13 ODD IN
14 Comp, G/Y, or Luma [bit 2] 14 XPXCK 14 GND
15 Comp, G/Y, or Luma [bit 3] 15 XRS [bit 3] 15 NTSC/PAL
16 Comp, G/Y, or Luma [bit 4] 16 XRS [bit 2] 16 CLAMP pulse
17 Comp, G/Y, or Luma [bit 5] 17 XRS [bit 1] 17 RGB
18 Comp, G/Y, or Luma [bit 6] 18 XRS [bit 0] 18
19 Comp, G/Y, or Luma [bit 7] 19 GND 19
20 Comp, G/Y, or Luma [bit 8] 20 -5V 20
21 Comp, G/Y, or Luma [bit 9] 21 -5V 21 LOCK
22 Chroma or B/U [bit 0] 22 -5V 22 D1
23 Chroma or B/U [bit 1] 23 GND 23 RESET
24 Chroma or B/U [bit 2] 24 PGM_OUT 24 SCL
25 Chroma or B/U [bit 3] 25 -12V 25 GND
26 Chroma or B/U [bit 4] 26 -12V 26 SDA
27 Chroma or B/U [bit 5] 27 IE (input enable) 27 OE (output enable)
28 Chroma or B/U [bit 6] 28 GND 28 BLANK
29 Chroma or B/U [bit 7] 29 29
30 Chroma or B/U [bit 8] 30 30
31 Chroma or B/U [bit 9] 31 +12V 31 +12V
32 GND 32 GND 32 GND
TMB2193MS100 PRODUCT SPECIFICATION Preliminary Information Output Edge Connector Design Notes 1. Boards with different revision letters may not be com- patible; damage may occur if they are connected together. 2. XPXCK is a two times pixel clock fed BACKW ARD. 3. XHSYNC and XVSYNC are timing reference signals fed BACKW ARD. 4. The MASTER/SLA VE signal states if a board is a MASTER or a SLA VE board. This signal is fed FOR- W ARD. A MASTER board produces the PXCK, HSYNC, and VSYNC signals, and a SLA VE board expects to receive XPXCK, XHSYNC, XVSYNC, etc. 5. XDIR is fed FORW ARD and controls in which direction the XRS[3:0] data flows. 6. PGM_OUT negative going signal pulse for initiating programming of down stream boards, generated once the devices on the board have been programmed. Care must be taken to ensure that multiple devices do not try to drive the RBUS at any given time. The Minimum width of PGM_OUT is 1uS. 7. The RESET pin on the output edge connector should be connected directly to the RESET pin on the input con- nector. A link should be used to connect any pulse to the RESET line. 8. The MASTER/SLA VE, XDIR, PGM_OUT and RESET pins on the output edge connector should be connected to +5V through a 10k pull up resistor. 9. The CLAMP signal is fed BACKW ARD from a MAS- TER to a SLA VE board. The CLAMP signal should not be fed FORW ARD.
Related Products
- TMB22153MS101 Decoder demonstration board
- TMB1185MS102 ADC demonstration board
- TMB0000UG100 RBUS Interface
- TMB0001MS100 Parallel D1 interface board
- Raydemo software Y/Composite LPF and Clamp Circuit Chrominance BPF and Clamp Circuit TMC1185 TMC1185 SW1 SW1 +5V 0V -5V 2:1 MUX 65-B2193-14 10 bit ADCs Digital LPFs TMC2242 EPROM FPGA Signal Flow FORWARD TMC2072 TMC3003 Low Quality LPF Low Quality LPF Low Quality LPF High Quality LPF High Quality LPF High Quality LPF TMC22153 DC Supply Decoder Input Logic TMC2242 SW2 Signal Flow BACKWARD
PRODUCT SPECIFICATION TMB2193MS100 Preliminary Information Notes:
TMB2193MS100 PRODUCT SPECIFICATION Preliminary Information 6/3/98 0.0m 002 Stock# DS7TMB2193 Ó 1998 Fairchild Semiconductor Corporation LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
Ordering Information
A schematic database is available in OrCAD™ format. Contact the factory. The TMB2193MS100 Demonstration Board, design documentation, and software are provided as a design example for the customers of Fairchild. Fairchild makes no warranties, express, statutory, or implied regarding merchantability or fitness for a particular purpose. FCC Compliance This device has not been approved by the Federal Communications Commission (FCC). This board is intended for the evalu- ation of Fairchild products only. This device is not and may not be offered for sale or lease or sold or leased until the approval of the FCC has been obtained. Product Number Temperature Range Speed Grade Screening Package Package Marking TMB2193MS100 25 °C 27 MHz Commercial 4" by 5" Printed Circuit Board TMB2193MS100