TMS370CX9X_05 TI1 | Alldatasheet
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS370Cx9x 8-BIT MICROCONTROLLER SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume Production – One-Time-Programmable (OTP) EPROM Devices for Low-Volume Production – Reprogrammable EPROM Devices for Prototyping Purposes /C0068Internal System Memory Configurations – On-Chip Program Memory Versions – ROM: 4K Bytes – EPROM: 8K Bytes – Data EEPROM: 256 Bytes – Static RAM: 128 Bytes Usable as Registers /C0068Flexible Operating Features – Low-Power Modes: STANDBY and HALT – Commercial, Industrial, and Automotive Temperature Ranges – Clock Options: – Divide-by-4 (0.5 MHz – 5 MHz SYSCLK) – Divide-by-1 (2 MHz – 5 MHz SYSCLK) PLL – Supply Voltage (V CC ): 5 V ± 10% /C006815-Channel 8-Bit A/D Converter 3 /C006816-Bit General-Purpose Timer – Software Configurable as a 16-Bit Event Counter, or a 16-Bit Pulse Accumulator, or a 16-Bit Input Capture Function, or Two Compare Registers, or a Self-Contained Pulse-Width-Modulation (PWM) Function – 8-Bit Prescaler, Providing a 24-Bit Real-Time Timer /C0068On-Chip 24-Bit Watchdog Timer – EPROM/OTP Devices: Standard Watchdog – Mask ROM Devices: Hard Watchdog, Simple Counter, or Standard Watchdog /C0068TMS370 Series Compatibility – Instructions Upwardly Compatible With All TMS370 Devices – Register-to-Register Architecture – 128 or 256 General-Purpose Registers – 14 Powerful Addressing Modes /C0068Flexible Interrupt Handling /C0068CMOS/Package /TTL-Compatible I/O Pins – 40- and 44-Pin Plastic and Ceramic Shrink Dual-In-Line and Leaded Chip Carrier Packages /16 Bidirectional;
9 Input Pins
– All Peripheral Function Pins Are Software Configurable for Digital I/O /C0068Workstation/PC-Based Software Development System – C Compiler and C Source Debugger – Real-Time In-Circuit Emulation – Extensive Breakpoint/Trace Capability – Software Performance Analysis – Multi-Window User Interface – Microcontroller Programmer AN11 AN12 AN13 AN14 AN5 AN6 AN7 AN8 AN9 NC AN10 RESET INT1 VCC VCC3 VSS3 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 T1EVT T1PWM MC T1IC/CR XTAL2/CLKIN XTAL1 V SS AN14 AN13 AN12 AN11 AN10 JC AND NJ PACKAGES (TOP VIEW) MC T1IC/CR XTAL2/CLKIN NC XTAL1 V SS 18 19 RESET INT1 VCC VCC3 VSS3 AN0 AN1 AN2 AN3 AN4 NC 20 21 22 23 FN AND FZ PACKAGES (TOP VIEW) T1EVT T1PWM 54 32164 4 NC 42 4043 24 25 26 27 28 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1997, Texas Instruments Incorporated
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ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ PIN ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NAME ÁÁÁ ÁÁÁ SDIP (40) ÁÁÁ ÁÁÁ LCC (44) ÁÁÁ ÁÁÁ I/O† ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DESCRIPTION ‡ ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Port A is a general-purpose bidirectional I/O port. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ D3/SYSCLK ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Port D is a general-purpose bidirectional I/O port. D3 is also configurable as SYSCLK. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ AN0/E0 AN1/E1 AN2/E2 AN3/E3 AN4/E4 AN5/E5 AN6/E6 AN7/E7 ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ADC3 analog input (AN0–AN7) or positive reference pins (AN6–AN7) Port E can be individually programmed as general-purpose input pins if not used as ADC3 analog in- put. Only AN6 and AN7 can be software-configured as positive reference input. ÁÁÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁÁ AN8 AN9 AN10 AN11 AN12 AN13 AN14 ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ ÁÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ADC3 analog input pins ÁÁÁÁÁ ÁÁÁÁÁ INT1 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ External (nonmaskable or maskable) interrupt/general-purpose input pin ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ T1IC/CR T1PWM T1EVT ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Timer1 input capture/counter reset input pin/general-purpose bidirectional pin Timer1 PWM output pin/general-purpose bidirectional pin Timer1 external event input pin/general-purpose bidirectional pin ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ RESET ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ I/O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ System-reset bidirectional pin. RESET, as an input, initializes the microcontroller; as open-drain output, RESET indicates an internal failure was detected by the watchdog or oscillator fault circuit. ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ MC ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode control (MC) pin. MC enables EEPROM write-protection override (WPO) mode, also EPROM VPP. ÁÁÁÁÁ ÁÁÁÁÁ XTAL2/CLKIN XTAL1 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ I O ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Internal oscillator crystal input/external clock source input Internal oscillator output for crystal ÁÁÁÁÁ ÁÁÁÁÁ VCC ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Positive supply voltage for digital logic ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Ground reference for digital logic ÁÁÁÁÁ ÁÁÁÁÁ VCC3 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Positive supply voltage for ADC3 ÁÁÁÁÁ ÁÁÁÁÁ VSS3 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Ground reference for ADC3 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 1, 17, 23, 36 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ These pins have no connection to the internal die. † I = input, O = output ‡ Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK.
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram Program Memory ROM: 4K Bytes EPROM: 8K Bytes VSS VCC RESETMCXTAL2/ CLKIN XTAL1INT1 E0–E7 or AN0–AN7 Data EEPROM
256 Bytes
128 BytesCPU
A-to-D Converter 3System Control Clock Options: Divide-by-4 or Divide-by-1(PLL) T1PWM T1EVT T1IC/CR VSS3 VCC3 Port A Interrupts Port D AN8–AN14
description
The TMS370C090A, TMS370C792, and SE370C792 devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx9x refers to these devices. The TMS370 family provides cost-effective real-time system control through integration of advanced peripheral function modules and various on-chip memory configurations. The TMS370Cx9x family is implemented using high-performance silicon-gate CMOS EPROM and EEPROM technologies. The low-operating power, wide-operating temperature range, and noise immunity of CMOS technology coupled with the high performance and extensive on-chip peripheral functions make the TMS370Cx9x devices attractive in system designs for automotive electronics, industrial motor control, computer peripheral control, telecommunications, and consumer application. All TMS370Cx9x devices contain the following on-chip peripheral modules: /C0068Fifteen-channel, 8-bit analog-to-digital converter 3 (ADC3) /C0068One 24-bit general-purpose watchdog timer /C0068One 16-bit general-purpose timer with an 8-bit prescaler
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Table 1 provides a memory configuration overview of the TMS370Cx9x devices. Table 1. Memory Configurations
44 PIN PLCC/CLCC, OR
40 PIN PSDIP/CSDIP
† System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized. package and did not need to be requalified. configuration of the device. ROM and EPROM devices have a different configuration as indicated in Table 2. ROM devices with the suffix letter A are configured through a programmable contact during manufacture. Table 2. Suffix Letter Configuration § Refer to the “device numbering conventions” section for device nomenclature and the “device part numbers” section for ordering. mask charge or cycle time for the low-cost mask-ROM device is not practical. breadboards and prototype systems while iterating initial designs.
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 description (continued) The TMS370Cx9x family provides the system designer with very economical, efficient solutions to real-time control applications. The TMS370 family compact development tool (CDT ) solves the challenge of efficiently developing the software and hardware required to design the TMS370Cx9x into an ever-increasing number of complex applications. The application source code can be written in assembly and C-language, and the output code can be generated by the linker. The TMS370 family CDT development tool can communicate through a standard RS-232-C interface with a personal computer. This allows the use of personal-computer editors and software utilities already familiar to the designer. The TMS370 family CDT emphasizes ease-of-use through extensive use of menus and screen windowing so that a system designer with minimal training can begin developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as reduced time-to-market cycle. The TMS370Cx9x family together with the TMS370 family CDT370 PACT, software tools, the SE370C792 reprogrammable device, comprehensive product documentation, and customer support provide a complete solution to the needs of the system designer. CPU The CPU used on TMS370Cx9x devices is the high-performance 8-bit TMS370 CPU module. The ’x9x implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x9x instruction set is summarized in Table 21. Figure 1 illustrates the CPU registers and memory blocks. CDT is a trademark of Texas Instruments Incorporated.
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015 Program Counter
7 Legend:
† Reserved means that the address space is reserved for future expansion. ‡ Not available means that the address space is not accessible. Figure 1. Programmer’s Model
128 bytes of the on-chip RAM memory. the conditional jump instructions) use these status bits to determine program flow. /C0068The two interrupt-enable bits control the two interrupt levels. The ST register and status bit notation are shown in Table 3. Table 3. Status Register
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registers contain the most-significant byte (MSbyte) and least-significant byte (LSbyte) of a 16-bit address. 6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector). Figure 2. Program Counter After Reset EEPROM, EPROM, input/output pins, peripheral functions, and system-interrupt vectors. through 7, addresses 1010h through 107Fh.
† Reserved = the address space is reserved for future expansion. ‡ Not available = address space is unavailable in the mode illustrated. Figure 3. TMS370Cx9x Memory Map beginning at location 0000h (R0) and continuing through location 007Fh (R127) which is shown in Figure 3. stack pointer is contained in register B. Registers A and B are the only registers cleared on reset. designator is P16. Table 4 shows the TMS370Cx9x peripheral files address map.
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
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peripheral file (PF) (continued) Table 4. TMS370Cx9x Peripheral File Address Map ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1000h–100Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P000–P00F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ 1010h–101Fh ÁÁÁÁÁÁÁ P010–P01F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ System and EEPROM/EPROM control registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1020h–103Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P020–P03F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Digital I/O port control registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1030h–103Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P030–P03F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1040h–104Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P040–P04F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Timer 1 registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1050h–106Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P050–P06F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1070h–107Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P070–P07F ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Analog-to-digital converter 3 registers ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1080h–10FFh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ P080–P0FF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Reserved data EEPROM The TMS370Cx9x devices contain 256 bytes of data EEPROM and have a memory map beginning at location 1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm examples are available in the TMS370 Family User’s Guide (literature number SPNU127), or the TMS370 Family Data Manual (literature number SPNS014B). The data EEPROM features include the following: /C0068Programming: – Bit, byte, and block write/erase modes – Internal charge pump circuitry: No external EEPROM programming voltage supply is needed. – Control register: Data EEPROM programming is controlled by the data EEPROM control register (DEECTL) located in the PF frame beginning at location P01A. – In-circuit programming capability: There is no need to remove the device to program. /C0068Write-protection: Writes to the data EEPROM are disabled during the following conditions: – Reset: All programming of the data EEPROM module is halted. – Write protection active: there is one write-protect bit per 32-byte EEPROM block. – Low-power mode operation /C0068Write protection can be overridden by applying 12 V to the MC pin. Table 5 shows the memory map of the control registers. Table 5. Data EEPROM and Program EPROM Control Registers Memory Map
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 program EPROM The TMS370C792 contains 8K bytes of program EPROM memory mapped beginning at location 6000h and continuing through location 7FFFh as shown in Figure 3. Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments (TI ) and addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh. Reading the program EPROM modules is identical to reading other internal memory. During programming, the EPROM is controlled by the program EPROM control register (EPCTL). The program EPROM modules’ features include: /C0068Programming – In-circuit programming capability if VPP is applied to the MC pin – Control register: Program EPROM programming is controlled by the program EPROM control registers EPCTL located at the addresses in PF frame 1 as shown in Table 5. /C0068Write protection: Writes to the program EPROM are disabled under the following conditions: – Reset: All programming to the EPROM module is halted. – Low-power modes – 13 V not applied to MC program ROM The program ROM consists of 4K bytes of mask-programmable ROM. The program ROM is used for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device fabrication. Memory addresses 7FE0h through 7FEBh are reserved for TI and addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh. system reset The system-reset operation ensures an orderly start-up sequence for the TMS370Cx9x CPU-based device. There are up to three different actions that can cause a system reset to the device. Two of these actions are internally generated, while one (RESET ) is controlled externally. These actions are as follows: /C0068External RESET pin. A low level signal can trigger an external reset. To assure a reset, the external signal should be held low for one SYSCLK cycle (it is possible, however, that a signal of less than one SYSCLK could cause a reset). See the TMS370 User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (SPNS014B) for more information. /C0068Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key register or if the re-initialization does not occur before the watchdog timer timeout . See the TMS370 User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (SPNS014B) for more information. /C0068Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range. See the TMS370 User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (SPNS014B) for more information. Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK cycles. This allows the ’x9x device to reset external system components. Additionally, if a cold start condition CC is off for several hundred milliseconds), oscillator failure occurs, or RESET pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active. After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag (COLD START, SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source of the reset. A reset does not clear these flags. Table 6 depicts the reset sources. TI is a trademark of Texas Instruments Incorporated.
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Table 6. Reset Sources
- The CPU registers are initialized: ST = 00h, SP = 01h (reset state).
- Registers A and B are initialized to 00h (no other RAM is changed).
- The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.
- The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.
- Program execution begins with an opcode fetch from the address pointed to by the PC.
register bits are initialized to their reset state. low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority.
Figure 4. Interrupt Control associated system interrupt. software-configured as a general-purpose input pin if the interrupt function is not required.
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Table 7. Hardware System Interrupts † Relative priority within an interrupt level. ‡ Releases microcontroller from STANDBY and HALT low-power modes. § Releases microcontroller from STANDBY low-power mode. nonprivileged mode and must be configured by software prior to exiting the privileged mode. Table 8. Privilege Bits
pin (normally not available in the end application except in a service or diagnostic environment). time when the mask is manufactured. is entered by executing the idle instruction when the PWRDWN/IDLE bit in register SCCR2 has been set to one. The HALT/STANDBY bit in SCCR2 controls which low-power mode is entered. , external interrupt on INT1, or timer 1 interrupt) is detected. In the HALT mode (HALT/STANDBY = 1), the TMS370Cx9x is placed in its lowest power-consumption mode. low-power mode selection bits are summarized in Table 9. Table 9. Low-Power/Idle Control Bits through a programmable contact, the device always enters the IDLE mode. means that the NMI is always generated, regardless of the interrupt enable flags. STANDBY and HALT modes, the clocking of the watchdog timer is inhibited.
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The ‘370Cx9x family provides two clock options which are referred to as divide-by-1 (PLL) and divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of a TMS370 microcontroller. The ‘370C090A ROM-masked devices offer both options to meet system engineering requirements. Only one of the two clock options is allowed on the ROM device while the EPROM device ’792 has only the divide-by-4 clock. The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with no added cost. The divide-by-1 provides a 1-to-1 match of the external resonator frequency (CLKIN) to the internal system clock (SYSCLK) frequency. The divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four. The clock module then divides the resulting signal by four to provide the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency. The frequencies are formulated as follows: Divide-by-4 option : SYSCLK/C0043external resonator frequency /C0043CLKIN Divide-by-1 option : SYSCLK/C0043external resonator frequency/C00324 4 /C0043CLKIN The main advantage of choosing a divide-by-1 oscillator is that EMI is reduced. The harmonics of low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators. The divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a steeper decay of emissions produced by the oscillator.
programming. The privileged bits are shown in a bold typeface and shaded. Table 10. Peripheral File Frame 1: System Configuration Registers
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specific addresses, registers, and control bits within this peripheral file frame. Table 11. Peripheral File Frame 2: Digital Port Control Registers † To configure pin D3 as SYSCLK, set port D control register 2 = 08h. Table 12. Port Configuration Register Setup block diagram is shown in Figure 5.
Figure 5. Timer 1 Block Diagram – Dual-compare mode: Provides PWM signal. – Capture/compare mode: Provides input capture pin. capture or compare registers. if watchdog feature is not needed. the input capture pins (T1IC/CR).
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/C0068Sixteen T1 module control registers: Located in the PF frame beginning at address P040. Table 13 lists the T1 module control registers. Table 13. Timer 1 Module Register Memory Map
bit 0, in the T1CTL2 register. Figure 6. Capture/Compare Mode
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bit 0, in the T1CTL2 register. Figure 7. Dual-Compare Mode
software programmed as an event counter, pulse accumulator, or interval timer if the WD function is not used. WD can be configured as one of the three mask options: standard WD, hard WD, or simple counter. Figure 8. Standard Watchdog
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Figure 9. Hard Watchdog
– Simple counter can be configured as an event counter, pulse accumulator, or an interval timer. Figure 10. Simple Counter
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The ADC3 module control registers are illustrated in Table 14. Table 14. ADC3 Module Control Register Memory Map
The A/D module block diagram is illustrated in Figure 11. Figure 11. ADC3 Block Diagram
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Table 15. ADC3 Peripheral Control Register (ADCTL) either SAMPLE START or CONVERT START is 1 invalidates the conversion in progress. not change during the entire conversion. this bit and aborts any sampling in progress. mode clears this bit and aborts any conversion in progress.
Table 16. ADC3 Peripheral Control Register (ADSTAT) This bit controls the ADC3 module’s ability to generate an interrupt. for a new conversion to start. Writing to this bit has no effect on its state. Table 17. ADC3 Table 18. AN0–AN7 Data Input Register (ADIN)
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is a 1. Pins configured as ADC3 channels are read as 0’s. Writing to this address has no effect. Table 19. AN0–AN7 Input-Enable Register (ADENA) corresponding bit in the ADIN register reads a 0. corresponding bit in the ADIN register. Table 20. Analog Interrupt Priority/Conversion Rate Register (ADPRI) selections allow maintaining minimum conversion time at lower system-clock rates. 8-bit precision of the ADC3 is not assured.
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997 31POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 analog-to-digital converter 3 module (continued) BIT 5 AD ESPEN (Emulator Suspend Enable) Normally this bit has no effect. However, when using the XDS emulator to debug a program, this bit determines what happens to the ADC3 when the program is suspended by an action such as a hardware or software breakpoint. 0 = When the emulator is suspended, the ADC3 continues to run until the conversion is complete. 1 = When the emulator is suspended, the ADC3 is frozen so that its state can be examined at the point that the emulator was suspended. The conversion data is indeterminate upon restart. BIT 6 AD PRIORITY (ADC3 interrupt priority select) This bit selects the priority level of the ADC3 interrupt. 0 = ADC3 Interrupt is a higher priority (level 1) request. 1 = ADC3 Interrupt is a lower priority (level 2) request. BIT 7 AD STEST (This bit must be cleared to ensure proper operation) instruction set overview Table 21 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the ‘370Cx9x instruction set. The numbers at the top of this table represent the most significant nibble (MSN) of the opcode while the numbers at the left side of the table represent the least significant nibble (LSN). The instruction of these two opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that opcode. For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes in eight SYSCLK cycles.
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Table 21. TMS370 Family Opcode/Instruction Map† instructions have a relative address as the last operand.
Table 21. TMS370 Family Opcode/Instruction Map† (Continued) instructions have a relative address as the last operand.
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development system support The TMS370 family development support tools include an assembler, a C compiler, a linker, CDT, and an EEPROM/UVEPROM programmer. /C0068Assembler/linker (Part No. TMDS3740850–02 for PC) – Includes extensive macro capability – Provides high-speed operation – Provides format conversion utilities for popular formats /C0068ANSI C compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700 , Sun-3 , or Sun-4 ) – Generates assembly code for the TMS370 that can be easily inspected – Improves code execution speed and reduces code size with optional optimizer pass – Enables direct referencing of the TMS370’s port registers by using a naming convention – Provides flexibility in specifying the storage for data objects – Interfaces C functions and assembly functions easily – Includes assembler and linker /C0068CDT370 (compact development tool) PACT real-time in-circuit emulation – Base (Part Number EDSCDT37P – for PC, requires cable) – Cable for 40-pin SDIP (Part No. EDSTRG40SDIL05) – Cable for 44-pin PLCC (Part No. EDSTRG44PLCC05) – Includes EEPROM and EPROM programming support – Allows inspection and modification of memory locations – Uploads/downloads program and data memory – Executes programs and software routines – Includes 1024-sample trace buffer – Includes single-step executable instructions – Uses software breakpoints to halt program execution at selected address /C0068Microcontroller programmer – Base (Part No. TMDS3760500A — for PC, requires programmer head) – Single unit head for 44-pin PLCC and 40-pin SDIP (Part No. TMDS3780513A) – Includes PC-based, window/function-key oriented user interface for ease of use and rapid learning environment HP700 is a trademark of Hewlett-Packard Company. Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc.
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Table 22. Device Part Numbers reliability has not been characterized. package and did not need to be requalified.
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Table 23. Peripheral File Frame Compilation Table 23 is a collection of all the peripheral file frames using the ’Cx9x (provided for a quick reference). † To configure pin D3 as SYSCLK, set port D control register 2 = 08h.
Table 23. Peripheral File Frame Compilation (Continued)
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ Electrical characteristics are specified with all output buffers loaded with specified IO current. Exceeding the specified IO current in any buffer can affect the levels on other buffers. NOTE 1: Unless otherwise noted, all voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage (see Note 1) 4.5 5 5.5 VVCC RAM data-retention supply voltage (see Note 2) 3 5.5 V VCC3 Analog supply voltage (see Note 1) 3 5.5 V VSS3 Analog supply ground – 0.3 0 0.3 V VIL Low level input voltage All pins except MC VSS 0.8 V VIL Low-level input voltage MC, normal operation VSS 0.3 V V Hi h l l i t lt All pins except MC, XTAL2/CLKIN, and RESET 2 VCC VVIH High-level input voltage XTAL2/CLKIN 0.8 VCC VCC V RESET 0.7 VCC VCC EEPROM write protect override (WPO) 11.7 12 13 VMC MC (mode control) voltage EPROM programming voltage (VPP ) 13 13.2 13.5 V Microcomputer VSS 0.3 L version 0 70 TA Operating free-air temperature A version – 40 85 °C T version – 40 105 NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS . 2. RESET must be externally activated when VCC or SYSCLK is out of the recommended operating range.
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997 41POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOL Low-level output voltage IOL = 1.4 mA 0.4 V VOH High level output voltage IOH = –50 mA 0.9 VCC VVOH High-level output voltage IOH = –2 mA 2.4 V 0 V < VI ≤ 0.3 V 10 mA II Input current MC 0.3 V < VI ≤ 13 V 650 mA II Input current
12 V ≤ VI ≤ 13 V See Note 3 50 mA
I/O pins 0 V ≤ VI ≤ VCC ± 10 mA IOL Low-level output current VOL = 0.4 V 1.4 mA IOH High level output current VOH = 0.9 VCC – 50 mA IOH High-level output current VOH = 2.4 V – 2 mA SYSCLK = 5 MHz See Notes 4 and 5 30 45SYSCLK = 5 MH z See Notes 4 and 5 30 45 Supply current (operating mode) SYSCLK = 3 MHz See Notes 4 and 5 20 30 mAy(g ) OSC POWER bit = 0 (see Note 6) SYSCLK = 3 MH z See Notes 4 and 5 20 30 mAOSC POWER bit = 0 (see Note 6) SYSCLK = 0 5 MHz See Notes 4 and 5 7 11SYSCLK = 0.5 MH z See Notes 4 and 5 7 11 S l t (STANDBY d ) SYSCLK = 5 MHz See Notes 4 and 5 10 17 ICC Supply current (STANDBY mode) OSC POWER bi t = 0 (see Note 7) SYSCLK = 3 MHz See Notes 4 and 5 8 11 mAOSC POWER bit = 0 (see Note 7) SYSCLK = 0.5 MHz See Notes 4 and 5 2 3.5 Supply current (STANDBY mode) SYSCLK = 3 MHz See Notes 4 and 5 6 8.6 mAy( ) OSC POWER bit = 1 (see Note 8) SYSCLK = 0.5 MHz See Notes 4 and 5 2 3 mA Supply current (HALT mode) XTAL2/CLKIN < 0.2 V See Note 4 2 30 mA NOTES: 3. Input current IPP is a maximum of 50 mA only when programming EPROM. 5. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 6. Maximum operating current for TMS370Cx9x = 7.6 (SYSCLK) + 7 mA. 7. Maximum standby current for TMS370Cx9x = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0).
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NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period. Figure 14. Recommended Crystal/Clock Connections driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated. Figure 15. Typical Output Load Circuit (see Note A) Figure 16. Typlcal Buffer Circuitry
All timings are measured between high and low measurement points as indicated in Figure 17 and Figure 18.
0.8 V (Low)
2 V (High)
0.8 VCC V (High)
Figure 17. XTAL2/CLKIN Measurement Points Figure 18. General Measurement Points
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† For VIL and VIH, refer to recommended operating conditions. low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. Figure 19. External Clock Timing for Divide-by-4 † For VIL and VIH, refer to recommended operating conditions. low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. Figure 20. External Clock Timing for Divide-by-1
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recommended EPROM operating conditions for programming MIN NOM MAX UNIT VCC Supply voltage 4.75 5.5 6 V VPP Supply voltage at MC pin 13 13.2 13.5 V IPP Supply current at MC pin during programming (VPP = 13 V) 30 50 mA SYSCLK System clock Divide-by-4 0.5 5 MHzSYSCLK System clock Divide-by-1 2 5 MH z recommended EPROM timing requirements for programming MIN NOM MAX UNIT tw(EPGM) Pulse duration, programming signal (see Note 10) 0.40 0.50 3 ms NOTE 10: Programming pulse is active when both EXE (EPCTL.0) and VPPS (EPCTL.6) are set.
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997 47POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 analog-to-digital converter 3 The ADC3 has a separate power bus for its analog circuitry. These pins are referred to as VCC3 and VSS3 . The purpose is to enhance ADC3 performance by preventing digital switching noise of the logic circuitry that can be present on V SS and VCC from coupling into the ADC3 analog stage. All ADC3 specifications are given with respect to VSS3 unless otherwise noted. recommended operating conditions MIN NOM MAX UNIT VCC3 Analog supply voltage 4.5 5 5.5 VVCC3 Analog supply voltage VCC –0.3 VCC +0.3 V VSS3 Analog ground VSS –0.3 VSS +0.3 V Vref Non-VCC3 reference† 2.5 VCC3 VCC3 + 0.1 V Analog input for conversion VSS3 Vref V † Vref must be stable, within ± 1/2 LSB of the required resolution, during the entire conversion time. operating characteristics over recommended ranges operating conditions PARAMETER MIN MAX UNIT Differential/integral linearity error‡§ VCC3 = 5.5 V V rerf = 5.1 V ± 0.9 LSB ICC3 Analog supply current Converting 2 mA ICC3 Analog supply current Nonconverting 5 mA II Input current, AN0–AN14 0 V ≤ VI ≤ 5.5 V 2 mA Iref Input charge current 1 mA Z f Source impedance of Vf SYSCLK ≤ 3 MHz 24 kW Zref Source impedance of Vref 3 MHz < SYSCLK ≤ 5 MHz 10 kW ‡ Absolute resolution = 20 mV. At Vref = 5 V, this is one LSB. As Vref decreases, LSB size decreases; therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase. § Excluding quantization error of 1/2 LSB
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signaling that a conversion has started and that the analog signal can be removed. † N = 16, 8, 4, or 2 upon selected conversion rate. ‡ The value given is valid for a signal with a source impedance > 1 kW . If the source impedance is < 1 kW , use a minimum sampling time of 1ms. Figure 23. Analog Timing
mechanical drawing by drawing number and name. Table 24. TMS370Cx9x Family Package Type and Mechanical Cross-Reference † NJ formerly known as N2; the mechanical drawing of the NJ is identical to the N2 package and did not need to be requalified.
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FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 4040005/B 03/95
20 PIN SHOWN
0.026 (0,66) 0.032 (0,81) D2/E2 0.020 (0,51) MIN 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D2/E2 0.013 (0,33) 0.021 (0,53) Seating Plane MAX D2/E2 0.219 (5,56) 0.169 (4,29) 0.319 (8,10) 0.469 (11,91) 0.569 (14,45) 0.369 (9,37) MAX 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.008 (0,20) NOM 1.158 (29,41) 0.958 (24,33) 0.756 (19,20) 0.191 (4,85) 0.141 (3,58) MIN 0.441 (11,20) 0.541 (13,74) 0.291 (7,39) 0.341 (8,66) D E1E MINMAXMIN PINS 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 84 1.185 (30,10) 0.985 (25,02) 0.785 (19,94) D/E 0.395 (10,03) 0.495 (12,57) 1.195 (30,35) 0.995 (25,27) 0.695 (17,65) 0.795 (20,19) NO. OF D1/E1 0.350 (8,89) 0.450 (11,43) 1.150 (29,21) 0.950 (24,13) 0.650 (16,51) 0.750 (19,05) 0.004 (0,10) M0.007 (0,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997 51POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA FZ (S-CQCC-J) J-LEADED CERAMIC CHIP CARRIER 4040219/B 03/95 0.180 (4,57) 0.140 (3,55) C 0.020 (0,51) 0.032 (0,81)A B A B 0.025 (0,64) R TYP 0.026 (0,66) 0.120 (3,05) 0.155 (3,94) 0.014 (0,36) 0.120 (3,05) 0.040 (1,02) MIN 0.090 (2,29) A MIN MAX 0.485 (12,32) (12,57) 0.495 0.455 (11,56)(10,92) 0.430 MAXMIN BC MIN MAX 0.410 (10,41) (10,92) 0.430 PINS NO. OFJEDEC MO-087AC MO-087AB MO-087AA OUTLINE
28 LEAD SHOWN
(at Seating Plane) 142 6 1812 5 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit.
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
JC (R-CDIP-T40) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE 4040223-2/B 04/95 0.016 (0,41) Seating Plane 0.610 (15,49) 0.032 (0,81) TYP 0.009 (0,23) 0.590 (14,99) 1.335 (33,91) 1.325 (33,66) 1.386 (35,20) 1.414 (35,92) 0.600 (15,24) 0.580 (14,73) 0.040 (1,02) 0.060 (1,52) 40 21 0.093 (2,38) 0.077 (1,96) 0.070 (1,78) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated.
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997 53POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA NJ (R-PDIP-T**) PLASTIC SHRINK DUAL-IN-LINE PACKAGE 4040034/B 04/95
40 PIN SHOWN
2.031 (51,60) 1.425 (36,20) DIM A MAX PINS ** 0.200 (5,08) MAX 0.560 (14,22) MAX 0.125 (3,18) MIN Seating Plane 0.010 (0,25) NOM 0.600 (15,24) A 0.048 (1,216) 0.032 (0,816) 0.014 (0,36) 0.022 (0,56) 0.020 (0,51) MIN 0°–15° M0.010 (0,25) 0.070 (1,78) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SE370C792FZT OBSOLETE JLCC FZ 44 TBD Call TI Call TI SE370C792JCT OBSOLETE CDIP SB JC 40 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 Addendum-Page 1
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