TM8SK64JPN

TM8SK64JPN TI1 | Alldatasheet

Document overview

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Technical content

/C0084/C0077/C0056/C0083/C0075/C0054/C0052/C0074/C0080/C0078 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS717 − JULY 1998 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Organization: − TM8SK64JPN . . . 8 388 608 x 64 Bits /C0068Single 3.3-V Power Supply (±10% Tolerance) /C0068Designed for 66-MHz 4-Clock Systems /C0068JEDEC 144-Pin Small Outline Dual-In-Line Memory Module (SODIMM) Without Buffer for Use With Socket /C0068Uses Eight 64M-Bit Synchronous Dynamic RAMs (SDRAMs) (8M × 8-Bit) in Plastic Thin Small-Outline Packages (TSOPs) /C0068Byte-Read/Write Capability /C0068Performance Ranges: /C0068High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface /C0068Read Latencies 2 and 3 Supported /C0068Support Burst-Interleave and Burst-Interrupt Operations /C0068Burst Length Programmable to 1, 2, 4, and 8 /C0068Four Banks for On-Chip Interleaving (Gapless Access) /C0068Ambient Temperature Range 0°C to 70°C /C0068Gold-Plated Contacts /C0068Pipeline Architecture /C0068Serial Presence Detect (SPD) Using EEPROM SYNCHRONOUS CLOCK CYCLE TIME ACCESS TIME CLOCK TO OUTPUT REFRESH INTERVAL tCK3 tCK2 tAC3 tAC2 tREF ’8SK64JPN-10 10 ns 15 ns 7.5 ns 7.5 ns 64 ms

description

The TM8SK64JPN is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS664814DGE, 8388608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695). operation The TM8SK64JPN operates as eight TMS664814DGE devices that are connected as shown in the functional block diagram. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1998, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0084/C0077/C0056/C0083/C0075/C0054/C0052/C0074/C0080/C0078 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS717 − JULY 1998

2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

DUAL-IN-LINE MEMORY MODULE (TOP VIEW) PIN NOMENCLATURE A[0:11] Row-Address Inputs A[0:8] Column-Address Inputs A13/BA0 Bank Select Zero A12/BA1 Bank Select One CAS Column-Address Strobe CKE0 Clock Enable CK[0:1] System Clock DQ[0:63] Data In/Data Out DQMB[0:7] Data in/Data Out Mask Enable NC No Connect RAS Row-Address Strobe S0 Chip Select SCL SPD Clock SDA SPD Address/Data VDD 3.3-V Supply VSS Ground WE Write Enable TM8SK64JPN (SIDE VIEW) 144

/C0084/C0077/C0056/C0083/C0075/C0054/C0052/C0074/C0080/C0078 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS717 − JULY 1998 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Pin Assignments PIN PIN PIN PIN NO. NAME NO. NAME NO. NAME NO. NAME

1 VSS 37 DQ8 73 NC 109 A9

2 VSS 38 DQ40 74 CK1 110 A12/BA1

3 DQ0 39 DQ9 75 VSS 111 A10

4 DQ32 40 DQ41 76 VSS 112 A11

5 DQ1 41 DQ10 77 NC 113 VDD

6 DQ33 42 DQ42 78 NC 114 VDD

7 DQ2 43 DQ11 79 NC 115 DQMB2

8 DQ34 44 DQ43 80 NC 116 DQMB6

9 DQ3 45 VDD 81 VDD 117 DQMB3

10 DQ35 46 VDD 82 VDD 118 DQMB7

11 VDD 47 DQ12 83 DQ16 119 VSS

12 VDD 48 DQ44 84 DQ48 120 VSS

13 DQ4 49 DQ13 85 DQ17 121 DQ24

14 DQ36 50 DQ45 86 DQ49 122 DQ56

15 DQ5 51 DQ14 87 DQ18 123 DQ25

16 DQ37 52 DQ46 88 DQ50 124 DQ57

17 DQ6 53 DQ15 89 DQ19 125 DQ26

18 DQ38 54 DQ47 90 DQ51 126 DQ58

19 DQ7 55 VSS 91 VSS 127 DQ27

20 DQ39 56 VSS 92 VSS 128 DQ59

21 VSS 57 NC 93 DQ20 129 VDD

22 VSS 58 NC 94 DQ52 130 VDD

23 DQMB0 59 NC 95 DQ21 131 DQ28

24 DQMB4 60 NC 96 DQ53 132 DQ60

25 DQMB1 61 CK0 97 DQ22 133 DQ29

26 DQMB5 62 CKE0 98 DQ54 134 DQ61

27 VDD 63 VDD 99 DQ23 135 DQ30

28 VDD 64 VDD 100 DQ55 136 DQ62

29 A0 65 RAS 101 VDD 137 DQ31

30 A3 66 CAS 102 VDD 138 DQ63

31 A1 67 WE 103 A6 139 VSS

32 A4 68 NC 104 A7 140 VSS

33 A2 69 S0 105 A8 141 SDA

34 A5 70 NC 106 A13/BA0 142 SCL

35 VSS 71 NC 107 VSS 143 VDD

36 VSS 72 NC 108 VSS 144 VDD

/C0084/C0077/C0056/C0083/C0075/C0054/C0052/C0074/C0080/C0078 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS717 − JULY 1998

4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

small-outline dual-in-line memory module and components The small-outline dual-in-line memory module and components include: /C0068PC substrate: 1,10 ± 0,1 mm (0.04 inch) nominal thickness /C0068Bypass capacitors: Multilayer ceramic /C0068Contact area: Nickel plate and gold plate over copper functional block diagram

8 DQ[0:7]8

DQ[0:7] DQMB4 DQ[32:39] DQM DQ[0:7] DQM RAS RAS : SDRAM U[0:3], UB[0:3] CK0 CK: U1, UB1 SPD EEPROM VSS A0 A1 A2 SCL SDA DQ[8:15] DQMB5 DQ[40:47] DQM DQ[0:7] DQM R = 10 Ω R C = 10 Ω DQ[16:23] DQMB6 DQ[48:55] DQM DQ[0:7] DQM DQ[24:31] DQMB7 DQ[56:63] DQM DQ[0:7] DQM CAS CAS : SDRAM U[0:3], UB[0:3] WE WE : SDRAM U[0:3], UB[0:3] CKE0 CKE: SDRAM U[0:3], UB[0:3] A[0:13] A[0:13]: SDRAM U[0:3], UB[0:3] R C R C VDD VSS Two 0.22 µF and one 0.01 µF per SDRAM U[0:3], UB[0:3] U[0:3], UB[0:3] CK1 CK: U2, UB2 CK: U3, UB3 R C R C CK: U0, UB0 LEGEND: CS = Chip select SPD = Serial Presence Detect

/C0084/C0077/C0056/C0083/C0075/C0054/C0052/C0074/C0080/C0078 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS717 − JULY 1998 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over operating ambient temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VDD Supply voltage 3 3.3 3.6 V VSS Supply voltage 0 V VIH High-level input voltage 2 VDD + 0.3 V VIH-SPD High-level input voltage for SPD device 2 5.5 V VIL Low-level input voltage −0.3 0.8 V TA Operating ambient temperature 0 70 °C capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)‡ PARAMETER MIN MAX UNITPARAMETER MIN MAX UNIT C i(CK) Input capacitance, CK input 2.5 4 pF C i(AC) Input capacitance, address and control inputs: A0−A13, RAS, CAS, WE 2.5 5 pF C i(CKE) Input capacitance, CKE input 5 pF C o Output capacitance 4 6.5 pF C i(DQMBx) Input capacitance, DQMBx input 2.5 5 pF C i(Sx) Input capacitance, Sx input 2.5 5 pF C i/o(SDA) Input/output capacitance, SDA input 9 pF C i(SPD) Input capacitance, SPD inputs (except SDA) 7 pF ‡ Specifications in this table represent a single SDRAM device. NOTE 2: V DD = 3.3 V ± 0.3 V. Bias on pins under test is 0 V.

/C0084/C0077/C0056/C0083/C0075/C0054/C0052/C0074/C0080/C0078 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS717 − JULY 1998

6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3)† PARAMETER TEST CONDITIONS MIN MAX UNITPARAMETER TEST CONDITIONS MIN MAX UNIT VOH High-level output voltage IOH = − 2 mA 2.4 V VOL Low-level output voltage IOL = 2 mA 0.4 V II Input current (leakage) 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD /C003410 µA IO Output current (leakage) 0 V < VO < VDD + 0.3 V, Output disabled /C003410 µA ICC1 Operating current Burst length = 1, tRC ≥ tRC MIN CAS latency = 2 105 mA ICC1 Operating current tRC ≥ tRC MIN IOH /IOL = 0 mA, (see Notes 4, 5, and 6) CAS latency = 3 115 mA ICC2P Precharge standby current in power-down mode CKE ≤ VIL MAX, tCK = 15 ns (see Note 7) 1 mA ICC2PS Precharge standby current in power-down mode CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 8) 1 mA ICC2N Precharge standby current in nonpower-downCKE ≥ VIH MIN, tCK = 15 ns (see Note 7) 40 mA ICC2NS Precharge standby current in nonpower-down mode tCK = ∞ (see Note 8) 5 mA ICC3P CKE ≤ VIL MAX, tCK = 15 ns (see Notes 4 and 7) 8 mA ICC3PS Active standby current in power-down modeCKE and CK ≤ VIL MAX, tCK = ∞ (see Notes 4 and 8) 8 mA ICC3N CKE ≥ VIH MIN, tCK = 15 ns (see Notes 4 and 7) 60 mA ICC3NS Active standby current in nonpower-down modeCKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞ (see Notes 4 and 8) 10 mA ICC4 Burst current Page burst, IOH /IOL = 0 mA All banks activated, CAS latency = 2 140 mA ICC4 Burst current All banks activated, nCCD = one cycle (see Notes 9 and 10) CAS latency = 3 200 mA ICC5 Autorefresh current tRC ≤ tRC MIN CAS latency = 2 150 mA ICC5 Autorefresh current tRC ≤ tRC MIN (see Notes 5 and 8) CAS latency = 3 150 mA ICC6 Self-refresh current CKE ≤ VIL MAX 2 mA † Specifications in this table represent a single SDRAM device. NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Only one bank is activated. 5. tRC ≥ tRC MIN 6. Control and address inputs change state twice during tRC . 7. Control and address inputs change state once every 30 ns. 8. Control and address inputs do not change state (stable). 9. Control and address inputs change state once every cycle. 10. Continuous burst access, nCCD = 1 cycle

/C0084/C0077/C0056/C0083/C0075/C0054/C0052/C0074/C0080/C0078 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS717 − JULY 1998 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ac timing requirements†‡ MIN MAX UNITMIN MAX UNIT tCK2 Cycle time, CK CAS latency = 2 15 ns tCK3 Cycle time, CK CAS latency = 3 10 ns tCH Pulse duration, CK high 3 ns tCL Pulse duration, CK low 3 ns tAC2 Access time, CK high to data out (see Note 11) CAS latency = 2 7.5 ns tAC3 Access time, CK high to data out (see Note 11) CAS latency = 3 7.5 ns tOH Hold time, CK high to data out 3 ns tLZ Delay time, CK high to DQ in low-impedance state (see Note 12) 2 ns tHZ Delay time, CK high to DQ in high-impedance state (see Note 13) 10 ns tIS Setup time, address, control, and data input 2 ns tIH Hold time, address, control, and data input 1 nstIH Hold time, address, control, and data input 1 ns tCESP Power down/self-refresh exit time 10 ns tRAS Delay time, ACTV command to DEAC or DCAB command 50 100000 ns tRC Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR command 80 ns tRCD Delay time ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 14) 30 ns tRP Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command 30 ns tRRD Delay time, ACTV command in one bank to ACTV command in the other bank 20 ns tRSA Delay time, MRS command to ACTV, MRS, REFR, or SLFR command 20 ns tAPR Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command tRP − (CL−1)* tCK ns tAPW Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command tRP + 1 tCK ns tT Transition time 1 5 ms † All references are made to the rising transition of CK unless otherwise noted. ‡ Specifications in this table represent a single SDRAM device. NOTES: 11. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CK that is read latency (one cycle after the READ command). Access time is measured at output reference level 1.4 V. 12. tLZ is measured from the rising transition of CK that is read latency (one cycle after the READ command). 13. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 14. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS .

/C0084/C0077/C0056/C0083/C0075/C0054/C0052/C0074/C0080/C0078 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS717 − JULY 1998

8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

clock timing requirements†‡ MIN MAX UNIT tREF Refresh interval 64 ms nCCD Delay time, READ or WRT command to an interrupting command 1 cycles nCDD Delay time, CS low or high to input enabled or inhibited 0 cycles nCLE Delay time, CKE high or low to CLK enabled or disabled 1 1 cycles nCWL Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P 1 cycles nDID Delay time, ENBL or MASK command to enabled or masked data in 0 0 cycles nDOD Delay time, ENBL or MASK command to enabled or masked data out 2 2 cycles nHZP2 Delay time, DEAC or DCAB, command to DQ in high-impedance state CAS latency = 2 2 cycles nHZP3 Delay time, DEAC or DCAB, command to DQ in high-impedance state CAS latency = 3 3 cycles nWCD Delay time, WRT command to first data in 0 0 cycles nWR Delay time, final data in of WRT operation to DEAC or DCAB command 1 cycle † All references are made to the rising transition of CK unless otherwise noted. ‡ A CK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated by CKE (those CK cycles occurring during the time when CKE is asserted low).

details. Table 1 lists the SPD contents. Table 1. Serial Presence Detect Data

0 Defines number of bytes written into serial memory during module manufacturing 128 bytes 80h

1 Total number of bytes of SPD memory device 256 bytes 08h

3 Number of row addresses on this assembly 12 0Ch

4 Number of column addresses on this assembly 9 09h

5 Number of module rows on this assembly 1 bank 01h

6 Data width of this assembly 64 bits 40h

7 Data width continuation 00h

8 Voltage interface standard of this assembly LVTTL 01h

9 SDRAM cycle time at maximum supported CAS latency (CL), CL = X tCK = 10 ns A0h

11 SODIMM configuration type (non-parity, parity, error correcting code [ECC]) Non-Parity 00h

13 SDRAM width, primary DRAM x8 08h

14 Error-checking SDRAM data width N/A 00h

15 Minimum clock delay, back-to-back random column addresses 1 CK cycle 01h

16 Burst lengths supported 1, 2, 4, and 8 0Fh

17 Number of banks on each SDRAM device 4 banks 04h

18 CAS latencies supported 2, 3 06h

19 CS latency 0 01h

20 Write latency 0 01h

21 SDRAM module attributes Non-buffered/

22 SDRAM device attributes: general

23 Minimum clock cycle time at CL = X − 1 tCK = 15 ns F0h

10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Table 1. Serial Presence Detect Data (Continued)

25 Minimum clock cycle time at CL = X − 2 N/A 00h

26 Maximum data-access time from clock at CL = X − 2 N/A 00h

27 Minimum row-precharge time tRP = 30 ns 1Eh

28 Minimum row-active to row-active delay tRRD = 20 ns 14h

29 Minimum RAS -to-CAS delay tRCD = 30 ns 1Eh

30 Minimum RAS pulse width tRAS =50 ns 32h

31 Command and address signal input setup time tIS = 2 ns 20h

32 Command and address signal input hold time tIH = 1 ns 10h

33 Data signal input setup time tIS = 2 ns 20h

34 Data signal input hold time tIH = 1 ns 10h

63 Checksum for byte 0−62 14 0Eh

72 Manufacturing location† TBD

73 Manufacturer’s part number T 54h

74 Manufacturer’s part number M 4Dh

75 Manufacturer’s part number 8 38h

76 Manufacturer’s part number S 53h

77 Manufacturer’s part number K 4Bh

78 Manufacturer’s part number 6 36h

79 Manufacturer’s part number 4 34h

80 Manufacturer’s part number J 4Ah

81 Manufacturer’s part number P 50h

82 Manufacturer’s part number N 4Eh

83 Manufacturer’s part number - 2Dh

84 Manufacturer’s part number 1 31h

85 Manufacturer’s part number 0 30h

91 Die revision code† TBD

92 PCB revision code† TBD

126 Clock frequency 66 MHz 66h

127 SDRAM component and clock interconnection details 199 C7h

† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).

/C0084/C0077/C0056/C0083/C0075/C0054/C0052/C0074/C0080/C0078 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS717 − JULY 1998 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device symbolization (TM8SK64JPN) -SS YYMMT YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE A: Location of symbolization may vary. TM8SK64JPN

/C0084/C0077/C0056/C0083/C0075/C0054/C0052/C0074/C0080/C0078 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS717 − JULY 1998

12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

BDQ (R-SODIMM-N144) SMALL OUTLINE DUAL IN-LINE MEMORY MODULE 0.010 (0,25) MAX 0.044 (1,12) 0.036 (0,91) 1.130 (28,70) 1.120 (28,45) 0.157 (4,00) 4088188/A 07/97 0.095 (2,41) MAX 0.150 (3,81) MAX (For Double-Sided Module Only) 0.126 (3,20) 0.788 (20,00) TYP 2.655 (67,44) 0.024 (0,61) TYP 2.665 (67,69) Notch 0.157 (4,00) x 0.079 (2,00) Deep

2 Places

0.196 (4,98) 0.098 (2,49) Notch 0.060 (1,52) x 0.158 (4,01) Deep 0.031 (0,79) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-190

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applications

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