TM893GBK32S-80

TM497FBK32 TI | Alldatasheet

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TM497FBK32, TM497FBK32S 4194304 BY 32-BIT TM893GBK32, TM893GBK32S 8388608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization – TM497FBK32/S: 4 194 304 x 32 – TM893GBK32/S: 8 388 608 x 32 /C0068Single 5-V Power Supply (±10% Tolerance) /C006872-Pin Single-In-Line Memory Module (SIMM) for Use With Sockets /C0068TM497FBK32/S – Uses Eight 16M-Bit Dynamic Random-Access Memories (DRAMs) in Plastic Small-Outline J-Lead (SOJ) Packages /C0068TM893GBK32/S – Uses Sixteen 16M-Bit DRAMs in Plastic SOJ Packages /C0068Long Refresh Period 32 ms (2 048 Cycles) /C0068All Inputs, Outputs, Clocks Fully TTL-Compatible /C00683-State Output /C0068Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks /C0068Extended Data Out (EDO) Operation With CAS -Before-RAS (CBR), RAS-Only, and Hidden Refresh /C0068Presence Detect /C0068Performance Ranges: ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE tRAC tAA tCAC tHPC (MAX) (MAX) (MAX) (MIN) ’497FBK32/S-60 60 ns 30 ns 15 ns 25 ns ’497FBK32/S-70 70 ns 35 ns 18 ns 30 ns ’497FBK32/S-80 80 ns 40 ns 20 ns 35 ns ’893GBK32/S-60 60 ns 30 ns 15 ns 25 ns ’893GBK32/S-70 70 ns 35 ns 18 ns 30 ns ’893GBK32/S-80 80 ns 40 ns 20 ns 35 ns /C0068Low Power Dissipation /C0068Operating Free-Air Temperature Range 0°C to 70°C /C0068Gold-Tabbed Version Available:† TM497FBK32, TM893GBK32 /C0068Tin-Lead (Solder-) Tabbed Version Available: TM497FBK32S, TM893GBK32S

description

The TM497FBK32 is a 16M-byte dynamic random-access memory (DRAM) organized as four times 4194304 × 8 bits in a 72-pin leadless single-in-line memory module (SIMM). The SIMM is composed of eight TMS417409DJ, 4194304 × 4-bit DRAMs, each in 24/26-lead plastic small-outline J-lead (SOJ) packages mounted on a substrate with decoupling capacitors. The TMS417409DJ is described in the TMS416409, TMS417409 data sheet (literature number SMKS884). The TM497FBK32 SIMM is available in the single-sided BK leadless module for use with sockets. The TM497FBK32 features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for operation from 0°C to 70°C. The TM893GBK32/S is a 32M-byte DRAM organized as four times 8388608 × 8 bits in a 72-pin leadless SIMM. The SIMM is composed of sixteen TMS417409DJ 4194304 × 4-bit DRAMs. The TM893GBK32/S SIMM is available in the double-sided BK leadless module for use with sockets. The TM893GBK32/S features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for operation from 0°C to 70°C. operation The TM497FBK32/S operates as eight TMS417409DJs connected as shown in Figure 1 and in Table 1. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. The TM893GBK32/S operates as sixteen TMS417409DJs connected as shown in Figure 2 and in Table 2. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. Copyright  1996, Texas Instruments Incorporated

TM497FBK32, TM497FBK32S 4194304 BY 32-BIT TM893GBK32, TM893GBK32S 8388608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996

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The refresh period is extended to 32 ms and, during this period, each of the 2 048 rows must be strobed with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power. power up To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh (RAS -only or CBR) cycle.

TM497FBK32, TM497FBK32S 4194304 BY 32-BIT TM893GBK32, TM893GBK32S 8388608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PRESENCE DETECT SIGNAL (PIN) PD1 (67) PD2 (68) PD3 (69) PD4 (70) 80 ns VSS NC NC VSS TM497FBK32/S 70 ns VSS NC VSS NC 60 ns VSS NC NC NC 80 ns NC VSS NC VSS TM893GBK32/S 70 ns NC VSS VSS NC 60 ns NC VSS NC NC NC NC CAS0 CAS2 CAS3 CAS1 RAS0 NC NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A10 DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 NC VCC NC RAS2 NC NC BK SINGLE-IN-LINE PACKAGE (TOP VIEW) PIN NOMENCLATURE A0–A10 Address Inputs CAS0 –CAS3 Column-Address Strobe DQ0–DQ31 Data In/Data Out NC No Connection PD1–PD4 Presence Detects RAS0 –RAS3 Row-Address Strobe VCC 5-V Supply VSS Ground W Write Enable VSS TM893GBK32/S (SIDE VIEW) TM497FBK32/S (SIDE VIEW)

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Table 1. TM497FBK32/S Connection Table Table 2. TM893GBK32/S Connection Table

4 M × 4

11114 M × 4

Figure 1. Functional Block Diagram of TM497FBK32

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Figure 2. Functional Block Diagram of TM893GBK32/S

TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) – 1 0.8 V TA Operating free-air temperature 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ ’497FBK32-60 ’497FBK32-70 ’497FBK32-80 UNITPARAMETER TEST CONDITIONS ‡ MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 Read- or write-cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 880 800 720 mA ICC2 Standby current VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high 16 16 16 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and CAS high 8 8 8 mA ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 880 800 720 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, tPC = MIN, RAS low, CAS cycling 560 480 400 mA ‡ For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH

TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996

8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS † ’893GBK32-60 ’893GBK32-70 ’893GBK32-80 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC ± 20 ± 20 ± 20 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC , CASx high ± 20 ± 20 ± 20 µA ICC1 Read- or write-cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 896 816 736 mA ICC2 Standby current VIH = 2.4 V (TTL), After one memory cycle, RASx and CASx high 32 32 32 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After one memory cycle, RASx and CASx high 16 16 16 mA ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, RASx cycling, (RASx only); Minimum cycle CASx low (CBR) CASx high RASx low after 1760 1600 1440 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, tPC = MIN, RASx low, CASx cycling 576 496 416 mA † For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5) PARAMETER TM497FBK32 TM893GBK32 UNITPARAMETER MIN MAX MIN MAX UNIT C i(A) Input capacitance, address inputs 50 80 pF C i(R) Input capacitance, RAS inputs 33 28 pF C i(C) Input capacitance, CAS inputs 17 28 pF C i(W) Input capacitance, write-enable input 66 112 pF C o(DQ) Output capacitance on DQ pins 9 14 pF NOTE 5: V CC = 5 V ± 0.5 V, and the bias on pins under test is 0 V.

TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’497FBK32-60 ’893GBK32-60 ’497FBK32-70 ’893GBK32-70 ’497FBK32-80 ’893GBK32-80 UNIT MIN MAX MIN MAX MIN MAX tAA Access time from column address 30 35 40 ns tCAC Access time from CAS low 15 18 20 ns tCPA Access time from column precharge 35 40 45 ns tRAC Access time from RAS low 60 70 80 ns tCLZ CAS to output in low-impedance state 0 0 0 ns tOH Output disable time from start of CAS high 3 3 3 ns tOFF Output disable time after CAS high (see Note 6) 0 15 0 18 0 20 ns NOTE 6: tOFF is specified when the output is no longer driven. EDO timing requirements over recommended ranges of supply voltage and operating free-air temperature ’497FBK32-60 ’893GBK32-60 ’497FBK32-70 ’893GBK32-70 ’497FBK32-80 ’893GBK32-80 UNIT MIN MAX MIN MAX MIN MAX tHPC Cycle time, EDO page mode read or write 25 30 35 ns tPRWC Cycle time, EDO read-write 80 90 100 ns tCSH Hold time, CAS after RAS 50 55 60 ns tDOH Hold time, output after RAS 3 3 3 ns tCAS Pulse duration, CAS 10 10 000 12 10 000 15 10 000 ns tWPE Pulse duration, W (output disable only) 5 5 5 ns tCP Precharge time, CAS 5 5 5 ns

TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996

10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timing requirements over recommended ranges of supply voltage and operating free-air temperature ’497FBK32-60 ’893GBK32-60 ’497FBK32-70 ’893GBK32-70 ’497FBK32-80 ’893GBK32-80 UNIT MIN MAX MIN MAX MIN MAX tRC Cycle time, random read or write (see Note 7) 110 130 150 ns tPC Cycle time, page-mode read or write (see Notes 7 and 8)40 45 50 ns tRASP Pulse duration, page-mode, RAS low 60 100 000 70 100 000 80 100 000 ns tRAS Pulse duration, non-page-mode, RAS low 60 10 000 70 10 000 80 10 000 ns tCAS Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns tCP Pulse duration, CAS high 10 10 10 ns tRP Pulse duration, RAS high (precharge) 40 50 60 ns tWP Pulse duration, W low 10 10 10 ns tASC Setup time, column address before CAS low 0 0 0 ns tASR Setup time, row address before RAS low 0 0 0 ns tDS Setup time, data before CAS low 0 0 0 ns tRCS Setup time, W high before CAS low 0 0 0 ns tCWL Setup time, W-low before CAS high 10 12 15 ns tRWL Setup time, W-low before RAS high 10 12 15 ns tWCS Setup time, W-low before CAS low 0 0 0 ns tWRP Setup time, W-high before RAS low (CBR refresh only) 10 10 10 ns tCAH Hold time, column address after CAS low 10 12 15 ns tRHCP Hold time, RAS high after CAS precharge 35 40 45 ns tDH Hold time, data after CAS low 10 12 15 ns tRAH Hold time, row address after RAS low 10 10 10 ns tRCH Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 9) 0 0 0 ns tWCH Hold time, W low after CAS low 10 12 15 ns tWRH Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns tCHR Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns tCRP Delay time, CAS high to RAS low 5 5 5 ns tCSH Delay time, RAS low to CAS high 50 55 60 ns tCSR Delay time, CAS low to RAS low (CBR refresh only) 5 5 5 ns tRAD Delay time, RAS low to column address (see Note 10) 15 30 15 35 15 40 ns tRAL Delay time, column address to RAS high 30 35 40 ns tCAL Delay time, column address to CAS high 30 35 40 ns tRCD Delay time, RAS low to CAS low (see Note 10) 20 45 20 52 20 60 ns tRPC Delay time, RAS high to CAS low (CBR only) 0 0 0 ns tRSH Delay time, CAS low to RAS high 10 12 15 ns tREF Refresh time interval 32 32 32 ms tT Transition time 3 30 3 30 3 30 ns NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be greater than or equal to tCP . 9. Either tRRH or tRCH must be satisfied for a read cycle. 10. The maximum value is specified only to assure access time.

TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT EXTENDED DATA OUT DYNAMIC RAM MODULES SMMS668 – NOVEMBER 1996 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA BK (R-PSIM-N72) SINGLE-IN-LINE MEMORY MODULE 4040197/B 02/96 0.208 (5,28) MAX 0.400 (10,16) TYP 0.010 (0,25) MAX 0.054 (1,37) 1.005 (25,53) 0.995 (25,27) 0.047 (1,19) 0.360 (9,14) MAX (For Double-Sided SIMM) 4.255 (108,08) 4.245 (107,82) 0.125 (3,18) TYP 0.040 (1,02) TYP 0.120 (3,05) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. device symbolization TM497FBK32 YYMMT -SS YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE: The location of the part number may vary.

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