TM893CBK32S

TM893CBK32 TI | Alldatasheet

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TM893CBK32, TM893CBK32S

8388608 BY 32-BIT

SMMS652A – FEBRUARY 1995 – REVISED JUNE 1995 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization TM893CBK32 ...8 3 8 8 6 0 8 × 32 Bit /C0068Single 5-V Power Supply (±10% Tolerance) /C006872-Pin, Leadless Single In-Line Memory Module (SIMM) for Use With Sockets /C0068TM893CBK32 – Utilizes Sixteen 16-Megabit Dynamic RAMs in Plastic Small-Outline J-Lead (SOJ) Packages /C0068Long Refresh Period 32 ms (2048 Cycles) /C0068All Inputs, Outputs, Clocks Fully TTL Compatible /C00683-State Output /C0068Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks /C0068Enhanced Page-Mode Operation With CAS -Before-RAS (CBR), RAS-Only, and Hidden Refresh /C0068Presence Detect /C0068Performance Ranges: ACCESS ACCESS ACCESS READ TIME TIME TIME OR tRAC tAA tCAC WRITE CYCLE (MAX) (MAX) (MAX) (MIN) ’893CBK32-60 60 ns 30 ns 15 ns 110 ns ’893CBK32-70 70 ns 35 ns 18 ns 130 ns ’893CBK32-80 80 ns 40 ns 20 ns 150 ns /C0068Low Power Dissipation /C0068Operating Free-Air-Temperature Range 0°C to 70°C /C0068Gold-Tabbed Versions Available:† TM893CBK32 /C0068Tin-Lead (Solder) Tabbed Versions Available: TM893CBK32S

description

The TM893CBK32 is a 32-megabyte, dynamic random-access memory organized as four times 8388608× 8 bits in a 72-pin, leadless single in-line memory module (SIMM). The SIMM is composed of 16 TMS417400DJ, 4194304 × 4-bit dynamic RAMs, each in 24/26-lead plastic small-outline J-lead (SOJ) packages mounted on a substrate with decoupling capacitors. The TMS417400DJ is described in the TMS417400 data sheet. The TM893CBK32 SIMM is available in the double-sided BK leadless module for use with sockets. operation The TM893CBK32 operates as sixteen TMS417400DJs connected as shown in the functional block diagram and Table 1. The common I/O feature dictates the use of early-write cycles to prevent contention on D and Q. refresh The refresh period is extended to 32 ms, and during this period each of the 2048 rows must be strobed with RAS to retain data. To conserve power, CAS can remain high during the refresh sequence. power up To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles must include at least one refresh (RAS -only or CBR) cycle. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1995, Texas Instruments Incorporated † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.

TM893CBK32, TM893CBK32S SMMS652A – FEBRUARY 1995 – REVISED JUNE 1995

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SIGNAL (PIN) PD1 (67) PD2 (68) PD3 (69) PD4 (70) 80 ns NC VSS NC VSS TM893CBK32 70 ns NC VSS VSS NC 60 ns NC VSS NC NC TM893CBK32 (SIDE VIEW) NC NC CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A10 DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 NC VCC RAS3 RAS2 NC NC BK SINGLE-IN-LINE PACKAGE (TOP VIEW) PIN NOMENCLATURE A0–A10 Address Inputs CAS0 –CAS3 Column-Address Strobe DQ0–DQ31 Data In/Data Out NC No Connection PD1–PD4 Presence Detects RAS0 –RAS3 Row-Address Strobe VCC 5-V Supply VSS Ground W Write Enable VSS

Table 1. Connection Table

TM893CBK32, TM893CBK32S SMMS652A – FEBRUARY 1995 – REVISED JUNE 1995 Temp late R elease D ate: 7–11–94

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functional block diagram (side 1)

4 M × 4

A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 DQ0– DQ3 11 1111

11114 M × 4

A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 RAS W CAS OE DQ1– DQ4 DQ8– DQ11 DQ16– DQ19 DQ24– DQ27 DQ4– DQ7 DQ12– DQ15 DQ20– DQ23 DQ28– DQ31 W RAS0 CAS0 CAS1 CAS2 CAS3 RAS2 functional block diagram (side 2) A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 DQ0– DQ3 11 1111 A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 RAS W CAS OE DQ1– DQ4 DQ8– DQ11 DQ16– DQ19 DQ24– DQ27 DQ4– DQ7 DQ12– DQ15 DQ20– DQ23 DQ28– DQ31 W RAS1 CAS0 CAS1 CAS2 CAS3 RAS3

TM893CBK32, TM893CBK32S SMMS652A – FEBRUARY 1995 – REVISED JUNE 1995 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) – 1 0.8 V TA Operating free-air temperature 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS ’893BBK32-60 ’893BBK32-70 ’893BBK32-80 UNITPARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltageIOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, V I = 0 V to 6.5 V, All others = 0 V to VCC ± 20 ± 20 ± 20 µA IO Output current (leakage) VCC = 5.5 V, V O = 0 V to VCC , CAS high ± 20 ± 20 ± 20 µA ICC1 Read or write cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 896 816 736 mA ICC2 Standby current VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 32 32 32 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high 16 16 16 mA ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 1760 1600 1440 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, t PC = Minimum, RAS low, CAS cycling 576 496 416 mA NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH

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capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5) PARAMETER ’893CBK32 UNITPARAMETER MIN MAX UNIT C i(A) Input capacitance, A0–A10 80 pF C i(R) Input capacitance, RAS inputs 28 pF C i(C) Input capacitance, CAS inputs 28 pF C i(W) Input capacitance, W 112 pF C o(DQ) Output capacitance on DQ pins 14 pF NOTE 5: V CC = 5 V ± 0.5 V and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’893CBK32-60 ’893CBK32-70 ’893CBK32-80 UNITPARAMETER MIN MAX MIN MAX MIN MAX UNIT tAA Access time from column-address 30 35 40 ns tCAC Access time from CAS low 15 18 20 ns tCPA Access time from column precharge 35 40 45 ns tRAC Access time from RAS low 60 70 80 ns tCLZ CAS to output in the low-impedance state 0 0 0 ns tOH Output disable from start of CAS high 3 3 3 ns tOFF Output disable time after CAS high (see Note 6) 0 15 0 18 0 20 ns NOTE 6: tOFF is specified when the output is no longer driven. timing requirements over recommended ranges of supply voltage and operating free-air temperature ’893CBK32-60 ’893CBK32-70 ’893CBK32-80 UNIT MIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, random read or write (see Note 7) 110 130 150 ns tPC Cycle time, page-mode read or write (see Notes 7 and 8)40 45 50 ns tRASP Pulse duration, page mode, RAS low 60 100 000 70 100 000 80 100 000 ns tRAS Pulse duration, nonpage mode, RAS low 60 10 000 70 10 000 80 10 000 ns tCAS Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns tCP Pulse duration, CAS high (precharge) 10 10 10 ns tRP Pulse duration, RAS high (precharge) 40 50 60 ns tWP Pulse duration, W low 10 10 10 ns tASC Setup time, column address before CAS low 0 0 0 ns tASR Setup time, row address before RAS low 0 0 0 ns tDS Setup time, data before CAS low 0 0 0 ns tRCS Setup time, W high before CAS low 0 0 0 ns tCWL Setup time, W low before CAS high 15 18 20 ns tRWL Setup time, W low before RAS high 15 18 20 ns tWCS Setup time, W low before (precharge) CAS low 0 0 0 ns tWRP Setup time, W high before RAS low (CBR refresh only) 10 10 10 ns NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be ≥ tCP .

TM893CBK32, TM893CBK32S SMMS652A – FEBRUARY 1995 – REVISED JUNE 1995 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (concluded) ’893CBK32-60 ’893CBK32-70 ’893CBK32-80 UNIT MIN MAX MIN MAX MIN MAX UNIT tCAH Hold time, column address after CAS low 10 15 15 ns tDH Hold time, data after CAS and W low 10 15 15 ns tRAH Hold time, row address after RAS low 10 10 10 ns tRCH Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 9) 0 0 0 ns tRHCP Hold time, RAS high from CAS precharge 35 40 45 ns tWCH Hold time, W low after CAS low 10 15 15 ns tWRH Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns tCHR Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns tCRP Delay time, CAS high to RAS low 5 5 5 ns tCSH Delay time, RAS low to CAS high 60 70 80 ns tCSR Delay time, CAS low to RAS low (CBR refresh only) 5 5 5 ns tRAD Delay time, RAS low to column address (see Note 10) 15 30 15 35 15 40 ns tRAL Delay time, column address to RAS high 30 35 40 ns tCAL Delay time, column address to CAS high 30 35 40 ns tRCD Delay time, RAS low to CAS low (see Note 10) 20 45 20 52 20 60 ns tRPC Delay time, RAS high to CAS low (CBR refresh only) 0 0 0 ns tRSH Delay time, CAS low to RAS high 15 18 20 ns tREF Refresh time interval 32 32 32 ms tT Transition time 3 30 3 30 3 30 ns NOTES: 9. Either tRRH or tRCH must be satisfied for a read cycle. 10. The maximum value is specified only to assure access time.

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