TM54S416T ETC | Alldatasheet

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@ Package 400-mil 54-pin TSOP(II) [ies corconcmems oo emcees oe @ JEDEC PC133/PC100 compatible @ Auto and Self Refresh @ Single 3.3V Power Supply @ 64ms refresh period (4K cycles) @-LVTTL Signal Compatible Ml cee oe woevee oes s organization @ Programmable TH o0e coc ccccccccecccce ces cescccees se cues - CAS Latency (3 or 2 clocks) @ Pin36 and 40 are “No Connected” - Burst Length (1,2,4,8 & full page) @ Fully synchronous operation referenced - Burst type (Sequential & Interleave) to clock rising edge [Toe + crccee ce co coc cree one cocerees conse ce Frequency vs. AC Parameter Se For reference only. 1 Rev: 1.0

Pin Name Function Pin Name Function Master Clock DQML/DQMU [Output Disable(Write Mask) CS Chip Select BAL,BAO Bank Address Row Address Strobe Column Address Strobe Power Supply for Output DQO-DOIS [Data /O vo [ |! 64 [7] Vss mo [ ]2 63 [| vais vooo [7] 3 52 |__| vsso oa [| 5 so; ] cas os [| 7 48 [| vai2 pw (| 8 47 [__] vat pes [__|10 45 [| vaio mes [i 44 [—] Dao vssa [__]12 43 |] vooa por [13 42[__] 008 voo [_]i4 TSOP( IL )-54 aif] ss pom. [__] 15 4o[] Top View Me [__]16 39 [_] bau Jas L_]iz as{__] ak /ras [__]18 af] oe yes [_]i9 36[__] ao [_|20 x{_ Jan py [fz al dag ap [_]22 33[- |] 8 wo [ja az{_ ja A [|e <The a2 [ls sof] 4 As [26 2a[ | A woo [_]27 28 |__] ss For reference only. 2 Rev: 1.0

[Pin | Name | Pin Function CLK System clock Active on the positive going edge to sample all inputs, /CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK,CKE and DQML/DQMU. ICKE Clock enable Masks system clock to freeze operation from ithe next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. AO~AIL Address input Row/column addresses are multiplexed on the same pins. Row address:A0~A11, Column address: AQ~A7 IBA1,BA0 Bank address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with /RAS low. Enables rows access & pre-charge. /CAS Column address strobe |Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. /WE Write enable Enables write operation and row pre-charge. Latches data in starting from /CAS,/WE active. IDQMU/DQML |Data I/O mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQML/DQMU active. IDQo~15 Data input/output Data inputs/outputs are multiplexed on the same pins. IVdd/Vss Power supply/ground |Power and ground for the input buffers and the core logic. VddQ/VssQ Data output power/ _|Isolated power supply and ground for the ground output buffers to provide improved noise immunity. INC/RFU No connection / This pin is recommended to be left no reserved for future use_|connection on the device. For reference only. 3 Rev: 1.0

Voltage supply relative to Vdd, Vdda -0.5 to 4.6 Vv \\Vss(VssQ [Powerdissipation = [PD tT [Output Shorted current___— ios, [50 | mA DC OPERATING CONDITIONS Recommended operating conditions(Referenced to Vss=0V,T,=0* sto 70° } | - Parameter Symbol | Min. | Typ. | Max. | Unit premio Pa +0.3 input Logic Low Voltage [Vy | 0.3 | - [os | v | Output Logic High Voltage Vou 24 - - Vv [Output Logic Low Voltage Vu | | = | oe Tv | linput/Output Leakage Current [In ty |S PTs DC Characteristics (Recommended operating condition T, = 0+ *to 70* +;unless otherwise noted.) Symbo Test Conditions coc (One bank active) tae = tec(min), tex = tex (min) Pre-charge Standby Current in lecoP CKE=V), (max), tex = 15ns 2 mA Power Down Pre-charge Standby Current in [IQ¢,N |CKE>=V,,(min)/CS> = Vix 20 mA INon-Power Down Mode (min) , ty = 15ns (min), CLK<= V,, (max) , ‘Active Standby Current in Power mA [Down Mode legPS_|CKE & CLK<=V,, (max) 5 Power Down Mode to, =15ns loc3NS |/CS=CKE=V (min), 35 mA CLK= V,, (max ) Operating Covent Bust mod) [iggy _[BL-ACL=3.Al Banks Acive [130 [100 [100 | mA | eifReiesh Curent inn, | KE 02V_—< 2 i mt For reference only. 4 Rev: 1.0

Recommended operating conditions(Vdd=VddQ=3.3V,Vss=0V,T,= 0 to 70° } Symbol Parameter PT ek Gee tmecs sof roy isp [al [oak requ Cts [frees [ss [3] ty. Clock Access TimecL-3 | | 80) | sa] | $a] m_| 4} ta, [Clock High Pulse Width 2.5 2.5 2.5 ns [3] te, [Clock Low Pulse Width [2.5 [25 f 2s [| m_| [4] — ty |input Setup timetall inputs | 15-[ | 18} | 15] | _| 7|__t,, _|Input Hold time(all inputs) 0.8 0.8 0.8 ns [8] —t, [Transition ime ofclock | 1.0 | 10 | 1.0 | 10 | 10] 10 | ms] [9] tp [Row t Column delay [18 |_| 18 |_| 20 |__| ms 10] tae __ |Row Cycle time 60 63 67 ns [Til as [Rowactivetime | @ | ||| #[ [m= | 12] ta» _|Row Pre-charge time 15 18 20 ns [13a [Row activeto active delay [2 [| 4 [|_| 3 [|_| ty; [Refehtime sid S| | | dP os For reference only. 5 Rev: 1.0

\\ Nores: 1. ALL DIMENSIONS ARE IN MM 2) DIMENSION D1 AND E1 DOES NO AK ldK | 3 CopLANARITY OF ALL LEADS SHA / F s (BEFORE TEST) UNLESS OTHERW -I—-— - *— - —+— - ——_ -—1 +} Fe 4. GENERAL PHYSICAL OUTLINE SPE “ab ‘~b- = VISUAL INSPECTION SPEC UNLES 5] 5 PLATING THICKNESS © 200~0 801 : HEBER REBAR EEooE i 0.8 BASIC SEATING BIANE — 4 TT $j € 3 ¢ 3 < [S]eose[=e- x DETAIL A oMIN. E! ° Ed 0,500.10 a == EOL—S0540400—001 RO DETAIL_A ee FORM:EG00005.¢ ew For reference only. 6 Rev: 1.0