TM4EP72CPN-60

TM4EP64BJN TI | Alldatasheet

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Technical content

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization – TM4EP64xxN-xx ...4 1 9 4304 × 64 Bits – TM4EP72xxN-xx ...4 1 9 4304 × 72 Bits /C0068Single 3.3-V Power Supply (±10% Tolerance) /C0068JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket /C0068TM4EP64xxN-xx — Utilizes Sixteen 16M-Bit High-Speed (4M× 4-Bit) Dynamic RAMs /C0068TM4EP72xxN-xx — Utilizes Eighteen 16M-Bit High-Speed (4M× 4-Bit) Dynamic RAMs /C0068High-Speed, Low-Noise LVTTL Interface /C0068High-Reliability Plastic 24/26-Lead 300-Mil-Wide Surface-Mount Small-Outline J-Lead (SOJ) Package (DJ Suffix) and 24/26-Lead 300-Mil-Wide Surface-Mount Thin Small-Outline Package (TSOP) (DGA Suffix) /C0068Long Refresh Periods: – TM4EPxxCxN: 64 ms (4096 Cycles) – TM4EPxxBxN: 32 ms (2048 Cycles) /C00683-State Output /C0068Extended-Data-Out (EDO) Operation With CAS -Before-RAS (CBR), RAS-Only, and Hidden Refresh /C0068Serial Presence-Detect (SPD) Using EEPROM /C0068Ambient Temperature Range 0°C to 70°C /C0068Gold-Plated Contacts /C0068Performance Ranges ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE tRAC tCAC tAA tHPC (MAX) (MAX) (MAX) (MIN) ’4EPxxxxN-50 50 ns 13 ns 25 ns 20 ns ’4EPxxxxN-60 60 ns 15 ns 30 ns 25 ns ’4EPxxxxN-70 70 ns 18 ns 35 ns 30 ns

description

The TM4EP64xxN is a 32M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of sixteen TMS42x409A, 4194304 × 4-bit EDO dynamic random-access memories (DRAMs), each in a 300-mil, 26-pin plastic thin small-outline package (TSOP) (DGA suffix) mounted on a substrate with decoupling capacitors. See the TMS42x409A data sheet (literature number SMKS893). The TM4EP64xJN is available with an SOJ package (DJ suffix). The TM4EP72xxN is a 32M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS42x409A, 4194304 × 4-bit EDO DRAMs, each in a 300-mil, 26-pin plastic TSOP (DGA suffix) mounted on a substrate with decoupling capacitors. See the TMS42x409A data sheet (literature number SMKS893). The TM4EP72xJN is available with an SOJ packaage (DJ suffix). operation The TM4EP64xxN operates as 16 TMS42x409As that are connected as shown in the TM4EP64xxN functional block diagram. The TM4EP72xxN operates as 18 TMS42x409As that are connected as shown in the TM4EP72xxN functional block diagram. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1998, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998

2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

DUAL-IN-LINE MEMORY MODULE (TOP VIEW) TM4EP72xxN (SIDE VIEW) PIN NOMENCLATURE – TM4EPxxBxN A[0:10] Row-Address Inputs A[0:10] Column-Address Inputs DQ[0:63] Data In/Data Out CB[0:7] Check Bit In/Check Bit Out CAS[0:7] Column-Address Strobe RAS0 and RAS2 Row-Address Strobe WE0 and WE2 Write Enable OE0 and OE2 Output Enable SA[0:2] Serial Presence Detect (SPD) Device Add Input SDA SPD Address/Data SCL SPD Clock NC No Connect VDD 3.3-V Supply VSS Ground TM4EP64xxN (SIDE VIEW) PIN NOMENCLATURE – TM4EPxxCxN A[0:11] Row-Address Inputs A[0:9] Column-Address Inputs DQ[0:63] Data In/Data Out CB[0:7] Check Bit In/Check Bit Out CAS[0:7] Column-Address Strobe RAS0 and RAS2 Row-Address Strobe WE0 and WE2 Write Enable OE0 and OE2 Output Enable SA[0:2] Serial Presence Detect (SPD) Device Add Input SDA SPD Address/Data SCL SPD Clock NC No Connect VDD 3.3-V Supply VSS Ground

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Assignments PIN PIN PIN PIN NO. NAME NO. NAME NO. NAME NO. NAME

1 VSS 43 VSS 85 VSS 127 VSS

2 DQ0 44 OE2 86 DQ32 128 NC

3 DQ1 45 RAS2 87 DQ33 129 NC

4 DQ2 46 CAS2 88 DQ34 130 CAS6

5 DQ3 47 CAS3 89 DQ35 131 CAS7

6 VDD 48 WE2 90 VDD 132 NC

7 DQ4 49 VDD 91 DQ36 133 VDD

8 DQ5 50 NC 92 DQ37 134 NC

9 DQ6 51 NC 93 DQ38 135 NC

10 DQ7 52 CB2 94 DQ39 136 CB6

11 DQ8 53 CB3 95 DQ40 137 CB7

12 VSS 54 VSS 96 VSS 138 VSS

13 DQ9 55 DQ16 97 DQ41 139 DQ48

14 DQ10 56 DQ17 98 DQ42 140 DQ49

15 DQ11 57 DQ18 99 DQ43 141 DQ50

16 DQ12 58 DQ19 100 DQ44 142 DQ51

17 DQ13 59 VDD 101 DQ45 143 VDD

18 VDD 60 DQ20 102 VDD 144 DQ52

19 DQ14 61 NC 103 DQ46 145 NC

20 DQ15 62 NC 104 DQ47 146 NC

21 CB0 63 NC 105 CB4 147 NC

22 CB1 64 VSS 106 CB5 148 VSS

23 VSS 65 DQ21 107 VSS 149 DQ53

24 NC 66 DQ22 108 NC 150 DQ54

25 NC 67 DQ23 109 NC 151 DQ55

26 VDD 68 VSS 110 VDD 152 VSS

27 WE0 69 DQ24 111 NC 153 DQ56

28 CAS0 70 DQ25 112 CAS4 154 DQ57

29 CAS1 71 DQ26 113 CAS5 155 DQ58

30 RAS0 72 DQ27 114 NC 156 DQ59

31 OE0 73 VDD 115 NC 157 VDD

32 VSS 74 DQ28 116 VSS 158 DQ60

33 A0 75 DQ29 117 A1 159 DQ61

34 A2 76 DQ30 118 A3 160 DQ62

35 A4 77 DQ31 119 A5 161 DQ63

36 A6 78 VSS 120 A7 162 VSS

37 A8 79 NC 121 A9 163 NC

38 A10 80 NC 122 A11 164 NC

39 NC 81 NC 123 NC 165 SA0

40 VDD 82 SDA 124 VDD 166 SA1

41 NC 83 SCL 125 NC 167 SA2

42 NC 84 VDD 126 NC 168 VDD

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998

4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

dual-in-line memory module and components The dual-in-line memory module and components include: /C0068PC substrate: 1,27 /C0034 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage /C0068Bypass capacitors: Multilayer ceramic /C0068Contact area: Nickel plate and gold plate over copper functional block diagram for the TM4EP64xxN CAS OE W RAS RAS0 WE0 OE0 CAS0 DQ[0:3] CAS OE W RAS UB0 RAS2 WE2 OE2 CAS4 DQ[32:35]DQ[0:3] DQ[0:3] CAS OE W RAS U1DQ[4:7] CAS OE W RAS UB1DQ[36:39]DQ[0:3] DQ[0:3] CAS OE W RAS CAS1 DQ[8:11] CAS OE W RAS UB2 CAS5 DQ[40:43]DQ[0:3] DQ[0:3] CAS OE W RAS U3DQ[12:15] CAS OE W RAS UB3DQ[44:47]DQ[0:3] DQ[0:3] CAS OE W RAS CAS2 DQ[16:19] CAS OE W RAS UB4 CAS6 DQ[48:51]DQ[0:3] DQ[0:3] CAS OE W RAS U5DQ[20:23] CAS OE W RAS UB5DQ[52:55]DQ[0:3] DQ[0:3] CAS OE W RAS CAS3 DQ[24:27] CAS OE W RAS UB6 CAS7 DQ[56:59]DQ[0:3] DQ[0:3] CAS OE W RAS U7DQ[28:31] CAS OE W RAS UB7DQ[60:63]DQ[0:3] DQ[0:3] TM4EP64xxN: VDD VSS Two 0.1 mF (minimum) per DRAM U[0:7], UB[0:7] U[0:7], UB[0:7] SPD EEPROM SA0 SA1 SA2 A0 A1 A2 SCL SDA † A11 is not used in TM4EP64BxN

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram for the TM4EP72xxN CAS OE W RAS RAS0 WE0 OE0 CAS0 DQ[0:3] CAS OE W RAS UB0 RAS2 WE2 OE2 CAS4 DQ[32:35]DQ[0:3] DQ[0:3] CAS OE W RAS U1DQ[4:7] CAS OE W RAS UB1DQ[36:39]DQ[0:3] DQ[0:3] CAS OE W RAS CAS1 DQ[8:11] CAS OE W RAS UB2 CAS5 DQ[40:43]DQ[0:3] DQ[0:3] CAS OE W RAS U3DQ[12:15] CAS OE W RAS UB3DQ[44:47]DQ[0:3] DQ[0:3] CAS OE W RAS CAS2 DQ[16:19] CAS OE W RAS UB4 CAS6 DQ[48:51]DQ[0:3] DQ[0:3] CAS OE W RAS U5DQ[20:23] CAS OE W RAS UB5DQ[52:55]DQ[0:3] DQ[0:3] CAS OE W RAS CAS3 DQ[24:27] CAS OE W RAS UB6 CAS7 DQ[56:59]DQ[0:3] DQ[0:3] CAS OE W RAS U7DQ[28:31] CAS OE W RAS UB7DQ[60:63]DQ[0:3] DQ[0:3] CAS OE W RAS CAS1 CB[0:3] CAS OE W RAS UB8 CAS5 CB[4:7]DQ[0:3] DQ[0:3] TM4EP72xxN: VDD VSS Two 0.1 mF (minimum) per DRAM U[0:8], UB[0:8] U[0:8], UB[0:8] SPD EEPROM SA0 SA1 SA2 A0 A1 A2 SCL SDA † A11 is not used in TM4EP72BxN

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998

6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

absolute maximum ratings over ambient temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VDD Supply voltage 3 3.3 3.6 V VSS Supply voltage 0 V VIH High-level input voltage 2 VDD + 0.3 V VIL-SPD High-level input voltage for the SPD device 2 5.5 V VIL Low-level input voltage –0.3 0.8 V TA Ambient temperature 0 70 °C

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) TM4EP64BxN PARAMETER TEST CONDITIONS † ’4EP64BxN-50 ’4EP64BxN-60 ’4EP64BxN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = – 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = – 100 mA LVCMOS VDD –0.2 VDD –0.2 VDD –0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 mA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 mA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 20 ± 20 ± 20 mA ICC1 ‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 1920 1600 1440 mA ICC2 Average standby VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 32 32 32 mA ICC2 standby current VIH = VDD – 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 16 16 16 mA ICC3 ‡§ Average refresh current (RASx-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) 1920 1600 1440 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 1760 1440 1280 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998

8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM4EP72BxN PARAMETER TEST CONDITIONS † ’4EP72BxN-50 ’4EP72BxN-60 ’4EP72BxN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = – 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = – 100 mA LVCMOS VDD –0.2 VDD –0.2 VDD –0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 mA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 mA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 20 ± 20 ± 20 mA ICC1 ‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 2160 1800 1620 mA ICC2 Average standby VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 36 36 36 mA ICC2 standby current VIH = VDD – 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 18 18 18 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) 2160 1800 1620 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 1980 1620 1440 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM4EP64CxN PARAMETER TEST CONDITIONS † ’4EP64CxN-50 ’4EP64CxN-60 ’4EP64CxN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = – 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = – 100 mA LVCMOS VDD –0.2 VDD –0.2 VDD –0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 mA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 mA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 20 ± 20 ± 20 mA ICC1 ‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 1440 1120 960 mA ICC2 Average standby VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 32 32 32 mA ICC2 standby current VIH = VDD – 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 16 16 16 mA ICC3 ‡§ Average refresh current (RASx-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) 1440 1120 960 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 1600 1440 1280 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998

10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM4EP72CxN PARAMETER TEST CONDITIONS † ’4EP72CxN-50 ’4EP72CxN-60 ’4EP72CxN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = – 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = – 100 mA LVCMOS VDD –0.2 VDD –0.2 VDD –0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 mA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 mA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 20 ± 20 ± 20 mA ICC1 ‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 1620 1260 1080 mA ICC2 Average standby VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 36 36 36 mA ICC2 standby current VIH = VDD – 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 18 18 18 mA ICC3 ‡§ Average refresh current (RASx-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) 1620 1260 1080 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 1800 1620 1440 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2) PARAMETER ’4EP64xxN ’4EP72xxN UNITPARAMETER MIN MAX MIN MAX UNIT C i(A) Input capacitance, A0–A11 82 92 pF C i(OE) Input capacitance, OEx 58 65 pF C i(CAS) Input capacitance, CASx 16 23 pF C i(RAS) Input capacitance, RASx 58 65 pF C i(W) Input capacitance, WEx 58 65 pF C o Output capacitance 8 8 pF C i/o(SDA) Input/output capacitance, SDA input 9 9 pF C i(SPD) Input capacitance, SA0, SA1, SA2, SCL inputs 7 7 pF NOTE 2: V DD = NOM supply voltage ± 10%, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 3) PARAMETER ’4EP64xxN-50 ’4EP72xxN-50 ’4EP64xxN-60 ’4EP72xxN-60 ’4EP64xxN-70 ’4EP72xxN-70 UNIT MIN MAX MIN MAX MIN MAX tAA Access time from column address (see Note 4) 25 30 35 ns tCAC Access time from CASx (see Note 4) 13 15 18 ns tCPA Access time from CASx precharge (see Note 4) 28 35 40 ns tRAC Access time from RASx (see Note 4) 50 60 70 ns tOEA Access time from OEx (see Note 4) 13 15 18 ns tCLZ Delay time, CASx to output in low impedance 0 0 0 ns tREZ Output buffer turn-off delay from RASx (see Note 5) 3 13 3 15 3 18 ns tCEZ Output buffer turn-off delay from CASx (see Note 5) 3 13 3 15 3 18 ns tOEZ Output buffer turn-off delay from OEx (see Note 5) 3 13 3 15 3 18 ns tWEZ Output buffer turn-off delay from WEx (see Note 5) 3 13 3 15 3 18 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 4. Access times are measured with output reference levels of VOH =2 V and VOL =0.8 V. 5. The maximum values of tREZ , tCEZ , tOEZ , and tWEZ are specified when the outputs are no longer driven. Data-in should not be driven until one of the applicable maximum values is satisfied.

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998

12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

EDO timing requirements (see Note 3) ’4EP64xxN-50 ’4EP72xxN-50 ’4EP64xxN-60 ’4EP72xxN-60 ’4EP64xxN-70 ’4EP72xxN-70 UNIT MIN MAX MIN MAX MIN MAX tHPC Cycle time, EDO page mode, read-write 20 25 30 ns tPRWC Cycle time, EDO read-write 57 68 78 ns tCSH Delay time, RASx active to CASx precharge 40 48 58 ns tCHO Hold time, OEx from CASx 7 10 10 ns tDOH Hold time, output from CASx 5 5 5 ns tCAS Pulse duration, CASx active 8 10000 10 10000 12 10000 ns tWPE Pulse duration, WEx active (output disable only) 7 7 7 ns tOCH Setup time, OEx before CASx 8 10 10 ns tCP Pulse duration, CASx precharge 8 10 10 ns tOEP Precharge time, OEx 5 5 5 ns NOTE 3: With ac parameters, it is assumed that tT = 2 ns.

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ac timing requirements (see Note 3) ’4EP64xxN-50 ’4EP72xxN-50 ’4EP64xxN-60 ’4EP72xxN-60 ’4EP64xxN-70 ’4EP72xxN-70 UNIT MIN MAX MIN MAX MIN MAX tRC Cycle time, random read or write 84 104 124 ns tRWC Cycle time, read-write 111 135 160 ns tRASP Pulse duration, RASx active, fast-page mode (see Note 6) 50 100 000 60 100 000 70 100 000 ns tRAS Pulse duration, RASx active, non-page mode (see Note 6) 50 10 000 60 10 000 70 10 000 ns tRP Pulse duration, RASx precharge 30 40 50 ns tWP Pulse duration, write command 8 10 10 ns tASC Setup time, column address 0 0 0 ns tASR Setup time, row address 0 0 0 ns tDS Setup time, data in (see Note 7) 0 0 0 ns tRCS Setup time, read command 0 0 0 ns tCWL Setup time, write command before CASx precharge 8 10 12 ns tRWL Setup time, write command before RASx precharge 8 10 12 ns tWCS Setup time, write command before CASx active (early-write only) 0 0 0 ns tWRP Setup time, WEx high before RASx low (CBR refresh only) 10 10 10 ns tWTS Setup time, WEx low before RASx low (test mode only) 10 10 10 ns tCSR Setup time, CASx referenced to RASx (CBR refresh only) 5 5 5 ns tCAH Hold time, column address 8 10 12 ns tDH Hold time, data in (see Note 7) 8 10 12 ns tRAH Hold time, row address 8 10 10 ns tRCH Hold time, read command referenced to CASx (see Note 8) 0 0 0 ns tRRH Hold time, read command referenced to RASx (see Note 8) 0 0 0 ns tWCH Hold time, write command during CASx active (early-write only)8 10 12 ns tROH Hold time, RASx referenced to OEx 10 10 10 ns tWRH Hold time, WEx high after RASx low (CBR refresh) 10 10 10 ns tWTH Hold time, WEx low after RASx low (test mode only) 10 10 10 ns tCHR Hold time, CASx referenced to RASx (CBR refresh only) 10 10 10 ns tOEH Hold time, OEx command 13 15 18 ns tCHS Hold time, CASx referenced to RASx (self-refresh only) – 50 – 50 – 50 ns tRHCP Hold time, RASx active from CASx precharge 28 35 40 ns tAWD Delay time, column address to write command (read-write only)42 49 57 ns tCPW Delay time, WEx low after CASx precharge (read-write only) 45 54 62 ns tCRP Delay time, CASx precharge to RASx 5 5 5 ns tCWD Delay time, CASx to write command (read-write only) 30 34 40 ns tOED Delay time, OEx to data in 13 15 18 ns tRAD Delay time, RASx to column address (see Note 9) 10 25 12 30 12 35 ns tRAL Delay time, column address to RASx precharge 25 30 35 ns tCAL Delay time, column address to CASx precharge 18 20 25 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 6. In a read-write cycle, tRWD and tRWL must be observed. 7. Referenced to the later of CASx or WEx in write operations 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. The maximum value is specified only to ensure access time.

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998

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ac timing requirements (see Note 3) (continued) ’4EP64xxN-50 ’4EP72xxN-50 ’4EP64xxN-60 ’4EP72xxN-60 ’4EP64xxN-70 ’4EP72xxN-70 UNIT MIN MAX MIN MAX MIN MAX tRCD Delay time, RASx to CASx (see Note 9) 12 37 14 45 14 52 ns tRPC Delay time, RASx precharge to CASx 0 0 0 ns tRSH Delay time, CASx active to RASx precharge 8 10 12 ns tRWD Delay time, RASx to write command (read-write only) 67 79 92 ns tTAA Access time from address (test mode) 30 35 40 ns tTCPA Access time from column precharge (test mode) 35 40 45 ns tTRAC Access time from RASx (test mode) 55 65 75 ns tREF Refresh time interval 32 32 32 ms tT Transition time 2 30 2 30 2 30 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 9. The maximum value is specified only to ensure access time.

(SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. Table 1. Serial-Presence-Detect Data for the TM4EP64BxN

1 Total number of bytes of SPD

2 Fundamental memory type

3 Number of row addresses on

4 Number of column addresses

5 Number of module banks on

6 Data width of this assembly 64 bits 40h 64 bits 40h 64 bits 40h

7 Data width continuation 00h 00h 00h

8 Voltage interface standard of

9 RASx access time of moduletRAC = 50 ns 32h tRAC = 60 ns 3Ch tRAC = 70 ns 46h

10 CASx access time of moduletRAC = 13 ns 0Dh tRAC = 15 ns 0Fh tRAC = 18 ns 12h

11 DIMM configuration type

13 DRAM width, primary DRAM x4 04h x4 04h x4 04h

14 Error-checking SDRAM data

63 Checksum for bytes 0–62 36 24h 48 30h 61 3Dh

72 Manufacturing location† TBD TBD TBD

91 Die revision code† TBD TBD TBD

92 PCB revision code† TBD TBD TBD

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Table 1. Serial-Presence-Detect Data for the TM4EP64BxN (Continued) † TBD indicates that values are determined at manufacturing time and are module-dependent. ‡ These TBD values are determined and programmed by the customer (optional).

Table 2. Serial-Presence-Detect Data for the TM4EP64CxN † TBD indicates that values are determined at manufacturing time and are module-dependent. ‡ These TBD values are determined and programmed by the customer (optional).

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Table 3. Serial-Presence-Detect Data for the TM4EP72BxN

6 Data width of this assembly 72 bits 48h 72 bits 48h 72 bits 48h

63 Checksum for bytes 0–62 50 32h 62 3Eh 75 4Bh

† TBD indicates that values are determined at manufacturing time and are module-dependent. ‡ These TBD values are determined and programmed by the customer (optional).

Table 4. Serial-Presence-Detect Data for the TM4EP72CxN † TBD indicates that values are determined at manufacturing time and are module-dependent. ‡ These TBD values are determined and programmed by the customer (optional).

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998

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device symbolization (TM4EP64BPN illustrated) -SS YYMMT YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE A: Location of symbolization may vary. Unbuffered Key Position 3.3-V Voltage Key Position TM4EP64BPN

TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES SMMS682A – AUGUST 1997– REVISED MARCH 1998 21POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA BR (R-PDIM-N168) DUAL IN-LINE MEMORY MODULE 0.118 (3,00) TYP 1.005 (25,53) 0.995 (25,27) 0.700 (17,78) TYP 0.014 (0,35) MAX 0.106 (2,70) MAX 0.054 (1,37) 0.046 (1,17) 4088180/A 07/97 0.157 (4,00) MAX (For Double Sided DIMM Only) (Note D) 5.255 (133,48) 5.245 (133,22) 0.118 (3,00) DIA

2 Places

0.125 (3,18) 0.039 (1,00) TYP Notch 0.157 (4,00) x 0.122 (3,10) Deep Notch 0.079 (2,00) x 0.122 (3,10) Deep 0.125 (3,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-161 D. Dimension includes de-panelization variations; applies between notch and tab edge. E. Outline may vary above notches to allow router/panelization irregularities.

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