TM4EP64DJN

TM2EP64DJN TI1 | Alldatasheet

Document overview

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Technical content

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Organization − TM2EP64DxN ...2 0 9 7152 × 64 Bits − TM2EP72DxN ...2 0 9 7152 × 72 Bits − TM4EP64DxN ...4 1 9 4304 × 64 Bits − TM4EP72DxN ...4 1 9 4304 × 72 Bits /C0068Single 3.3-V Power Supply (±10% Tolerance) /C0068TM2EP64DxN — Uses Eight 16M-Bit (2M ×8-Bit) Dynamic Random Access Memories (DRAMs) in Thin Small-Outline Package (TSOP), or Small-Outline J-Lead Package (SOJ) /C0068TM2EP72DxN — Uses Nine 16M-Bit (2M ×8-Bit) DRAMs in TSOP, or SOJ /C0068TM4EP64DxN — Uses 16 16M-Bit (2M ×8-Bit) DRAMs in TSOP, or SOJ /C0068TM4EP72DxN — Uses 18 16M-Bit (2M ×8-Bit) DRAMs in TSOP, or SOJ /C0068Performance ranges ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE tRAC tCAC tAA tHPC MAX MAX MAX MIN ’xEPxxDxN-50 50 ns 13 ns 25 ns 20 ns ’xEPxxDxN-60 60 ns 15 ns 30 ns 25 ns ’xEPxxDxN-70 70 ns 18 ns 35 ns 30 ns /C0068JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket /C0068High-Speed, Low-Noise LVTTL Interface /C0068Long Refresh Period: 32 ms (2 048 Cycles) /C00683-State Output /C0068Extended-Data-Out (EDO) Operation With CAS -Before-RAS (CBR), RAS-Only, and Hidden Refresh /C0068Serial Presence Detect (SPD) Using EEPROM /C0068Ambient Air Temperature Range 0°C to 70°C /C0068Gold-Plated Contacts

description

The TM2EP64DPN is a 16M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of eight TMS427809A, 2097152 byte × 8-bit 2K-refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS887). The TM2EP64DJN is available with an SOJ package (DZ suffix). The TM2EP72DPN is a 16M-byte, 168-pin DIMM. The DIMM is composed of nine TMS427809A, 2097152 byte × 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS887). The TM2EP72DJN is available with an SOJ package (DZ suffix). The TM4EP64DPN is a 32M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of sixteen TMS427809A, 2097152 × 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. The TM4EP64DJN is available with an SOJ package (DZ suffix). The TM4EP72DPN is a 32M-byte, 168-pin DIMM. The DIMM is composed of 18 TMS427809A, 2097152 × 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS887). The TM4EP72DJN is available with an SOJ package (DZ suffix). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1998, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

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The TMxEPxxDxN DIMMs operate as displayed in Table 1. Table 1. TMxEPxxDxN DIMM Device Table

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 DUAL-IN-LINE MEMORY MODULE (TOP VIEW) TM4EP72DPN (SIDE VIEW) PIN NOMENCLATURE A[0:10] Row Address Inputs A[0:9] Column Address Inputs DQ[0:63] Data In/Data Out CB[0:7] Check-Bit In/Check-Bit Out CAS[0:7] Column-Address Strobe RAS[0:3] Row-Address Strobe WE0 and WE2 Write Enable OE0 and OE2 Output Enable SA[0:2] Serial Presence Detect (SPD) Device Add Input SDA SPD Address/Data SCL SPD Clock NC No-Connect Pin VDD 3.3-V Supply VSS Ground TM2EP64DPN (SIDE VIEW)

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Pin Assignments ÁÁÁÁÁÁÁÁ PIN ÁÁÁÁÁÁÁÁ PIN ÁÁÁÁÁÁÁ PIN ÁÁÁÁÁÁÁÁ PIN ÁÁÁÁ ÁÁÁÁ NO. ÁÁÁÁÁ ÁÁÁÁÁ NAME ÁÁÁ ÁÁÁ NO. ÁÁÁÁÁÁ ÁÁÁÁÁÁ NAME ÁÁÁ ÁÁÁ NO. ÁÁÁÁÁ ÁÁÁÁÁ NAME ÁÁÁÁ ÁÁÁÁ NO. ÁÁÁÁÁ ÁÁÁÁÁ NAME ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ 127 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ0 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ OE2 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ32 ÁÁÁÁ ÁÁÁÁ 128 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ1 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ RAS2 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ33 ÁÁÁÁ ÁÁÁÁ 129 ÁÁÁÁÁ ÁÁÁÁÁ RAS3 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ2 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ CAS2 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ34 ÁÁÁÁ ÁÁÁÁ 130 ÁÁÁÁÁ ÁÁÁÁÁ CAS6 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ3 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ CAS3 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ35 ÁÁÁÁ ÁÁÁÁ 131 ÁÁÁÁÁ ÁÁÁÁÁ CAS7 ÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁÁÁÁ WE2 ÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ 132 ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ4 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ36 ÁÁÁÁ ÁÁÁÁ 133 ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ5 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ37 ÁÁÁÁ ÁÁÁÁ 134 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ6 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ38 ÁÁÁÁ ÁÁÁÁ 135 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ7 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ CB2 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ39 ÁÁÁÁ ÁÁÁÁ 136 ÁÁÁÁÁ ÁÁÁÁÁ CB6 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ8 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ CB3 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ40 ÁÁÁÁ ÁÁÁÁ 137 ÁÁÁÁÁ ÁÁÁÁÁ CB7 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ 138 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ9 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ16 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ41 ÁÁÁÁ ÁÁÁÁ 139 ÁÁÁÁÁ ÁÁÁÁÁ DQ48 ÁÁÁÁ ÁÁÁÁÁ DQ10 ÁÁÁ ÁÁÁÁÁÁ DQ17 ÁÁÁ ÁÁÁÁÁ DQ42 ÁÁÁÁ 140 ÁÁÁÁÁ DQ49 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ11 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ18 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ43 ÁÁÁÁ ÁÁÁÁ 141 ÁÁÁÁÁ ÁÁÁÁÁ DQ50 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ12 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ19 ÁÁÁ ÁÁÁ 100 ÁÁÁÁÁ ÁÁÁÁÁ DQ44 ÁÁÁÁ ÁÁÁÁ 142 ÁÁÁÁÁ ÁÁÁÁÁ DQ51 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ13 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ 101 ÁÁÁÁÁ ÁÁÁÁÁ DQ45 ÁÁÁÁ ÁÁÁÁ 143 ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ20 ÁÁÁ ÁÁÁ 102 ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ 144 ÁÁÁÁÁ ÁÁÁÁÁ DQ52 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ14 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 103 ÁÁÁÁÁ ÁÁÁÁÁ DQ46 ÁÁÁÁ ÁÁÁÁ 145 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ15 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 104 ÁÁÁÁÁ ÁÁÁÁÁ DQ47 ÁÁÁÁ ÁÁÁÁ 146 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CB0 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 105 ÁÁÁÁÁ ÁÁÁÁÁ CB4 ÁÁÁÁ ÁÁÁÁ 147 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CB1 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 106 ÁÁÁÁÁ ÁÁÁÁÁ CB5 ÁÁÁÁ ÁÁÁÁ 148 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁÁÁÁ DQ21 ÁÁÁ 107 ÁÁÁÁÁ VSS ÁÁÁÁ 149 ÁÁÁÁÁ DQ53 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ22 ÁÁÁ ÁÁÁ 108 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 150 ÁÁÁÁÁ ÁÁÁÁÁ DQ54 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ23 ÁÁÁ ÁÁÁ 109 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 151 ÁÁÁÁÁ ÁÁÁÁÁ DQ55 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 110 ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ 152 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ WE0 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ24 ÁÁÁ ÁÁÁ 111 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 153 ÁÁÁÁÁ ÁÁÁÁÁ DQ56 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CAS0 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ25 ÁÁÁ ÁÁÁ 112 ÁÁÁÁÁ ÁÁÁÁÁ CAS4 ÁÁÁÁ ÁÁÁÁ 154 ÁÁÁÁÁ ÁÁÁÁÁ DQ57 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CAS1 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ26 ÁÁÁ ÁÁÁ 113 ÁÁÁÁÁ ÁÁÁÁÁ CAS5 ÁÁÁÁ ÁÁÁÁ 155 ÁÁÁÁÁ ÁÁÁÁÁ DQ58 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ RAS0 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ27 ÁÁÁ ÁÁÁ 114 ÁÁÁÁÁ ÁÁÁÁÁ RAS1 ÁÁÁÁ ÁÁÁÁ 156 ÁÁÁÁÁ ÁÁÁÁÁ DQ59 ÁÁÁÁ ÁÁÁÁÁ OE0 ÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ 115 ÁÁÁÁÁ NC ÁÁÁÁ 157 ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ28 ÁÁÁ ÁÁÁ 116 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ 158 ÁÁÁÁÁ ÁÁÁÁÁ DQ60 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ29 ÁÁÁ ÁÁÁ 117 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 159 ÁÁÁÁÁ ÁÁÁÁÁ DQ61 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ30 ÁÁÁ ÁÁÁ 118 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 160 ÁÁÁÁÁ ÁÁÁÁÁ DQ62 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ31 ÁÁÁ ÁÁÁ 119 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 161 ÁÁÁÁÁ ÁÁÁÁÁ DQ63 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 120 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 162 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 121 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 163 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ A10 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 122 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 164 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 123 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 165 ÁÁÁÁÁ ÁÁÁÁÁ SA0 ÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁÁÁÁ SDA ÁÁÁ 124 ÁÁÁÁÁ VDD ÁÁÁÁ 166 ÁÁÁÁÁ SA1 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ SCL ÁÁÁ ÁÁÁ 125 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 167 ÁÁÁÁÁ ÁÁÁÁÁ SA2 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ 126 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 168 ÁÁÁÁÁ ÁÁÁÁÁ VDD

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 dual-in-line memory module and components The dual-in-line memory module and components include: /C0068PC substrate: 1,27 /C0034 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage /C0068Bypass capacitors: Multilayer ceramic /C0068Contact area: Nickel plate and gold plate over copper

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block diagram The following table shows the four DIMM modules and locations (Ux/UBx) that are used. COMPONENT TABLE MODULE LOCATIONS USED TM2EP64DxN U[0:7] TM2EP72DxN U[0:8] TM4EP64DxN U[0:7], UB[0:7] TM4EP72DxN U[0:8], UB[0:8] CAS OE W RAS RAS0 WE0 OE0 CAS0 DQ[0:7] CAS OE W RAS CAS1 DQ[8:15] CAS OE W RAS CAS1 CB[0:7] CAS OE W RAS CAS2 DQ[16:23] CAS OE W RAS RAS2 WE2 OE2 CAS4 DQ[32:39] CAS OE W RAS CAS5 DQ[40:47] CAS OE W RAS CAS6 DQ[48:55] CAS OE W RAS CAS7 DQ[56:63] A0 A1 SCL SA0 SA1 SPD EEPROM CAS OE W RAS CAS3 DQ[24:31] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] CAS OE W RAS UB0 RAS1 WE0 OE0 CAS OE W RAS UB1 CAS OE W RAS UB8 CAS OE W RAS UB2 CAS OE W RAS UB3 DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] CAS OE W RAS UB4 RAS3 WE2 OE2 CAS OE W RAS UB5 CAS OE W RAS UB6 CAS OE W RAS UB7 DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] SA2 SDA VDD VSS Two 0.1 µF (minimum) per DRAM U[0:8], UB[0:8] U[0:8], UB[0:8] Legend: SPD = Serial Presence Detect

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over ambient temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ MIN ÁÁÁ ÁÁÁ NOM ÁÁÁÁ ÁÁÁÁ MAX ÁÁÁ ÁÁÁ UNIT ÁÁÁÁ ÁÁÁÁ VDD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 3.3 ÁÁÁÁ ÁÁÁÁ 3.6 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VSS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ V ÁÁÁÁ VIH ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ High-level input voltage ÁÁÁ ÁÁÁ ÁÁÁÁ VDD + 0.3 ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VIH−SPD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ High-level input voltage for the SPD device ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 5.5 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VIL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Low-level input voltage ÁÁÁ ÁÁÁ −0.3 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 0.8 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ TA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Ambient temperature ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2) PARAMETER ’2EP64DxN ’2EP72DxN ’4EP64DxN ’4EP72DxN UNITPARAMETER MIN MAX MIN MAX MIN MAX MIN MAX UNIT C i(A) Input capacitance, A0−A10 42 47 82 92 pF C i(OE) Input capacitance, OEx 30 37 58 72 pF C i(CAS) Input capacitance, CASx 9 16 16 30 pF C i(RAS) Input capacitance, RASx 30 37 30 37 pF C i(W) Input capacitance, WEx 30 37 38 37 pF C o Output capacitance 9 9 16 16 pF C i/o(SDA) Input/output capacitance, SDA input 9 9 9 9 pF C i(SPD) Input capacitance, SA0,SA1,SA2,SCL inputs 7 7 7 7 pF NOTE 2: V DD = NOM supply voltage ±10%, and the bias on pins under test is 0 V.

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) TM2EP64DxN PARAMETER TEST CONDITIONS † ’2EP64DxN-50 ’2EP64DxN-60 ’2EP64DxN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 10 ± 10 ± 10 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 10 ± 10 ± 10 µA ICC1 ‡§ Read- or write-cycle current VDD = 3.6 V, Minimum cycle 960 800 720 mA Standby VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 16 16 16 mA ICC2 Standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 8 8 8 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RASx low after CASx low (CBR) 960 800 720 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 880 720 640 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM2EP72DxN PARAMETER TEST CONDITIONS † ’2EP72DxN-50 ’2EP72DxN-60 ’2EP72DxN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 10 ± 10 ± 10 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 10 ± 10 ± 10 µA ICC1 ‡§ Read- or write-cycle current VDD = 3.6 V, Minimum cycle 976 816 736 mA Standby VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 18 18 18 mA ICC2 Standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 9 9 9 mA ICC3 ‡§ Average refresh current (RASx-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RASx low after CASx low (CBR) 976 816 736 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 990 810 720 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM4EP64DxN PARAMETER TEST CONDITIONS † ’4EP64DxN-50 ’4EP64DxN-60 ’4EP64DxN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 20 ± 20 ± 20 µA ICC1 ‡§ Read- or write-cycle current VDD = 3.6 V, Minimum cycle 976 816 736 mA Standby VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 32 32 32 mA ICC2 Standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 16 16 16 mA ICC3 ‡§ Average refresh current (RASx-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RASx low after CASx low (CBR) 976 816 736 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 896 736 656 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM4EP72DxN PARAMETER TEST CONDITIONS † ’4EP72DxN-50 ’4EP72DxN-60 ’4EP72DxN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 20 ± 20 ± 20 µA ICC1 ‡§ Read- or write-cycle current VDD = 3.6 V, Minimum cycle 1098 918 828 mA Standby VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 36 36 36 mA ICC2 Standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 18 18 18 mA ICC3 ‡§ Average refresh current (RASx-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RASx low after CASx low (CBR) 1098 918 828 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 1008 828 738 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 3) PARAMETER ’xEP64DxN-50 ’xEP72DxN-50 ’xEP64DxN-60 ’xEP72DxN-60 ’xEP64DxN-70 ’xEP72DxN-70 UNITPARAMETER MIN MAX MIN MAX MIN MAX UNIT tAA Access time from column address (see Note 4) 25 30 35 ns tCAC Access time from CASx (see Note 4) 13 15 18 ns tCPA Access time from CASx precharge (see Note 4) 28 35 40 ns tRAC Access time from RASx (see Note 4) 50 60 70 ns tOEA Access time from OEx (see Note 4) 13 15 18 ns tCLZ Delay time, CASx to output in low impedance 0 0 0 ns tREZ Output buffer turn off delay from RASx (see Note 5) 3 13 3 15 3 18 ns tCEZ Output buffer turn off delay from CASx (see Note 5) 3 13 3 15 3 18 ns tOEZ Output buffer turn off delay from OEx (see Note 5) 3 13 3 15 3 18 ns tWEZ Output buffer turn off delay from WEx (see Note 5) 3 13 3 15 3 18 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 4. Access times are measured with output reference levels of VOH =2 V and VOL =0.8 V. 5. The maximum values of tREZ , tCEZ , tOEZ , and tWEZ are specified when the outputs are no longer driven. Data-in should not be driven until one of the applicable maximum values is satisfied. EDO timing requirements (see Note 3) ’xEP64DxN-50 ’xEP72DxN-50 ’xEP64DxN-60 ’xEP72DxN-60 ’xEP64DxN-70 ’xEP72DxN-70 UNIT MIN MAX MIN MAX MIN MAX UNIT tHPC Cycle time, EDO page mode, read-write 20 25 30 ns tPRWC Cycle time, EDO read-write 57 68 78 ns tCSH Delay time, RASx active to CASx precharge 40 48 58 ns tCHO Hold time, OEx from CASx 7 10 10 ns tDOH Hold time, output from CASx 5 5 5 ns tOEP Precharge time, OEx 5 5 5 ns tCAS Pulse duration, CASx active 8 10000 10 10000 12 10000 ns tWPE Pulse duration, WEx active (output disable only) 7 7 7 ns tCP Pulse duration, CASx precharge 8 10 10 ns tOCH Setup time, OEx before CASx 8 10 10 ns tOEP Precharge time, OEx 5 5 5 ns NOTE 3: With ac parameters, it is assumed that tT = 2 ns.

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ac timing requirements ’xEP64DxN-50 ’xEP72DxN-50 ’xEP64DxN-60 ’xEP72DxN-60 ’xEP64DxN-70 ’xEP72DxN-70 UNIT MIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, random read or write 84 104 124 ns tRWC Cycle time, read-write 111 135 160 ns tRASP Pulse duration, RASx active, fast page mode (see Note 6)50 100 000 60 100 000 70 100 000 ns tRAS Pulse duration, RASx active, non-page mode (see Note 6) 50 10 000 60 10 000 70 10 000 ns tRP Pulse duration, RASx precharge 30 40 50 ns tWP Pulse duration, write command 8 10 10 ns tRASS Pulse duration, RASx active, self refresh (see Note 7) 100 100 100 /C0109s tRPS Pulse duration, RASx precharge after self refresh 90 110 130 ns tASC Setup time, column address 0 0 0 ns tASR Setup time, row address 0 0 0 ns tDS Setup time, data in (see Note 8) 0 0 0 ns tRCS Setup time, read command 0 0 0 ns tCWL Setup time, write command before CASx precharge 8 10 12 ns tRWL Setup time, write command before RASx precharge 8 10 12 ns tWCS Setup time, write command before CASx active (early-write only) 0 0 0 ns tWRP Setup time, WEx high before RASx low (CBR refresh only) 10 10 10 ns tCSR Setup time, CASx referenced to RASx (CBR refresh only) 5 5 5 ns tCAH Hold time, column address 8 10 12 ns tDH Hold time, data in (see Note 8) 8 10 12 ns tRAH Hold time, row address 8 10 10 ns tRCH Hold time, read command referenced to CASx (see Note 9) 0 0 0 ns tRRH Hold time, read command referenced to RASx (see Note 9) 0 0 0 ns tWCH Hold time, write command during CASx active (early-write only) 8 10 12 ns tROH Hold time, RASx referenced to OEx 8 10 10 ns tWRH Hold time, WEx high after RASx low (CBR refresh only) 10 10 10 ns tCHR Hold time, CASx referenced to RASx (CBR refresh only) 10 10 10 ns tOEH Hold time, OEx command 13 15 18 ns tRHCP Hold time, RASx active from CASx precharge 28 35 40 ns tCHS Hold time, CASx referenced to RASx (self refresh only) − 50 − 50 − 50 ns tAWD Delay time, column address to write command (read-write only) 42 49 57 ns tCRP Delay time, CASx precharge to RASx 5 5 5 ns NOTES: 6. In a read-write cycle, tRWD and tRWL must be observed. 7. During the period of 10 µs ≤ tRASS ≤100 µs, the device is in a transition state from normal-operation mode to self-refresh mode. 8. Referenced to the later of CASx or WEx in write operations 9. Either tRRH or tRCH must be satisfied for a read cycle.

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ac timing requirements (continued) ’xEP64DxN-50 ’xEP72DxN-50 ’xEP64DxN-60 ’xEP72DxN-60 ’xEP64DxN-70 ’xEP72DxN-70 UNIT MIN MAX MIN MAX MIN MAX UNIT tCWD Delay time, CASx to write command (read-write only) 30 34 40 ns tOED Delay time, OEx to data in 13 15 18 ns tRAD Delay time, RASx to column address (see Note 10) 10 25 12 30 12 35 ns tRAL Delay time, column address to RASx precharge 25 30 35 ns tCAL Delay time, column address to CASx precharge 18 20 25 ns tRCD Delay time, RASx to CASx (see Note 10) 12 37 14 45 14 52 ns tRPC Delay time, RASx precharge to CASx 5 5 5 ns tRSH Delay time, CASx active to RASx precharge 8 10 12 ns tRWD Delay time, RASx to write command (read-write only) 67 79 92 ns tCPW Delay time, CASx precharge to write command (read-write only) 45 54 62 ns tREF Refresh time interval 32 32 32 ms tT Transition time 2 30 2 30 2 30 ns NOTE 10: The maximum value is specified only to ensure access time.

(SCL) and data (SDA) signals. All Texas Instruments module comply with the current JEDEC SPD Standard. Table 2. Serial Presence Detect Data for the TM2EP64DxN

1 Total number of bytes of SPD

2 Fundamental memory type (FPM,

3 Number of row addresses on this

4 Number of column addresses on

5 Number of module banks on this

6 Data width of this assembly 64 bits 40h 64 bits 40h 64 bits 40h

7 Data width continuation 00h 00h 00h

8 Voltage interface standard of this

9 RASx access time of module tRAC = 50 ns 32h tRAC = 60 ns 3Ch tRAC = 70 ns 46h

10 CASx access time of module tCAC = 13 ns 0Dh tCAC = 15 ns 0Fh tCAC = 18 ns 12h

11 DIMM configuration type

13 DRAM width, primary DRAM x8 08h x8 08h x8 08h

14 Error-checking SDRAM data width N/A 00h N/A 00h N/A 00h

63 Checksum for bytes 0−62 41 29h 53 35h 66 42h

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 2. Serial Presence Detect Data for the TM2EP64DxN (Continued)

72 Manufacturing location† TBD TBD TBD

91 Die revision code† TBD TBD TBD

92 PCB revision code† TBD TBD TBD

† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).

Table 3. Serial Presence Detect Data for the TM2EP72DxN

6 Data width of this assembly 72 bits 48h 72 bits 48h 72 bits 48h

14 Error-checking SDRAM data width x8 08h x8 08h x8 08h

63 Checksum for bytes 0−62 59 3Bh 71 47h 84 54h

† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 4. Serial Presence Detect Data for the TM4EP64DxN

63 Checksum for bytes 0−62 42 2Ah 54 36h 67 43h

† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).

Table 5. Serial Presence Detect for the TM4EP72DxN

63 Checksum for bytes 0−62 60 3Ch 72 48h 85 55h

† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device symbolization (TM4EP64DPN illustrated) TM4EP64DPN -SS YYMMT YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE A: Location of symbolization may vary. Unbuffered Key Position 3.3-V Voltage Key Position

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MECHANICAL DATA BR (R-PDIM-N168) DUAL IN-LINE MEMORY MODULE 0.118 (3,00) TYP 1.005 (25,53) 0.995 (25,27) 0.700 (17,78) TYP 0.014 (0,35) MAX 0.106 (2,70) MAX 0.054 (1,37) 0.046 (1,17) 4088180/A 07/97 0.157 (4,00) MAX (For Double Sided DIMM Only) (Note D) 5.255 (133,48) 5.245 (133,22) 0.118 (3,00) DIA

2 Places

0.125 (3,18) 0.039 (1,00) TYP Notch 0.157 (4,00) x 0.122 (3,10) Deep Notch 0.079 (2,00) x 0.122 (3,10) Deep 0.125 (3,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-161 D. Dimension includes de-panelization variations; applies between notch and tab edge. E. Outline may vary above notches to allow router/panelization irregularities.

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Organization − TM2EP64DxN ...2 0 9 7152 × 64 Bits − TM2EP72DxN ...2 0 9 7152 × 72 Bits − TM4EP64DxN ...4 1 9 4304 × 64 Bits − TM4EP72DxN ...4 1 9 4304 × 72 Bits /C0068Single 3.3-V Power Supply (±10% Tolerance) /C0068TM2EP64DxN — Uses Eight 16M-Bit (2M ×8-Bit) Dynamic Random Access Memories (DRAMs) in Thin Small-Outline Package (TSOP), or Small-Outline J-Lead Package (SOJ) /C0068TM2EP72DxN — Uses Nine 16M-Bit (2M ×8-Bit) DRAMs in TSOP, or SOJ /C0068TM4EP64DxN — Uses 16 16M-Bit (2M ×8-Bit) DRAMs in TSOP, or SOJ /C0068TM4EP72DxN — Uses 18 16M-Bit (2M ×8-Bit) DRAMs in TSOP, or SOJ /C0068Performance ranges ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE tRAC tCAC tAA tHPC MAX MAX MAX MIN ’xEPxxDxN-50 50 ns 13 ns 25 ns 20 ns ’xEPxxDxN-60 60 ns 15 ns 30 ns 25 ns ’xEPxxDxN-70 70 ns 18 ns 35 ns 30 ns /C0068JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket /C0068High-Speed, Low-Noise LVTTL Interface /C0068Long Refresh Period: 32 ms (2 048 Cycles) /C00683-State Output /C0068Extended-Data-Out (EDO) Operation With CAS -Before-RAS (CBR), RAS-Only, and Hidden Refresh /C0068Serial Presence Detect (SPD) Using EEPROM /C0068Ambient Air Temperature Range 0°C to 70°C /C0068Gold-Plated Contacts The TM2EP64DPN is a 16M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of eight TMS427809A, 2097152 byte × 8-bit 2K-refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS887). The TM2EP64DJN is available with an SOJ package (DZ suffix). The TM2EP72DPN is a 16M-byte, 168-pin DIMM. The DIMM is composed of nine TMS427809A, 2097152 byte × 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS887). The TM2EP72DJN is available with an SOJ package (DZ suffix). The TM4EP64DPN is a 32M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of sixteen TMS427809A, 2097152 × 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. The TM4EP64DJN is available with an SOJ package (DZ suffix). The TM4EP72DPN is a 32M-byte, 168-pin DIMM. The DIMM is composed of 18 TMS427809A, 2097152 × 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS887). The TM4EP72DJN is available with an SOJ package (DZ suffix). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1998, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The TMxEPxxDxN DIMMs operate as displayed in Table 1.

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 DUAL-IN-LINE MEMORY MODULE (TOP VIEW) TM4EP72DPN (SIDE VIEW) PIN NOMENCLATURE A[0:10] Row Address Inputs A[0:9] Column Address Inputs DQ[0:63] Data In/Data Out CB[0:7] Check-Bit In/Check-Bit Out CAS[0:7] Column-Address Strobe RAS[0:3] Row-Address Strobe WE0 and WE2 Write Enable OE0 and OE2 Output Enable SA[0:2] Serial Presence Detect (SPD) Device Add Input SDA SPD Address/Data SCL SPD Clock NC No-Connect Pin VDD 3.3-V Supply VSS Ground TM2EP64DPN (SIDE VIEW)

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Pin Assignments ÁÁÁÁÁÁÁÁ PIN ÁÁÁÁÁÁÁÁ PIN ÁÁÁÁÁÁÁ PIN ÁÁÁÁÁÁÁÁ PIN ÁÁÁÁ ÁÁÁÁ NO. ÁÁÁÁÁ ÁÁÁÁÁ NAME ÁÁÁ ÁÁÁ NO. ÁÁÁÁÁÁ ÁÁÁÁÁÁ NAME ÁÁÁ ÁÁÁ NO. ÁÁÁÁÁ ÁÁÁÁÁ NAME ÁÁÁÁ ÁÁÁÁ NO. ÁÁÁÁÁ ÁÁÁÁÁ NAME ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ 127 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ0 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ OE2 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ32 ÁÁÁÁ ÁÁÁÁ 128 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ1 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ RAS2 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ33 ÁÁÁÁ ÁÁÁÁ 129 ÁÁÁÁÁ ÁÁÁÁÁ RAS3 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ2 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ CAS2 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ34 ÁÁÁÁ ÁÁÁÁ 130 ÁÁÁÁÁ ÁÁÁÁÁ CAS6 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ3 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ CAS3 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ35 ÁÁÁÁ ÁÁÁÁ 131 ÁÁÁÁÁ ÁÁÁÁÁ CAS7 ÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁÁÁÁ WE2 ÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ 132 ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ4 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ36 ÁÁÁÁ ÁÁÁÁ 133 ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ5 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ37 ÁÁÁÁ ÁÁÁÁ 134 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ6 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ38 ÁÁÁÁ ÁÁÁÁ 135 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ7 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ CB2 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ39 ÁÁÁÁ ÁÁÁÁ 136 ÁÁÁÁÁ ÁÁÁÁÁ CB6 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ8 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ CB3 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ40 ÁÁÁÁ ÁÁÁÁ 137 ÁÁÁÁÁ ÁÁÁÁÁ CB7 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ 138 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ9 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ16 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ41 ÁÁÁÁ ÁÁÁÁ 139 ÁÁÁÁÁ ÁÁÁÁÁ DQ48 ÁÁÁÁ ÁÁÁÁÁ DQ10 ÁÁÁ ÁÁÁÁÁÁ DQ17 ÁÁÁ ÁÁÁÁÁ DQ42 ÁÁÁÁ 140 ÁÁÁÁÁ DQ49 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ11 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ18 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ43 ÁÁÁÁ ÁÁÁÁ 141 ÁÁÁÁÁ ÁÁÁÁÁ DQ50 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ12 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ19 ÁÁÁ ÁÁÁ 100 ÁÁÁÁÁ ÁÁÁÁÁ DQ44 ÁÁÁÁ ÁÁÁÁ 142 ÁÁÁÁÁ ÁÁÁÁÁ DQ51 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ13 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ 101 ÁÁÁÁÁ ÁÁÁÁÁ DQ45 ÁÁÁÁ ÁÁÁÁ 143 ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ20 ÁÁÁ ÁÁÁ 102 ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ 144 ÁÁÁÁÁ ÁÁÁÁÁ DQ52 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ14 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 103 ÁÁÁÁÁ ÁÁÁÁÁ DQ46 ÁÁÁÁ ÁÁÁÁ 145 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ15 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 104 ÁÁÁÁÁ ÁÁÁÁÁ DQ47 ÁÁÁÁ ÁÁÁÁ 146 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CB0 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 105 ÁÁÁÁÁ ÁÁÁÁÁ CB4 ÁÁÁÁ ÁÁÁÁ 147 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CB1 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 106 ÁÁÁÁÁ ÁÁÁÁÁ CB5 ÁÁÁÁ ÁÁÁÁ 148 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁÁÁÁ DQ21 ÁÁÁ 107 ÁÁÁÁÁ VSS ÁÁÁÁ 149 ÁÁÁÁÁ DQ53 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ22 ÁÁÁ ÁÁÁ 108 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 150 ÁÁÁÁÁ ÁÁÁÁÁ DQ54 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ23 ÁÁÁ ÁÁÁ 109 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 151 ÁÁÁÁÁ ÁÁÁÁÁ DQ55 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 110 ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ 152 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ WE0 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ24 ÁÁÁ ÁÁÁ 111 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 153 ÁÁÁÁÁ ÁÁÁÁÁ DQ56 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CAS0 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ25 ÁÁÁ ÁÁÁ 112 ÁÁÁÁÁ ÁÁÁÁÁ CAS4 ÁÁÁÁ ÁÁÁÁ 154 ÁÁÁÁÁ ÁÁÁÁÁ DQ57 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CAS1 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ26 ÁÁÁ ÁÁÁ 113 ÁÁÁÁÁ ÁÁÁÁÁ CAS5 ÁÁÁÁ ÁÁÁÁ 155 ÁÁÁÁÁ ÁÁÁÁÁ DQ58 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ RAS0 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ27 ÁÁÁ ÁÁÁ 114 ÁÁÁÁÁ ÁÁÁÁÁ RAS1 ÁÁÁÁ ÁÁÁÁ 156 ÁÁÁÁÁ ÁÁÁÁÁ DQ59 ÁÁÁÁ ÁÁÁÁÁ OE0 ÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ 115 ÁÁÁÁÁ NC ÁÁÁÁ 157 ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ28 ÁÁÁ ÁÁÁ 116 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ 158 ÁÁÁÁÁ ÁÁÁÁÁ DQ60 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ29 ÁÁÁ ÁÁÁ 117 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 159 ÁÁÁÁÁ ÁÁÁÁÁ DQ61 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ30 ÁÁÁ ÁÁÁ 118 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 160 ÁÁÁÁÁ ÁÁÁÁÁ DQ62 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ31 ÁÁÁ ÁÁÁ 119 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 161 ÁÁÁÁÁ ÁÁÁÁÁ DQ63 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 120 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 162 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 121 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 163 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ A10 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 122 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 164 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 123 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 165 ÁÁÁÁÁ ÁÁÁÁÁ SA0 ÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁÁÁÁ SDA ÁÁÁ 124 ÁÁÁÁÁ VDD ÁÁÁÁ 166 ÁÁÁÁÁ SA1 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ SCL ÁÁÁ ÁÁÁ 125 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 167 ÁÁÁÁÁ ÁÁÁÁÁ SA2 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ 126 ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 168 ÁÁÁÁÁ ÁÁÁÁÁ VDD

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 dual-in-line memory module and components The dual-in-line memory module and components include: /C0068PC substrate: 1,27 /C0034 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage /C0068Bypass capacitors: Multilayer ceramic /C0068Contact area: Nickel plate and gold plate over copper

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block diagram The following table shows the four DIMM modules and locations (Ux/UBx) that are used. COMPONENT TABLE MODULE LOCATIONS USED TM2EP64DxN U[0:7] TM2EP72DxN U[0:8] TM4EP64DxN U[0:7], UB[0:7] TM4EP72DxN U[0:8], UB[0:8] CAS OE W RAS RAS0 WE0 OE0 CAS0 DQ[0:7] CAS OE W RAS CAS1 DQ[8:15] CAS OE W RAS CAS1 CB[0:7] CAS OE W RAS CAS2 DQ[16:23] CAS OE W RAS RAS2 WE2 OE2 CAS4 DQ[32:39] CAS OE W RAS CAS5 DQ[40:47] CAS OE W RAS CAS6 DQ[48:55] CAS OE W RAS CAS7 DQ[56:63] A0 A1 SCL SA0 SA1 SPD EEPROM CAS OE W RAS CAS3 DQ[24:31] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] CAS OE W RAS UB0 RAS1 WE0 OE0 CAS OE W RAS UB1 CAS OE W RAS UB8 CAS OE W RAS UB2 CAS OE W RAS UB3 DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] CAS OE W RAS UB4 RAS3 WE2 OE2 CAS OE W RAS UB5 CAS OE W RAS UB6 CAS OE W RAS UB7 DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] SA2 SDA VDD VSS Two 0.1 µF (minimum) per DRAM U[0:8], UB[0:8] U[0:8], UB[0:8] Legend: SPD = Serial Presence Detect

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 29POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over ambient temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ MIN ÁÁÁ ÁÁÁ NOM ÁÁÁÁ ÁÁÁÁ MAX ÁÁÁ ÁÁÁ UNIT ÁÁÁÁ ÁÁÁÁ VDD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 3.3 ÁÁÁÁ ÁÁÁÁ 3.6 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VSS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ V ÁÁÁÁ VIH ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ High-level input voltage ÁÁÁ ÁÁÁ ÁÁÁÁ VDD + 0.3 ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VIH−SPD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ High-level input voltage for the SPD device ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 5.5 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VIL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Low-level input voltage ÁÁÁ ÁÁÁ −0.3 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 0.8 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ TA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Ambient temperature ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2) PARAMETER ’2EP64DxN ’2EP72DxN ’4EP64DxN ’4EP72DxN UNITPARAMETER MIN MAX MIN MAX MIN MAX MIN MAX UNIT C i(A) Input capacitance, A0−A10 42 47 82 92 pF C i(OE) Input capacitance, OEx 30 37 58 72 pF C i(CAS) Input capacitance, CASx 9 16 16 30 pF C i(RAS) Input capacitance, RASx 30 37 30 37 pF C i(W) Input capacitance, WEx 30 37 38 37 pF C o Output capacitance 9 9 16 16 pF C i/o(SDA) Input/output capacitance, SDA input 9 9 9 9 pF C i(SPD) Input capacitance, SA0,SA1,SA2,SCL inputs 7 7 7 7 pF NOTE 2: V DD = NOM supply voltage ±10%, and the bias on pins under test is 0 V.

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) TM2EP64DxN PARAMETER TEST CONDITIONS † ’2EP64DxN-50 ’2EP64DxN-60 ’2EP64DxN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 10 ± 10 ± 10 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 10 ± 10 ± 10 µA ICC1 ‡§ Read- or write-cycle current VDD = 3.6 V, Minimum cycle 960 800 720 mA Standby VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 16 16 16 mA ICC2 Standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 8 8 8 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RASx low after CASx low (CBR) 960 800 720 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 880 720 640 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM2EP72DxN PARAMETER TEST CONDITIONS † ’2EP72DxN-50 ’2EP72DxN-60 ’2EP72DxN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 10 ± 10 ± 10 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 10 ± 10 ± 10 µA ICC1 ‡§ Read- or write-cycle current VDD = 3.6 V, Minimum cycle 976 816 736 mA Standby VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 18 18 18 mA ICC2 Standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 9 9 9 mA ICC3 ‡§ Average refresh current (RASx-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RASx low after CASx low (CBR) 976 816 736 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 990 810 720 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM4EP64DxN PARAMETER TEST CONDITIONS † ’4EP64DxN-50 ’4EP64DxN-60 ’4EP64DxN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 20 ± 20 ± 20 µA ICC1 ‡§ Read- or write-cycle current VDD = 3.6 V, Minimum cycle 976 816 736 mA Standby VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 32 32 32 mA ICC2 Standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 16 16 16 mA ICC3 ‡§ Average refresh current (RASx-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RASx low after CASx low (CBR) 976 816 736 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 896 736 656 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 33POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM4EP72DxN PARAMETER TEST CONDITIONS † ’4EP72DxN-50 ’4EP72DxN-60 ’4EP72DxN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 20 ± 20 ± 20 µA ICC1 ‡§ Read- or write-cycle current VDD = 3.6 V, Minimum cycle 1098 918 828 mA Standby VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 36 36 36 mA ICC2 Standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 18 18 18 mA ICC3 ‡§ Average refresh current (RASx-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RASx low after CASx low (CBR) 1098 918 828 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 1008 828 738 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 3) PARAMETER ’xEP64DxN-50 ’xEP72DxN-50 ’xEP64DxN-60 ’xEP72DxN-60 ’xEP64DxN-70 ’xEP72DxN-70 UNITPARAMETER MIN MAX MIN MAX MIN MAX UNIT tAA Access time from column address (see Note 4) 25 30 35 ns tCAC Access time from CASx (see Note 4) 13 15 18 ns tCPA Access time from CASx precharge (see Note 4) 28 35 40 ns tRAC Access time from RASx (see Note 4) 50 60 70 ns tOEA Access time from OEx (see Note 4) 13 15 18 ns tCLZ Delay time, CASx to output in low impedance 0 0 0 ns tREZ Output buffer turn off delay from RASx (see Note 5) 3 13 3 15 3 18 ns tCEZ Output buffer turn off delay from CASx (see Note 5) 3 13 3 15 3 18 ns tOEZ Output buffer turn off delay from OEx (see Note 5) 3 13 3 15 3 18 ns tWEZ Output buffer turn off delay from WEx (see Note 5) 3 13 3 15 3 18 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 4. Access times are measured with output reference levels of VOH =2 V and VOL =0.8 V. 5. The maximum values of tREZ , tCEZ , tOEZ , and tWEZ are specified when the outputs are no longer driven. Data-in should not be driven until one of the applicable maximum values is satisfied. EDO timing requirements (see Note 3) ’xEP64DxN-50 ’xEP72DxN-50 ’xEP64DxN-60 ’xEP72DxN-60 ’xEP64DxN-70 ’xEP72DxN-70 UNIT MIN MAX MIN MAX MIN MAX UNIT tHPC Cycle time, EDO page mode, read-write 20 25 30 ns tPRWC Cycle time, EDO read-write 57 68 78 ns tCSH Delay time, RASx active to CASx precharge 40 48 58 ns tCHO Hold time, OEx from CASx 7 10 10 ns tDOH Hold time, output from CASx 5 5 5 ns tOEP Precharge time, OEx 5 5 5 ns tCAS Pulse duration, CASx active 8 10000 10 10000 12 10000 ns tWPE Pulse duration, WEx active (output disable only) 7 7 7 ns tCP Pulse duration, CASx precharge 8 10 10 ns tOCH Setup time, OEx before CASx 8 10 10 ns tOEP Precharge time, OEx 5 5 5 ns NOTE 3: With ac parameters, it is assumed that tT = 2 ns.

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 35POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ac timing requirements ’xEP64DxN-50 ’xEP72DxN-50 ’xEP64DxN-60 ’xEP72DxN-60 ’xEP64DxN-70 ’xEP72DxN-70 UNIT MIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, random read or write 84 104 124 ns tRWC Cycle time, read-write 111 135 160 ns tRASP Pulse duration, RASx active, fast page mode (see Note 6)50 100 000 60 100 000 70 100 000 ns tRAS Pulse duration, RASx active, non-page mode (see Note 6) 50 10 000 60 10 000 70 10 000 ns tRP Pulse duration, RASx precharge 30 40 50 ns tWP Pulse duration, write command 8 10 10 ns tRASS Pulse duration, RASx active, self refresh (see Note 7) 100 100 100 /C0109s tRPS Pulse duration, RASx precharge after self refresh 90 110 130 ns tASC Setup time, column address 0 0 0 ns tASR Setup time, row address 0 0 0 ns tDS Setup time, data in (see Note 8) 0 0 0 ns tRCS Setup time, read command 0 0 0 ns tCWL Setup time, write command before CASx precharge 8 10 12 ns tRWL Setup time, write command before RASx precharge 8 10 12 ns tWCS Setup time, write command before CASx active (early-write only) 0 0 0 ns tWRP Setup time, WEx high before RASx low (CBR refresh only) 10 10 10 ns tCSR Setup time, CASx referenced to RASx (CBR refresh only) 5 5 5 ns tCAH Hold time, column address 8 10 12 ns tDH Hold time, data in (see Note 8) 8 10 12 ns tRAH Hold time, row address 8 10 10 ns tRCH Hold time, read command referenced to CASx (see Note 9) 0 0 0 ns tRRH Hold time, read command referenced to RASx (see Note 9) 0 0 0 ns tWCH Hold time, write command during CASx active (early-write only) 8 10 12 ns tROH Hold time, RASx referenced to OEx 8 10 10 ns tWRH Hold time, WEx high after RASx low (CBR refresh only) 10 10 10 ns tCHR Hold time, CASx referenced to RASx (CBR refresh only) 10 10 10 ns tOEH Hold time, OEx command 13 15 18 ns tRHCP Hold time, RASx active from CASx precharge 28 35 40 ns tCHS Hold time, CASx referenced to RASx (self refresh only) − 50 − 50 − 50 ns tAWD Delay time, column address to write command (read-write only) 42 49 57 ns tCRP Delay time, CASx precharge to RASx 5 5 5 ns NOTES: 6. In a read-write cycle, tRWD and tRWL must be observed. 7. During the period of 10 µs ≤ tRASS ≤100 µs, the device is in a transition state from normal-operation mode to self-refresh mode. 8. Referenced to the later of CASx or WEx in write operations 9. Either tRRH or tRCH must be satisfied for a read cycle.

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ac timing requirements (continued) ’xEP64DxN-50 ’xEP72DxN-50 ’xEP64DxN-60 ’xEP72DxN-60 ’xEP64DxN-70 ’xEP72DxN-70 UNIT MIN MAX MIN MAX MIN MAX UNIT tCWD Delay time, CASx to write command (read-write only) 30 34 40 ns tOED Delay time, OEx to data in 13 15 18 ns tRAD Delay time, RASx to column address (see Note 10) 10 25 12 30 12 35 ns tRAL Delay time, column address to RASx precharge 25 30 35 ns tCAL Delay time, column address to CASx precharge 18 20 25 ns tRCD Delay time, RASx to CASx (see Note 10) 12 37 14 45 14 52 ns tRPC Delay time, RASx precharge to CASx 5 5 5 ns tRSH Delay time, CASx active to RASx precharge 8 10 12 ns tRWD Delay time, RASx to write command (read-write only) 67 79 92 ns tCPW Delay time, CASx precharge to write command (read-write only) 45 54 62 ns tREF Refresh time interval 32 32 32 ms tT Transition time 2 30 2 30 2 30 ns NOTE 10: The maximum value is specified only to ensure access time.

(SCL) and data (SDA) signals. All Texas Instruments module comply with the current JEDEC SPD Standard.

38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).

† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).

40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).

† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device symbolization (TM4EP64DPN illustrated) TM4EP64DPN -SS YYMMT YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE A: Location of symbolization may vary. Unbuffered Key Position 3.3-V Voltage Key Position

/C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0054/C0052/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0054/C0052/C0068/C0074/C0078 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0069/C0080/C0055/C0050/C0068/C0074/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0080/C0078/C0044 /C0084/C0077/C0052/C0069/C0080/C0055/C0050/C0068/C0074/C0078 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 43POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MECHANICAL DATA BR (R-PDIM-N168) DUAL IN-LINE MEMORY MODULE 0.118 (3,00) TYP 1.005 (25,53) 0.995 (25,27) 0.700 (17,78) TYP 0.014 (0,35) MAX 0.106 (2,70) MAX 0.054 (1,37) 0.046 (1,17) 4088180/A 07/97 0.157 (4,00) MAX (For Double Sided DIMM Only) (Note D) 5.255 (133,48) 5.245 (133,22) 0.118 (3,00) DIA 0.125 (3,18) 0.039 (1,00) TYP Notch 0.157 (4,00) x 0.122 (3,10) Deep Notch 0.079 (2,00) x 0.122 (3,10) Deep 0.125 (3,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-161 D. Dimension includes de-panelization variations; applies between notch and tab edge. E. Outline may vary above notches to allow router/panelization irregularities.

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