TM4EJ64KPU | DigiCamel IC Datasheet

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/C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Organization − TM4xJ64xPU-xx...4 1 9 4304 × 64 Bits − TM8xJ64xPU-xx...8 3 8 8608 × 64 Bits /C0068Single 3.3-V Power Supply (±10% Tolerance) /C0068JEDEC 144-Pin Small-Outline Dual-In-Line Memory Module (SODIMM) Without Buffer for Use With Socket /C0068TM4xJ64xPU-xx — Utilizes Four 64M-Bit High-Speed (4M×16-Bit) Dynamic RAMs /C0068TM4xJ64xPU-xx — Utilizes Eight 64M-Bit High-Speed (4M×16-Bit) Dynamic RAMs /C0068High-Speed, Low-Noise LVTTL Interface /C0068High-Reliability 50-Lead 400-Mil-Wide Surface-Mount Thin Small-Outline Package (TSOP) (DGE Suffix) /C00683-State Output /C0068Gold-Plated Contacts /C0068Long Refresh Periods: − TMxEJ64KPU: 64 ms (4096 Cycles) − TMxEJ64NPU: 64 ms (8192 Cycles) − TMxFJ64KPU: 128 ms (4096 Cycles) − TMxFJ64NPU: 128 ms (8192 Cycles) /C0068Extended Data Out (EDO) Operation With CAS -Before-RAS (CBR), RAS-Only, and Hidden Refresh /C0068Serial Presence-Detect (SPD) Using EEPROM /C0068Ambient Temperature Range 0°C to 70°C /C0068Performance Ranges ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE tRAC tCAC tAA tHPC (MAX) (MAX) (MAX) (MIN) ’xxJ64xPU-40 40 ns 11 ns 20 ns 16 ns ’xxJ64xPU-50 50 ns 13 ns 25 ns 20 ns ’xxJ64xPU-60 60 ns 15 ns 30 ns 25 ns

description

The TM4xJ64KPU is a 32M-byte, 144-pin, small-outline dual-in-line memory module (SODIMM). The SODIMM is composed of four TMS465169/P, 4194304 × 16-bit 4K normal or low-power battery-backup refresh EDO dynamic random-access memory (DRAM) devices, each in a 400-mil, 50-pin plastic thin small-outline package (TSOP) (DGE suffix) package mounted on a substrate with decoupling capacitors. See the TMS465169/P data sheet (literature number SMHS566). The TM4xJ64NPU is a 32M-byte, 144-pin SODIMM. The SODIMM is composed of four TMS464169/P, 4194304 × 16-bit 8K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic TSOP (DGE suffix) mounted on a substrate with decoupling capacitors. See the TMS464169/P data sheet (literature number SMHS566). The TM8xJ64KPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS465169/P, 4194304 × 16-bit 4K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic TSOP (DGE suffix) mounted on a substrate with decoupling capacitors. The TM8xJ64NPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS464169/P, 4194304 × 16-bit 8K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic TSOP (DGE suffix) mounted on a substrate with decoupling capacitors. operation The TM4xJ64xPU operates as four TMS46x169/Ps that are connected as shown in the TMxxJ64xPU functional block diagram. The TM8xJ64xPU operates as eight TMS46x169/Ps that are connected as shown in the TMxxJ64xPU functional block diagram. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW Copyright  1997, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084 /C0080/C0082/C0069/C0086/C0073/C0069/C0087 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0099/C0111/C0110/C0099/C0101/C0114/C0110/C0115 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0105/C0110 /C0116/C0104/C0101 /C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0118/C0101 /C0111/C0114 /C0100/C0101/C0115/C0105/C0103/C0110 /C0112/C0104/C0097/C0115/C0101 /C0111/C0102 /C0100/C0101/C0118/C0101/C0108/C0111/C0112/C0109/C0101/C0110/C0116/C0046 /C0067/C0104/C0097/C0114/C0097/C0099/C0116/C0101/C0114/C0105/C0115/C0116/C0105/C0099 /C0100/C0097/C0116/C0097 /C0097/C0110/C0100 /C0111/C0116/C0104/C0101/C0114 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0097/C0114/C0101 /C0100/C0101/C0115/C0105/C0103/C0110 /C0103/C0111/C0097/C0108/C0115/C0046 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0114/C0101/C0115/C0101/C0114/C0118/C0101/C0115 /C0116/C0104/C0101 /C0114/C0105/C0103/C0104/C0116 /C0116/C0111 /C0099/C0104/C0097/C0110/C0103/C0101 /C0111/C0114 /C0100/C0105/C0115/C0099/C0111/C0110/C0116/C0105/C0110/C0117/C0101 /C0116/C0104/C0101/C0115/C0101 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0119/C0105/C0116/C0104/C0111/C0117/C0116 /C0110/C0111/C0116/C0105/C0099/C0101/C0046

/C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997

2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

DUAL-IN-LINE MEMORY MODULE (TOP VIEW) TM8xJ64xPU (SIDE VIEW) PIN NOMENCLATURE − TMxxJ64KPU A[0:11] Row Address Inputs A[0:9] Column Address Inputs DQ[0:63] Data In/Data Out CAS[0:7] Column-Address Strobe RAS0 and RAS1 Row-Address Strobe WE0 Write Enable OE0 Output Enable SDA Serial PD Address/Data SCL Serial PD Clock NC No-Connect Pin VDD 3.3-V Supply VSS Ground TM4xJ64xPU (SIDE VIEW) PIN NOMENCLATURE − TMxxJ64NPU A[0:12] Row Address Inputs A[0:8] Column Address Inputs DQ[0:63] Data In/Data Out CAS[0:7] Column-Address Strobe RAS0 and RAS1 Row-Address Strobe WE0 Write Enable OE0 Output Enable SDA Serial PD Address/Data SCL Serial PD Clock NC No-Connect Pin VDD 3.3-V Supply VSS Ground 143 PRODUCT PREVIEW

/C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Pin Assignments ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ PIN ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ PIN ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ PIN ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ PIN ÁÁÁ NO. ÁÁÁÁÁ NAME ÁÁÁÁ NO. ÁÁÁÁÁ NAME ÁÁÁÁ NO. ÁÁÁÁÁ NAME ÁÁÁ NO. ÁÁÁÁÁÁ NAME ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ8 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ OE0 ÁÁÁ ÁÁÁ 109 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ40 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 110 ÁÁÁÁÁÁ ÁÁÁÁÁÁ A12 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ9 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 111 ÁÁÁÁÁÁ ÁÁÁÁÁÁ A10 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ32 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ41 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 112 ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ1 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ10 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 113 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ33 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ42 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 114 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁÁÁ DQ2 ÁÁÁÁ ÁÁÁÁÁ DQ11 ÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ 115 ÁÁÁÁÁÁ CAS2 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ34 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ43 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 116 ÁÁÁÁÁÁ ÁÁÁÁÁÁ CAS6 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ3 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ 117 ÁÁÁÁÁÁ ÁÁÁÁÁÁ CAS3 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ35 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ 118 ÁÁÁÁÁÁ ÁÁÁÁÁÁ CAS7 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ12 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ16 ÁÁÁ ÁÁÁ 119 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ44 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ48 ÁÁÁ ÁÁÁ 120 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ4 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ13 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ17 ÁÁÁ ÁÁÁ 121 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ24 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ36 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ45 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ49 ÁÁÁ ÁÁÁ 122 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ56 ÁÁÁ ÁÁÁÁÁ DQ5 ÁÁÁÁ ÁÁÁÁÁ DQ14 ÁÁÁÁ ÁÁÁÁÁ DQ18 ÁÁÁ 123 ÁÁÁÁÁÁ DQ25 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ37 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ46 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ50 ÁÁÁ ÁÁÁ 124 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ57 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ6 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ15 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ19 ÁÁÁ ÁÁÁ 125 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ26 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ38 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ47 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ51 ÁÁÁ ÁÁÁ 126 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ58 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ7 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 127 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ27 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ39 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 128 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ59 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ20 ÁÁÁ ÁÁÁ 129 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ52 ÁÁÁ ÁÁÁ 130 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CAS0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ21 ÁÁÁ ÁÁÁ 131 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ28 ÁÁÁ ÁÁÁÁÁ CAS4 ÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁÁ DQ53 ÁÁÁ 132 ÁÁÁÁÁÁ DQ60 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CAS1 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ22 ÁÁÁ ÁÁÁ 133 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ29 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CAS5 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ54 ÁÁÁ ÁÁÁ 134 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ61 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ23 ÁÁÁ ÁÁÁ 135 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ30 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ 100 ÁÁÁÁÁ ÁÁÁÁÁ DQ55 ÁÁÁ ÁÁÁ 136 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ62 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 101 ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ 137 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ31 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 102 ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ 138 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ63 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ WE0 ÁÁÁÁ ÁÁÁÁ 103 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ 139 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ 104 ÁÁÁÁÁ ÁÁÁ 140 ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ RAS0 ÁÁÁÁ ÁÁÁÁ 105 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ 141 ÁÁÁÁÁÁ ÁÁÁÁÁÁ SDA ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 106 ÁÁÁÁÁ ÁÁÁÁÁ A11 ÁÁÁ ÁÁÁ 142 ÁÁÁÁÁÁ ÁÁÁÁÁÁ SCL ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ RAS1 ÁÁÁÁ ÁÁÁÁ 107 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 143 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 108 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 144 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD PRODUCT PREVIEW

4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

The following table shows the SODIMM modules and devices (Ux/UBx) that are used. Table 1. Component Table

/C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over ambient temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ MIN ÁÁÁ ÁÁÁ NOM ÁÁÁÁ ÁÁÁÁ MAX ÁÁÁ ÁÁÁ UNIT ÁÁÁÁ ÁÁÁÁ VDD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 3.3 ÁÁÁÁ ÁÁÁÁ 3.6 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VSS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VIH ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ High-level input voltage ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ VDD + 0.3 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VIH-SPD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ High-level input voltage for the SPD device ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 5.5 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VIL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Low-level input voltage ÁÁÁ ÁÁÁ −0.3 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 0.8 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ TA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Ambient temperature ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ PRODUCT PREVIEW

/C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997

6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) TM4xJ64KPU PARAMETER TEST CONDITIONS † ’4xJ64KPU-40 ’4xJ64KPU-50 ’4xJ64KPU-60 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 10 ± 10 ± 10 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 10 ± 10 ± 10 µA ICC1 ‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 640 520 440 mA Average VIH = 2 V LVTTL), After one memory cycle, RASx and CASx high 4 4 4 mA ICC2 Average standby current VIH = VDD − 0.2 V (LVCMOS), ’4EJ64KPU 2 2 2 mA current (LVCMOS), After one memory cycle, RASx and CASx high ’4FJ64KPU .6 .6 .6 mA ICC3 § RASx -only refresh, average refresh curren VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high 640 520 440 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 600 480 400 mA ICC5 Average CBR refresh current VDD = 3.6 V, Minimum cycle, RASx low after CASx low 640 520 440 mA ICC6 # Average self-refresh current CASx < 0.2 V, RASx < 0.2 V, Measured after tRASS min 1.2 1.2 1.2 mA ICC10 # Average battery back-up operating current, CBR only tRC = 31.25 µs, tRAS ≤ 300 ns, VDD − 0.2 V ≤ VIH ≤ 3.9 V, 0 V ≤ VIL ≤ 0.2 V, WE0 and OE0 = VIH, Address and data stable 1.6 1.6 1.6 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC# For TM4FJ64KPU only PRODUCT PREVIEW

/C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM4xJ64NPU PARAMETER TEST CONDITIONS † ’4xJ64NPU-40 ’4xJ64NPU-50 ’4xJ64NPU-60 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 10 ± 10 ± 10 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 10 ± 10 ± 10 µA ICC1 ‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 540 440 400 mA Average VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 4 4 4 mA ICC2 Average standby current VIH = VDD − 0.2 V (LVCMOS), ’4EJ64NPU 2 2 2 mA current (LVCMOS), After one memory cycle, RAS and CASx high ’4FJ64NPU .6 .6 .6 mA ICC3 § RASx -only refresh, average refresh curren VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high 540 440 400 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 560 440 360 mA ICC5 Average CBR refresh current VDD = 3.6 V, Minimum cycle, RASx low after CASx low 640 520 440 mA ICC6 # Average self-refresh current CASx < 0.2 V, RASx < 0.2 V, Measured after tRASS min 1.2 1.2 1.2 mA ICC10 # Average battery back-up operating current, CBR only tRC = 31.25 µs, tRAS ≤ 300 ns, VDD − 0.2 V ≤ VIH ≤ 3.9 V, 0 V ≤ VIL ≤ 0.2 V, WE0 and OE0 = VIH, Address and data stable 1.6 1.6 1.6 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC# For TM4FJ64NPU only PRODUCT PREVIEW

/C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997

8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM8xJ64KPU PARAMETER TEST CONDITIONS † ’8xJ64KPU-40 ’8xJ64KPU-50 ’8xJ64KPU-60 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 10 ± 10 ± 10 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 10 ± 10 ± 10 µA ICC1 ‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 644 524 444 mA Average VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 8 8 8 mA ICC2 Average standby current VIH = VDD − 0.2 V (LVCMOS), ’8EJ64KPU 4 4 4 mA current (LVCMOS), After one memory cycle, RASx and CASx high ’8FJ64KPU 1.2 1.2 1.2 mA ICC3 § RASx -only refresh, average refresh curren VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high 644 524 444 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 604 484 404 mA ICC5 Average CBR refresh current VDD = 3.6 V, Minimum cycle, RASx low after CASx low 644 524 444 mA ICC6 # Average self-refresh current CASx < 0.2 V, RASx < 0.2 V, Measured after tRASS min 2.4 2.4 2.4 mA ICC10 # Average battery back-up operating current, CBR only tRC = 31.25 µs, tRAS ≤ 300 ns, VDD − 0.2 V ≤ VIH ≤ 3.9 V, 0 V ≤ VIL ≤ 0.2 V, WE0 and OE0 = VIH, Address and data stable 3.2 3.2 3.2 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC# For TM8FJ64KPU only PRODUCT PREVIEW

/C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM8xJ64NPU PARAMETER TEST CONDITIONS † ’8xJ64NPU-40 ’8xJ64NPU-50 ’8xJ64NPU-60 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 10 ± 10 ± 10 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 10 ± 10 ± 10 µA ICC1 ‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 544 444 404 mA Average VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 8 8 8 mA ICC2 Average standby current VIH = VDD − 0.2 V (LVCMOS), ’8EJ64NPU 4 4 4 mA current (LVCMOS), After one memory cycle, RASx and CASx high ’8FJ64NPU 1.2 1.2 1.2 mA ICC3 § RASx -only refresh, average refresh curren VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high 544 444 404 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 564 444 364 mA ICC5 Average CBR refresh current VDD = 3.6 V, Minimum cycle, RASx low after CASx low 644 524 444 mA ICC6 # Average self-refresh current CASx < 0.2 V, RASx < 0.2 V, Measured after tRASS min 2.4 2.4 2.4 mA ICC10 # Average battery back-up operating current, CBR only tRC = 31.25 µs, tRAS ≤ 300 ns, VDD − 0.2 V ≤ VIH ≤ 3.9 V, 0 V ≤ VIL ≤ 0.2 V, WE0 and OE0 = VIH, Address and data stable 3.2 3.2 3.2 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC# For TM8FJ64NPU only PRODUCT PREVIEW

/C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997

10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2) PARAMETER ’4xJ64xPU ’8xJ64xPU UNITPARAMETER MIN MAX MIN MAX UNIT C i(A) Input capacitance, A0−A12 22 42 pF C i(OE) Input capacitance, OE0 16 30 pF C i(CAS) Input capacitance, CASx 9 9 pF C i(RAS) Input capacitance, RASx 16 16 pF C i(W) Input capacitance, WE0 16 30 pF C o Output capacitance 9 16 pF C i/o(SDA) Input/output capacitance, SDA input 9 9 pF C i(SPD) Input capacitance,SPD inputs (except SDA) 7 7 pF NOTE 2: V DD = NOM supply voltage ±10%, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 3) PARAMETER ’xxJ64xPU-40 ’xxJ64xPU-50 ’xxJ64xPU-60 UNITPARAMETER MIN MAX MIN MAX MIN MAX UNIT tAA Access time from column address (see Note 4) 20 25 30 ns tCAC Access time from CASx (see Note 4) 11 13 15 ns tCPA Access time from CASx precharge (see Note 4) 22 28 35 ns tRAC Access time from RASx (see Note 4) 40 50 60 ns tOEA Access time from OE0 (see Note 4) 11 13 15 ns tCLZ Delay time, CASx to output in the low-impedance state 0 0 0 ns tOEZ Output buffer turnoff delay from OE0 (see Note 5) 3 11 3 13 3 15 ns tREZ Output buffer turnoff delay from RASx (see Note 5) 3 11 3 13 3 15 ns tCEZ Output buffer turnoff delay from CASx (see Note 5) 3 11 3 13 3 15 ns tWEZ Output buffer turnoff delay from WE0 (see Note 5) 3 11 3 13 3 15 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 5. The MAX specifications of tREZ , tCEZ , tWEZ and tOEZ are specified when the output is no longer driven. Data-in should not be driven until one of the applicable maximum specifications is satsified. EDO timing requirements (see Note 3) ’xxJ64xPU-40 ’xxJ64xPU-50 ’xxJ64xPU-60 UNITMIN MAX MIN MAX MIN MAX UNIT tHPC Cycle time, EDO page-mode read or write 16 20 25 ns tPRWC Cycle time, EDO read-write 47 57 68 ns tCSH Delay time, RASx active to CASx precharge 32 40 48 ns tCHO Hold time, OE0 from CASx 5 5 5 ns tDOH Hold time, output from CASx active 5 5 5 ns tCAS Pulse duration, CASx active (see Note 6) 6 10000 8 10000 10 10000 ns tWPE Pulse duration, WE0 (output disable only) 5 5 5 ns tCP Pulse duration, CASx precharge 6 8 10 ns tOCH Setup time, OE0 before CASx 5 5 5 ns tOEP Precharge time, OE0 (output disable only) 5 5 5 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 6. In a read-write cycle, tCWD and tCWL must be observed. PRODUCT PREVIEW

/C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ac timing requirements (see Note 3) ’xxJ64xPU-40 ’xxJ64xPU-50 ’xxJ64xPU-60 UNITMIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, read 69 84 104 ns tRWC Cycle time, read-write 92 111 135 ns tRASP Pulse duration, RASx active, page mode (see Note 7) 40 100 000 50 100 000 60 100 000 ns tRAS Pulse duration, RASx active, nonpage mode (see Note 7) 40 10 000 50 10 000 60 10 000 ns tRP Pulse duration, RASx precharge 25 30 40 ns tWP Pulse duration, write command 6 8 10 ns tASC Setup time, column address 0 0 0 ns tASR Setup time, row address 0 0 0 ns tDS Setup time, data in (see Note 8) 0 0 0 ns tRCS Setup time, read command 0 0 0 ns tCWL Setup time, write command before CASx precharge 6 8 10 ns tRWL Setup time, write command before RASx precharge 6 8 10 ns tWCS Setup time, write command before CASx active (early-write only) 0 0 0 ns tWRP Setup time, write before RASx active (CBR refresh only) 5 5 5 ns tCSR Setup time, CASx referenced to RASx (CBR refresh only) 5 5 5 ns tCAH Hold time, column address 6 8 10 ns tDH Hold time, data in (see Note 8) 6 8 10 ns tRAH Hold time, row address 6 8 10 ns tRCH Hold time, read command referenced to CASx (see Note 9) 0 0 0 ns tRRH Hold time, read command referenced to RASx (see Note 9) 0 0 0 ns tWCH Hold time, write command during CASx active (early-write only) 6 8 10 ns tRHCP Hold time, RASx active from CASx precharge 22 28 35 ns tOEH Hold time, OE0 command 11 13 15 ns tROH Hold time, RASx referenced to OE0 6 8 10 ns tWRH Hold time, write after RASx active (CBR refresh only) 6 8 10 ns tCHS Hold time, CASx active after RASx precharge (self-refresh) − 50 − 50 − 50 ns tAWD Delay time, column address to write command (read-write only) 35 42 49 ns tCHR Delay time, CASx referenced to RASx (CBR refresh only) 6 8 10 ns tCRP Delay time, CASx precharge to RASx 5 5 5 ns tCWD Delay time, CASx to write command (read-write operation only) 26 30 34 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 7. In a read-write cycle, tRWD and tRWL must be observed. 8. Referenced to the later of CASx or WE0 in write operations 9. Either tRRH or tRCH must be satisfied for a read cycle. PRODUCT PREVIEW

/C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0052/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0069/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0075/C0080/C0085/C0044 /C0084/C0077/C0056/C0070/C0074/C0054/C0052/C0078/C0080/C0085/C0044 /C0056/C0257/C0051/C0056/C0056/C0257/C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997

12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

ac timing requirements (see Note 3) (continued) ’xxJ64xPU-40 ’xxJ64xPU-50 ’xxJ64xPU-60 UNITMIN MAX MIN MAX MIN MAX UNIT tOED Delay time, OE0 to data in 11 13 15 ns tRAD Delay time, RASx to column address (see Note 10) 8 20 10 25 12 30 ns tRAL Delay time, column address to RASx precharge 20 25 30 ns tCAL Delay time, column address to CASx precharge 12 15 18 ns tRCD Delay time, RASx to CASx (see Note 10) 10 29 12 37 14 45 ns tRPC Delay time, RASx precharge to CASx 5 5 5 ns tRSH Delay time, CASx active to RASx precharge 6 8 10 ns tRWD Delay time, RASx active to write command (read-write only) 55 67 79 ns tCPW Delay time, CASx precharge to write command (read-write only)37 45 54 ns tRASS Pulse duration, RASx active, self-refresh (see Note 11) 100 100 100 µs tRPS Pulse duration, RASx precharge after self refresh 70 90 110 ns tREF Refresh time interval ’xEJ64xPU 64 64 64 ms tREF Refresh time interval ’xFJ64xPU 128 128 128 ms tT Transition time 1 50 1 50 1 50 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 10. The maximum value is specified only to assure access time. 11. During the period of 10 µs ≤ tRASS ≤ 100 µs, the device is in transition state from normal operational mode to self-refresh mode. PRODUCT PREVIEW

(SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. Table 2. Serial-Presence-Detect Data for the TM4EJ64KPU

1 Total number of bytes of SPD

2 Fundamental memory type

3 Number of row addresses on

4 Number of column addresses

5 Number of module banks on

6 Data width of this assembly 64 bits 40h 64 bits 40h 64 bits 40h

7 Data width continuation 00h 00h 00h

8 Voltage interface standard of

9 RASx access time of module tRAC = 40 ns 28h tRAC = 50 ns 32h tRAC = 60 ns 3Ch

10 CASx access time of module tCAC = 11 ns 0Bh tCAC = 13 ns 0Dh tCAC = 15 ns 0Fh

13 DRAM width, primary DRAM x16 10h x16 10h x16 10h

14 Error-checking SDRAM data

63 Checksum for bytes 0−62 38 26h 50 32h 62 3Eh

14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Table 2. Serial-Presence-Detect Data for the TM4EJ64KPU (Continued)