TM4C1233D5PZI7R

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Tiva™ TM4C1233D5PZ Microcontroller DATA SHEET Copyright © 2007-2014 Texas Instruments Incorporated DS-TM4C1233D5PZ-15842.2741 SPMS347E TEXAS INSTRUMENTS-PRODUCTION DATA

Copyright © 2007-2014 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others. PRODUCTION DA TA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Texas Instruments Incorporated

108 Wild Basin, Suite 350

Austin, TX 78746 http://www.ti.com/tm4c http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm June 12, 20142 Texas Instruments-Production Data

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7.3.7 Power Control Using HIB

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Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive 15June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table 19-3. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and Table 19-4. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and June 12, 201416 Texas Instruments-Production Data Table of Contents

Table 22-38. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and Table 22-39. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and 17June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

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Register 31: Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART), offset Register 47: Universal Asynchronous Receiver/Transmitter Software Reset (SRUART), offset 0x518 .... 312 Register 57: 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER), offset Register 58: General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO), offset Register 59: Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA), offset Register 61: Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART), Register 62: Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI), offset 21June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register 66: Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC), offset 0x638 .... 342 Register 69: 32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control (RCGCWTIMER), Register 71: 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER), offset Register 72: General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO), offset Register 73: Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA), offset Register 75: Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control Register 76: Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI), offset Register 80: Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC), offset Register 83: 32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating Control (SCGCWTIMER), Register 85: 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER), Register 86: General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO), offset Register 87: Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA), offset Register 89: Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control Register 90: Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI), offset Register 91: Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C), offset Register 92: Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB), offset Register 93: Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN), offset Register 94: Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC), offset Register 95: Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP), offset June 12, 201422 Texas Instruments-Production Data Table of Contents

Register 97: 32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating Control Register 103: Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART), offset 23June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

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Register 26: ADC Sample Sequence Extended Input Multiplexer Select 0 (ADCSSEMUX0), offset Register 35: ADC Sample Sequence Extended Input Multiplexer Select 1 (ADCSSEMUX1), offset Register 36: ADC Sample Sequence Extended Input Multiplexer Select 2 (ADCSSEMUX2), offset 0x098 Register 41: ADC Sample Sequence Extended Input Multiplexer Select 3 (ADCSSEMUX3), offset June 12, 201428 Texas Instruments-Production Data Table of Contents

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Register 25: USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF), offset 0x07D .... 1118 Register 26: USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF), offset 0x07E .... 1119 31June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

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The revision history table notes changes made between the indicated revisions of the TM4C1233D5PZ data sheet. Table1.RevisionHistory DescriptionRevisionDate 15842.2741June 2014 ■ In System Control Chapter, corrected description forMINSYSDIVbitfield inDeviceCapabilities1 (DC1)legacy register. ■ In Timers chapter, removed erroneous references toTCACTbit field. ■ In SSI chapter, corrected that during idle periods the transmit data line SSInTx is tristated. ■ In Package Information appendix: Corrected Key to Part Numbers diagram.– – Moved Orderable Part Numbers table to addendum. – Deleted Packaging Materials section and put into separate packaging document. ■ Additional minor data sheet clarifications and corrections. 15741.2722March 2014 ■ In the Internal Memory chapter, in the EEPROM section: Added section on soft reset handling.– – Added important information on EEPROM initialization and configuration. ■ In the DMA chapter, added information regarding interrupts and transfers from the UART or SSI modules. ■ In the Hibernation chapter, noted that theEXTWbit is set in theHIBRISregister regardless of the PINWENsetting in theHIBCTLregister. ■ In the GPIO chapter: Corrected table GPIO Pins with Special Considerations.– – Added information on preventing false interrupts. ■ In the Timer chapter: Clarified initialization and configuration for Input-Edge Count mode.– – Clarified behavior of TnMIEand TnCINTDbits in theGPTMTimernMode(GPTMTnMR) register. ■ In the USB chapter, added note to SUSPEND section regarding bus-powered devices. ■ In the Electrical Characteristics chapter: In table Reset Characteristics, clarified internal reset time parameter values.– – In table Hibernation Oscillator Input Characteristics, added parameter CINSE Input capacitance. – In tables Hibernation Oscillator Input Characteristics and Main Oscillator Input Characteristics, removed parameter C0 Crystal shunt capacitance. – Updated table Crystal Parameters. – In table GPIO Module Characteristics, added parameter CGPIO GPIO Digital Input Capacitance. – Added table PWM Timing Characteristics. ■ In the Package Information appendix: Updated Orderable Devices section to reflect silicon revision 7 part numbers.– – Added Tape and Reel pin 1 location. ■ Additional minor data sheet clarifications and corrections. 15553.2700November 2013 ■ In System Control chapter, clarified PIOSC features and accuracy. ■ In Hibernation Module chapter: June 12, 201434 Texas Instruments-Production Data

Revision History

Table1.RevisionHistory (continued) DescriptionRevisionDate Corrected figures "Using a Crystal as the Hibernation Clock Source with a Single Battery Source" and "Using a Regulator for Both VDD and VBAT". – Replaced RTC Trim tables with two new figures "Counter Behavior with a TRIM Value of 0x8002" and "Counter Behavior with a TRIM Value of 0x7FFC". – Clarified HibernationData(HIBDATA) register description. ■ In Watchdog Timers chapter, clarifiedWatchdogControl(WDTCTL) register description. ■ In ADC chapter: – Clarified functionality when using an ADC digital comparator as a fault source. – Clarified signals used for ADC voltage reference. – Corrected VREFbit inADCControl(ADCCTL) register from 2-bit field [1:0] to 1-bit field [0]. ■ In UART chapter, clarified DMA operation. ■ In SSI chapter: – Corrected timing guidelines in figures "Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0" and "Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0". – Clarified SSI Initialization and Configuration. – Corrected bit 3 inSSIControl1(SSICR1) register fromSOD(SSI Slave Mode Output Disable) to reserved. ■ In Signal Tables chapter: – In Unused Signals table, corrected preferred and acceptable practices forRSTpin. – Clarified GNDXpin description. ■ In Electrical Characteristics chapter: – In Power-On and Brown-Out Levels table, corrected TVDDC_RISE parameter min and max values. – In PIOSC Clock Characteristics table, clarified FPIOSC parameter values by defining values for both factory calibration and recalibration. Also added PIOSC startup time parameter to table. – In Main Oscillator Specifications section, corrected minimum value for External load capacitance on OSC0, OSC1pins. Also added two 25-MHz crystals to Crystal Parameters table. – Corrected figure "Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1". – In I 2C Characteristics table, clarified TDH data hold time parameter values by defining values for both slave and master. In addition, added parameter I10 TDV data valid. – Modified figure "I2C Timing" to add new parameter I10. ■ In Packaging Information appendix, added Packaging Materials figures. 15033.2672July 16, 2013 ■ In the Electrical Characteristics chapter: – Added maximum junction temperature to Maximum Ratings table. Also moved Unpowered storage temperature range parameter to this table. – In SSI Characteristics table, corrected values for TRXDMS, TRXDMH, and TRXDSSU. Also clarified footnotes to table. 35June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table1.RevisionHistory (continued) DescriptionRevisionDate – Corrected parameter numbers in figures "Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1" and "Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1". ■ Additional minor data sheet clarifications and corrections. 14995.2667July 2013 ■ In the System Control chapter, corrected resets for bits [7:4] inSystemProperties(SYSPROP) register. ■ In the Hibernation Module chapter: – Corrected figures "Using a Crystal as the Hibernation Clock Source with a Single Battery Source" and "Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON Mode". – Clarified when the Hibernation module can generate interrupts. ■ In the Internal Memory chapter, removed theINVPLbit from theEEPROMDoneStatus(EEDONE) register. ■ In the uDMA chapter, in the µDMA Channel Assignments table, corrected names of timers 6-11 to wide timers 0-5. ■ In the Timers chapter: – Clarified that the timer must be configured for one-shot or periodic time-out mode to produce an ADC trigger assertion and that the GPTM does not generate triggers for match, compare events or compare match events. – Added a step in the RTC Mode initialization and configuration: If the timer has been operating in a different mode prior to this, clear any residual set bits in theGPTMTimernMode (GPTMTnMR)register before reconfiguring. ■ In the Watchdog Timer chapter, added a note that locking the watchdog registers using the WDTLOCKregister does not affect theWDTICRregister and allows interrupts to always be serviced. ■ In the SSI chapter, clarified note in Bit Rate Generation section to indicate that the System Clock or the PIOSC can be used as the source forSSIClk. Also corrected to indicate maximum SSIClk limit in SSI slave mode as well as the fact that SYSCLK has to be at least 12 times that of SSICLk. ■ In the Electrical Characteristics chapter: – Moved Maximum Ratings and ESD Absolute Maximum Ratings to the front of the chapter. – Added VBATRMP parameter to Maximum Ratings and Hibernation Module Battery Characteristics tables. – Added ambient and junction temperatures to Temperature Characteristics table and clarified values in Thermal Characteristics table. – Added clarifying footnote to VVDD_POK parameter in Power-On and Brown-Out Levels table. – Corrected GPIO Package Side Assignments table. – In the Flash Memory and EEPROM Characteristics tables, added a parameter for page/mass erase times for 10k cycles and corrected existing values for all page and mass erase parameters. – Corrected DNL max value in ADC Electrical Characteristics table. – In the SSI Characteristics table, changed parameter names for S7-S14, provided a max number instead of a min for S7, and corrected values for S9-S14. – Replaced figure "SSI Timing for SPI Frame Format (FRF=00), with SPH=1" with two figures, one for Master Mode and one for Slave Mode. June 12, 201436 Texas Instruments-Production Data

Table1.RevisionHistory (continued) DescriptionRevisionDate – Updated and added values to the table Table 22-40 on page 1233. ■ In the Package Information appendix, moved orderable devices table from addendum to appendix, clarified part markings and moved packaging diagram from addendum to appendix. ■ Additional minor data sheet clarifications and corrections. 37June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

This data sheet provides reference information for the TM4C1233D5PZ microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M4F core. Audience This manual is intended for system software developers, hardware designers, and application developers. AboutThisManual This document is organized into sections that correspond to each major feature. RelatedDocuments The following related documents are available on the Tiva™ C Series web site at http://www.ti.com/tiva-c: ■ Tiva™ C Series TM4C123x Silicon Errata (literature number SPMZ849) ■ TivaWare™ Boot Loader for C Series User's Guide (literature number SPMU301) ■ TivaWare™ Graphics Library for C Series User's Guide (literature number SPMU300) ■ TivaWare™ for C Series Release Notes (literature number SPMU299) ■ TivaWare™ Peripheral Driver Library for C Series User's Guide (literature number SPMU298) ■ TivaWare™ USB Library for C Series User's Guide (literature number SPMU297) ■ Tiva™ C Series TM4C123x ROM User’s Guide (literature number SPMU367) The following related documents may also be useful: ■ ARM® Cortex™-M4 Errata (literature number SPMZ637) ■ ARM® Cortex™-M4 Technical Reference Manual ■ ARM® Debug Interface V5 Architecture Specification ■ ARM® Embedded Trace Macrocell Architecture Specification ■ Cortex™-M4 instruction set chapter in theARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A ) ■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the web site for additional documentation, including application notes and white papers. June 12, 201438 Texas Instruments-Production Data About This Document

This document uses the conventions shown in Table 2 on page 39. Table2.DocumentationConventions MeaningNotation GeneralRegisterNotation APB registers are indicated in uppercase bold. For example,PBORCTLis the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example,SRCRnrepresents any (or all) of the three Software Reset Control registers: SRCR0,SRCR1 , andSRCR2. REGISTER A single bit in a register.bit Two or more consecutive and related bits.bit field A hexadecimal increment to a register's address, relative to that module's base address as specified in Table 2-4 on page 85. offset 0xnnn Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. Register N Register bits markedreserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. reserved The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. yy:xx This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. RegisterBit/Field Types Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC Software can read this field. Always write the chip reset value.RO Software can read or write this field.RW Software can read or write this field. Writing to it with any value clears the register.RWC Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. RW1C Software can read or write a 1 to this field. A write of a 0 to a RW1S bit does not affect the bit value in the register. RW1S Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. W1C Only a write by software is valid; a read of the register returns no meaningful data.WO This value in the register bit diagram shows the bit/field value after any reset, unless noted.RegisterBit/Field ResetValue Bit cleared to 0 on chip reset.0 Bit set to 1 on chip reset.1 Nondeterministic.- Pin/SignalNotation Pin alternate function; a pin defaults to the signal without the brackets.[ ] Refers to the physical connection on the package.pin Refers to the electrical signal encoding of a pin.signal 39June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table2.DocumentationConventions (continued) MeaningNotation Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (seeSIGNALand SIGNAL below). assert a signal Change the value of the signal from the logically True state to the logically False state.deassert a signal Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assertSIGNAL is to drive it Low; to deassertSIGNALis to drive it High. SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNALis to drive it High; to deassertSIGNALis to drive it Low. SIGNAL Numbers An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. X Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. June 12, 201440 Texas Instruments-Production Data About This Document

1 ArchitecturalOverview

Texas Instrument's Tiva™ C Series microcontrollers provide designers a high-performance ARM® Cortex™-M-based architecture with a broad set of integration capabilities and a strong ecosystem of software and development tools. Targeting performance and flexibility, the Tiva™ C Series architecture offers a 80 MHz Cortex-M with FPU, a variety of integrated memories and multiple programmable GPIO. Tiva™ C Series devices offer consumers compelling cost-effective solutions by integrating application-specific peripherals and providing a comprehensive library of software tools which minimize board costs and design-cycle time. Offering quicker time-to-market and cost savings, the Tiva™ C Series microcontrollers are the leading choice in high-performance 32-bit applications. This chapter contains an overview of the Tiva™ C Series microcontrollers as well as details on the TM4C1233D5PZ microcontroller: ■ “Tiva™ C Series Overview” on page 41 ■ “TM4C1233D5PZ Microcontroller Overview” on page 42 ■ “TM4C1233D5PZ Microcontroller Features” on page 44 ■ “TM4C1233D5PZ Microcontroller Hardware Details” on page 60 ■ “Kits” on page 61 ■ “Support Information” on page 61

1.1 Tiva™CSeriesOverview

The Tiva™ C Series ARM Cortex-M4 microcontrollers provide top performance and advanced integration. The product family is positioned for cost-conscious applications requiring significant control processing and connectivity capabilities such as: ■ Low power, hand-held smart devices ■ Gaming equipment ■ Home and commercial site monitoring and control ■ Motion control ■ Medical instrumentation ■ Test and measurement equipment ■ Factory automation ■ Fire and security ■ Smart Energy/Smart Grid solutions ■ Intelligent lighting control ■ Transportation For applications requiring extreme conservation of power, the TM4C1233D5PZ microcontroller features a battery-backed Hibernation module to efficiently power down the TM4C1233D5PZ to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a real-time counter (RTC), multiple wake-from-hibernate options, and dedicated battery-backed memory, the Hibernation module positions the TM4C1233D5PZ microcontroller perfectly for battery applications. In addition, the TM4C1233D5PZ microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, much of the TM4C1233D5PZ microcontroller code is compatible to the Tiva™ C Series product line, providing flexibility across designs. 41June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Texas Instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network.

1.2 TM4C1233D5PZMicrocontrollerOverview

The TM4C1233D5PZ microcontroller combines complex integration and high performance with the features shown in Table 1-1. Table1-1.TM4C1233D5PZMicrocontrollerFeatures DescriptionFeature Performance ARM Cortex-M4F processor coreCore 80-MHz operation; 100 DMIPS performancePerformance

64 KB single-cycle Flash memoryFlash

24 KB single-cycle SRAMSystem SRAM

Internal ROM loaded with TivaWare™ for C Series softwareInternal ROM Security CommunicationInterfaces Eight UARTsUniversal Asynchronous Receivers/Transmitter (UART) Four SSI modulesSynchronous Serial Interface (SSI) Six I2C modules with four transmission speeds including high-speed mode Inter-Integrated Circuit (I2C) CAN 2.0 A/B controllersController Area Network (CAN) USB 2.0 DeviceUniversal Serial Bus (USB) SystemIntegration ARM® PrimeCell® 32-channel configurable μDMA controllerMicro Direct Memory Access (µDMA) Six 16/32-bit GPTM blocks and six 32/64-bit Wide GPTM blocksGeneral-Purpose Timer (GPTM) Two watchdog timersWatchdog Timer (WDT) Low-power battery-backed Hibernation moduleHibernation Module (HIB) 10 physical GPIO blocksGeneral-Purpose Input/Output (GPIO) AnalogSupport Two 12-bit ADC modules, each with a maximum sample rate of one million samples/second Analog-to-Digital Converter (ADC) Three independent integrated analog comparatorsAnalog Comparator Controller 16 digital comparatorsDigital Comparator One JTAG module with integrated ARM SWDJTAG and Serial Wire Debug (SWD) PackageInformation 100-pin LQFPPackage Industrial (-40°C to 85°C) temperature rangeOperating Range (Ambient) Figure 1-1 on page 43 shows the features on the TM4C1233D5PZ microcontroller. Note that there are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB) bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back access performance than the APB bus. June 12, 201442 Texas Instruments-Production Data Architectural Overview

Figure1-1.Tiva ™ TM4C1233D5PZMicrocontrollerHigh-LevelBlockDiagram ARM® Cortex™-M4F (80MHz) NVIC MPU FPUETM Flash (64KB) Boot Loader DriverLib AES & CRC ROM DCode bus ICode bus JTAG/SWD System Control and Clocks (w/ Precis. Osc.) Bus Matrix System Bus SRAM (24KB) SYSTEM PERIPHERALS Watchdog Timer (2) DMA Hibernation Module EEPROM (2K) General- Purpose Timer (12) GPIOs (69) SERIAL PERIPHERALS UART (8) USB Device (FS PHY) I2C (6) SSI (4) CAN Controller (1) ANALOG PERIPHERALS 12- Bit ADC Channels (22) Analog Comparator (3) Advanced Peripheral Bus (APB) Advanced High-Performance Bus (AHB) TM4C1233D5PZ 43June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

1.3 TM4C1233D5PZMicrocontrollerFeatures

The TM4C1233D5PZ microcontroller component features and general function are discussed in more detail in the following section.

1.3.1 ARMCortex-M4FProcessorCore

All members of the Tiva™ C Series, including the TM4C1233D5PZ microcontroller, are designed around an ARM Cortex-M processor core. The ARM Cortex-M processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.

1.3.1.1 ProcessorCore (seepage62)

■ 32-bit ARM Cortex-M4F architecture optimized for small-footprint embedded applications ■ 80-MHz operation; 100 DMIPS performance ■ Outstanding processing performance combined with fast interrupt handling ■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications – Single-cycle multiply instruction and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control – Unaligned data access, enabling data to be efficiently packed into memory ■ IEEE754-compliant single-precision Floating-Point Unit (FPU) ■ 16-bit SIMD vector processing unit ■ Fast code execution permits slower processor clock or increases sleep mode time ■ Harvard architecture characterized by separate buses for instruction and data ■ Efficient processor core, system and memories ■ Hardware division and fast digital-signal-processing orientated multiply accumulate ■ Saturating arithmetic for signal processing ■ Deterministic, high-performance interrupt handling for time-critical applications ■ Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality ■ Enhanced system debug with extensive breakpoint and trace capabilities ■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing June 12, 201444 Texas Instruments-Production Data Architectural Overview

■ Migration from the ARM7™ processor family for better performance and power efficiency ■ Optimized for single-cycle Flash memory usage up to specific frequencies; see “Internal Memory” on page 507 for more information. ■ Ultra-low power consumption with integrated sleep modes

1.3.1.2 SystemTimer(SysTick) (seepage116)

ARM Cortex-M4F includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine ■ A high-speed alarm timer using the system clock ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter ■ A simple counter used to measure time to completion and time used ■ An internal clock-source control based on missing/meeting durations

1.3.1.3 NestedVectoredInterruptController(NVIC) (seepage117)

The TM4C1233D5PZ controller includes the ARM Nested Vectored Interrupt Controller (NVIC). The NVIC and Cortex-M4F prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that back-to-back interrupts can be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 72 interrupts. ■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining (these values reflect no FPU stacking) ■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler for safety critical applications ■ Dynamically reprioritizable interrupts ■ Exceptional interrupt handling via hardware implementation of required register manipulations

1.3.1.4 SystemControlBlock(SCB) (seepage118)

The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions.

1.3.1.5 MemoryProtectionUnit(MPU) (seepage118)

The MPU supports the standard ARM7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 45June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

1.3.1.6 Floating-PointUnit(FPU) (seepage123)

The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions. ■ 32-bit instructions for single-precision (C float) data-processing operations ■ Combined multiply and accumulate instructions for increased precision (Fused MAC) ■ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate, division, and square-root ■ Hardware support for denormals and all IEEE rounding modes ■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers ■ Decoupled three stage pipeline

1.3.2 On-ChipMemory

The TM4C1233D5PZ microcontroller is integrated with the following set of on-chip memory and features: ■ 24 KB single-cycle SRAM ■ 64 KB Flash memory ■ 2KB EEPROM ■ Internal ROM loaded with TivaWare™ for C Series software: – TivaWare ™ Peripheral Driver Library – TivaWare Boot Loader – Advanced Encryption Standard (AES) cryptography tables – Cyclic Redundancy Check (CRC) error detection functionality

1.3.2.1 SRAM (seepage508)

The TM4C1233D5PZ microcontroller provides 24 KB of single-cycle on-chip SRAM. The internal SRAM of the device is located at offset 0x2000.0000 of the device memory map. Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding technology in the Cortex-M4F processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. Data can be transferred to and from SRAM by the following masters: ■ µDMA ■ USB

1.3.2.2 FlashMemory (seepage511)

The TM4C1233D5PZ microcontroller provides 64 KB of single-cycle on-chip Flash memory. The Flash memory is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of June 12, 201446 Texas Instruments-Production Data Architectural Overview

2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger.

1.3.2.3 ROM (seepage509)

The TM4C1233D5PZ ROM is preprogrammed with the following software and programs: ■ TivaWare Peripheral Driver Library ■ TivaWare Boot Loader ■ Advanced Encryption Standard (AES) cryptography tables ■ Cyclic Redundancy Check (CRC) error-detection functionality The TivaWare Peripheral Driver Library is a royalty-free software library for controlling on-chip peripherals with a boot-loader capability. The library performs both peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library is designed to take full advantage of the stellar interrupt performance of the ARM Cortex-M4F core. No special pragmas or custom assembly code prologue/epilogue functions are required. For applications that require in-field programmability, the royalty-free TivaWare Boot Loader can act as an application loader and support in-field firmware updates. The Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the U.S. Government. AES is a strong encryption method with reasonable performance and size. In addition, it is fast in both hardware and software, is fairly easy to implement, and requires little memory. The Texas Instruments encryption package is available with full source code, and is based on Lesser General Public License (LGPL) source. An LGPL means that the code can be used within an application without any copyleft implications for the application (the code does not automatically become open source). Modifications to the package source, however, must be open source. CRC (Cyclic Redundancy Check) is a technique to validate a span of data has the same contents as when previously checked. This technique can be used to validate correct receipt of messages (nothing lost or modified in transit), to validate data after decompression, to validate that Flash memory contents have not been changed, and for other cases where the data needs to be validated. A CRC is preferred over a simple checksum (for example, XOR all bits) because it catches changes more readily.

1.3.2.4 EEPROM (seepage517)

The TM4C1233D5PZ microcontroller includes an EEPROM with the following features: ■ 2Kbytes of memory accessible as 512 32-bit words ■ 32 blocks of 16 words (64 bytes) each ■ Built-in wear leveling ■ Access protection per block ■ Lock protection option for the whole peripheral as well as per block using 32-bit to 96-bit unlock codes (application selectable) 47June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

■ Interrupt support for write completion to avoid polling ■ Endurance of 500K writes (when writing at fixed offset in every alternate page in circular fashion) to 15M operations (when cycling through two pages ) per each 2-page block.

1.3.3 SerialCommunicationsPeripherals

The TM4C1233D5PZ controller supports both asynchronous and synchronous serial communications with: ■ CAN 2.0 A/B controller ■ USB 2.0 Device ■ Eight UARTs with IrDA, 9-bit and ISO 7816 support. ■ Six I2C modules with four transmission speeds including high-speed mode ■ Four Synchronous Serial Interface modules (SSI) The following sections provide more detail on each of these communications functions.

1.3.3.1 ControllerAreaNetwork(CAN)(seepage1038)

Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy environments and can utilize a differential balanced line like RS-485 or twisted-pair wire. Originally created for automotive purposes, it is now used in many embedded control applications (for example, industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at 500m). A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis of the identifier received whether it should process the message. The identifier also determines the priority that the message enjoys in competition for bus access. Each CAN message can transmit from 0 to 8 bytes of user information. The TM4C1233D5PZ microcontroller includes one CAN unit with the following features: ■ CAN protocol version 2.0 part A/B ■ Bit rates up to 1 Mbps ■ 32 message objects with individual identifier masks ■ Maskable interrupt ■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications ■ Programmable loopback mode for self-test operation ■ Programmable FIFO mode enables storage of multiple message objects ■ Gluelessly attaches to an external CAN transceiver through theCANnTXand CANnRXsignals June 12, 201448 Texas Instruments-Production Data Architectural Overview

1.3.3.2 UniversalSerialBus(USB) (seepage1088)

Universal Serial Bus (USB) is a serial bus standard designed to allow peripherals to be connected and disconnected using a standardized interface without rebooting the system. The TM4C1233D5PZ microcontroller supports the USB 2.0 full-speed configuration in Device mode. The USB module has the following features: ■ Complies with USB-IF (Implementer's Forum) certification standards ■ USB 2.0 full-speed (12 Mbps) operation with integrated PHY ■ 4 transfer types: Control, Interrupt, Bulk, and Isochronous ■ 16 endpoints – 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint – 7 configurable IN endpoints and 7 configurable OUT endpoints ■ 4 KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte isochronous packet size ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive for up to three IN endpoints and three OUT endpoints – Channel requests asserted when FIFO contains required amount of data

1.3.3.3 UART (seepage881)

A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The TM4C1233D5PZ microcontroller includes eight fully programmable 16C550-type UARTs. Although the functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART can generate individually masked interrupts from the Rx, Tx, modem flow control, modem status, and error conditions. The module generates a single combined interrupt when any of the interrupts are asserted and are unmasked. The eight UARTs have the following features: ■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by 16) and 10 Mbps for high speed (divide by 8) ■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ■ Standard asynchronous communication bits for start, stop, and parity ■ Line-break generation and detection 49June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

■ Fully programmable serial interface characteristics – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing – Programmable use of IrDA Serial Infrared (SIR) or UART input/output – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration ■ Support for communication with ISO 7816 smart cards ■ Modem flow control and status (on UART1) ■ EIA-485 9-bit support ■ Standard FIFO-level and End-of-Transmission interrupts ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level

1.3.3.4 I 2C (seepage987)

The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. Each device on the I2C bus can be designated as either a master or a slave. I2C module supports both sending and receiving data as either a master or a slave and can operate simultaneously as both a master and a slave. Both the I2C master and slave can generate interrupts. The TM4C1233D5PZ microcontroller includes six I2C modules with the following features: ■ Devices on the I2C bus can be designated as either a master or a slave – Supports both transmitting and receiving data as either a master or a slave – Supports simultaneous master and slave operation June 12, 201450 Texas Instruments-Production Data Architectural Overview

■ Four I2C modes – Master transmit – Master receive – Slave transmit – Slave receive ■ Four transmission speeds: – Standard (100 Kbps) – Fast-mode (400 Kbps) – Fast-mode plus (1 Mbps) – High-speed mode (3.33 Mbps) ■ Clock low timeout interrupt ■ Dual slave address capability ■ Glitch suppression ■ Master and slave interrupt generation – Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) – Slave generates interrupts when data has been transferred or requested by a master or when a START or STOP condition is detected ■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode

1.3.3.5 SSI (seepage942)

Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface that converts data between parallel and serial. The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. The TM4C1233D5PZ microcontroller includes four SSI modules with the following features: ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ Master or slave operation 51June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

■ Programmable clock bit rate and prescaler ■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep ■ Programmable data frame size from 4 to 16 bits ■ Internal loopback test mode for diagnostic/debug testing ■ Standard FIFO-based interrupts and End-of-Transmission interrupt ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted when FIFO contains 4 entries – Transmit single request asserted when there is space in the FIFO; burst request asserted when four or more entries are available to be written in the FIFO

1.3.4 SystemIntegration

The TM4C1233D5PZ microcontroller provides a variety of standard system functions integrated into the device, including: ■ Direct Memory Access Controller (DMA) ■ System control and clocks including on-chip precision 16-MHz oscillator ■ Six 32-bit timers (up to twelve 16-bit) ■ Six wide 64-bit timers (up to twelve 32-bit) ■ Twelve 32/64-bit Capture Compare PWM (CCP) pins ■ Lower-power battery-backed Hibernation module ■ Real-Time Clock in Hibernation module ■ Two Watchdog Timers – One timer runs off the main oscillator – One timer runs off the precision internal oscillator ■ Up to 69 GPIOs, depending on configuration – Highly flexible pin muxing allows use as GPIO or one of several peripheral functions – Independently configurable to 2-, 4- or 8-mA drive capability – Up to 4 GPIOs can have 18-mA drive capability The following sections provide more detail on each of these functions.

1.3.4.1 DirectMemoryAccess (seepage567)

The TM4C1233D5PZ microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex-M4F processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has June 12, 201452 Texas Instruments-Production Data Architectural Overview

dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The μDMA controller provides the following features: ■ ARM PrimeCell® 32-channel configurable µDMA controller ■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes – Basic for simple transfer scenarios – Ping-pong for continuous data flow – Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single request ■ Highly flexible and configurable channel operation – Independently configured and operated channels – Dedicated channels for supported on-chip modules – Flexible channel assignments – One channel each for receive and transmit path for bidirectional modules – Dedicated channel for software-initiated transfers – Per-channel configurable priority scheme – Optional software-initiated requests for any channel ■ Two levels of priority ■ Design optimizations for improved bus access performance between µDMA controller and the processor core – µDMA controller access is subordinate to core access – RAM striping – Peripheral bus segmentation ■ Data sizes of 8, 16, and 32 bits ■ Transfer size is programmable in binary steps from 1 to 1024 ■ Source and destination address increment size of byte, half-word, word, or no increment ■ Maskable peripheral requests ■ Interrupt on transfer completion, with a separate interrupt per channel 53June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

1.3.4.2 SystemControlandClocks (seepage205)

System control determines the overall operation of the device. It provides information about the device, controls power-saving features, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. ■ Device identification information: version, part number, SRAM size, Flash memory size, and so on ■ Power control – On-chip fixed Low Drop-Out (LDO) voltage regulator – Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits – Low-power options for microcontroller: Sleep and Deep-Sleep modes with clock gating – Low-power options for on-chip modules: software controls shutdown of individual peripherals and memory – 3.3-V supply brown-out detection and reporting via interrupt or reset ■ Multiple clock sources for microcontroller system clock. The following clock sources are provided to the TM4C1233D5PZ microcontroller: – Precision Internal Oscillator (PIOSC) providing a 16-MHz frequency

16 MHz ±3% across temperature and voltage•

• Can be recalibrated with 7-bit trim resolution to achieve better accuracy (16 MHz ±1%)
• Software power down control for low power modes – Main Oscillator (MOSC): A frequency-accurate clock source by one of two means: an external single-ended clock source is connected to theOSC0input pin, or an external crystal is connected across theOSC0input andOSC1output pins. – Low Frequency Internal Oscillator (LFIOSC): On-chip resource used during power-saving modes – Hibernate RTC oscillator (RTCOSC) clock that can be configured to be the 32.768-kHz external oscillator source from the Hibernation (HIB) module or the HIB Low Frequency clock source (HIB LFIOSC), which is located within the Hibernation Module. ■ Flexible reset sources – Power-on reset (POR) – Reset pin assertion – Brown-out reset (BOR) detector alerts to system power drops – Software reset – Watchdog timer reset – MOSC failure June 12, 201454 Texas Instruments-Production Data Architectural Overview

1.3.4.3 ProgrammableTimers (seepage690)

Programmable timers can be used to count or time external events that drive the Timer input pins. Each 16/32-bit GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Each 32/64-bit Wide GPTM block provides two 32-bit timers/counters that can be configured to operate independently as timersor event counters, or configured to operate as one 64-bit timer or one 64-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions and DMA transfers. The General-Purpose Timer Module (GPTM) contains six 16/32-bit GPTM blocks and six 32/64-bit Wide GPTM blocks with the following functional options: ■ 16/32-bit operating modes: – 16- or 32-bit programmable one-shot timer – 16- or 32-bit programmable periodic timer – 16-bit general-purpose timer with an 8-bit prescaler – 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input – 16-bit input-edge count- or time-capture modes with an 8-bit prescaler – 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM signal ■ 32/64-bit operating modes: – 32- or 64-bit programmable one-shot timer – 32- or 64-bit programmable periodic timer – 32-bit general-purpose timer with a 16-bit prescaler – 64-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input – 32-bit input-edge count- or time-capture modes with a16-bit prescaler – 32-bit PWM mode with a 16-bit prescaler and software-programmable output inversion of the PWM signal ■ Count up or down ■ Twelve 16/32-bit Capture Compare PWM pins (CCP) ■ Twelve 32/64-bit Capture Compare PWM pins (CCP) ■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events ■ Timer synchronization allows selected timers to start counting on the same clock cycle ■ ADC event trigger ■ User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding RTC mode) 55June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each timer – Burst request generated on timer interrupt

1.3.4.4 CCPPins (seepage699)

Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM output on the CCP pin. The TM4C1233D5PZ microcontroller includes twelve 16/32-bit CCP pins that can be programmed to operate in the following modes: ■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input. The GP Timer captures and stores the current timer value when a programmed event occurs. ■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input. The GP Timer compares the current value with a stored value and generates an interrupt when a match occurs. ■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated based on a match between the counter value and a value stored in a match register and is output on the CCP pin.

1.3.4.5 HibernationModule(HIB) (seepage476)

The Hibernation module provides logic to switch power off to the main processor and peripherals and to wake on external or time-based events. The Hibernation module includes power-sequencing logic and has the following features: ■ 32-bit real-time seconds counter (RTC) with 1/32,768 second resolution and a 15-bit sub-seconds counter – 32-bit RTC seconds match register and a 15-bit sub seconds match for timed wake-up and interrupt generation with 1/32,768 second resolution – RTC predivider trim for making fine adjustments to the clock rate ■ Two mechanisms for power control – System power control using discrete external regulator – On-chip power control using internal switches under register control ■ Dedicated pin for waking using an external signal ■ RTC operational and hibernation memory valid as long as VDD or VBAT is valid ■ Low-battery detection, signaling, and interrupt generation, with optional wake on low battery ■ GPIO pin state can be retained during hibernation June 12, 201456 Texas Instruments-Production Data Architectural Overview

■ Clock source from a 32.768-kHz external crystal or oscillator ■ Sixteen 32-bit words of battery-backed memory to save state during hibernation ■ Programmable interrupts for: – RTC match – External wake – Low battery

1.3.4.6 WatchdogTimers (seepage760)

A watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The TM4C1233D5PZ Watchdog Timer can generate an interrupt, a non-maskable interrupt, or a reset when a time-out value is reached. In addition, the Watchdog Timer is ARM FiRM-compliant and can be configured to generate an interrupt to the microcontroller on its first time-out, and to generate a reset signal on its second timeout. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. The TM4C1233D5PZ microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Watchdog Timer module has the following features: ■ 32-bit down counter with a programmable load register ■ Separate watchdog clock with an enable ■ Programmable interrupt generation logic with interrupt masking and optional NMI function ■ Lock register protection from runaway software ■ Reset generation logic with an enable/disable ■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug

1.3.4.7 ProgrammableGPIOs (seepage631)

General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The TM4C1233D5PZ GPIO module is comprised of ten physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 0-69 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 1161 for the signals available to each GPIO pin). ■ Up to 69 GPIOs, depending on configuration ■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions ■ 5-V-tolerant in input configuration ■ Fast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for ports on APB ■ Programmable control for GPIO interrupts 57June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

– Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ Bit masking in both read and write operations through address lines ■ Can be used to initiate an ADC sample sequence or a μDMA transfer ■ Pin state can be retained during Hibernation mode ■ Pins configured as digital inputs are Schmitt-triggered ■ Programmable control for GPIO pad configuration – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA for high-current applications – Slew rate control for 8-mA pad drive – Open drain enables – Digital input enables

1.3.5 Analog

The TM4C1233D5PZ microcontroller provides analog functions integrated into the device, including: ■ Two 12-bit Analog-to-Digital Converters (ADC), with a total of 22 analog input channels and each with a sample rate of one million samples/second ■ Three analog comparators ■ On-chip voltage regulator The following provides more detail on these analog functions.

1.3.5.1 ADC (seepage785)

An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The TM4C1233D5PZ ADC module features 12-bit conversion resolution and supports 22 input channels plus an internal temperature sensor. Four buffered sample sequencers allow rapid sampling of up to 22 analog input sources without controller intervention. Each sample sequencer provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequencer priority. Each ADC module has a digital comparator function that allows the conversion value to be diverted to a comparison unit that provides eight digital comparators. The TM4C1233D5PZ microcontroller provides two ADC modules, each with the following features: ■ 22 shared analog input channels ■ 12-bit precision ADC June 12, 201458 Texas Instruments-Production Data Architectural Overview

■ Single-ended and differential-input configurations ■ On-chip internal temperature sensor ■ Maximum sample rate of one million samples/second ■ Optional phase shift in sample time programmable from 22.5º to 337.5º ■ Four programmable sample conversion sequencers from one to eight entries long, with corresponding conversion result FIFOs ■ Flexible trigger control – Controller (software) – Timers – Analog Comparators – GPIO ■ Hardware averaging of up to 64 samples ■ Eight digital comparators ■ Converter uses two external reference signals (VREFA+and VREFA-) orVDDAand GNDAas the voltage reference ■ Power and ground for the analog circuitry is separate from the digital power and ground ■ Efficient transfers using Micro Direct Memory Access Controller (µDMA) – Dedicated channel for each sample sequencer – ADC module uses burst requests for DMA

1.3.5.2 AnalogComparators (seepage1144)

An analog comparator is a peripheral that compares two analog voltages and provides a logical output that signals the comparison result. The TM4C1233D5PZ microcontroller provides three independent integrated analog comparators that can be configured to drive an output or generate an interrupt or ADC event. The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. The TM4C1233D5PZ microcontroller provides three independent integrated analog comparators with the following functions: ■ Compare external pin input to external pin input or to internal programmable voltage reference ■ Compare a test voltage against any one of the following voltages: – An individual external reference voltage 59June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

– A shared single external reference voltage – A shared internal reference voltage

1.3.6 JTAGandARMSerialWireDebug (seepage193)

The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas Instruments replaces the ARM SW-DP and JTAG-DP with the ARM Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module providing all the normal JTAG debug and test functionality plus real-time access to system memory without halting the core or requiring any target resident code. The SWJ-DP interface has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Embedded Trace Macrocell (ETM) for instruction trace capture – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer

1.3.7 PackagingandTemperature

■ 100-pin RoHS-compliant LQFP package ■ Industrial (-40°C to 85°C) ambient temperature range

1.4 TM4C1233D5PZMicrocontrollerHardwareDetails

Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 1160 ■ “Signal Tables” on page 1161 ■ “Electrical Characteristics” on page 1191 June 12, 201460 Texas Instruments-Production Data Architectural Overview

■ “Package Information” on page 1236

1.5 Kits

The Tiva™ C Series provides the hardware and software tools that engineers need to begin development quickly. ■ Reference Design Kits accelerate product development by providing ready-to-run hardware and comprehensive documentation including hardware design files ■ Evaluation Kits provide a low-cost and effective means of evaluating TM4C1233D5PZ microcontrollers before purchase ■ Development Kits provide you with all the tools you need to develop and prototype embedded applications right out of the box See the Tiva series website athttp://www.ti.com/tiva-c for the latest tools available, or ask your distributor.

1.6 SupportInformation

For support on Tiva™ C Series products, contact theTI Worldwide Product Information Center nearest you. 61June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

2 TheCortex-M4FProcessor

The ARM® Cortex™-M4F processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: ■ 32-bit ARM® Cortex™-M4F architecture optimized for small-footprint embedded applications ■ 80-MHz operation; 100 DMIPS performance ■ Outstanding processing performance combined with fast interrupt handling ■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications – Single-cycle multiply instruction and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control – Unaligned data access, enabling data to be efficiently packed into memory ■ IEEE754-compliant single-precision Floating-Point Unit (FPU) ■ 16-bit SIMD vector processing unit ■ Fast code execution permits slower processor clock or increases sleep mode time ■ Harvard architecture characterized by separate buses for instruction and data ■ Efficient processor core, system and memories ■ Hardware division and fast digital-signal-processing orientated multiply accumulate ■ Saturating arithmetic for signal processing ■ Deterministic, high-performance interrupt handling for time-critical applications ■ Memory protection unit (MPU) to provide a privileged mode for protected operating system functionality ■ Enhanced system debug with extensive breakpoint and trace capabilities ■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing ■ Migration from the ARM7™ processor family for better performance and power efficiency ■ Optimized for single-cycle Flash memory usage up to specific frequencies; see “Internal Memory” on page 507 for more information. ■ Ultra-low power consumption with integrated sleep modes June 12, 201462 Texas Instruments-Production Data The Cortex-M4F Processor

The Tiva™ C Series microcontrollers builds on this core to bring high-performance 32-bit computing to This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4F processor, including the programming model, the memory model, the exception model, fault handling, and power management. For technical details on the instruction set, see the Cortex™-M4 instruction set chapter in theARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A ).

2.1 BlockDiagram

The Cortex-M4F processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including IEEE754-compliant single-precision floating-point computation, a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division. To facilitate the design of cost-sensitive devices, the Cortex-M4F processor implements tightly coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M4F processor implements a version of the Thumb® instruction set based on Thumb-2 technology, ensuring high code density and reduced program memory requirements. The Cortex-M4F instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M4F processor closely integrates a nested interrupt controller (NVIC), to deliver industry-leading interrupt performance. The TM4C1233D5PZ NVIC includes a non-maskable interrupt (NMI) and provides eight interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be rapidly powered down. 63June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Figure2-1.CPUBlockDiagram Private Peripheral Bus ( internal) Data W atchpoint and T race Interrupts Debug Sleep Instrumentation T race Macrocell T race Port Interface Unit CM 4 Core Instructions Data Flash Patch and Breakpoint Memory Protection Unit Debug Access Port Nested V ectored Interrupt Controller Serial Wire JT AG Debug Port Bus Matrix Adv . Peripheral Bus I-code bus D-code bus System bus ROM T able Serial Wire Output T race Port ( SWO) ARM Cortex -M 4 F FPU Embedded T race Macrocell

2.2 Overview

2.2.1 System-LevelInterface

The Cortex-M4F processor provides multiple interfaces using AMBA® technology to provide high-speed, low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data handling. The Cortex-M4F processor has a memory protection unit (MPU) that provides fine-grain memory control, enabling applications to implement security privilege levels and separate code, data and stack on a task-by-task basis.

2.2.2 IntegratedConfigurableDebug

The Cortex-M4F processor implements a complete hardware debug solution, providing high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Tiva™ C Series implementation replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See theARM® Debug Interface V5 Architecture Specification for details on SWJ-DP . For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. June 12, 201464 Texas Instruments-Production Data The Cortex-M4F Processor

The Embedded Trace Macrocell (ETM) delivers unrivaled instruction trace capture in an area smaller than traditional trace units, enabling full instruction trace. For more details on the ARM ETM, see the ARM® Embedded Trace Macrocell Architecture Specification . The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions for up to eight words of program code in the code memory region. This FPB enables applications stored in a read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory. If a patch is required, the application programs the FPB to remap a number of addresses. When those addresses are accessed, the accesses are redirected to a remap table specified in the FPB configuration. For more information on the Cortex-M4F debug capabilities, see theARM® Debug Interface V5 Architecture Specification.

2.2.3 TracePortInterfaceUnit(TPIU)

The TPIU acts as a bridge between the Cortex-M4F trace data from the ITM, and an off-chip Trace Port Analyzer, as shown in Figure 2-2 on page 65. Figure2-2.TPIUBlockDiagram ARM® T race Bus (A TB) Interface Asynchronous FIFO Advance Peripheral Bus (APB) Interface T race Out ( serializer) Debug A TB Slave Port APB Slave Port Serial Wire T race Port ( SWO)

2.2.4 Cortex-M4FSystemComponentDetails

The Cortex-M4F includes the following system components: ■ SysTick A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer or as a simple counter (see “System Timer (SysTick)” on page 116). ■ Nested Vectored Interrupt Controller (NVIC) 65June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

An embedded interrupt controller that supports low latency interrupt processing (see “Nested Vectored Interrupt Controller (NVIC)” on page 117). ■ System Control Block (SCB) The programming model interface to the processor. The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions (see “System Control Block (SCB)” on page 118). ■ Memory Protection Unit (MPU) Improves system reliability by defining the memory attributes for different memory regions. The MPU provides up to eight different regions and an optional predefined background region (see “Memory Protection Unit (MPU)” on page 118). ■ Floating-Point Unit (FPU) Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square-root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions (see “Floating-Point Unit (FPU)” on page 123).

2.3 ProgrammingModel

This section describes the Cortex-M4F programming model. In addition to the individual core register descriptions, information about the processor modes and privilege levels for software execution and stacks is included.

2.3.1 ProcessorModeandPrivilegeLevelsforSoftwareExecution

The Cortex-M4F has two modes of operation: ■ Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset. ■ Handler mode Used to handle exceptions. When the processor has finished exception processing, it returns to Thread mode. In addition, the Cortex-M4F has two privilege levels: ■ Unprivileged In this mode, software has the following restrictions: – Limited access to theMSRand MRSinstructions and no use of theCPSinstruction – No access to the system timer, NVIC, or system control block – Possibly restricted access to memory or peripherals ■ Privileged In this mode, software can use all the instructions and has access to all resources. In Thread mode, theCONTROLregister (see page 81) controls whether software execution is privileged or unprivileged. In Handler mode, software execution is always privileged. June 12, 201466 Texas Instruments-Production Data The Cortex-M4F Processor

Only privileged software can write to theCONTROLregister to change the privilege level for software execution in Thread mode. Unprivileged software can use theSVCinstruction to make a supervisor call to transfer control to privileged software.

2.3.2 Stacks

The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements two stacks: the main stack and the process stack, with a pointer for each held in independent registers (see the SPregister on page 71). In Thread mode, theCONTROLregister (see page 81) controls whether the processor uses the main stack or the process stack. In Handler mode, the processor always uses the main stack. The options for processor operations are shown in Table 2-1 on page 67. Table2-1.SummaryofProcessorMode,PrivilegeLevel,andStackUse StackUsedPrivilegeLevelUseProcessorMode Main stack or process stackaPrivileged or unprivilegedaApplicationsThread Main stackAlways privilegedException handlersHandler a. SeeCONTROL(page 81).

2.3.3 RegisterMap

Figure 2-3 on page 68 shows the Cortex-M4F register set. Table 2-2 on page 68 lists the Core registers. The core registers are not memory mapped and are accessed by register name, so the base address is n/a (not applicable) and there is no offset. 67June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Figure2-3.Cortex-M4FRegisterSet SP (R13) LR (R14) PC (R15) R 0 R 1 R 3 R 4 R 2 R10 R1 1 R12 L ow registers H igh registers M SP P S P PSR PRIMASK F AUL TMASK BASEPRI CONTROL General-purpose registers Stack Pointer Link Register Program Counter Program status register Exception mask registers CONTROL register Special registers Banked version of SP Table2-2.ProcessorRegisterMap See pageDescriptionResetTypeNameOffset 70Cortex General-Purpose Register 0-RWR0 - 70Cortex General-Purpose Register 1-RWR1 - 70Cortex General-Purpose Register 2-RWR2 - 70Cortex General-Purpose Register 3-RWR3 - 70Cortex General-Purpose Register 4-RWR4 - 70Cortex General-Purpose Register 5-RWR5 - 70Cortex General-Purpose Register 6-RWR6 - 70Cortex General-Purpose Register 7-RWR7 - 70Cortex General-Purpose Register 8-RWR8 - 70Cortex General-Purpose Register 9-RWR9 - 70Cortex General-Purpose Register 10-RWR10- 70Cortex General-Purpose Register 11-RWR11- June 12, 201468 Texas Instruments-Production Data The Cortex-M4F Processor

Table2-2.ProcessorRegisterMap (continued) See pageDescriptionResetTypeNameOffset 70Cortex General-Purpose Register 12-RWR12- 71Stack Pointer-RWSP - 72Link Register0xFFFF.FFFFRWLR - 73Program Counter-RWPC - 74Program Status Register0x0100.0000RWPSR- 78Priority Mask Register0x0000.0000RWPRIMASK- 79Fault Mask Register0x0000.0000RWFAULTMASK- 80Base Priority Mask Register0x0000.0000RWBASEPRI- 81Control Register0x0000.0000RWCONTROL- 83Floating-Point Status Control-RWFPSC-

2.3.4 RegisterDescriptions

This section lists and describes the Cortex-M4F registers, in the order shown in Figure 2-3 on page 68. The core registers are not memory mapped and are accessed by register name rather than offset. Note: The register type shown in the register descriptions refers to type during program execution in Thread mode and Handler mode. Debug access can differ. 69June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register1:CortexGeneral-PurposeRegister0(R0) Register2:CortexGeneral-PurposeRegister1(R1) Register3:CortexGeneral-PurposeRegister2(R2) Register4:CortexGeneral-PurposeRegister3(R3) Register5:CortexGeneral-PurposeRegister4(R4) Register6:CortexGeneral-PurposeRegister5(R5) Register7:CortexGeneral-PurposeRegister6(R6) Register8:CortexGeneral-PurposeRegister7(R7) Register9:CortexGeneral-PurposeRegister8(R8) Register10:CortexGeneral-PurposeRegister9(R9) Register11:CortexGeneral-PurposeRegister10(R10) Register12:CortexGeneral-PurposeRegister11(R11) Register13:CortexGeneral-PurposeRegister12(R12) The Rnregisters are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode. Cortex General-Purpose Register 0 (R0) Type RW, reset - 16171819202122232425262728293031 DATA RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0123456789101112131415 DATA RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType DescriptionResetTypeNameBit/Field Register data.-RWDATA31:0 June 12, 201470 Texas Instruments-Production Data The Cortex-M4F Processor

Register14:StackPointer(SP) The StackPointer(SP) is register R13. In Thread mode, the function of this register changes depending on theASPbit in theControlRegister(CONTROL) register. When theASPbit is clear, this register is theMainStackPointer(MSP) . When theASPbit is set, this register is theProcess StackPointer(PSP) . On reset, theASPbit is clear, and the processor loads theMSPwith the value from address 0x0000.0000. TheMSPcan only be accessed in privileged mode; thePSPcan be accessed in either privileged or unprivileged mode. Stack Pointer (SP) Type RW, reset - 16171819202122232425262728293031 SP RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0123456789101112131415 SP RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType DescriptionResetTypeNameBit/Field This field is the address of the stack pointer.-RWSP31:0 71June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register15:LinkRegister(LR) The LinkRegister(LR ) is register R14, and it stores the return information for subroutines, function calls, and exceptions. The Link Register can be accessed from either privileged or unprivileged mode. EXC_RETURNis loaded into theLRon exception entry. See Table 2-10 on page 104 for the values and description. Link Register (LR) Type RW, reset 0xFFFF.FFFF 16171819202122232425262728293031 LINK RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1111111111111111Reset 0123456789101112131415 LINK RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1111111111111111Reset DescriptionResetTypeNameBit/Field This field is the return address.0xFFFF.FFFFRWLINK31:0 June 12, 201472 Texas Instruments-Production Data The Cortex-M4F Processor

Register16:ProgramCounter(PC) The ProgramCounter(PC) is register R15, and it contains the current program address. On reset, the processor loads thePCwith the value of the reset vector, which is at address 0x0000.0004. Bit 0 of the reset vector is loaded into theTHUMBbit of theEPSRat reset and must be 1. ThePCregister can be accessed in either privileged or unprivileged mode. Program Counter (PC) Type RW, reset - 16171819202122232425262728293031 PC RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0123456789101112131415 PC RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType DescriptionResetTypeNameBit/Field This field is the current program address.-RWPC31:0 73June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register17:ProgramStatusRegister(PSR) Note: This register is also referred to asxPSR. The ProgramStatusRegister(PSR) has three functions, and the register bits are assigned to the different functions: ■ ApplicationProgramStatusRegister(APSR) , bits 31:27, bits 19:16 ■ ExecutionProgramStatusRegister(EPSR) , bits 26:24, 15:10 ■ InterruptProgramStatusRegister(IPSR) , bits 7:0 The PSR, IPSR, andEPSRregisters can only be accessed in privileged mode; theAPSRregister can be accessed in either privileged or unprivileged mode. APSRcontains the current state of the condition flags from previous instruction executions. EPSRcontains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read theEPSRdirectly through application software using theMSRinstruction always return zero. Attempts to write theEPSRusing theMSRinstruction in application software are always ignored. Fault handlers can examine theEPSRvalue in the stackedPSRto determine the operation that faulted (see “Exception Entry and Return” on page 101). IPSRcontains the exception type number of the current Interrupt Service Routine (ISR). These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument to theMSRor MRSinstructions. For example, all of the registers can be read usingPSRwith theMRSinstruction, orAPSRonly can be written to using APSRwith theMSRinstruction. page 74 shows the possible register combinations for thePSR. See the MRSand MSRinstruction descriptions in the Cortex™-M4 instruction set chapter in theARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information about how to access the program status registers. Table2-3.PSRRegisterCombinations CombinationTypeRegister APSR, EPSR, andIPSRRWa, bPSR EPSRand IPSRROIEPSR APSRand IPSRRWaIAPSR APSRand EPSRRWbEAPSR a. The processor ignores writes to theIPSRbits. b. Reads of theEPSRbits return zero, and the processor ignores writes to these bits. Program Status Register (PSR) Type RW, reset 0x0100.0000 16171819202122232425262728293031 GEreservedTHUMBICI / ITQVCZN RWRWRWRWRORORORORORORORWRWRWRWRWType 0000000010000000Reset 0123456789101112131415 ISRNUMreservedICI / IT ROROROROROROROROROROROROROROROROType 0000000000000000Reset June 12, 201474 Texas Instruments-Production Data The Cortex-M4F Processor

DescriptionResetTypeNameBit/Field APSRNegative or Less Flag DescriptionValue The previous operation result was negative or less than.1 The previous operation result was positive, zero, greater than, or equal. The value of this bit is only meaningful when accessingPSRor APSR. 0RWN31 APSRZero Flag DescriptionValue The previous operation result was zero.1 The previous operation result was non-zero.0 The value of this bit is only meaningful when accessingPSRor APSR. 0RWZ30 APSRCarry or Borrow Flag DescriptionValue The previous add operation resulted in a carry bit or the previous subtract operation did not result in a borrow bit. The previous add operation did not result in a carry bit or the previous subtract operation resulted in a borrow bit. The value of this bit is only meaningful when accessingPSRor APSR. 0RWC29 APSROverflow Flag DescriptionValue The previous operation resulted in an overflow.1 The previous operation did not result in an overflow.0 The value of this bit is only meaningful when accessingPSRor APSR. 0RWV28 APSRDSP Overflow and Saturation Flag DescriptionValue DSP Overflow or saturation has occurred when using a SIMD instruction. DSP overflow or saturation has not occurred since reset or since the bit was last cleared. The value of this bit is only meaningful when accessingPSRor APSR. This bit is cleared by software using anMRSinstruction. 0RWQ27 75June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field EPSRICI / IT status These bits, along with bits 15:10, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of theITinstruction. When EPSRholds theICIexecution state, bits 26:25 are zero. The If-Then block contains up to four instructions following anIT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex™-M4 instruction set chapter in theARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information. The value of this field is only meaningful when accessingPSRor EPSR. Note that theseEPSRbits cannot be accessed usingMRSand MSR instructions but the definitions are provided to allow the stacked (E)PSR value to be decoded within an exception handler. 0x0ROICI / IT26:25 EPSRThumb State This bit indicates the Thumb state and should always be set. The following can clear theTHUMBbit: ■ The BLX, BXand POP{PC}instructions ■ Restoration from the stackedxPSRvalue on an exception return ■ Bit 0 of the vector value on an exception entry or reset Attempting to execute instructions when this bit is clear results in a fault or lockup. See “Lockup” on page 106 for more information. The value of this bit is only meaningful when accessingPSRor EPSR. 1ROTHUMB24 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved23:20 Greater Than or Equal Flags See the description of theSELinstruction in the Cortex™-M4 instruction set chapter in theARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A ) for more information. The value of this field is only meaningful when accessingPSRor APSR. 0x0RWGE19:16 June 12, 201476 Texas Instruments-Production Data The Cortex-M4F Processor

DescriptionResetTypeNameBit/Field EPSRICI / IT status These bits, along with bits 26:25, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of theITinstruction. When an interrupt occurs during the execution of anLDM, STM, PUSH POP, VLDM, VSTM, VPUSH, orVPOPinstruction, the processor stops the load multiple or store multiple instruction operation temporarily and stores the next register operand in the multiple operation to bits 15:12. After servicing the interrupt, the processor returns to the register pointed to by bits 15:12 and resumes execution of the multiple load or store instruction. WhenEPSRholds theICIexecution state, bits 11:10 are zero. The If-Then block contains up to four instructions following a 16-bitIT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex™-M4 instruction set chapter in theARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information. The value of this field is only meaningful when accessingPSRor EPSR. 0x0ROICI / IT15:10 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved9:8 IPSRISR Number This field contains the exception type number of the current Interrupt Service Routine (ISR). DescriptionValue Thread mode0x00 Reserved0x01 NMI0x02 Hard fault0x03 Memory management fault0x04 Bus fault0x05 Usage fault0x06 Reserved0x07-0x0A SVCall0x0B Reserved for Debug0x0C Reserved0x0D PendSV0x0E SysTick0x0F Interrupt Vector 00x10 Interrupt Vector 10x11 Interrupt Vector 1380x9A See “Exception Types” on page 95 for more information. The value of this field is only meaningful when accessingPSRor IPSR. 0x00ROISRNUM7:0 77June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register18:PriorityMaskRegister(PRIMASK) The PRIMASKregister prevents activation of all exceptions with programmable priority. Reset, non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. TheMSRand MRSinstructions are used to access thePRIMASKregister, and the CPSinstruction may be used to change the value of thePRIMASKregister. See the Cortex™-M4 instruction set chapter in theARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A ) for more information on these instructions. For more information on exception priority levels, see “Exception Types” on page 95. Priority Mask Register (PRIMASK) Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PRIMASKreserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:1 Priority Mask DescriptionValue Prevents the activation of all exceptions with configurable priority. No effect.0 0RWPRIMASK0 June 12, 201478 Texas Instruments-Production Data The Cortex-M4F Processor

Register19:FaultMaskRegister(FAULTMASK) The FAULTMASKregister prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. TheMSRand MRSinstructions are used to access the FAULTMASKregister, and theCPSinstruction may be used to change the value of theFAULTMASK register. See the Cortex™-M4 instruction set chapter in theARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A ) for more information on these instructions. For more information on exception priority levels, see “Exception Types” on page 95. Fault Mask Register (FAULTMASK) Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 FAULTMASKreserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:1 Fault Mask DescriptionValue Prevents the activation of all exceptions except for NMI.1 No effect.0 The processor clears theFAULTMASKbit on exit from any exception handler except the NMI handler. 0RWFAULTMASK0 79June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register20:BasePriorityMaskRegister(BASEPRI) The BASEPRIregister defines the minimum priority for exception processing. WhenBASEPRIis set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as theBASEPRIvalue. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. For more information on exception priority levels, see “Exception Types” on page 95. Base Priority Mask Register (BASEPRI) Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedBASEPRIreserved RORORORORORWRWRWROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 Base Priority Any exception that has a programmable priority level with the same or lower priority as the value of this field is masked. ThePRIMASKregister can be used to mask all exceptions with programmable priority levels. Higher priority exceptions have lower priority levels. DescriptionValue All exceptions are unmasked.0x0 All exceptions with priority level 1-7 are masked.0x1 All exceptions with priority level 2-7 are masked.0x2 All exceptions with priority level 3-7 are masked.0x3 All exceptions with priority level 4-7 are masked.0x4 All exceptions with priority level 5-7 are masked.0x5 All exceptions with priority level 6-7 are masked.0x6 All exceptions with priority level 7 are masked.0x7 0x0RWBASEPRI7:5 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved4:0 June 12, 201480 Texas Instruments-Production Data The Cortex-M4F Processor

Register21:ControlRegister(CONTROL) The CONTROLregister controls the stack used and the privilege level for software execution when the processor is in Thread mode, and indicates whether the FPU state is active. This register is only accessible in privileged mode. Handler mode always uses theMSP, so the processor ignores explicit writes to theASPbit of the CONTROLregister when in Handler mode. The exception entry and return mechanisms automatically update theCONTROLregister based on the EXC_RETURN value (see Table 2-10 on page 104). In an OS environment, threads running in Thread mode should use the process stack and the kernel and exception handlers should use the main stack. By default, Thread mode uses theMSP. To switch the stack pointer used in Thread mode to thePSP, either use theMSRinstruction to set the ASPbit, as detailed in the Cortex™-M4 instruction set chapter in theARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A ), or perform an exception return to Thread mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 104. Note: When changing the stack pointer, software must use anISBinstruction immediately after the MSRinstruction, ensuring that instructions after theISBexecute use the new stack pointer. See the Cortex™-M4 instruction set chapter in theARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A ). Control Register (CONTROL) Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TMPLASPFPCAreserved RWRWRWROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:3 Floating-Point Context Active DescriptionValue Floating-point context active1 No floating-point context active0 The Cortex-M4F uses this bit to determine whether to preserve floating-point state when processing an exception. Important: Two bits control whenFPCAcan be enabled: theASPEN bit in theFloating-PointContextControl(FPCC) register and theDISFPCAbit in theAuxiliaryControl (ACTLR)register. 0RWFPCA2 81June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Active Stack Pointer DescriptionValue The PSPis the current stack pointer.1 The MSPis the current stack pointer0 In Handler mode, this bit reads as zero and ignores writes. The Cortex-M4F updates this bit automatically on exception return. 0RWASP1 Thread Mode Privilege Level DescriptionValue Unprivileged software can be executed in Thread mode.1 Only privileged software can be executed in Thread mode.0 0RWTMPL0 June 12, 201482 Texas Instruments-Production Data The Cortex-M4F Processor

Register22:Floating-PointStatusControl(FPSC) The FPSCregister provides all necessary user-level control of the floating-point system. Floating-Point Status Control (FPSC) Type RW, reset - 16171819202122232425262728293031 reservedRMODEFZDNAHPreservedVCZN RORORORORORORWRWRWRWRWRORWRWRWRWType 0123456789101112131415 IOCDZCOFCUFCIXCreservedIDCreserved RWRWRWRWRWRORORWROROROROROROROROType DescriptionResetTypeNameBit/Field Negative Condition Code Flag Floating-point comparison operations update this condition code flag. -RWN31 Zero Condition Code Flag Floating-point comparison operations update this condition code flag. -RWZ30 Carry Condition Code Flag Floating-point comparison operations update this condition code flag. -RWC29 Overflow Condition Code Flag Floating-point comparison operations update this condition code flag. -RWV28 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27 Alternative Half-Precision When set, alternative half-precision format is selected. When clear, IEEE half-precision format is selected. The AHPbit in theFPDSCregister holds the default value for this bit. -RWAHP26 Default NaN Mode When set, any operation involving one or more NaNs returns the Default NaN. When clear, NaN operands propagate through to the output of a floating-point operation. The DNbit in theFPDSCregister holds the default value for this bit. -RWDN25 Flush-to-Zero Mode When set, Flush-to-Zero mode is enabled. When clear, Flush-to-Zero mode is disabled and the behavior of the floating-point system is fully compliant with the IEEE 754 standard. The FZbit in theFPDSCregister holds the default value for this bit. -RWFZ24 83June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Rounding Mode The specified rounding mode is used by almost all floating-point instructions. The RMODEbit in theFPDSCregister holds the default value for this bit. DescriptionValue Round to Nearest (RN) mode0x0 Round towards Plus Infinity (RP) mode0x1 Round towards Minus Infinity (RM) mode0x2 Round towards Zero (RZ) mode0x3 -RWRMODE23:22 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved21:8 Input Denormal Cumulative Exception When set, indicates this exception has occurred since 0 was last written to this bit. -RWIDC7 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved6:5 Inexact Cumulative Exception When set, indicates this exception has occurred since 0 was last written to this bit. -RWIXC4 Underflow Cumulative Exception When set, indicates this exception has occurred since 0 was last written to this bit. -RWUFC3 Overflow Cumulative Exception When set, indicates this exception has occurred since 0 was last written to this bit. -RWOFC2 Division by Zero Cumulative Exception When set, indicates this exception has occurred since 0 was last written to this bit. -RWDZC1 Invalid Operation Cumulative Exception When set, indicates this exception has occurred since 0 was last written to this bit. -RWIOC0 June 12, 201484 Texas Instruments-Production Data The Cortex-M4F Processor

2.3.5 ExceptionsandInterrupts

The Cortex-M4F processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses Handler mode to handle all exceptions except for reset. See “Exception Entry and Return” on page 101 for more information. The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” on page 117 for more information.

2.3.6 DataTypes

The Cortex-M4F supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports 64-bit data transfer instructions. All instruction and data memory accesses are little endian. See “Memory Regions, Types and Attributes” on page 88 for more information.

2.4 MemoryModel

This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory. The memory map for the TM4C1233D5PZ controller is provided in Table 2-4 on page 85. In this manual, register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data (see “Bit-Banding” on page 90). The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers (see “Cortex-M4 Peripherals” on page 115). Note: Within the memory map, attempts to read or write addresses in reserved spaces result in a bus fault. In addition, attempts to write addresses in the flash range also result in a bus fault. Table2-4.MemoryMap Fordetails, seepage... DescriptionEndStart Memory 522On-chip Flash0x0000.FFFF0x0000.0000 -Reserved0x1FFF.FFFF0x0001.0000 508Bit-banded on-chip SRAM0x2000.5FFF0x2000.0000 -Reserved0x21FF.FFFF0x2000.6000 508Bit-band alias of bit-banded on-chip SRAM starting at 0x2000.0000 0x220B.FFFF0x2200.0000 -Reserved0x3FFF.FFFF0x220C.0000 Peripherals 762Watchdog timer 00x4000.0FFF0x4000.0000 762Watchdog timer 10x4000.1FFF0x4000.1000 -Reserved0x4000.3FFF0x4000.2000 641GPIO Port A0x4000.4FFF0x4000.4000 641GPIO Port B0x4000.5FFF0x4000.5000 85June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table2-4.MemoryMap (continued) Fordetails, seepage... DescriptionEndStart 641GPIO Port C0x4000.6FFF0x4000.6000 641GPIO Port D0x4000.7FFF0x4000.7000 957SSI00x4000.8FFF0x4000.8000 957SSI10x4000.9FFF0x4000.9000 957SSI20x4000.AFFF0x4000.A000 957SSI30x4000.BFFF0x4000.B000 892UART00x4000.CFFF0x4000.C000 892UART10x4000.DFFF0x4000.D000 892UART20x4000.EFFF0x4000.E000 892UART30x4000.FFFF0x4000.F000 892UART40x4001.0FFF0x4001.0000 892UART50x4001.1FFF0x4001.1000 892UART60x4001.2FFF0x4001.2000 892UART70x4001.3FFF0x4001.3000 -Reserved0x4001.FFFF0x4001.4000 Peripherals 1007I2C 00x4002.0FFF0x4002.0000 1007I2C 10x4002.1FFF0x4002.1000 1007I2C 20x4002.2FFF0x4002.2000 1007I2C 30x4002.3FFF0x4002.3000 641GPIO Port E0x4002.4FFF0x4002.4000 641GPIO Port F0x4002.5FFF0x4002.5000 641GPIO Port G0x4002.6FFF0x4002.6000 641GPIO Port H0x4002.7FFF0x4002.7000 -Reserved0x4002.FFFF0x4002.8000 71116/32-bit Timer 00x4003.0FFF0x4003.0000 71116/32-bit Timer 10x4003.1FFF0x4003.1000 71116/32-bit Timer 20x4003.2FFF0x4003.2000 71116/32-bit Timer 30x4003.3FFF0x4003.3000 71116/32-bit Timer 40x4003.4FFF0x4003.4000 71116/32-bit Timer 50x4003.5FFF0x4003.5000 71132/64-bit Timer 00x4003.6FFF0x4003.6000 71132/64-bit Timer 10x4003.7FFF0x4003.7000 804ADC00x4003.8FFF0x4003.8000 804ADC10x4003.9FFF0x4003.9000 -Reserved0x4003.BFFF0x4003.A000 1150Analog Comparators0x4003.CFFF0x4003.C000 641GPIO Port J0x4003.DFFF0x4003.D000 -Reserved0x4003.FFFF0x4003.E000 1057CAN0 Controller0x4004.0FFF0x4004.0000 -Reserved0x4004.BFFF0x4004.1000 June 12, 201486 Texas Instruments-Production Data The Cortex-M4F Processor

Table2-4.MemoryMap (continued) Fordetails, seepage... DescriptionEndStart 71132/64-bit Timer 20x4004.CFFF0x4004.C000 71132/64-bit Timer 30x4004.DFFF0x4004.D000 71132/64-bit Timer 40x4004.EFFF0x4004.E000 71132/64-bit Timer 50x4004.FFFF0x4004.F000 1096USB0x4005.0FFF0x4005.0000 -Reserved0x4005.7FFF0x4005.1000 641GPIO Port A (AHB aperture)0x4005.8FFF0x4005.8000 641GPIO Port B (AHB aperture)0x4005.9FFF0x4005.9000 641GPIO Port C (AHB aperture)0x4005.AFFF0x4005.A000 641GPIO Port D (AHB aperture)0x4005.BFFF0x4005.B000 641GPIO Port E (AHB aperture)0x4005.CFFF0x4005.C000 641GPIO Port F (AHB aperture)0x4005.DFFF0x4005.D000 641GPIO Port G (AHB aperture)0x4005.EFFF0x4005.E000 641GPIO Port H (AHB aperture)0x4005.FFFF0x4005.F000 641GPIO Port J (AHB aperture)0x4006.0FFF0x4006.0000 641GPIO Port K (AHB aperture)0x4006.1FFF0x4006.1000 -Reserved0x400A.EFFF0x4006.2000 522EEPROM and Key Locker0x400A.FFFF0x400A.F000 -Reserved0x400B.FFFF0x400B.0000 1007I2C 40x400C.0FFF0x400C.0000 1007I2C 50x400C.1FFF0x400C.1000 -Reserved0x400F.8FFF0x400C.2000 468System Exception Module0x400F.9FFF0x400F.9000 -Reserved0x400F.BFFF0x400F.A000 488Hibernation Module0x400F.CFFF0x400F.C000 522Flash memory control0x400F.DFFF0x400F.D000 224System control0x400F.EFFF0x400F.E000 588µDMA0x400F.FFFF0x400F.F000 -Reserved0x41FF.FFFF0x4010.0000 -Bit-banded alias of 0x4000.0000 through 0x400F.FFFF0x43FF.FFFF0x4200.0000 -Reserved0xDFFF.FFFF0x4400.0000 PrivatePeripheralBus 64Instrumentation Trace Macrocell (ITM)0xE000.0FFF0xE000.0000 64Data Watchpoint and Trace (DWT)0xE000.1FFF0xE000.1000 64Flash Patch and Breakpoint (FPB)0xE000.2FFF0xE000.2000 -Reserved0xE000.DFFF0xE000.3000 127Cortex-M4F Peripherals (SysTick, NVIC, MPU, FPU and SCB)0xE000.EFFF0xE000.E000 -Reserved0xE003.FFFF0xE000.F000 65Trace Port Interface Unit (TPIU)0xE004.0FFF0xE004.0000 64Embedded Trace Macrocell (ETM)0xE004.1FFF0xE004.1000 -Reserved0xFFFF.FFFF0xE004.2000 87June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

2.4.1 MemoryRegions,TypesandAttributes

The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are: ■ Normal: The processor can re-order transactions for efficiency and perform speculative reads. ■ Device: The processor preserves transaction order relative to other transactions to Device or Strongly Ordered memory. ■ Strongly Ordered: The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly Ordered memory mean that the memory system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory. An additional memory attribute is Execute Never (XN), which means the processor prevents instruction accesses. A fault exception is generated only on execution of an instruction executed from an XN region.

2.4.2 MemorySystemOrderingofMemoryAccesses

For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing the order does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions (see “Software Ordering of Memory Accesses” on page 89). However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always observed before A2.

2.4.3 BehaviorofMemoryAccesses

Table 2-5 on page 88 shows the behavior of accesses to each region in the memory map. See “Memory Regions, Types and Attributes” on page 88 for more information on memory types and the XN attribute. Tiva™ C Series devices may have reserved memory areas within the address ranges shown below (refer to Table 2-4 on page 85 for more information). Table2-5.MemoryAccessBehavior DescriptionExecute Never (XN) MemoryTypeMemoryRegionAddressRange This executable region is for program code. Data can also be stored here. -NormalCode0x0000.0000 - 0x1FFF.FFFF This executable region is for data. Code can also be stored here. This region includes bit band and bit band alias areas (see Table 2-6 on page 90). -NormalSRAM0x2000.0000 - 0x3FFF.FFFF This region includes bit band and bit band alias areas (see Table 2-7 on page 91). XNDevicePeripheral0x4000.0000 - 0x5FFF.FFFF This executable region is for data.-NormalExternal RAM0x6000.0000 - 0x9FFF.FFFF June 12, 201488 Texas Instruments-Production Data The Cortex-M4F Processor

Table2-5.MemoryAccessBehavior (continued) DescriptionExecute Never (XN) MemoryTypeMemoryRegionAddressRange This region is for external device memory.XNDeviceExternal device0xA000.0000 - 0xDFFF.FFFF This region includes the NVIC, system timer, and system control block. XNStrongly Ordered Private peripheral bus 0xE000.0000- 0xE00F.FFFF ---Reserved0xE010.0000- 0xFFFF.FFFF The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that programs always use the Code region because the Cortex-M4F has separate buses that can perform instruction fetches and data accesses simultaneously. The MPU can override the default memory access behavior described in this section. For more information, see “Memory Protection Unit (MPU)” on page 118. The Cortex-M4F prefetches instructions ahead of execution and speculatively prefetches from branch target addresses.

2.4.4 SoftwareOrderingofMemoryAccesses

The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions for the following reasons: ■ The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. ■ The processor has multiple bus interfaces. ■ Memory or devices in the memory map have different wait states. ■ Some memory accesses are buffered or speculative. “Memory System Ordering of Memory Accesses” on page 88 describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. The Cortex-M4F has the following memory barrier instructions: ■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. ■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. ■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. Memory barrier instructions can be used in the following situations: ■ MPU programming – If the MPU settings are changed and the change must be effective on the very next instruction, use aDSBinstruction to ensure the effect of the MPU takes place immediately at the end of context switching. 89June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

– Use an ISBinstruction to ensure the new MPU setting takes effect immediately after programming the MPU region or regions, if the MPU configuration code was accessed using a branch or call. If the MPU configuration code is entered using exception mechanisms, then an ISBinstruction is not required. ■ Vector table If the program changes an entry in the vector table and then enables the corresponding exception, use aDMBinstruction between the operations. TheDMBinstruction ensures that if the exception is taken immediately after being enabled, the processor uses the new exception vector. ■ Self-modifying code If a program contains self-modifying code, use anISBinstruction immediately after the code modification in the program. TheISBinstruction ensures subsequent instruction execution uses the updated program. ■ Memory map switching If the system contains a memory map switching mechanism, use aDSBinstruction after switching the memory map in the program. TheDSBinstruction ensures subsequent instruction execution uses the updated memory map. ■ Dynamic exception priority change When an exception priority has to change when the exception is pending or active, useDSB instructions after the change. The change then takes effect on completion of theDSBinstruction. Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require the use ofDMBinstructions. For more information on the memory barrier instructions, see the Cortex™-M4 instruction set chapter in theARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A ).

2.4.5 Bit-Banding

A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table 2-6 on page 90. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band region, as shown in Table 2-7 on page 91. For the specific address range of the bit-band regions, see Table 2-4 on page 85. Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in the SRAM or peripheral bit-band region. A word access to a bit band address results in a word access to the underlying memory, and similarly for halfword and byte accesses. This allows bit band accesses to match the access requirements of the underlying peripheral. Table2-6.SRAMMemoryBit-BandingRegions InstructionandDataAccessesMemoryRegion AddressRange EndStart Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. SRAM bit-band region0x2000.5FFF0x2000.0000 June 12, 201490 Texas Instruments-Production Data The Cortex-M4F Processor

Table2-6.SRAMMemoryBit-BandingRegions (continued) InstructionandDataAccessesMemoryRegion AddressRange EndStart Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped. SRAM bit-band alias0x220B.FFFF0x2200.0000 Table2-7.PeripheralMemoryBit-BandingRegions InstructionandDataAccessesMemoryRegion AddressRange EndStart Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. Peripheral bit-band region 0x400F.FFFF0x4000.0000 Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. Peripheral bit-band alias0x43FF.FFFF0x4200.0000 The following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset where: bit_word_offset The position of the target bit in the bit-band memory region. bit_word_addr The address of the word in the alias memory region that maps to the targeted bit. bit_band_base The starting address of the alias region. byte_offset The number of the byte in the bit-band region that contains the targeted bit. bit_number The bit position, 0-7, of the targeted bit. Figure 2-4 on page 92 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region: ■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4) ■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4) ■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: 91June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000: Figure2-4.Bit-BandMapping 0x23FF .FFE4 0x2200.0004 32-MB Alias Region 7 0 0x2000.00000x2000.00010x2000.00020x2000.0003 6 5 4 3 2 1 07 6 5 4 3 2 1 7 6 5 4 3 2 1 07 6 5 4 3 2 1 07 6 5 4 3 2 1 6 5 4 3 2 107 6 5 4 3 2 1 07 6 5 4 3 2 1 0x200F .FFFC0x200F .FFFD0x200F .FFFE0x200F .FFFF 1-MB SRAM Bit-Band Region

2.4.5.1 DirectlyAccessinganAliasRegion

Writing to a word in the alias region updates a single bit in the bit-band region. Bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a value with bit 0 clear writes a 0 to the bit-band bit. Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E. When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set.

2.4.5.2 DirectlyAccessingaBit-BandRegion

“Behavior of Memory Accesses” on page 88 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions.

2.4.6 DataStorage

The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte. Figure 2-5 on page 93 illustrates how data is stored. June 12, 201492 Texas Instruments-Production Data The Cortex-M4F Processor

Figure2-5.DataStorage Memory Register Address A A+1 lsbyte msbyte A+2 A+3 B0B1B3 B2 31 24 23 16 15 8 7 0

2.4.7 SynchronizationPrimitives

The Cortex-M4F instruction set includes pairs of synchronization primitives which provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use these primitives to perform a guaranteed read-modify-write memory update sequence or for a semaphore mechanism. A pair of synchronization primitives consists of: ■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests exclusive access to that location. ■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and returns a status bit to a register. If this status bit is clear, it indicates that the thread or process gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates that the thread or process did not gain exclusive access to the memory and no write was performed. The pairs of Load-Exclusive and Store-Exclusive instructions are: ■ The word instructionsLDREXand STREX ■ The halfword instructionsLDREXHand STREXH ■ The byte instructionsLDREXBand STREXB Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform an exclusive read-modify-write of a memory location, software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Modify the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location. 4. Test the returned status bit. If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no write was performed, which indicates that the value returned at step 1 might be out of date. The software must retry the entire read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 93June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. 2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address. 3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the semaphore after the software performed step 1. The Cortex-M4F includes an exclusive access monitor that tags the fact that the processor has executed a Load-Exclusive instruction. The processor removes its exclusive access tag if: ■ It executes aCLREXinstruction. ■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds. ■ An exception occurs, which means the processor can resolve semaphore conflicts between different threads. For more information about the synchronization primitive instructions, see the Cortex™-M4 instruction set chapter in theARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A).

2.5 ExceptionModel

The ARM Cortex-M4F processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 2-8 on page 96 lists all exception types. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 72 interrupts (listed in Table 2-9 on page 97). Priorities on the system handlers are set with the NVICSystemHandlerPriorityn(SYSPRIn) registers. Interrupts are enabled through the NVICInterruptSetEnablen(ENn) register and prioritized with the NVICInterruptPriorityn(PRIn) registers. Priorities can be grouped by splitting priority levels into preemption priorities and subpriorities. All the interrupt registers are described in “Nested Vectored Interrupt Controller (NVIC)” on page 117. Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset, Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for all the programmable priorities. Important: After a write to clear an interrupt source, it may take several processor cycles for the NVIC to see the interrupt source deassert. Thus if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer). See “Nested Vectored Interrupt Controller (NVIC)” on page 117 for more information on exceptions and interrupts. June 12, 201494 Texas Instruments-Production Data The Cortex-M4F Processor

2.5.1 ExceptionStates

Each exception is in one of the following states: ■ Inactive.The exception is not active and not pending. ■ Pending.The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. ■ Active.An exception that is being serviced by the processor but has not completed. Note: An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state. ■ ActiveandPending. The exception is being serviced by the processor, and there is a pending exception from the same source.

2.5.2 ExceptionTypes

The exception types are: ■ Reset.Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. ■ NMI.A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by software using theInterruptControlandState(INTCTRL) register. This exception has the highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs cannot be masked or prevented from activation by any other exception or preempted by any exception other than reset. ■ HardFault. A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. ■ MemoryManagementFault. A memory management fault is an exception that occurs because of a memory protection related fault, including access violation and no match. The MPU or the fixed memory protection constraints determine this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled. ■ BusFault. A bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. This fault can be enabled or disabled. ■ UsageFault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution 95June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

– An error on exception return An unaligned address on a word or halfword memory access or division by zero can cause a usage fault when the core is properly configured. ■ SVCall.A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. ■ DebugMonitor.This exception is caused by the debug monitor (when not halting). This exception is only active when enabled. This exception does not activate if it is a lower priority than the current activation. ■ PendSV.PendSV is a pendable, interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. PendSV is triggered using theInterruptControlandState(INTCTRL) register. ■ SysTick.A SysTick exception is an exception that the system timer generates when it reaches zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception using theInterruptControlandState(INTCTRL) register. In an OS environment, the processor can use this exception as system tick. ■ Interrupt(IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 on page 97 lists the interrupts on the TM4C1233D5PZ controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that Table 2-8 on page 96 shows as having configurable priority (see theSYSHNDCTRLregister on page 166 and theDIS0register on page 137). For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault Handling” on page 104. Table2-8.ExceptionTypes ActivationVectorAddressor Offsetb PriorityaVector Number ExceptionType Stack top is loaded from the first entry of the vector table on reset. 0x0000.0000-0- Asynchronous0x0000.0004-3 (highest)1Reset Asynchronous0x0000.0008-22Non-Maskable Interrupt (NMI) -0x0000.000C-13Hard Fault Synchronous0x0000.0010programmablec4Memory Management Synchronous when precise and asynchronous when imprecise 0x0000.0014programmablec5Bus Fault Synchronous0x0000.0018programmablec6Usage Fault Reserved--7-10- Synchronous0x0000.002Cprogrammablec11SVCall Synchronous0x0000.0030programmablec12Debug Monitor Reserved--13- June 12, 201496 Texas Instruments-Production Data The Cortex-M4F Processor

Table2-8.ExceptionTypes (continued) ActivationVectorAddressor Offsetb PriorityaVector Number ExceptionType Asynchronous0x0000.0038programmablec14PendSV Asynchronous0x0000.003Cprogrammablec15SysTick Asynchronous0x0000.0040 and aboveprogrammabled16 and aboveInterrupts a. 0 is the default priority for all the programmable priorities. b. See “Vector Table” on page 99. c. SeeSYSPRI1on page 163. d. SeePRInregisters on page 145. Table2-9.Interrupts DescriptionVectorAddressor Offset InterruptNumber(Bit inInterruptRegisters) VectorNumber Processor exceptions0x0000.0000 - 0x0000.003C -0-15 GPIO Port A0x0000.0040016 GPIO Port B0x0000.0044117 GPIO Port C0x0000.0048218 GPIO Port D0x0000.004C319 GPIO Port E0x0000.0050420 UART00x0000.0054521 UART10x0000.0058622 SSI00x0000.005C723 I2C00x0000.0060824 Reserved-9-1325-29 ADC0 Sequence 00x0000.00781430 ADC0 Sequence 10x0000.007C1531 ADC0 Sequence 20x0000.00801632 ADC0 Sequence 30x0000.00841733 Watchdog Timers 0 and 10x0000.00881834 16/32-Bit Timer 0A0x0000.008C1935 16/32-Bit Timer 0B0x0000.00902036 16/32-Bit Timer 1A0x0000.00942137 16/32-Bit Timer 1B0x0000.00982238 16/32-Bit Timer 2A0x0000.009C2339 16/32-Bit Timer 2B0x0000.00A02440 Analog Comparator 00x0000.00A42541 Analog Comparator 10x0000.00A82642 Analog Comparator 20x0000.00AC2743 System Control0x0000.00B02844 Flash Memory Control and EEPROM Control0x0000.00B42945 GPIO Port F0x0000.00B83046 GPIO Port G0x0000.00BC3147 GPIO Port H0x0000.00C03248 97June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table2-9.Interrupts (continued) DescriptionVectorAddressor Offset InterruptNumber(Bit inInterruptRegisters) VectorNumber UART20x0000.00C43349 SSI10x0000.00C83450 16/32-Bit Timer 3A0x0000.00CC3551 16/32-Bit Timer 3B0x0000.00D03652 I2C10x0000.00D43753 Reserved-3854 CAN00x0000.00DC3955 Reserved-40-4256-58 Hibernation Module0x0000.00EC4359 USB0x0000.00F04460 Reserved-4561 µDMA Software0x0000.00F84662 µDMA Error0x0000.00FC4763 ADC1 Sequence 00x0000.01004864 ADC1 Sequence 10x0000.01044965 ADC1 Sequence 20x0000.01085066 ADC1 Sequence 30x0000.010C5167 Reserved-52-5368-69 GPIO Port J0x0000.01185470 GPIO Port K0x0000.011C5571 Reserved-5672 SSI20x0000.01245773 SSI30x0000.01285874 UART30x0000.012C5975 UART40x0000.01306076 UART50x0000.01346177 UART60x0000.01386278 UART70x0000.013C6379 Reserved0x0000.0140 - 0x0000.014C 64-6780-83 I2C20x0000.01506884 I2C30x0000.01546985 16/32-Bit Timer 4A0x0000.01587086 16/32-Bit Timer 4B0x0000.015C7187 Reserved0x0000.0160 - 0x0000.01AC 72-9188-107 16/32-Bit Timer 5A0x0000.01B092108 16/32-Bit Timer 5B0x0000.01B493109 32/64-Bit Timer 0A0x0000.01B894110 32/64-Bit Timer 0B0x0000.01BC95111 32/64-Bit Timer 1A0x0000.01C096112 32/64-Bit Timer 1B0x0000.01C497113 June 12, 201498 Texas Instruments-Production Data The Cortex-M4F Processor

Table2-9.Interrupts (continued) DescriptionVectorAddressor Offset InterruptNumber(Bit inInterruptRegisters) VectorNumber 32/64-Bit Timer 2A0x0000.01C898114 32/64-Bit Timer 2B0x0000.01CC99115 32/64-Bit Timer 3A0x0000.01D0100116 32/64-Bit Timer 3B0x0000.01D4101117 32/64-Bit Timer 4A0x0000.01D8102118 32/64-Bit Timer 4B0x0000.01DC103119 32/64-Bit Timer 5A0x0000.01E0104120 32/64-Bit Timer 5B0x0000.01E4105121 System Exception (imprecise)0x0000.01E8106122 Reserved-107-108123-124 I2C40x0000.01F4109125 I2C50x0000.01F8110126 Reserved-111-138127-154

2.5.3 ExceptionHandlers

The processor handles exceptions using: ■ InterruptServiceRoutines(ISRs). Interrupts (IRQx) are the exceptions handled by ISRs. ■ FaultHandlers. Hard fault, memory management fault, usage fault, and bus fault are fault exceptions handled by the fault handlers. ■ SystemHandlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system exceptions that are handled by system handlers.

2.5.4 VectorTable

The vector table contains the reset value of the stack pointer and the start addresses, also called exception vectors, for all exception handlers. The vector table is constructed using the vector address or offset shown in Table 2-8 on page 96. Figure 2-6 on page 100 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code 99June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Figure2-6.VectorTable Initial SP value Reset Hard fault NMI Memory management fault Usage fault Bus fault 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 Reserved SVCall PendSV Reserved for Debug Systick IRQ0 Reserved 0x002C 0x0038 0x003C 0x0040 Of fsetException number 1 1 V ector IRQ1 IRQ2 0x0044 IRQ131 0x0048 0x004C 154 0x0268 IRQ number -14 -13 -12 -1 1 -10 138 On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to the VectorTableOffset(VTABLE) register to relocate the vector table start address to a different memory location, in the range 0x0000.0400 to 0x3FFF.FC00 (see “Vector Table” on page 99). Note that when configuring theVTABLEregister, the offset must be aligned on a 1024-byte boundary.

2.5.5 ExceptionPriorities

As Table 2-8 on page 96 shows, all exceptions have an associated priority, with a lower priority value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities, see page 163 and page 145. Note: Configurable priority values for the Tiva™ C Series implementation are in the range 0-7. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. June 12, 2014100 Texas Instruments-Production Data The Cortex-M4F Processor

If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending.

2.5.6 InterruptPriorityGrouping

To increase priority control in systems with interrupts, the NVIC supports priority grouping. This grouping divides each interrupt priority register entry into two fields: ■ An upper field that defines the group priority ■ A lower field that defines a subpriority within the group Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler. If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. For information about splitting the interrupt priority fields into group priority and subpriority, see page 157.

2.5.7 ExceptionEntryandReturn

Descriptions of exception handling use the following terms: ■ Preemption.When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See “Interrupt Priority Grouping” on page 101 for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” on page 102 more information. ■ Return.Return occurs when the exception handler is completed, and there is no pending exception with sufficient priority to be serviced and the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See “Exception Return” on page 103 for more information. ■ Tail-Chaining.This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. ■ Late-Arriving.This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore, the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On 101June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply.

2.5.7.1 ExceptionEntry

Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means the exception has more priority than any limits set by the mask registers (see PRIMASKon page 78,FAULTMASKon page 79, andBASEPRIon page 80). An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred to as stacking and the structure of eight data words is referred to asstack frame. When using floating-point routines, the Cortex-M4F processor automatically stacks the architected floating-point state on exception entry. Figure 2-7 on page 103 shows the Cortex-M4F stack frame layout when floating-point state is preserved on the stack as the result of an interrupt or an exception. Note: Where stack space for floating-point state is not allocated, the stack frame is the same as that of ARMv7-M implementations without an FPU. Figure 2-7 on page 103 shows this stack frame also. June 12, 2014102 Texas Instruments-Production Data The Cortex-M4F Processor

Figure2-7.ExceptionStackFrame Pre-IRQ top of stack x PSR PC LR R 12 R 3 R 2 R 1 {aligner} IRQ top of stack Decreasing memory address x PSR PC LR R 12 R 3 R 2 R 1 S 3 S 2 S 1 FPSCR S15 S14 S1 3 S1 2 S1 1 S10 {aligner} IRQ top of stack ... Exception frame with floating -point storage Exception frame without floating -point storage Pre-IRQ top of stack ... Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The stack frame includes the return address, which is the address of the next instruction in the interrupted program. This value is restored to thePCat exception return so that the interrupted program resumes. In parallel with the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to theLR, indicating which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. If no higher-priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception.

2.5.7.2 ExceptionReturn

Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into thePC: 103June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

■ An LDMor POPinstruction that loads thePC ■ A BXinstruction using any register ■ An LDRinstruction with thePCas the destination EXC_RETURN is the value loaded into theLRon exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. Table 2-10 on page 104 shows the EXC_RETURN values with a description of the exception return behavior. EXC_RETURN bits 31:5 are all set. When this value is loaded into thePC, it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. Table2-10.ExceptionReturnBehavior DescriptionEXC_RETURN[31:0] Reserved0xFFFF.FFE0 Return to Handler mode. Exception return uses floating-point state fromMSP. Execution usesMSPafter return. 0xFFFF.FFE1 Reserved0xFFFF.FFE2 - 0xFFFF.FFE8 Return to Thread mode. Exception return uses floating-point state fromMSP. Execution usesMSPafter return. 0xFFFF.FFE9 Reserved0xFFFF.FFEA - 0xFFFF.FFEC Return to Thread mode. Exception return uses floating-point state fromPSP. Execution usesPSPafter return. 0xFFFF.FFED Reserved0xFFFF.FFEE - 0xFFFF.FFF0 Return to Handler mode. Exception return uses non-floating-point state fromMSP. Execution usesMSPafter return. 0xFFFF.FFF1 Reserved0xFFFF.FFF2 - 0xFFFF.FFF8 Return to Thread mode. Exception return uses non-floating-point state fromMSP. Execution usesMSPafter return. 0xFFFF.FFF9 Reserved0xFFFF.FFFA - 0xFFFF.FFFC Return to Thread mode. Exception return uses non-floating-point state fromPSP. Execution usesPSPafter return. 0xFFFF.FFFD Reserved0xFFFF.FFFE - 0xFFFF.FFFF

2.6 FaultHandling

Faults are a subset of the exceptions (see “Exception Model” on page 94). The following conditions generate a fault: ■ A bus error on an instruction fetch or vector table load or a data access. June 12, 2014104 Texas Instruments-Production Data The Cortex-M4F Processor

■ An internally detected error such as an undefined instruction or an attempt to change state with a BXinstruction. ■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN). ■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region.

2.6.1 FaultTypes

Table 2-11 on page 105 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates the fault has occurred. See page 170 for more information about the fault status registers. Table2-11.Faults BitNameFaultStatusRegisterHandlerFault VECTHardFaultStatus(HFAULTSTAT)Hard faultBus error on a vector read FORCEDHardFaultStatus(HFAULTSTAT)Hard faultFault escalated to a hard fault IERRaMemoryManagementFaultStatus (MFAULTSTAT) Memory management fault MPU or default memory mismatch on instruction access DERRMemoryManagementFaultStatus (MFAULTSTAT) Memory management fault MPU or default memory mismatch on data access MSTKEMemoryManagementFaultStatus (MFAULTSTAT) Memory management fault MPU or default memory mismatch on exception stacking MUSTKEMemoryManagementFaultStatus (MFAULTSTAT) Memory management fault MPU or default memory mismatch on exception unstacking MLSPERRMemoryManagementFaultStatus (MFAULTSTAT) Memory management fault MPU or default memory mismatch during lazy floating-point state preservation BSTKEBusFaultStatus(BFAULTSTAT)Bus faultBus error during exception stacking BUSTKEBusFaultStatus(BFAULTSTAT)Bus faultBus error during exception unstacking IBUSBusFaultStatus(BFAULTSTAT)Bus faultBus error during instruction prefetch BLSPEBusFaultStatus(BFAULTSTAT)Bus faultBus error during lazy floating-point state preservation PRECISEBusFaultStatus(BFAULTSTAT)Bus faultPrecise data bus error IMPREBusFaultStatus(BFAULTSTAT)Bus faultImprecise data bus error NOCPUsageFaultStatus(UFAULTSTAT)Usage faultAttempt to access a coprocessor UNDEFUsageFaultStatus(UFAULTSTAT)Usage faultUndefined instruction INVSTATUsageFaultStatus(UFAULTSTAT)Usage faultAttempt to enter an invalid instruction set stateb INVPCUsageFaultStatus(UFAULTSTAT)Usage faultInvalid EXC_RETURN value UNALIGNUsageFaultStatus(UFAULTSTAT)Usage faultIllegal unaligned load or store DIV0UsageFaultStatus(UFAULTSTAT)Usage faultDivide by 0 a. Occurs on an access to an XN region even if the MPU is disabled. b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiply instruction with ICIcontinuation.

2.6.2 FaultEscalationandHardFaults

All fault exceptions except for hard fault have configurable exception priority (seeSYSPRI1on page 163). Software can disable execution of the handlers for these faults (seeSYSHNDCTRLon page 166). 105June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in “Exception Model” on page 94. In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority escalation, and the fault is described asescalated to hard fault . Escalation to hard fault occurs when: ■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level. ■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation happens because the handler for the new fault cannot preempt the currently executing fault handler. ■ An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. ■ A fault occurs and the handler for that fault is not enabled. If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted. Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than Reset, NMI, or another hard fault.

2.6.3 FaultStatusRegistersandFaultAddressRegisters

The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 2-12 on page 106. Table2-12.FaultStatusandFaultAddressRegisters RegisterDescriptionAddressRegisterNameStatusRegisterNameHandler page 176-HardFaultStatus(HFAULTSTAT)Hard fault page 170 page 177 MemoryManagementFault Address(MMADDR) MemoryManagementFaultStatus (MFAULTSTAT) Memory management fault page 170 page 178 BusFaultAddress (FAULTADDR) BusFaultStatus(BFAULTSTAT)Bus fault page 170-UsageFaultStatus(UFAULTSTAT)Usage fault

2.6.4 Lockup

The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in the lockup state, it does not execute any instructions. The processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger. Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the lockup state. June 12, 2014106 Texas Instruments-Production Data The Cortex-M4F Processor

2.7 PowerManagement

The Cortex-M4F processor sleep modes reduce power consumption: ■ Sleep mode stops the processor clock. ■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory. The SLEEPDEEPbit of theSystemControl(SYSCTRL) register selects which sleep mode is used (see page 159). For more information about the behavior of the sleep modes, see “System Control” on page 219. This section describes the mechanisms for entering sleep mode and the conditions for waking up from sleep mode, both of which apply to Sleep mode and Deep-sleep mode.

2.7.1 EnteringSleepModes

This section describes the mechanisms software can use to put the processor into one of the sleep modes. The system can generate spurious wake-up events, for example a debug operation wakes up the processor. Therefore, software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode.

2.7.1.1 WaitforInterrupt

The wait for interrupt instruction,WFI, causes immediate entry to sleep mode unless the wake-up condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 108). When the processor executes aWFIinstruction, it stops executing instructions and enters sleep mode. See the Cortex™-M4 instruction set chapter in theARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A ) for more information.

2.7.1.2 WaitforEvent

The wait for event instruction,WFE, causes entry to sleep mode conditional on the value of a one-bit event register. When the processor executes aWFEinstruction, it checks the event register. If the register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1, the processor clears the register and continues executing instructions without entering sleep mode. If the event register is 1, the processor must not enter sleep mode on execution of aWFEinstruction. Typically, this situation occurs if anSEVinstruction has been executed. Software cannot access this register directly. See the Cortex™-M4 instruction set chapter in theARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A ) for more information.

2.7.1.3 Sleep-on-Exit

If theSLEEPEXITbit of theSYSCTRLregister is set, when the processor completes the execution of all exception handlers, it returns to Thread mode and immediately enters sleep mode. This mechanism can be used in applications that only require the processor to run when an exception occurs.

2.7.2 WakeUpfromSleepMode

The conditions for the processor to wake up depend on the mechanism that caused it to enter sleep mode. 107June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

2.7.2.1 WakeUpfromWFIorSleep-on-Exit

Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler can be delayed by setting thePRIMASKbit and clearing theFAULTMASKbit. If an interrupt arrives that is enabled and has a higher priority than current exception priority, the processor wakes up but does not execute the interrupt handler until the processor clearsPRIMASK. For more information about PRIMASKand FAULTMASK, see page 78 and page 79.

2.7.2.2 WakeUpfromWFE

The processor wakes up if it detects an exception with sufficient priority to cause exception entry. In addition, if theSEVONPENDbit in theSYSCTRLregister is set, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information aboutSYSCTRL, see page 159.

2.8 InstructionSetSummary

The processor implements a version of the Thumb instruction set. Table 2-13 on page 108 lists the supported instructions. Note: In Table 2-13 on page 108: ■ Angle brackets, <>, enclose alternative forms of the operand ■ Braces, {}, enclose optional operands ■ The Operands column is not exhaustive ■ Op2is a flexible second operand that can be either a register or a constant ■ Most instructions can use an optional condition code suffix For more information on the instructions and operands, see the instruction descriptions in the ARM® Cortex™-M4 Technical Reference Manual. Table2-13.Cortex-M4FInstructionSummary FlagsBriefDescriptionOperandsMnemonic N,Z,C,VAdd with carry{Rd,} Rn, Op2ADC, ADCS N,Z,C,VAdd{Rd,} Rn, Op2ADD, ADDS -Add{Rd,} Rn , #imm12ADD, ADDW -Load PC-relative addressRd, labelADR N,Z,CLogical AND{Rd,} Rn, Op2AND, ANDS N,Z,CArithmetic shift rightRd, Rm, <Rs|#n>ASR, ASRS -BranchlabelB -Bit field clearRd, #lsb, #widthBFC -Bit field insertRd, Rn, #lsb, #widthBFI N,Z,CBit clear{Rd,} Rn, Op2BIC, BICS -Breakpoint#immBKPT -Branch with linklabelBL -Branch indirect with linkRmBLX -Branch indirectRmBX -Compare and branch if non-zeroRn, labelCBNZ June 12, 2014108 Texas Instruments-Production Data The Cortex-M4F Processor

Table2-13.Cortex-M4FInstructionSummary (continued) FlagsBriefDescriptionOperandsMnemonic -Compare and branch if zeroRn, labelCBZ -Clear exclusive-CLREX -Count leading zerosRd, RmCLZ N,Z,C,VCompare negativeRn, Op2CMN N,Z,C,VCompareRn, Op2CMP -Change processor state, disable interrupts iCPSID -Change processor state, enable interrupts iCPSIE -Data memory barrier-DMB -Data synchronization barrier-DSB N,Z,CExclusive OR{Rd,} Rn, Op2EOR, EORS -Instruction synchronization barrier-ISB -If-Then condition block-IT -Load multiple registers, increment afterRn{!}, reglistLDM -Load multiple registers, decrement before Rn{!}, reglistLDMDB, LDMEA -Load multiple registers, increment afterRn{!}, reglistLDMFD, LDMIA -Load register with wordRt, [Rn, #offset]LDR -Load register with byteRt, [Rn, #offset]LDRB, LDRBT -Load register with two bytesRt, Rt2, [Rn, #offset]LDRD -Load register exclusiveRt, [Rn, #offset]LDREX -Load register exclusive with byteRt, [Rn]LDREXB -Load register exclusive with halfwordRt, [Rn]LDREXH -Load register with halfwordRt, [Rn, #offset]LDRH, LDRHT -Load register with signed byteRt, [Rn, #offset]LDRSB, LDRSBT -Load register with signed halfwordRt, [Rn, #offset]LDRSH, LDRSHT -Load register with wordRt, [Rn, #offset]LDRT N,Z,CLogical shift leftRd, Rm, <Rs|#n>LSL, LSLS N,Z,CLogical shift rightRd, Rm, <Rs|#n>LSR, LSRS -Multiply with accumulate, 32-bit resultRd, Rn, Rm, RaMLA -Multiply and subtract, 32-bit resultRd, Rn, Rm, RaMLS N,Z,CMoveRd, Op2MOV, MOVS N,Z,CMove 16-bit constantRd, #imm16MOV, MOVW -Move topRd, #imm16MOVT -Move from special register to general register Rd, spec_regMRS N,Z,C,VMove from general register to special register spec_reg, RmMSR N,ZMultiply, 32-bit result{Rd,} Rn, RmMUL, MULS N,Z,CMove NOTRd, Op2MVN, MVNS -No operation-NOP N,Z,CLogical OR NOT{Rd,} Rn, Op2ORN, ORNS 109June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table2-13.Cortex-M4FInstructionSummary (continued) FlagsBriefDescriptionOperandsMnemonic N,Z,CLogical OR{Rd,} Rn, Op2ORR, ORRS -Pack halfword{Rd,} Rn, Rm, Op2PKHTB, PKHBT -Pop registers from stackreglistPOP -Push registers onto stackreglistPUSH QSaturating add{Rd,} Rn, RmQADD -Saturating add 16{Rd,} Rn, RmQADD16 -Saturating add 8{Rd,} Rn, RmQADD8 -Saturating add and subtract with exchange {Rd,} Rn, RmQASX QSaturating double and add{Rd,} Rn, RmQDADD QSaturating double and subtract{Rd,} Rn, RmQDSUB -Saturating subtract and add with exchange {Rd,} Rn, RmQSAX QSaturating subtract{Rd,} Rn, RmQSUB -Saturating subtract 16{Rd,} Rn, RmQSUB16 -Saturating subtract 8{Rd,} Rn, RmQSUB8 -Reverse bitsRd, RnRBIT -Reverse byte order in a wordRd, RnREV -Reverse byte order in each halfwordRd, RnREV16 -Reverse byte order in bottom halfword and sign extend Rd, RnREVSH N,Z,CRotate rightRd, Rm, <Rs|#n>ROR, RORS N,Z,CRotate right with extendRd, RmRRX, RRXS N,Z,C,VReverse subtract{Rd,} Rn, Op2RSB, RSBS GESigned add 16{Rd,} Rn, RmSADD16 GESigned add 8{Rd,} Rn, RmSADD8 GESigned add and subtract with exchange{Rd,} Rn, RmSASX N,Z,C,VSubtract with carry{Rd,} Rn, Op2SBC, SBCS -Signed bit field extractRd, Rn, #lsb, #widthSBFX -Signed divide{Rd,} Rn, RmSDIV -Select bytes{Rd,} Rn, RmSEL -Send event-SEV -Signed halving add 16{Rd,} Rn, RmSHADD16 -Signed halving add 8{Rd,} Rn, RmSHADD8 -Signed halving add and subtract with exchange {Rd,} Rn, RmSHASX -Signed halving add and subtract with exchange {Rd,} Rn, RmSHSAX -Signed halving subtract 16{Rd,} Rn, RmSHSUB16 -Signed halving subtract 8{Rd,} Rn, RmSHSUB8 June 12, 2014110 Texas Instruments-Production Data The Cortex-M4F Processor

Table2-13.Cortex-M4FInstructionSummary (continued) FlagsBriefDescriptionOperandsMnemonic QSigned multiply accumulate long (halfwords) Rd, Rn, Rm, RaSMLABB, SMLABT, SMLATB, SMLATT QSigned multiply accumulate dualRd, Rn, Rm, RaSMLAD, SMLADX -Signed multiply with accumulate (32x32+64), 64-bit result RdLo, RdHi, Rn, RmSMLAL -Signed multiply accumulate long (halfwords) RdLo, RdHi, Rn, RmSMLALBB, SMLALBT, SMLALTB, SMLALTT -Signed multiply accumulate long dualRdLo, RdHi, Rn, RmSMLALD, SMLALDX QSigned multiply accumulate, word by halfword Rd, Rn, Rm, RaSMLAWB,SMLAWT QSigned multiply subtract dualRd, Rn, Rm, RaSMLSD SMLSDX Signed multiply subtract long dualRdLo, RdHi, Rn, RmSMLSLD SMLSLDX -Signed most significant word multiply accumulate Rd, Rn, Rm, RaSMMLA -Signed most significant word multiply subtract Rd, Rn, Rm, RaSMMLS, SMMLR -Signed most significant word multiply{Rd,} Rn, RmSMMUL, SMMULR QSigned dual multiply add{Rd,} Rn, RmSMUAD SMUADX -Signed multiply halfwords{Rd,} Rn, RmSMULBB, SMULBT, SMULTB, SMULTT -Signed multiply (32x32), 64-bit resultRdLo, RdHi, Rn, RmSMULL -Signed multiply by halfword{Rd,} Rn, RmSMULWB, SMULWT -Signed dual multiply subtract{Rd,} Rn, RmSMUSD, SMUSDX QSigned saturateRd, #n, Rm {,shift #s}SSAT QSigned saturate 16Rd, #n, RmSSAT16 GESaturating subtract and add with exchange {Rd,} Rn, RmSSAX -Signed subtract 16{Rd,} Rn, RmSSUB16 -Signed subtract 8{Rd,} Rn, RmSSUB8 -Store multiple registers, increment afterRn{!}, reglistSTM 111June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table2-13.Cortex-M4FInstructionSummary (continued) FlagsBriefDescriptionOperandsMnemonic -Store multiple registers, decrement before Rn{!}, reglistSTMDB, STMEA -Store multiple registers, increment afterRn{!}, reglistSTMFD, STMIA -Store register wordRt, [Rn {, #offset}]STR -Store register byteRt, [Rn {, #offset}]STRB, STRBT -Store register two wordsRt, Rt2, [Rn {, #offset}]STRD -Store register exclusiveRt, Rt, [Rn {, #offset}]STREX -Store register exclusive byteRd, Rt, [Rn]STREXB -Store register exclusive halfwordRd, Rt, [Rn]STREXH -Store register halfwordRt, [Rn {, #offset}]STRH, STRHT -Store register signed byteRt, [Rn {, #offset}]STRSB, STRSBT -Store register signed halfwordRt, [Rn {, #offset}]STRSH, STRSHT -Store register wordRt, [Rn {, #offset}]STRT N,Z,C,VSubtract{Rd,} Rn, Op2SUB, SUBS N,Z,C,VSubtract 12-bit constant{Rd,} Rn, #imm12SUB, SUBW -Supervisor call#immSVC -Extend 8 bits to 32 and add{Rd,} Rn, Rm, {,ROR #}SXTAB -Dual extend 8 bits to 16 and add{Rd,} Rn, Rm,{,ROR #}SXTAB16 -Extend 16 bits to 32 and add{Rd,} Rn, Rm,{,ROR #}SXTAH -Signed extend byte 16{Rd,} Rm {,ROR #n}SXTB16 -Sign extend a byte{Rd,} Rm {,ROR #n}SXTB -Sign extend a halfword{Rd,} Rm {,ROR #n}SXTH -Table branch byte[Rn, Rm]TBB -Table branch halfword[Rn, Rm, LSL #1]TBH N,Z,CTest equivalenceRn, Op2TEQ N,Z,CTestRn, Op2TST GEUnsigned add 16{Rd,} Rn, RmUADD16 GEUnsigned add 8{Rd,} Rn, RmUADD8 GEUnsigned add and subtract with exchange {Rd,} Rn, RmUASX -Unsigned halving add 16{Rd,} Rn, RmUHADD16 -Unsigned halving add 8{Rd,} Rn, RmUHADD8 -Unsigned halving add and subtract with exchange {Rd,} Rn, RmUHASX -Unsigned halving subtract and add with exchange {Rd,} Rn, RmUHSAX -Unsigned halving subtract 16{Rd,} Rn, RmUHSUB16 -Unsigned halving subtract 8{Rd,} Rn, RmUHSUB8 -Unsigned bit field extractRd, Rn, #lsb, #widthUBFX -Unsigned divide{Rd,} Rn, RmUDIV -Unsigned multiply accumulate accumulate long (32x32+64), 64-bit result RdLo, RdHi, Rn, RmUMAAL June 12, 2014112 Texas Instruments-Production Data The Cortex-M4F Processor

Table2-13.Cortex-M4FInstructionSummary (continued) FlagsBriefDescriptionOperandsMnemonic -Unsigned multiply with accumulate (32x32+32+32), 64-bit result RdLo, RdHi, Rn, RmUMLAL -Unsigned multiply (32x 2), 64-bit resultRdLo, RdHi, Rn, RmUMULL -Unsigned Saturating Add 16{Rd,} Rn, RmUQADD16 -Unsigned Saturating Add 8{Rd,} Rn, RmUQADD8 -Unsigned Saturating Add and Subtract with Exchange {Rd,} Rn, RmUQASX -Unsigned Saturating Subtract and Add with Exchange {Rd,} Rn, RmUQSAX -Unsigned Saturating Subtract 16{Rd,} Rn, RmUQSUB16 -Unsigned Saturating Subtract 8{Rd,} Rn, RmUQSUB8 -Unsigned Sum of Absolute Differences{Rd,} Rn, RmUSAD8 -Unsigned Sum of Absolute Differences and Accumulate {Rd,} Rn, Rm, RaUSADA8 QUnsigned SaturateRd, #n, Rm {,shift #s}USAT QUnsigned Saturate 16Rd, #n, RmUSAT16 GEUnsigned Subtract and add with Exchange {Rd,} Rn, RmUSAX GEUnsigned Subtract 16{Rd,} Rn, RmUSUB16 GEUnsigned Subtract 8{Rd,} Rn, RmUSUB8 -Rotate, extend 8 bits to 32 and Add{Rd,} Rn, Rm, {,ROR #}UXTAB -Rotate, dual extend 8 bits to 16 and Add{Rd,} Rn, Rm, {,ROR #}UXTAB16 -Rotate, unsigned extend and Add Halfword {Rd,} Rn, Rm, {,ROR #}UXTAH -Zero extend a Byte{Rd,} Rm, {,ROR #n}UXTB -Unsigned Extend Byte 16{Rd,} Rm, {,ROR #n}UXTB16 -Zero extend a Halfword{Rd,} Rm, {,ROR #n}UXTH -Floating-point AbsoluteSd, SmVABS.F32 -Floating-point Add{Sd,} Sn, SmVADD.F32 FPSCRCompare two floating-point registers, or one floating-point register and zero Sd, <Sm | #0.0>VCMP.F32 FPSCRCompare two floating-point registers, or one floating-point register and zero with Invalid Operation check Sd, <Sm | #0.0>VCMPE.F32 -Convert between floating-point and integer Sd, SmVCVT.S32.F32 -Convert between floating-point and fixed point Sd, Sd, #fbitsVCVT.S16.F32 -Convert between floating-point and integer with rounding Sd, SmVCVTR.S32.F32 -Converts half-precision value to single-precision Sd, SmVCVT<B|H>.F32.F16 -Converts single-precision register to half-precision Sd, SmVCVTT<B|T>.F32.F16 -Floating-point Divide{Sd,} Sn, SmVDIV.F32 -Floating-point Fused Multiply Accumulate{Sd,} Sn, SmVFMA.F32 113June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table2-13.Cortex-M4FInstructionSummary (continued) FlagsBriefDescriptionOperandsMnemonic -Floating-point Fused Negate Multiply Accumulate {Sd,} Sn, SmVFNMA.F32 -Floating-point Fused Multiply Subtract{Sd,} Sn, SmVFMS.F32 -Floating-point Fused Negate Multiply Subtract {Sd,} Sn, SmVFNMS.F32 -Load Multiple extension registersRn{!}, listVLDM.F<32|64> -Load an extension register from memory<Dd|Sd>, [Rn]VLDR.F<32|64> -Floating-point Multiply Accumulate{Sd,} Sn, SmVLMA.F32 -Floating-point Multiply Subtract{Sd,} Sn, SmVLMS.F32 -Floating-point Move immediateSd, #immVMOV.F32 -Floating-point Move registerSd, SmVMOV -Copy ARM core register to single precision Sn, RtVMOV -Copy 2 ARM core registers to 2 single precision Sm, Sm1, Rt, Rt2VMOV -Copy ARM core register to scalarDd[x], RtVMOV -Copy scalar to ARM core registerRt, Dn[x]VMOV N,Z,C,VMove FPSCR to ARM core register or APSR Rt, FPSCRVMRS FPSCRMove to FPSCR from ARM Core registerFPSCR, RtVMSR -Floating-point Multiply{Sd,} Sn, SmVMUL.F32 -Floating-point NegateSd, SmVNEG.F32 -Floating-point Multiply and Add{Sd,} Sn, SmVNMLA.F32 -Floating-point Multiply and Subtract{Sd,} Sn, SmVNMLS.F32 -Floating-point Multiply{Sd,} Sn, SmVNMUL -Pop extension registerslistVPOP -Push extension registerslistVPUSH -Calculates floating-point Square RootSd, SmVSQRT.F32 -Floating-point register Store MultipleRn{!}, listVSTM -Stores an extension register to memorySd, [Rn]VSTR.F3<32|64> -Floating-point Subtract{Sd,} Sn, SmVSUB.F<32|64> -Wait for event-WFE -Wait for interrupt-WFI June 12, 2014114 Texas Instruments-Production Data The Cortex-M4F Processor

3 Cortex-M4Peripherals

This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor peripherals, including: ■ SysTick (see page 116) Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. ■ Nested Vectored Interrupt Controller (NVIC) (see page 117) – Facilitates low-latency exception and interrupt handling – Controls power management – Implements system control registers ■ System Control Block (SCB) (see page 118) Provides system implementation information and system control, including configuration, control, and reporting of system exceptions. ■ Memory Protection Unit (MPU) (see page 118) Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. ■ Floating-Point Unit (FPU) (see page 123) Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions. Table 3-1 on page 115 shows the address map of the Private Peripheral Bus (PPB). Some peripheral register regions are split into two address regions, as indicated by two addresses listed. Table3-1.CorePeripheralRegisterRegions Description(seepage...)CorePeripheralAddress 116System Timer0xE000.E010-0xE000.E01F 117Nested Vectored Interrupt Controller0xE000.E100-0xE000.E4EF 0xE000.EF00-0xE000.EF03 118System Control Block0xE000.E008-0xE000.E00F 0xE000.ED00-0xE000.ED3F 118Memory Protection Unit0xE000.ED90-0xE000.EDB8 123Floating Point Unit0xE000.EF30-0xE000.EF44

3.1 FunctionalDescription

This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor peripherals: SysTick, NVIC, SCB, MPU, FPU. 115June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

3.1.1 SystemTimer(SysTick)

Cortex-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example as: ■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter used to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. TheCOUNTbit in the STCTRLcontrol and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. The timer consists of three registers: ■ SysTickControlandStatus(STCTRL) : A control and status counter to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status. ■ SysTickReloadValue(STRELOAD) : The reload value for the counter, used to provide the counter's wrap value. ■ SysTickCurrentValue(STCURRENT) : The current value of the counter. When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps) to the value in theSTRELOADregister on the next clock edge, then decrements on subsequent clocks. Clearing theSTRELOADregister disables the counter on the next wrap. When the counter reaches zero, theCOUNTstatus bit is set. TheCOUNTbit clears on reads. Writing to theSTCURRENTregister clears the register and theCOUNTstatus bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. The SysTick counter runs on either the system clock or the precision internal oscillator (PIOSC) divided by 4. If this clock signal is stopped for low power mode, the SysTick counter stops. SysTick can be kept running during Deep-sleep mode by setting theCLK_SRCbit in theSysTickControl andStatusRegister(STCTRL) register and ensuring that thePIOSCPDbit in theDeepSleep ClockConfiguration(DSLPCLKCFG)register is clear. Ensure software uses aligned word accesses to access the SysTick registers. The SysTick counter reload and current value are undefined at reset; the correct initialization sequence for the SysTick counter is: 1. Program the value in theSTRELOADregister. 2. Clear theSTCURRENTregister by writing to it with any value. 3. Configure theSTCTRLregister for the required operation. Note: When the processor is halted for debugging, the counter does not decrement. June 12, 2014116 Texas Instruments-Production Data Cortex-M4 Peripherals

3.1.2 NestedVectoredInterruptController(NVIC)

This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: ■ 72 interrupts. ■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. ■ Low-latency exception and interrupt handling. ■ Level and pulse detection of interrupt signals. ■ Dynamic reprioritization of interrupts. ■ Grouping of priority values into group priority and subpriority fields. ■ Interrupt tail-chaining. ■ An external Non-maskable interrupt (NMI). The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low latency exception handling.

3.1.2.1 Level-SensitiveandPulseInterrupts

The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt. When the processor enters the ISR, it automatically removes the pending state from the interrupt (see “Hardware and Software Control of Interrupts” on page 117 for more information). For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. As a result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing.

3.1.2.2 HardwareandSoftwareControlofInterrupts

The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons: ■ The NVIC detects that the interrupt signal is High and the interrupt is not active. ■ The NVIC detects a rising edge on the interrupt signal. ■ Software writes to the corresponding interrupt set-pending register bit, or to theSoftwareTrigger Interrupt(SWTRIG) register to make a Software-Generated Interrupt pending. See theINTbit in thePEND0register on page 139 orSWTRIGon page 149. A pending interrupt remains pending until one of the following: 117June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to active. Then: – For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive. – For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive. ■ Software writes to the corresponding interrupt clear-pending register bit – For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. – For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending or to active, if the state was active and pending.

3.1.3 SystemControlBlock(SCB)

The System Control Block (SCB) provides system implementation information and system control, including configuration, control, and reporting of the system exceptions.

3.1.4 MemoryProtectionUnit(MPU)

This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions and defines the location, size, access permissions, and memory attributes of each region. The MPU supports independent attribute settings for each region, overlapping regions, and export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines eight separate memory regions, 0-7, and a background region. When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. The Cortex-M4 MPU memory map is unified, meaning that instruction accesses and data accesses have the same region settings. If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management fault, causing a fault exception and possibly causing termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection. Configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes” on page 88 for more information). June 12, 2014118 Texas Instruments-Production Data Cortex-M4 Peripherals

Table 3-2 on page 119 shows the possible MPU region attributes. See the section called “MPU Configuration for a Tiva™ C Series Microcontroller” on page 123 for guidelines for programming a microcontroller implementation. Table3-2.MemoryAttributesSummary DescriptionMemoryType All accesses to Strongly Ordered memory occur in program order.Strongly Ordered Memory-mapped peripheralsDevice Normal memoryNormal To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure software uses aligned accesses of the correct size to access MPU registers: ■ Except for theMPURegionAttributeandSize(MPUATTR) register, all MPU registers must be accessed with aligned word accesses. ■ The MPUATTRregister can be accessed with byte or aligned halfword or word accesses. The processor does not support unaligned accesses to MPU registers. When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup.

3.1.4.1 UpdatinganMPURegion

To update the attributes for an MPU region, theMPURegionNumber(MPUNUMBER) , MPU RegionBaseAddress(MPUBASE) and MPUATTRregisters must be updated. Each register can be programmed separately or with a multiple-word write to program all of these registers. You can use theMPUBASExand MPUATTRxaliases to program up to four regions simultaneously using an STMinstruction. Updating an MPU Region Using Separate Words This example simple code configures one region: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R4, [R0, #0x4] ; Region Base Address STRH R2, [R0, #0x8] ; Region Size and Enable STRH R3, [R0, #0xA] ; Region Attribute Disable a region before writing new region settings to the MPU if you have previously enabled the region being changed. For example: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register 119June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

STR R1, [R0, #0x0] ; Region Number BIC R2, R2, #1 ; Disable STRH R2, [R0, #0x8] ; Region Size and Enable STR R4, [R0, #0x4] ; Region Base Address STRH R3, [R0, #0xA] ; Region Attribute ORR R2, #1 ; Enable STRH R2, [R0, #0x8] ; Region Size and Enable Software must use memory barrier instructions: ■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings. ■ After MPU setup, if it includes memory transfers that must use the new MPU settings. However, memory barrier instructions are not required if the MPU setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanism cause memory barrier behavior. Software does not need any memory barrier instructions during MPU setup, because it accesses the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region. For example, if all of the memory access behavior is intended to take effect immediately after the programming sequence, then aDSBinstruction and anISBinstruction should be used. ADSBis required after changing MPU settings, such as at the end of context switch. AnISBis required if the code that programs the MPU region or regions is entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then an ISBis not required. Updating an MPU Region Using Multi-Word Writes The MPU can be programmed directly using multi-word writes, depending how the information is divided. Consider the following reprogramming: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R2, [R0, #0x4] ; Region Base Address STR R3, [R0, #0x8] ; Region Attribute, Size and Enable An STMinstruction can be used to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ; Region number, address, attribute, size and enable This operation can be done in two words for prepacked information, meaning that theMPURegion BaseAddress(MPUBASE) register (see page 183) contains the required region number and has the VALIDbit set. This method can be used when the data is statically packed, for example in a boot loader: June 12, 2014120 Texas Instruments-Production Data Cortex-M4 Peripherals

; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and region number combined ; with VALID (bit 4) set STR R2, [R0, #0x4] ; Region Attribute, Size and Enable Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in theSRDfield of theMPURegionAttributeandSize(MPUATTR) register (see page 185) to disable a subregion. The least-significant bit of theSRDfield controls the first subregion, and the most-significant bit controls the last subregion. Disabling a subregion means another region overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion, the MPU issues a fault. Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, theSRD field must be configured to0x00, otherwise the MPU behavior is unpredictable. Example of SRD Use Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB. To ensure the attributes from region one apply to the first 128 KB region, configure theSRDfield for region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 121 shows. Figure3-1.SRDUseExample Region 1 Disabled subregion Disabled subregion Region 2, with subregions Base address of both regions Of fset from base address 64KB 128KB 192KB 256KB 320KB 384KB 448KB 512KB

3.1.4.2 MPUAccessPermissionAttributes

The access permission bits,TEX, S, C, B, AP, andXNof theMPUATTRregister, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. Table 3-3 on page 121 shows the encodings for theTEX, C, B, andSaccess permission bits. All encodings are shown for completeness, however the current implementation of the Cortex-M4 does not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration for a Tiva™ C Series Microcontroller” on page 123 for information on programming the MPU for TM4C1233D5PZ implementations. Table3-3.TEX,S,C,andBBitFieldEncoding OtherAttributesShareabilityMemoryTypeB CSTEX -ShareableStrongly Ordered0 0xa000b -ShareableDevice1 0xa000 121June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table3-3.TEX,S,C,andBBitFieldEncoding (continued) OtherAttributesShareabilityMemoryTypeB CSTEX Outer and inner write-through. No write allocate. Not shareableNormal0 10000 ShareableNormal0 11000 Not shareableNormal1 10000 ShareableNormal1 11000 Outer and inner non-cacheable. Not shareableNormal0 00001 ShareableNormal0 01001 --Reserved encoding1 0xa001 --Reserved encoding0 1xa001 Outer and inner write-back. Write and read allocate. Not shareableNormal1 10001 ShareableNormal1 11001 Nonshared Device.Not shareableDevice0 0xa010 --Reserved encoding1 0xa010 --Reserved encodingxa1xa010 Cached memory (BB = outer policy, AA = inner policy). See Table 3-4 for the encoding of the AA and BB bits. Not shareableNormalA A01BB ShareableNormalA A11BB a. The MPU ignores the value of this bit. Table 3-4 on page 122 shows the cache policy for memory attribute encodings with aTEXvalue in the range of 0x4-0x7. Table3-4.CachePolicyforMemoryAttributeEncoding CorrespondingCachePolicyEncoding,AAorBB Non-cacheable00 Write back, write and read allocate01 Write through, no write allocate10 Write back, no write allocate11 Table 3-5 on page 122 shows theAPencodings in theMPUATTRregister that define the access permissions for privileged and unprivileged software. Table3-5.APBitFieldEncoding DescriptionUnprivileged Permissions Privileged Permissions AP BitField All accesses generate a permission fault.No accessNo access000 Access from privileged software only.No accessRW001 Writes by unprivileged software generate a permission fault. RORW010 Full access.RWRW011 Reserved.UnpredictableUnpredictable100 Reads by privileged software only.No accessRO101 June 12, 2014122 Texas Instruments-Production Data Cortex-M4 Peripherals

Table3-5.APBitFieldEncoding (continued) DescriptionUnprivileged Permissions Privileged Permissions AP BitField Read-only, by privileged or unprivileged software.RORO110 Read-only, by privileged or unprivileged software.RORO111 MPU Configuration for a Tiva™ C Series Microcontroller Tiva™ C Series microcontrollers have only a single processor and no caches. As a result, the MPU should be programmed as shown in Table 3-6 on page 123. Table3-6.MemoryRegionAttributesforTiva™CSeriesMicrocontrollers MemoryTypeandAttributesB C STEXMemoryRegion Normal memory, non-shareable, write-through0 1 0000bFlash memory Normal memory, shareable, write-through0 1 1000bInternal SRAM Normal memory, shareable, write-back, write-allocate 1 1 1000bExternal SRAM Device memory, shareable1 0 1000bPeripherals In current Tiva™ C Series microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations.

3.1.4.3 MPUMismatch

When an access violates the MPU permissions, the processor generates a memory management fault (see “Exceptions and Interrupts” on page 85 for more information). TheMFAULTSTATregister indicates the cause of the fault. See page 170 for more information.

3.1.5 Floating-PointUnit(FPU)

This section describes the Floating-Point Unit (FPU) and the registers it uses. The FPU provides: ■ 32-bit instructions for single-precision (C float) data-processing operations ■ Combined multiply and accumulate instructions for increased precision (Fused MAC) ■ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate, division, and square-root ■ Hardware support for denormals and all IEEE rounding modes ■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers ■ Decoupled three stage pipeline The Cortex-M4F FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions. The FPU provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard. The FPU's single-precision extension registers can also be accessed as 16 doubleword registers for load, store, and move operations. 123June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

3.1.5.1 FPUViewsoftheRegisterBank

The FPU provides an extension register file containing 32 single-precision registers. These can be viewed as: ■ Sixteen 64-bit doubleword registers, D0-D15 ■ Thirty-two 32-bit single-word registers, S0-S31 ■ A combination of registers from the above views Figure3-2.FPURegisterBank ... D14 D15 S28 S29 S30 S31 ... The mapping between the registers is as follows: ■ S<2n> maps to the least significant half of D<n> ■ S<2n+1> maps to the most significant half of D<n> For example, you can access the least significant half of the value in D6 by accessing S12, and the most significant half of the elements by accessing S13.

3.1.5.2 ModesofOperation

The FPU provides three modes of operation to accommodate a variety of applications. Full-Compliancemode. In Full-Compliance mode, the FPU processes all operations according to the IEEE 754 standard in hardware. Flush-to-Zeromode. Setting theFZbit of theFloating-PointStatusandControl(FPSC) register enables Flush-to-Zero mode. In this mode, the FPU treats all subnormal input operands of arithmetic CDP operations as zeros in the operation. Exceptions that result from a zero operand are signalled appropriately. VABS, VNEG, and VMOV are not considered arithmetic CDP operations and are not affected by Flush-to-Zero mode. A result that is tiny, as described in the IEEE 754 standard, where the destination precision is smaller in magnitude than the minimum normal value before rounding, is replaced with a zero. TheIDCbit inFPSCindicates when an input flush occurs. TheUFCbit in FPSCindicates when a result flush occurs. DefaultNaNmode. Setting theDNbit in theFPSCregister enables default NaN mode. In this mode, the result of any arithmetic data processing operation that involves an input NaN, or that generates a NaN result, returns the default NaN. Propagation of the fraction bits is maintained only by VABS, June 12, 2014124 Texas Instruments-Production Data Cortex-M4 Peripherals

VNEG, and VMOV operations. All other CDP operations ignore any information in the fraction bits of an input NaN.

3.1.5.3 CompliancewiththeIEEE754standard

When Default NaN (DN) and Flush-to-Zero (FZ) modes are disabled, FPv4 functionality is compliant with the IEEE 754 standard in hardware. No support code is required to achieve this compliance.

3.1.5.4 CompleteImplementationoftheIEEE754standard

The Cortex-M4F floating point instruction set does not support all operations defined in the IEEE 754-2008 standard. Unsupported operations include, but are not limited to the following: ■ Remainder ■ Round floating-point number to integer-valued floating-point number ■ Binary-to-decimal conversions ■ Decimal-to-binary conversions ■ Direct comparison of single-precision and double-precision values The Cortex-M4 FPU supports fused MAC operations as described in the IEEE standard. For complete implementation of the IEEE 754-2008 standard, floating-point functionality must be augmented with library functions.

3.1.5.5 IEEE754standardimplementationchoices

All single-precision values with the maximum exponent field value and a nonzero fraction field are valid NaNs. A most-significant fraction bit of zero indicates a Signaling NaN (SNaN). A one indicates a Quiet NaN (QNaN). Two NaN values are treated as different NaNs if they differ in any bit. The below table shows the default NaN values. FractionFractionSign bit [22] = 1, bits [21:0] are all zeros0xFF0 Processing of input NaNs for ARM floating-point functionality and libraries is defined as follows: ■ In full-compliance mode, NaNs are handled as described in the ARM Architecture Reference Manual. The hardware processes the NaNs directly for arithmetic CDP instructions. For data transfer operations, NaNs are transferred without raising the Invalid Operation exception. For the non-arithmetic CDP instructions, VABS, VNEG, and VMOV, NaNs are copied, with a change of sign if specified in the instructions, without causing the Invalid Operation exception. ■ In default NaN mode, arithmetic CDP instructions involving NaN operands return the default NaN regardless of the fractions of any NaN operands. SNaNs in an arithmetic CDP operation set the IOC flag, FPSCR[0]. NaN handling by data transfer and non-arithmetic CDP instructions is the same as in full-compliance mode. 125June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table3-7.QNaNandSNaNHandling WithSNaNOperandWithQNaNOperandDefaultNaN Mode InstructionType IOCa set. The SNaN is quieted and the result NaN is determined by the rules given in the ARM Architecture Reference Manual. The QNaN or one of the QNaN operands, if there is more than one, is returned according to the rules given in the ARM Architecture Reference Manual. Off Arithmetic CDP IOCa set. Default NaN returns.Default NaN returns.On NaN passes to destination with sign changed as appropriate.Off/OnNon-arithmetic CDP IOC set. Unordered compare.Unordered compare.-FCMP(Z) IOC set. Unordered compare.IOC set. Unordered compare.-FCMPE(Z) All NaNs transferred.Off/OnLoad/store a. IOC is the Invalid Operation exception flag, FPSCR[0]. Comparisons Comparison results modify the flags in the FPSCR. You can use the MVRS APSR_nzcv instruction (formerly FMSTAT) to transfer the current flags from the FPSCR to the APSR. See the ARM Architecture Reference Manual for mapping of IEEE 754-2008 standard predicates to ARM conditions. The flags used are chosen so that subsequent conditional execution of ARM instructions can test the predicates defined in the IEEE standard. Underflow The Cortex-M4F FPU uses the before rounding form of tininess and the inexact result form of loss of accuracy as described in the IEEE 754-2008 standard to generate Underflow exceptions. In flush-to-zero mode, results that are tiny before rounding, as described in the IEEE standard, are flushed to a zero, and the UFC flag, FPSCR[3], is set. See the ARM Architecture Reference Manual for information on flush-to-zero mode. When the FPU is not in flush-to-zero mode, operations are performed on subnormal operands. If the operation does not produce a tiny result, it returns the computed result, and the UFC flag, FPSCR[3], is not set. The IXC flag, FPSCR[4], is set if the operation is inexact. If the operation produces a tiny result, the result is a subnormal or zero value, and the UFC flag, FPSCR[3], is set if the result was also inexact.

3.1.5.6 Exceptions

The FPU sets the cumulative exception status flag in the FPSCR register as required for each instruction, in accordance with the FPv4 architecture. The FPU does not support user-mode traps. The exception enable bits in the FPSCR read-as-zero, and writes are ignored. The processor also has six output pins, FPIXC, FPUFC, FPOFC, FPDZC, FPIDC, and FPIOC, that each reflect the status of one of the cumulative exception flags. For a description of these outputs, see theARM Cortex-M4 Integration and Implementation Manual (ARM DII 0239, available from ARM). The processor can reduce the exception latency by using lazy stacking. See Auxiliary Control Register, ACTLR on page 4-5. This means that the processor reserves space on the stack for the FP state, but does not save that state information to the stack. See the ARMv7-M Architecture Reference Manual (available from ARM) for more information.

3.1.5.7 EnablingtheFPU

The FPU is disabled from reset. You must enable it before you can use any floating-point instructions. The processor must be in privileged mode to read from and write to theCoprocessorAccess June 12, 2014126 Texas Instruments-Production Data Cortex-M4 Peripherals

Control(CPAC) register. The below example code sequence enables the FPU in both privileged and user modes. ; CPACR is located at address 0xE000ED88 LDR.W R0, =0xE000ED88 ; Read CPACR LDR R1, [R0] ; Set bits 20-23 to enable CP10 and CP11 coprocessors ORR R1, R1, #(0xF << 20) ; Write back the modified value to the CPACR STR R1, [R0]; wait for store to complete DSB ;reset pipeline now the FPU is enabled ISB

3.2 RegisterMap

Table 3-8 on page 127 lists the Cortex-M4 Peripheral SysTick, NVIC, MPU, FPU and SCB registers. The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals base address of 0xE000.E000. Note: Register spaces that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Table3-8.PeripheralsRegisterMap See pageDescriptionResetTypeNameOffset SystemTimer(SysTick)Registers 131SysTick Control and Status Register0x0000.0004RWSTCTRL0x010 133SysTick Reload Value Register-RWSTRELOAD0x014 134SysTick Current Value Register-RWCSTCURRENT0x018 NestedVectoredInterruptController(NVIC)Registers 135Interrupt 0-31 Set Enable0x0000.0000RWEN00x100 135Interrupt 32-63 Set Enable0x0000.0000RWEN10x104 135Interrupt 64-95 Set Enable0x0000.0000RWEN20x108 135Interrupt 96-127 Set Enable0x0000.0000RWEN30x10C 136Interrupt 128-138 Set Enable0x0000.0000RWEN40x110 137Interrupt 0-31 Clear Enable0x0000.0000RWDIS00x180 137Interrupt 32-63 Clear Enable0x0000.0000RWDIS10x184 137Interrupt 64-95 Clear Enable0x0000.0000RWDIS20x188 137Interrupt 96-127 Clear Enable0x0000.0000RWDIS30x18C 138Interrupt 128-138 Clear Enable0x0000.0000RWDIS40x190 139Interrupt 0-31 Set Pending0x0000.0000RWPEND00x200 139Interrupt 32-63 Set Pending0x0000.0000RWPEND10x204 127June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table3-8.PeripheralsRegisterMap (continued) See pageDescriptionResetTypeNameOffset 139Interrupt 64-95 Set Pending0x0000.0000RWPEND20x208 139Interrupt 96-127 Set Pending0x0000.0000RWPEND30x20C 140Interrupt 128-138 Set Pending0x0000.0000RWPEND40x210 141Interrupt 0-31 Clear Pending0x0000.0000RWUNPEND00x280 141Interrupt 32-63 Clear Pending0x0000.0000RWUNPEND10x284 141Interrupt 64-95 Clear Pending0x0000.0000RWUNPEND20x288 141Interrupt 96-127 Clear Pending0x0000.0000RWUNPEND30x28C 142Interrupt 128-138 Clear Pending0x0000.0000RWUNPEND40x290 143Interrupt 0-31 Active Bit0x0000.0000ROACTIVE00x300 143Interrupt 32-63 Active Bit0x0000.0000ROACTIVE10x304 143Interrupt 64-95 Active Bit0x0000.0000ROACTIVE20x308 143Interrupt 96-127 Active Bit0x0000.0000ROACTIVE30x30C 144Interrupt 128-138 Active Bit0x0000.0000ROACTIVE40x310 145Interrupt 0-3 Priority0x0000.0000RWPRI00x400 145Interrupt 4-7 Priority0x0000.0000RWPRI10x404 145Interrupt 8-11 Priority0x0000.0000RWPRI20x408 145Interrupt 12-15 Priority0x0000.0000RWPRI30x40C 145Interrupt 16-19 Priority0x0000.0000RWPRI40x410 145Interrupt 20-23 Priority0x0000.0000RWPRI50x414 145Interrupt 24-27 Priority0x0000.0000RWPRI60x418 145Interrupt 28-31 Priority0x0000.0000RWPRI70x41C 145Interrupt 32-35 Priority0x0000.0000RWPRI80x420 145Interrupt 36-39 Priority0x0000.0000RWPRI90x424 145Interrupt 40-43 Priority0x0000.0000RWPRI100x428 145Interrupt 44-47 Priority0x0000.0000RWPRI110x42C 145Interrupt 48-51 Priority0x0000.0000RWPRI120x430 145Interrupt 52-55 Priority0x0000.0000RWPRI130x434 145Interrupt 56-59 Priority0x0000.0000RWPRI140x438 145Interrupt 60-63 Priority0x0000.0000RWPRI150x43C 147Interrupt 64-67 Priority0x0000.0000RWPRI160x440 147Interrupt 68-71 Priority0x0000.0000RWPRI170x444 147Interrupt 72-75 Priority0x0000.0000RWPRI180x448 June 12, 2014128 Texas Instruments-Production Data Cortex-M4 Peripherals

Table3-8.PeripheralsRegisterMap (continued) See pageDescriptionResetTypeNameOffset 147Interrupt 76-79 Priority0x0000.0000RWPRI190x44C 147Interrupt 80-83 Priority0x0000.0000RWPRI200x450 147Interrupt 84-87 Priority0x0000.0000RWPRI210x454 147Interrupt 88-91 Priority0x0000.0000RWPRI220x458 147Interrupt 92-95 Priority0x0000.0000RWPRI230x45C 147Interrupt 96-99 Priority0x0000.0000RWPRI240x460 147Interrupt 100-103 Priority0x0000.0000RWPRI250x464 147Interrupt 104-107 Priority0x0000.0000RWPRI260x468 147Interrupt 108-111 Priority0x0000.0000RWPRI270x46C 147Interrupt 112-115 Priority0x0000.0000RWPRI280x470 147Interrupt 116-119 Priority0x0000.0000RWPRI290x474 147Interrupt 120-123 Priority0x0000.0000RWPRI300x478 147Interrupt 124-127 Priority0x0000.0000RWPRI310x47C 147Interrupt 128-131 Priority0x0000.0000RWPRI320x480 147Interrupt 132-135 Priority0x0000.0000RWPRI330x484 147Interrupt 136-138 Priority0x0000.0000RWPRI340x488 149Software Trigger Interrupt0x0000.0000WOSWTRIG0xF00 SystemControlBlock(SCB)Registers 150Auxiliary Control0x0000.0000RWACTLR0x008 152CPU ID Base0x410F.C241ROCPUID0xD00 153Interrupt Control and State0x0000.0000RWINTCTRL0xD04 156Vector Table Offset0x0000.0000RWVTABLE0xD08 157Application Interrupt and Reset Control0xFA05.0000RWAPINT0xD0C 159System Control0x0000.0000RWSYSCTRL0xD10 161Configuration and Control0x0000.0200RWCFGCTRL0xD14 163System Handler Priority 10x0000.0000RWSYSPRI10xD18 164System Handler Priority 20x0000.0000RWSYSPRI20xD1C 165System Handler Priority 30x0000.0000RWSYSPRI30xD20 166System Handler Control and State0x0000.0000RWSYSHNDCTRL0xD24 170Configurable Fault Status0x0000.0000RW1CFAULTSTAT0xD28 176Hard Fault Status0x0000.0000RW1CHFAULTSTAT0xD2C 177Memory Management Fault Address-RWMMADDR0xD34 129June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table3-8.PeripheralsRegisterMap (continued) See pageDescriptionResetTypeNameOffset 178Bus Fault Address-RWFAULTADDR0xD38 MemoryProtectionUnit(MPU)Registers 179MPU Type0x0000.0800ROMPUTYPE0xD90 180MPU Control0x0000.0000RWMPUCTRL0xD94 182MPU Region Number0x0000.0000RWMPUNUMBER0xD98 183MPU Region Base Address0x0000.0000RWMPUBASE0xD9C 185MPU Region Attribute and Size0x0000.0000RWMPUATTR0xDA0 183MPU Region Base Address Alias 10x0000.0000RWMPUBASE10xDA4 185MPU Region Attribute and Size Alias 10x0000.0000RWMPUATTR10xDA8 183MPU Region Base Address Alias 20x0000.0000RWMPUBASE20xDAC 185MPU Region Attribute and Size Alias 20x0000.0000RWMPUATTR20xDB0 183MPU Region Base Address Alias 30x0000.0000RWMPUBASE30xDB4 185MPU Region Attribute and Size Alias 30x0000.0000RWMPUATTR30xDB8 Floating-PointUnit(FPU)Registers 188Coprocessor Access Control0x0000.0000RWCPAC0xD88 189Floating-Point Context Control0xC000.0000RWFPCC0xF34 191Floating-Point Context Address-RWFPCA0xF38 192Floating-Point Default Status Control0x0000.0000RWFPDSC0xF3C

3.3 SystemTimer(SysTick)RegisterDescriptions

This section lists and describes the System Timer registers, in numerical order by address offset. June 12, 2014130 Texas Instruments-Production Data Cortex-M4 Peripherals

Register1:SysTickControlandStatusRegister(STCTRL),offset0x010 Note: This register can only be accessed from privileged mode. The SysTickSTCTRLregister enables the SysTick features. SysTick Control and Status Register (STCTRL) Base 0xE000.E000 Offset 0x010 Type RW, reset 0x0000.0004 16171819202122232425262728293031 COUNTreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ENABLEINTENCLK_SRCreserved RWRWRWROROROROROROROROROROROROROType 0010000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved31:17 Count Flag DescriptionValue The SysTick timer has not counted to 0 since the last time this bit was read. The SysTick timer has counted to 0 since the last time this bit was read. This bit is cleared by a read of the register or if theSTCURRENTregister is written with any value. If read by the debugger using the DAP, this bit is cleared only if the MasterTypebit in theAHB-APControlRegister is clear. Otherwise, the COUNTbit is not changed by the debugger read. See theARM® Debug Interface V5 Architecture Specification for more information on MasterType. 0ROCOUNT16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved15:3 Clock Source DescriptionValue Precision internal oscillator (PIOSC) divided by 40 System clock1 1RWCLK_SRC2 131June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Interrupt Enable DescriptionValue Interrupt generation is disabled. Software can use the COUNTbit to determine if the counter has ever reached 0. An interrupt is generated to the NVIC when SysTick counts to 0. 0RWINTEN1 Enable DescriptionValue The counter is disabled.0 Enables SysTick to operate in a multi-shot way. That is, the counter loads theRELOADvalue and begins counting down. On reaching 0, theCOUNTbit is set and an interrupt is generated if enabled byINTEN. The counter then loads the RELOADvalue again and begins counting. 0RWENABLE0 June 12, 2014132 Texas Instruments-Production Data Cortex-M4 Peripherals

Register2:SysTickReloadValueRegister(STRELOAD),offset0x014 Note: This register can only be accessed from privileged mode. The STRELOADregister specifies the start value to load into theSysTickCurrentValue (STCURRENT)register when the counter reaches 0. The start value can be between 0x1 and 0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the COUNTbit are activated when counting from 1 to 0. SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required every 100 clock pulses, 99 must be written into theRELOADfield. Note that in order to access this register correctly, the system clock must be faster than 8 MHz. SysTick Reload Value Register (STRELOAD) Base 0xE000.E000 Offset 0x014 Type RW, reset - 16171819202122232425262728293031 RELOADreserved RWRWRWRWRWRWRWRWROROROROROROROROType 0000000000000000Reset 0123456789101112131415 RELOAD RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:24 Reload Value Value to load into theSysTickCurrentValue(STCURRENT) register when the counter reaches 0. 0x00.0000RWRELOAD23:0 133June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register3:SysTickCurrentValueRegister(STCURRENT),offset0x018 Note: This register can only be accessed from privileged mode. The STCURRENTregister contains the current value of the SysTick counter. SysTick Current Value Register (STCURRENT) Base 0xE000.E000 Offset 0x018 Type RWC, reset - 16171819202122232425262728293031 CURRENTreserved RWCRWCRWCRWCRWCRWCRWCRWCROROROROROROROROType 0000000000000000Reset 0123456789101112131415 CURRENT RWCRWCRWCRWCRWCRWCRWCRWCRWCRWCRWCRWCRWCRWCRWCRWCType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:24 Current Value This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears theCOUNTbit of theSTCTRLregister. 0x00.0000RWCCURRENT23:0

3.4 NVICRegisterDescriptions

This section lists and describes the NVIC registers, in numerical order by address offset. The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended while in unprivileged mode by enabling theConfigurationandControl(CFGCTRL) register. Any other unprivileged mode access causes a bus fault. Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. An interrupt can enter the pending state even if it is disabled. Before programming theVTABLEregister to relocate the vector table, ensure the vector table entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such as interrupts. For more information, see page 156. June 12, 2014134 Texas Instruments-Production Data Cortex-M4 Peripherals

Register4:Interrupt0-31SetEnable(EN0),offset0x100 Register5:Interrupt32-63SetEnable(EN1),offset0x104 Register6:Interrupt64-95SetEnable(EN2),offset0x108 Register7:Interrupt96-127SetEnable(EN3),offset0x10C Note: This register can only be accessed from privileged mode. The ENnregisters enable interrupts and show which interrupts are enabled. Bit 0 ofEN0corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 ofEN1corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 ofEN2corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 ofEN3corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 ofEN4(see page 136) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 97 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 0-31 Set Enable (EN0) Base 0xE000.E000 Offset 0x100 Type RW, reset 0x0000.0000 16171819202122232425262728293031 INT RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset 0123456789101112131415 INT RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Interrupt Enable DescriptionValue On a read, indicates the interrupt is disabled. On a write, no effect. On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the correspondingINT[n]bit in the DISnregister. 0x0000.0000RWINT31:0 135June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register8:Interrupt128-138SetEnable(EN4),offset0x110 Note: This register can only be accessed from privileged mode. The EN4register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 97 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 128-138 Set Enable (EN4) Base 0xE000.E000 Offset 0x110 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INTreserved RWRWRWRWRWRWRWRWRWRWRWROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:11 Interrupt Enable DescriptionValue On a read, indicates the interrupt is disabled. On a write, no effect. On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can only be cleared by setting the correspondingINT[n]bit in the DIS4register. 0x0RWINT10:0 June 12, 2014136 Texas Instruments-Production Data Cortex-M4 Peripherals

Register9:Interrupt0-31ClearEnable(DIS0),offset0x180 Register10:Interrupt32-63ClearEnable(DIS1),offset0x184 Register11:Interrupt64-95ClearEnable(DIS2),offset0x188 Register12:Interrupt96-127ClearEnable(DIS3),offset0x18C Note: This register can only be accessed from privileged mode. The DISnregisters disable interrupts. Bit 0 ofDIS0corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 ofDIS1corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of DIS2corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 ofDIS3corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 ofDIS4(see page 138) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 97 for interrupt assignments. Interrupt 0-31 Clear Enable (DIS0) Base 0xE000.E000 Offset 0x180 Type RW, reset 0x0000.0000 16171819202122232425262728293031 INT RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset 0123456789101112131415 INT RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Interrupt Disable DescriptionValue On a read, indicates the interrupt is disabled. On a write, no effect. On a read, indicates the interrupt is enabled. On a write, clears the correspondingINT[n]bit in theEN0 register, disabling interrupt [n]. 0x0000.0000RWINT31:0 137June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register13:Interrupt128-138ClearEnable(DIS4),offset0x190 Note: This register can only be accessed from privileged mode. The DIS4register disables interrupts. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 97 for interrupt assignments. Interrupt 128-138 Clear Enable (DIS4) Base 0xE000.E000 Offset 0x190 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INTreserved RWRWRWRWRWRWRWRWRWRWRWROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:11 Interrupt Disable DescriptionValue On a read, indicates the interrupt is disabled. On a write, no effect. On a read, indicates the interrupt is enabled. On a write, clears the correspondingINT[n]bit in theEN4 register, disabling interrupt [n]. 0x0RWINT10:0 June 12, 2014138 Texas Instruments-Production Data Cortex-M4 Peripherals

Register14:Interrupt0-31SetPending(PEND0),offset0x200 Register15:Interrupt32-63SetPending(PEND1),offset0x204 Register16:Interrupt64-95SetPending(PEND2),offset0x208 Register17:Interrupt96-127SetPending(PEND3),offset0x20C Note: This register can only be accessed from privileged mode. The PENDnregisters force interrupts into the pending state and show which interrupts are pending. Bit 0 ofPEND0corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 ofPEND1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 ofPEND2corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 ofPEND3corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 ofPEND4(see page 140) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 97 for interrupt assignments. Interrupt 0-31 Set Pending (PEND0) Base 0xE000.E000 Offset 0x200 Type RW, reset 0x0000.0000 16171819202122232425262728293031 INT RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset 0123456789101112131415 INT RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Interrupt Set Pending DescriptionValue On a read, indicates that the interrupt is not pending. On a write, no effect. On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the correspondingINT[n]bit in the UNPEND0register. 0x0000.0000RWINT31:0 139June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register18:Interrupt128-138SetPending(PEND4),offset0x210 Note: This register can only be accessed from privileged mode. The PEND4register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 97 for interrupt assignments. Interrupt 128-138 Set Pending (PEND4) Base 0xE000.E000 Offset 0x210 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INTreserved RWRWRWRWRWRWRWRWRWRWRWROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:11 Interrupt Set Pending DescriptionValue On a read, indicates that the interrupt is not pending. On a write, no effect. On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the correspondingINT[n]bit in the UNPEND4register. 0x0RWINT10:0 June 12, 2014140 Texas Instruments-Production Data Cortex-M4 Peripherals

Register19:Interrupt0-31ClearPending(UNPEND0),offset0x280 Register20:Interrupt32-63ClearPending(UNPEND1),offset0x284 Register21:Interrupt64-95ClearPending(UNPEND2),offset0x288 Register22:Interrupt96-127ClearPending(UNPEND3),offset0x28C Note: This register can only be accessed from privileged mode. The UNPENDnregisters show which interrupts are pending and remove the pending state from interrupts. Bit 0 ofUNPEND0corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of UNPEND1corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 ofUNPEND2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 ofUNPEND3corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 ofUNPEND4(see page 142) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 97 for interrupt assignments. Interrupt 0-31 Clear Pending (UNPEND0) Base 0xE000.E000 Offset 0x280 Type RW, reset 0x0000.0000 16171819202122232425262728293031 INT RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset 0123456789101112131415 INT RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Interrupt Clear Pending DescriptionValue On a read, indicates that the interrupt is not pending. On a write, no effect. On a read, indicates that the interrupt is pending. On a write, clears the correspondingINT[n]bit in thePEND0 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. 0x0000.0000RWINT31:0 141June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register23:Interrupt128-138ClearPending(UNPEND4),offset0x290 Note: This register can only be accessed from privileged mode. The UNPEND4register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 97 for interrupt assignments. Interrupt 128-138 Clear Pending (UNPEND4) Base 0xE000.E000 Offset 0x290 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INTreserved RWRWRWRWRWRWRWRWRWRWRWROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:11 Interrupt Clear Pending DescriptionValue On a read, indicates that the interrupt is not pending. On a write, no effect. On a read, indicates that the interrupt is pending. On a write, clears the correspondingINT[n]bit in thePEND4 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. 0x0RWINT10:0 June 12, 2014142 Texas Instruments-Production Data Cortex-M4 Peripherals

Register24:Interrupt0-31ActiveBit(ACTIVE0),offset0x300 Register25:Interrupt32-63ActiveBit(ACTIVE1),offset0x304 Register26:Interrupt64-95ActiveBit(ACTIVE2),offset0x308 Register27:Interrupt96-127ActiveBit(ACTIVE3),offset0x30C Note: This register can only be accessed from privileged mode. The UNPENDnregisters indicate which interrupts are active. Bit 0 ofACTIVE0corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 ofACTIVE1corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 ofACTIVE2corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 ofACTIVE3corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 ofACTIVE4(see page 144) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 97 for interrupt assignments. Caution – Do not manually set or clear the bits in this register . Interrupt 0-31 Active Bit (ACTIVE0) Base 0xE000.E000 Offset 0x300 Type RO, reset 0x0000.0000 16171819202122232425262728293031 INT ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INT ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Interrupt Active DescriptionValue The corresponding interrupt is not active.0 The corresponding interrupt is active, or active and pending.1 0x0000.0000ROINT31:0 143June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register28:Interrupt128-138ActiveBit(ACTIVE4),offset0x310 Note: This register can only be accessed from privileged mode. The ACTIVE4register indicates which interrupts are active. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 131. See Table 2-9 on page 97 for interrupt assignments. Caution – Do not manually set or clear the bits in this register . Interrupt 128-138 Active Bit (ACTIVE4) Base 0xE000.E000 Offset 0x310 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INTreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:11 Interrupt Active DescriptionValue The corresponding interrupt is not active.0 The corresponding interrupt is active, or active and pending.1 0x0ROINT10:0 June 12, 2014144 Texas Instruments-Production Data Cortex-M4 Peripherals

Register29:Interrupt0-3Priority(PRI0),offset0x400 Register30:Interrupt4-7Priority(PRI1),offset0x404 Register31:Interrupt8-11Priority(PRI2),offset0x408 Register32:Interrupt12-15Priority(PRI3),offset0x40C Register33:Interrupt16-19Priority(PRI4),offset0x410 Register34:Interrupt20-23Priority(PRI5),offset0x414 Register35:Interrupt24-27Priority(PRI6),offset0x418 Register36:Interrupt28-31Priority(PRI7),offset0x41C Register37:Interrupt32-35Priority(PRI8),offset0x420 Register38:Interrupt36-39Priority(PRI9),offset0x424 Register39:Interrupt40-43Priority(PRI10),offset0x428 Register40:Interrupt44-47Priority(PRI11),offset0x42C Register41:Interrupt48-51Priority(PRI12),offset0x430 Register42:Interrupt52-55Priority(PRI13),offset0x434 Register43:Interrupt56-59Priority(PRI14),offset0x438 Register44:Interrupt60-63Priority(PRI15),offset0x43C Note: This register can only be accessed from privileged mode. The PRInregisters (see also page 147) provide 3-bit priority fields for each interrupt. These registers are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows: InterruptPRInRegisterBitField Interrupt [4n+3]Bits 31:29 Interrupt [4n+2]Bits 23:21 Interrupt [4n+1]Bits 15:13 Interrupt [4n]Bits 7:5 See Table 2-9 on page 97 for interrupt assignments. Each priority level can be split into separate group priority and subpriority fields. ThePRIGROUP field in theApplicationInterruptandResetControl(APINT) register (see page 157) indicates the position of the binary point that splits the priority and subpriority fields. These registers can only be accessed from privileged mode. 145June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Interrupt 0-3 Priority (PRI0) Base 0xE000.E000 Offset 0x400 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reservedINTCreservedINTD RORORORORORWRWRWRORORORORORWRWRWType 0000000000000000Reset 0123456789101112131415 reservedINTAreservedINTB RORORORORORWRWRWRORORORORORWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Interrupt Priority for Interrupt [4n+3] This field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number of theInterruptPriority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 0x0RWINTD31:29 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved28:24 Interrupt Priority for Interrupt [4n+2] This field holds a priority value, 0-7, for the interrupt with the number [4n+2], where n is the number of theInterruptPriority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 0x0RWINTC23:21 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved20:16 Interrupt Priority for Interrupt [4n+1] This field holds a priority value, 0-7, for the interrupt with the number [4n+1], where n is the number of theInterruptPriority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 0x0RWINTB15:13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved12:8 Interrupt Priority for Interrupt [4n] This field holds a priority value, 0-7, for the interrupt with the number [4n], where n is the number of theInterruptPriority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 0x0RWINTA7:5 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved4:0 June 12, 2014146 Texas Instruments-Production Data Cortex-M4 Peripherals

Register45:Interrupt64-67Priority(PRI16),offset0x440 Register46:Interrupt68-71Priority(PRI17),offset0x444 Register47:Interrupt72-75Priority(PRI18),offset0x448 Register48:Interrupt76-79Priority(PRI19),offset0x44C Register49:Interrupt80-83Priority(PRI20),offset0x450 Register50:Interrupt84-87Priority(PRI21),offset0x454 Register51:Interrupt88-91Priority(PRI22),offset0x458 Register52:Interrupt92-95Priority(PRI23),offset0x45C Register53:Interrupt96-99Priority(PRI24),offset0x460 Register54:Interrupt100-103Priority(PRI25),offset0x464 Register55:Interrupt104-107Priority(PRI26),offset0x468 Register56:Interrupt108-111Priority(PRI27),offset0x46C Register57:Interrupt112-115Priority(PRI28),offset0x470 Register58:Interrupt116-119Priority(PRI29),offset0x474 Register59:Interrupt120-123Priority(PRI30),offset0x478 Register60:Interrupt124-127Priority(PRI31),offset0x47C Register61:Interrupt128-131Priority(PRI32),offset0x480 Register62:Interrupt132-135Priority(PRI33),offset0x484 Register63:Interrupt136-138Priority(PRI34),offset0x488 Note: This register can only be accessed from privileged mode. The PRInregisters (see also page 145) provide 3-bit priority fields for each interrupt. These registers are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows: InterruptPRInRegisterBitField Interrupt [4n+3]Bits 31:29 Interrupt [4n+2]Bits 23:21 Interrupt [4n+1]Bits 15:13 Interrupt [4n]Bits 7:5 See Table 2-9 on page 97 for interrupt assignments. Each priority level can be split into separate group priority and subpriority fields. ThePRIGROUP field in theApplicationInterruptandResetControl(APINT) register (see page 157) indicates the position of the binary point that splits the priority and subpriority fields . These registers can only be accessed from privileged mode. 147June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Interrupt 64-67 Priority (PRI16) Base 0xE000.E000 Offset 0x440 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reservedINTCreservedINTD RORORORORORWRWRWRORORORORORWRWRWType 0000000000000000Reset 0123456789101112131415 reservedINTAreservedINTB RORORORORORWRWRWRORORORORORWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Interrupt Priority for Interrupt [4n+3] This field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number of theInterruptPriority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 0x0RWINTD31:29 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved28:24 Interrupt Priority for Interrupt [4n+2] This field holds a priority value, 0-7, for the interrupt with the number [4n+2], where n is the number of theInterruptPriority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 0x0RWINTC23:21 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved20:16 Interrupt Priority for Interrupt [4n+1] This field holds a priority value, 0-7, for the interrupt with the number [4n+1], where n is the number of theInterruptPriority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 0x0RWINTB15:13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved12:8 Interrupt Priority for Interrupt [4n] This field holds a priority value, 0-7, for the interrupt with the number [4n], where n is the number of theInterruptPriority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 0x0RWINTA7:5 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved4:0 June 12, 2014148 Texas Instruments-Production Data Cortex-M4 Peripherals

Register64:SoftwareTriggerInterrupt(SWTRIG),offset0xF00 Note: Only privileged software can enable unprivileged access to theSWTRIGregister. Writing an interrupt number to theSWTRIGregister generates a Software Generated Interrupt (SGI). See Table 2-9 on page 97 for interrupt assignments. When theMAINPENDbit in theConfigurationandControl(CFGCTRL) register (see page 161) is set, unprivileged software can access theSWTRIGregister. Software Trigger Interrupt (SWTRIG) Base 0xE000.E000 Offset 0xF00 Type WO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INTIDreserved WOWOWOWOWOWOWOWOROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:8 Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. 0x00WOINTID7:0

3.5 SystemControlBlock(SCB)RegisterDescriptions

This section lists and describes the System Control Block (SCB) registers, in numerical order by address offset. The SCB registers can only be accessed from privileged mode. All registers must be accessed with aligned word accesses except for theFAULTSTATand SYSPRI1-SYSPRI3registers, which can be accessed with byte or aligned halfword or word accesses. The processor does not support unaligned accesses to system control block registers. 149June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register65:AuxiliaryControl(ACTLR),offset0x008 Note: This register can only be accessed from privileged mode. The ACTLRregister provides disable bits forITfolding, write buffer use for accesses to the default memory map, and interruption of multi-cycle instructions. By default, this register is set to provide optimum performance from the Cortex-M4 processor and does not normally require modification. Auxiliary Control (ACTLR) Base 0xE000.E000 Offset 0x008 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 DISMCYCDISWBUFDISFOLDreservedDISFPCADISOOFPreserved RWRWRWRORORORORORWRWROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:10 Disable Out-Of-Order Floating Point Disables floating-point instructions completing out of order with respect to integer instructions. 0RWDISOOFP9 Disable CONTROL.FPCA Disable automatic update of theFPCAbit in theCONTROLregister. Important: Two bits control whenFPCAcan be enabled: theASPEN bit in theFloating-PointContextControl(FPCC) register and theDISFPCAbit in theAuxiliaryControl (ACTLR)register. 0RWDISFPCA8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved7:3 Disable IT Folding DescriptionValue No effect.0 Disables ITfolding.1 In some situations, the processor can start executing the first instruction in anITblock while it is still executing theITinstruction. This behavior is calledIT folding, and improves performance, However,ITfolding can cause jitter in looping. If a task must avoid jitter, set theDISFOLDbit before executing the task, to disableITfolding. 0RWDISFOLD2 June 12, 2014150 Texas Instruments-Production Data Cortex-M4 Peripherals

DescriptionResetTypeNameBit/Field Disable Write Buffer DescriptionValue No effect.0 Disables write buffer use during default memory map accesses. In this situation, all bus faults are precise bus faults but performance is decreased because any store to memory must complete before the processor can execute the next instruction. Note: This bit only affects write buffers implemented in the Cortex-M4 processor. 0RWDISWBUF1 Disable Interrupts of Multiple Cycle Instructions DescriptionValue No effect.0 Disables interruption of load multiple and store multiple instructions. In this situation, the interrupt latency of the processor is increased because anyLDMor STMmust complete before the processor can stack the current state and enter the interrupt handler. 0RWDISMCYC0 151June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register66:CPUIDBase(CPUID),offset0xD00 Note: This register can only be accessed from privileged mode. The CPUIDregister contains the ARM® Cortex™-M4 processor part number, version, and implementation information. CPU ID Base (CPUID) Base 0xE000.E000 Offset 0xD00 Type RO, reset 0x410F.C241 16171819202122232425262728293031 CONVARIMP ROROROROROROROROROROROROROROROROType 1111000010000010Reset 0123456789101112131415 REVPARTNO ROROROROROROROROROROROROROROROROType 1000001001000011Reset DescriptionResetTypeNameBit/Field Implementer Code DescriptionValue ARM0x41 0x41ROIMP31:24 Variant Number DescriptionValue The rn value in the rnpn product revision identifier, for example, the 0 in r0p0. 0x0 0x0ROVAR23:20 Constant DescriptionValue Always reads as 0xF.0xF 0xFROCON19:16 Part Number DescriptionValue Cortex-M4 processor.0xC24 0xC24ROPARTNO15:4 Revision Number DescriptionValue The pn value in the rnpn product revision identifier, for example, the 1 in r0p1. 0x1 0x1ROREV3:0 June 12, 2014152 Texas Instruments-Production Data Cortex-M4 Peripherals

Register67:InterruptControlandState(INTCTRL),offset0xD04 Note: This register can only be accessed from privileged mode. The INCTRLregister provides a set-pending bit for the NMI exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate the exception number of the exception being processed, whether there are preempted active exceptions, the exception number of the highest priority pending exception, and whether any interrupts are pending. When writing toINCTRL, the effect is unpredictable when writing a 1 to both thePENDSVand UNPENDSVbits, or writing a 1 to both thePENDSTSETand PENDSTCLRbits. Interrupt Control and State (INTCTRL) Base 0xE000.E000 Offset 0xD04 Type RW, reset 0x0000.0000 16171819202122232425262728293031 VECPENDreservedISRPENDISRPREreservedPENDSTCLRPENDSTSETUNPENDSVPENDSVreservedNMISET ROROROROROROROROROWORWWORWRORORWType 0000000000000000Reset 0123456789101112131415 VECACTreservedRETBASEVECPEND ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field NMI Set Pending DescriptionValue On a read, indicates an NMI exception is not pending. On a write, no effect. On a read, indicates an NMI exception is pending. On a write, changes the NMI exception state to pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt handler. A read of this bit by the NMI exception handler returns 1 only if theNMIsignal is reasserted while the processor is executing that handler. 0RWNMISET31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved30:29 PendSV Set Pending DescriptionValue On a read, indicates a PendSV exception is not pending. On a write, no effect. On a read, indicates a PendSV exception is pending. On a write, changes the PendSV exception state to pending. Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing a 1 to theUNPENDSVbit. 0RWPENDSV28 153June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field PendSV Clear Pending DescriptionValue On a write, no effect.0 On a write, removes the pending state from the PendSV exception. This bit is write only; on a register read, its value is unknown. 0WOUNPENDSV27 SysTick Set Pending DescriptionValue On a read, indicates a SysTick exception is not pending. On a write, no effect. On a read, indicates a SysTick exception is pending. On a write, changes the SysTick exception state to pending. This bit is cleared by writing a 1 to thePENDSTCLRbit. 0RWPENDSTSET26 SysTick Clear Pending DescriptionValue On a write, no effect.0 On a write, removes the pending state from the SysTick exception. This bit is write only; on a register read, its value is unknown. 0WOPENDSTCLR25 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved24 Debug Interrupt Handling DescriptionValue The release from halt does not take an interrupt.0 The release from halt takes an interrupt.1 This bit is only meaningful in Debug mode and reads as zero when the processor is not in Debug mode. 0ROISRPRE23 Interrupt Pending DescriptionValue No interrupt is pending.0 An interrupt is pending.1 This bit provides status for all interrupts excluding NMI and Faults. 0ROISRPEND22 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved21:20 June 12, 2014154 Texas Instruments-Production Data Cortex-M4 Peripherals

DescriptionResetTypeNameBit/Field Interrupt Pending Vector Number This field contains the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of theBASEPRIand FAULTMASKregisters, but not any effect of the PRIMASKregister. DescriptionValue No exceptions are pending0x00 Reserved0x01 NMI0x02 Hard fault0x03 Memory management fault0x04 Bus fault0x05 Usage fault0x06 Reserved0x07-0x0A SVCall0x0B Reserved for Debug0x0C Reserved0x0D PendSV0x0E SysTick0x0F Interrupt Vector 00x10 Interrupt Vector 10x11 Interrupt Vector 1380x9A 0x00ROVECPEND19:12 Return to Base DescriptionValue There are preempted active exceptions to execute.0 There are no active exceptions, or the currently executing exception is the only active exception. This bit provides status for all interrupts excluding NMI and Faults. This bit only has meaning if the processor is currently executing an ISR (the InterruptProgramStatus(IPSR) register is non-zero). 0RORETBASE11 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved10:8 Interrupt Pending Vector Number This field contains the active exception number. The exception numbers can be found in the description for theVECPENDfield. If this field is clear, the processor is in Thread mode. This field contains the same value as the ISRNUMfield in theIPSRregister. Subtract 16 from this value to obtain the IRQ number required to index into theInterruptSetEnable(ENn) , InterruptClearEnable(DISn ), InterruptSetPending(PENDn), InterruptClearPending(UNPENDn), and InterruptPriority(PRIn) registers (see page 74). 0x00ROVECACT7:0 155June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register68:VectorTableOffset(VTABLE),offset0xD08 Note: This register can only be accessed from privileged mode. The VTABLEregister indicates the offset of the vector table base address from memory address 0x0000.0000. Vector Table Offset (VTABLE) Base 0xE000.E000 Offset 0xD08 Type RW, reset 0x0000.0000 16171819202122232425262728293031 OFFSET RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset 0123456789101112131415 reservedOFFSET RORORORORORORORORORORWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Vector Table Offset When configuring theOFFSETfield, the offset must be aligned to the number of exception entries in the vector table. Because there are 138 interrupts, the offset must be aligned on a 1024-byte boundary. 0x000.00RWOFFSET31:10 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved9:0 June 12, 2014156 Texas Instruments-Production Data Cortex-M4 Peripherals

Register69:ApplicationInterruptandResetControl(APINT),offset0xD0C Note: This register can only be accessed from privileged mode. The APINTregister provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, 0x05FA must be written to the VECTKEYfield, otherwise the write is ignored. The PRIGROUPfield indicates the position of the binary point that splits theINTxfields in the InterruptPriority(PRIx) registers into separate group priority and subpriority fields. Table 3-9 on page 157 shows how thePRIGROUPvalue controls this split. The bit numbers in the Group Priority Field and Subpriority Field columns in the table refer to the bits in theINTAfield. For the INTBfield, the corresponding bits are 15:13; forINTC, 23:21; and forINTD, 31:29. Note: Determining preemption of an exception uses only the group priority field. Table3-9.InterruptPriorityLevels SubprioritiesGroup Priorities SubpriorityFieldGroupPriorityFieldBinaryPointaPRIGROUP BitField 18None[7:5]bxxx.0x0 - 0x4 24[5][7:6]bxx.y0x5 42[6:5][7]bx.yy0x6 81[7:5]Noneb.yyy0x7 a. INTxfield showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit. Application Interrupt and Reset Control (APINT) Base 0xE000.E000 Offset 0xD0C Type RW, reset 0xFA05.0000 16171819202122232425262728293031 VECTKEY RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1010000001011111Reset 0123456789101112131415 VECTRESETVECTCLRACTSYSRESREQreservedPRIGROUPreservedENDIANESS WOWOWORORORORORORWRWRWROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Register Key This field is used to guard against accidental writes to this register. 0x05FA must be written to this field in order to change the bits in this register. On a read, 0xFA05 is returned. 0xFA05RWVECTKEY31:16 Data Endianess The Tiva™ C Series implementation uses only little-endian mode so this is cleared to 0. 0ROENDIANESS15 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved14:11 157June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Interrupt Priority Grouping This field determines the split of group priority from subpriority (see Table 3-9 on page 157 for more information). 0x0RWPRIGROUP10:8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved7:3 System Reset Request DescriptionValue No effect.0 Resets the core and all on-chip peripherals except the Debug interface. This bit is automatically cleared during the reset of the core and reads as 0. 0WOSYSRESREQ2 Clear Active NMI / Fault This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. 0WOVECTCLRACT1 System Reset This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. 0WOVECTRESET0 June 12, 2014158 Texas Instruments-Production Data Cortex-M4 Peripherals

Register70:SystemControl(SYSCTRL),offset0xD10 Note: This register can only be accessed from privileged mode. The SYSCTRLregister controls features of entry to and exit from low-power state. System Control (SYSCTRL) Base 0xE000.E000 Offset 0xD10 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedSLEEPEXITSLEEPDEEPreservedSEVONPENDreserved RORWRWRORWROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:5 Wake Up on Pending DescriptionValue Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. Enabled events and all interrupts, including disabled interrupts, can wake up the processor. When an event or interrupt enters the pending state, the event signal wakes up the processor fromWFE. If the processor is not waiting for an event, the event is registered and affects the nextWFE. The processor also wakes up on execution of aSEVinstruction or an external event. 0RWSEVONPEND4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 Deep Sleep Enable DescriptionValue Use Sleep mode as the low power mode.0 Use Deep-sleep mode as the low power mode.1 0RWSLEEPDEEP2 159June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Sleep on ISR Exit DescriptionValue When returning from Handler mode to Thread mode, do not sleep when returning to Thread mode. When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an ISR. Setting this bit enables an interrupt-driven application to avoid returning to an empty main application. 0RWSLEEPEXIT1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved0 June 12, 2014160 Texas Instruments-Production Data Cortex-M4 Peripherals

Register71:ConfigurationandControl(CFGCTRL),offset0xD14 Note: This register can only be accessed from privileged mode. The CFGCTRLregister controls entry to Thread mode and enables: the handlers for NMI, hard fault and faults escalated by theFAULTMASKregister to ignore bus faults; trapping of divide by zero and unaligned accesses; and access to theSWTRIGregister by unprivileged software (see page 149). Configuration and Control (CFGCTRL) Base 0xE000.E000 Offset 0xD14 Type RW, reset 0x0000.0200 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 BASETHRMAINPENDreservedUNALIGNEDDIV0reservedBFHFNMIGNSTKALIGNreserved RWRWRORWRWRORORORWRWROROROROROROType 0000000001000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:10 Stack Alignment on Exception Entry DescriptionValue The stack is 4-byte aligned.0 The stack is 8-byte aligned.1 On exception entry, the processor uses bit 9 of the stackedPSRto indicate the stack alignment. On return from the exception, it uses this stacked bit to restore the correct stack alignment. 1RWSTKALIGN9 Ignore Bus Fault in NMI and Fault This bit enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. The setting of this bit applies to the hard fault, NMI, andFAULTMASKescalated handlers. DescriptionValue Data bus faults caused by load and store instructions cause a lock-up. Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. Set this bit only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. 0RWBFHFNMIGN8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved7:5 161June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Trap on Divide by 0 This bit enables faulting or halting when the processor executes an SDIVor UDIVinstruction with a divisor of 0. DescriptionValue Do not trap on divide by 0. A divide by zero returns a quotient of 0. Trap on divide by 0.1 0RWDIV04 Trap on Unaligned Access DescriptionValue Do not trap on unaligned halfword and word accesses.0 Trap on unaligned halfword and word accesses. An unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, andSTRDinstructions always fault regardless of whetherUNALIGNEDis set. 0RWUNALIGNED3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2 Allow Main Interrupt Trigger DescriptionValue Disables unprivileged software access to theSWTRIGregister.0 Enables unprivileged software access to theSWTRIGregister (see page 149). 0RWMAINPEND1 Thread State Control DescriptionValue The processor can enter Thread mode only when no exception is active. The processor can enter Thread mode from any level under the control of an EXC_RETURN value (see “Exception Return” on page 103 for more information). 0RWBASETHR0 June 12, 2014162 Texas Instruments-Production Data Cortex-M4 Peripherals

Register72:SystemHandlerPriority1(SYSPRI1),offset0xD18 Note: This register can only be accessed from privileged mode. The SYSPRI1register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management fault exception handlers. This register is byte-accessible. System Handler Priority 1 (SYSPRI1) Base 0xE000.E000 Offset 0xD18 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reservedUSAGEreserved RORORORORORWRWRWROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedMEMreservedBUS RORORORORORWRWRWRORORORORORWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:24 Usage Fault Priority This field configures the priority level of the usage fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0RWUSAGE23:21 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved20:16 Bus Fault Priority This field configures the priority level of the bus fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0RWBUS15:13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved12:8 Memory Management Fault Priority This field configures the priority level of the memory management fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0RWMEM7:5 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved4:0 163June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register73:SystemHandlerPriority2(SYSPRI2),offset0xD1C Note: This register can only be accessed from privileged mode. The SYSPRI2register configures the priority level, 0 to 7 of the SVCall handler. This register is byte-accessible. System Handler Priority 2 (SYSPRI2) Base 0xE000.E000 Offset 0xD1C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reservedSVC RORORORORORORORORORORORORORWRWRWType 0000000000000000Reset 0123456789101112131415 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field SVCall Priority This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0RWSVC31:29 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000.0000ROreserved28:0 June 12, 2014164 Texas Instruments-Production Data Cortex-M4 Peripherals

Register74:SystemHandlerPriority3(SYSPRI3),offset0xD20 Note: This register can only be accessed from privileged mode. The SYSPRI3register configures the priority level, 0 to 7 of the SysTick exception and PendSV handlers. This register is byte-accessible. System Handler Priority 3 (SYSPRI3) Base 0xE000.E000 Offset 0xD20 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reservedPENDSVreservedTICK RORORORORORWRWRWRORORORORORWRWRWType 0000000000000000Reset 0123456789101112131415 reservedDEBUGreserved RORORORORORWRWRWROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field SysTick Exception Priority This field configures the priority level of the SysTick exception. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0RWTICK31:29 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved28:24 PendSV Priority This field configures the priority level of PendSV. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0RWPENDSV23:21 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved20:8 Debug Priority This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. 0x0RWDEBUG7:5 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0.0000ROreserved4:0 165June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register75:SystemHandlerControlandState(SYSHNDCTRL),offset0xD24 Note: This register can only be accessed from privileged mode. The SYSHNDCTRLregister enables the system handlers, and indicates the pending status of the usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status of the system handlers. If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as a hard fault. This register can be modified to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type. Caution – Software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. Ensure software that writes to this register retains and subsequently restores the current active status. If the value of a bit in this register must be modified after enabling the system handlers, a read-modify-write procedure must be used to ensure that only the required bit is modified. System Handler Control and State (SYSHNDCTRL) Base 0xE000.E000 Offset 0xD24 Type RW, reset 0x0000.0000 16171819202122232425262728293031 MEMBUSUSAGEreserved RWRWRWROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 MEMABUSAreservedUSGAreservedSVCAMONreservedPNDSVTICKUSAGEPMEMPBUSPSVC RWRWRORWRORORORWRWRORWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved31:19 Usage Fault Enable DescriptionValue Disables the usage fault exception.0 Enables the usage fault exception.1 0RWUSAGE18 Bus Fault Enable DescriptionValue Disables the bus fault exception.0 Enables the bus fault exception.1 0RWBUS17 June 12, 2014166 Texas Instruments-Production Data Cortex-M4 Peripherals

DescriptionResetTypeNameBit/Field Memory Management Fault Enable DescriptionValue Disables the memory management fault exception.0 Enables the memory management fault exception.1 0RWMEM16 SVC Call Pending DescriptionValue An SVC call exception is not pending.0 An SVC call exception is pending.1 This bit can be modified to change the pending status of the SVC call exception. 0RWSVC15 Bus Fault Pending DescriptionValue A bus fault exception is not pending.0 A bus fault exception is pending.1 This bit can be modified to change the pending status of the bus fault exception. 0RWBUSP14 Memory Management Fault Pending DescriptionValue A memory management fault exception is not pending.0 A memory management fault exception is pending.1 This bit can be modified to change the pending status of the memory management fault exception. 0RWMEMP13 Usage Fault Pending DescriptionValue A usage fault exception is not pending.0 A usage fault exception is pending.1 This bit can be modified to change the pending status of the usage fault exception. 0RWUSAGEP12 SysTick Exception Active DescriptionValue A SysTick exception is not active.0 A SysTick exception is active.1 This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit. 0RWTICK11 167June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field PendSV Exception Active DescriptionValue A PendSV exception is not active.0 A PendSV exception is active.1 This bit can be modified to change the active status of the PendSV exception, however, see the Caution above before setting this bit. 0RWPNDSV10 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved9 Debug Monitor Active DescriptionValue The Debug monitor is not active.0 The Debug monitor is active.1 0RWMON8 SVC Call Active DescriptionValue SVC call is not active.0 SVC call is active.1 This bit can be modified to change the active status of the SVC call exception, however, see the Caution above before setting this bit. 0RWSVCA7 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved6:4 Usage Fault Active DescriptionValue Usage fault is not active.0 Usage fault is active.1 This bit can be modified to change the active status of the usage fault exception, however, see the Caution above before setting this bit. 0RWUSGA3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2 Bus Fault Active DescriptionValue Bus fault is not active.0 Bus fault is active.1 This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. 0RWBUSA1 June 12, 2014168 Texas Instruments-Production Data Cortex-M4 Peripherals

DescriptionResetTypeNameBit/Field Memory Management Fault Active DescriptionValue Memory management fault is not active.0 Memory management fault is active.1 This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. 0RWMEMA0 169June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register76:ConfigurableFaultStatus(FAULTSTAT),offset0xD28 Note: This register can only be accessed from privileged mode. The FAULTSTATregister indicates the cause of a memory management fault, bus fault, or usage fault. Each of these functions is assigned to a subregister as follows: ■ UsageFaultStatus(UFAULTSTAT) , bits 31:16 ■ BusFaultStatus(BFAULTSTAT) , bits 15:8 ■ MemoryManagementFaultStatus(MFAULTSTAT) , bits 7:0 FAULTSTATis byte accessible.FAULTSTATor its subregisters can be accessed as follows: ■ The complete FAULTSTATregister, with a word access to offset 0xD28 ■ The MFAULTSTAT, with a byte access to offset 0xD28 ■ The MFAULTSTATand BFAULTSTAT, with a halfword access to offset 0xD28 ■ The BFAULTSTAT, with a byte access to offset 0xD29 ■ The UFAULTSTAT, with a halfword access to offset 0xD2A Bits are cleared by writing a 1 to them. In a fault handler, the true faulting address can be determined by: 1. Read and save theMemoryManagementFaultAddress(MMADDR) or BusFaultAddress (FAULTADDR)value. 2. Read theMMARVbit inMFAULTSTAT, or theBFARVbit inBFAULTSTATto determine if the MMADDRor FAULTADDRcontents are valid. Software must follow this sequence because another higher priority exception might change the MMADDRor FAULTADDRvalue. For example, if a higher priority handler preempts the current fault handler, the other fault might change theMMADDRor FAULTADDRvalue. Configurable Fault Status (FAULTSTAT) Base 0xE000.E000 Offset 0xD28 Type RW1C, reset 0x0000.0000 16171819202122232425262728293031 UNDEFINVSTATINVPCNOCPreservedUNALIGNDIV0reserved RW1CRW1CRW1CRW1CRORORORORW1CRW1CROROROROROROType 0000000000000000Reset 0123456789101112131415 IERRDERRreservedMUSTKEMSTKEMLSPERRreservedMMARVIBUSPRECISEIMPREBUSTKEBSTKEBLSPERRreservedBFARV RW1CRW1CRORW1CRW1CRW1CRORW1CRW1CRW1CRW1CRW1CRW1CRW1CRORW1CType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:26 June 12, 2014170 Texas Instruments-Production Data Cortex-M4 Peripherals

DescriptionResetTypeNameBit/Field Divide-by-Zero Usage Fault DescriptionValue No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled. The processor has executed anSDIVor UDIVinstruction with a divisor of 0. When this bit is set, thePCvalue stacked for the exception return points to the instruction that performed the divide by zero. Trapping on divide-by-zero is enabled by setting theDIV0bit in the ConfigurationandControl(CFGCTRL) register (see page 161). This bit is cleared by writing a 1 to it. 0RW1CDIV025 Unaligned Access Usage Fault DescriptionValue No unaligned access fault has occurred, or unaligned access trapping is not enabled. The processor has made an unaligned memory access.1 Unaligned LDM, STM, LDRD, andSTRDinstructions always fault regardless of the configuration of this bit. Trapping on unaligned access is enabled by setting theUNALIGNEDbit in theCFGCTRLregister (see page 161). This bit is cleared by writing a 1 to it. 0RW1CUNALIGN24 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved23:20 No Coprocessor Usage Fault DescriptionValue A usage fault has not been caused by attempting to access a coprocessor. The processor has attempted to access a coprocessor.1 This bit is cleared by writing a 1 to it. 0RW1CNOCP19 Invalid PC Load Usage Fault DescriptionValue A usage fault has not been caused by attempting to load an invalid PCvalue. The processor has attempted an illegal load of EXC_RETURN to thePCas a result of an invalid context or an invalid EXC_RETURN value. When this bit is set, thePCvalue stacked for the exception return points to the instruction that tried to perform the illegal load of thePC. This bit is cleared by writing a 1 to it. 0RW1CINVPC18 171June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Invalid State Usage Fault DescriptionValue A usage fault has not been caused by an invalid state.0 The processor has attempted to execute an instruction that makes illegal use of theEPSRregister. When this bit is set, thePCvalue stacked for the exception return points to the instruction that attempted the illegal use of theExecution ProgramStatusRegister(EPSR) register. This bit is not set if an undefined instruction uses theEPSRregister. This bit is cleared by writing a 1 to it. 0RW1CINVSTAT17 Undefined Instruction Usage Fault DescriptionValue A usage fault has not been caused by an undefined instruction.0 The processor has attempted to execute an undefined instruction. When this bit is set, thePCvalue stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. This bit is cleared by writing a 1 to it. 0RW1CUNDEF16 Bus Fault Address Register Valid DescriptionValue The value in theBusFaultAddress(FAULTADDR) register is not a valid fault address. The FAULTADDRregister is holding a valid fault address.1 This bit is set after a bus fault, where the address is known. Other faults can clear this bit, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active bus fault handler whoseFAULTADDR register value has been overwritten. This bit is cleared by writing a 1 to it. 0RW1CBFARV15 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved14 Bus Fault on Floating-Point Lazy State Preservation DescriptionValue No bus fault has occurred during floating-point lazy state preservation. A bus fault has occurred during floating-point lazy state preservation. This bit is cleared by writing a 1 to it. 0RW1CBLSPERR13 June 12, 2014172 Texas Instruments-Production Data Cortex-M4 Peripherals

DescriptionResetTypeNameBit/Field Stack Bus Fault DescriptionValue No bus fault has occurred on stacking for exception entry.0 Stacking for an exception entry has caused one or more bus faults. When this bit is set, theSPis still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDRregister. This bit is cleared by writing a 1 to it. 0RW1CBSTKE12 Unstack Bus Fault DescriptionValue No bus fault has occurred on unstacking for a return from exception. Unstacking for a return from exception has caused one or more bus faults. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. TheSPis not adjusted from the failing return, a new save is not performed, and a fault address is not written to the FAULTADDRregister. This bit is cleared by writing a 1 to it. 0RW1CBUSTKE11 Imprecise Data Bus Error DescriptionValue An imprecise data bus error has not occurred.0 A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. When this bit is set, a fault address is not written to theFAULTADDR register. This fault is asynchronous. Therefore, if the fault is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher-priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both theIMPREbit is set and one of the precise fault status bits is set. This bit is cleared by writing a 1 to it. 0RW1CIMPRE10 Precise Data Bus Error DescriptionValue A precise data bus error has not occurred.0 A data bus error has occurred, and thePCvalue stacked for the exception return points to the instruction that caused the fault. When this bit is set, the fault address is written to theFAULTADDR register. This bit is cleared by writing a 1 to it. 0RW1CPRECISE9 173June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Instruction Bus Error DescriptionValue An instruction bus error has not occurred.0 An instruction bus error has occurred.1 The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to theFAULTADDR register. This bit is cleared by writing a 1 to it. 0RW1CIBUS8 Memory Management Fault Address Register Valid DescriptionValue The value in theMemoryManagementFaultAddress (MMADDR)register is not a valid fault address. The MMADDRregister is holding a valid fault address.1 If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active memory management fault handler whoseMMADDRregister value has been overwritten. This bit is cleared by writing a 1 to it. 0RW1CMMARV7 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved6 Memory Management Fault on Floating-Point Lazy State Preservation DescriptionValue No memory management fault has occurred during floating-point lazy state preservation. No memory management fault has occurred during floating-point lazy state preservation. This bit is cleared by writing a 1 to it. 0RW1CMLSPERR5 Stack Access Violation DescriptionValue No memory management fault has occurred on stacking for exception entry. Stacking for an exception entry has caused one or more access violations. When this bit is set, theSPis still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the MMADDRregister. This bit is cleared by writing a 1 to it. 0RW1CMSTKE4 June 12, 2014174 Texas Instruments-Production Data Cortex-M4 Peripherals

DescriptionResetTypeNameBit/Field Unstack Access Violation DescriptionValue No memory management fault has occurred on unstacking for a return from exception. Unstacking for a return from exception has caused one or more access violations. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. TheSPis not adjusted from the failing return, a new save is not performed, and a fault address is not written to the MMADDRregister. This bit is cleared by writing a 1 to it. 0RW1CMUSTKE3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2 Data Access Violation DescriptionValue A data access violation has not occurred.0 The processor attempted a load or store at a location that does not permit the operation. When this bit is set, thePCvalue stacked for the exception return points to the faulting instruction and the address of the attempted access is written to theMMADDRregister. This bit is cleared by writing a 1 to it. 0RW1CDERR1 Instruction Access Violation DescriptionValue An instruction access violation has not occurred.0 The processor attempted an instruction fetch from a location that does not permit execution. This fault occurs on any access to an XN region, even when the MPU is disabled or not present. When this bit is set, thePCvalue stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to theMMADDRregister. This bit is cleared by writing a 1 to it. 0RW1CIERR0 175June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register77:HardFaultStatus(HFAULTSTAT),offset0xD2C Note: This register can only be accessed from privileged mode. The HFAULTSTATregister gives information about events that activate the hard fault handler. Bits are cleared by writing a 1 to them. Hard Fault Status (HFAULTSTAT) Base 0xE000.E000 Offset 0xD2C Type RW1C, reset 0x0000.0000 16171819202122232425262728293031 reservedFORCEDDBG RORORORORORORORORORORORORORORW1CRW1CType 0000000000000000Reset 0123456789101112131415 reservedVECTreserved RORW1CROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Debug Event This bit is reserved for Debug use. This bit must be written as a 0, otherwise behavior is unpredictable. 0RW1CDBG31 Forced Hard Fault DescriptionValue No forced hard fault has occurred.0 A forced hard fault has been generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled. When this bit is set, the hard fault handler must read the other fault status registers to find the cause of the fault. This bit is cleared by writing a 1 to it. 0RW1CFORCED30 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved29:2 Vector Table Read Fault DescriptionValue No bus fault has occurred on a vector table read.0 A bus fault occurred on a vector table read.1 This error is always handled by the hard fault handler. When this bit is set, thePCvalue stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by writing a 1 to it. 0RW1CVECT1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved0 June 12, 2014176 Texas Instruments-Production Data Cortex-M4 Peripherals

Register78:MemoryManagementFaultAddress(MMADDR),offset0xD34 Note: This register can only be accessed from privileged mode. The MMADDRregister contains the address of the location that generated a memory management fault. When an unaligned access faults, the address in theMMADDRregister is the actual address that faulted. Because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. Bits in theMemory ManagementFaultStatus(MFAULTSTAT) register indicate the cause of the fault and whether the value in theMMADDRregister is valid (see page 170). Memory Management Fault Address (MMADDR) Base 0xE000.E000 Offset 0xD34 Type RW, reset - 16171819202122232425262728293031 ADDR RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0123456789101112131415 ADDR RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType DescriptionResetTypeNameBit/Field Fault Address When theMMARVbit ofMFAULTSTATis set, this field holds the address of the location that generated the memory management fault. -RWADDR31:0 177June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register79:BusFaultAddress(FAULTADDR),offset0xD38 Note: This register can only be accessed from privileged mode. The FAULTADDRregister contains the address of the location that generated a bus fault. When an unaligned access faults, the address in theFAULTADDRregister is the one requested by the instruction, even if it is not the address of the fault. Bits in theBusFaultStatus(BFAULTSTAT) register indicate the cause of the fault and whether the value in theFAULTADDRregister is valid (see page 170). Bus Fault Address (FAULTADDR) Base 0xE000.E000 Offset 0xD38 Type RW, reset - 16171819202122232425262728293031 ADDR RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0123456789101112131415 ADDR RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType DescriptionResetTypeNameBit/Field Fault Address When theFAULTADDRVbit ofBFAULTSTATis set, this field holds the address of the location that generated the bus fault. -RWADDR31:0

3.6 MemoryProtectionUnit(MPU)RegisterDescriptions

This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by address offset. The MPU registers can only be accessed from privileged mode. June 12, 2014178 Texas Instruments-Production Data Cortex-M4 Peripherals

Register80:MPUType(MPUTYPE),offset0xD90 Note: This register can only be accessed from privileged mode. The MPUTYPEregister indicates whether the MPU is present, and if so, how many regions it supports. MPU Type (MPUTYPE) Base 0xE000.E000 Offset 0xD90 Type RO, reset 0x0000.0800 16171819202122232425262728293031 IREGIONreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 SEPARATEreservedDREGION ROROROROROROROROROROROROROROROROType 0000000000010000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:24 Number of I Regions This field indicates the number of supported MPU instruction regions. This field always contains 0x00. The MPU memory map is unified and is described by theDREGIONfield. 0x00ROIREGION23:16 Number of D Regions DescriptionValue Indicates there are eight supported MPU data regions.0x08 0x08RODREGION15:8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved7:1 Separate or Unified MPU DescriptionValue Indicates the MPU is unified.0 0ROSEPARATE0 179June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register81:MPUControl(MPUCTRL),offset0xD94 Note: This register can only be accessed from privileged mode. The MPUCTRLregister enables the MPU, enables the default memory map background region, and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), andFaultMask Register(FAULTMASK) escalated handlers. When theENABLEand PRIVDEFENbits are both set: ■ For privileged accesses, the default memory map is as described in “Memory Model” on page 85. Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. ■ Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless of the value of theENABLEbit. When theENABLEbit is set, at least one region of the memory map must be enabled for the system to function unless thePRIVDEFENbit is set. If thePRIVDEFENbit is set and no regions are enabled, then only privileged software can operate. When theENABLEbit is clear, the system uses the default memory map, which has the same memory attributes as if the MPU is not implemented (see Table 2-5 on page 88 for more information). The default memory map applies to accesses from both privileged and unprivileged software. When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are accessible based on regions and whetherPRIVDEFENis set. Unless HFNMIENAis set, the MPU is not enabled when the processor is executing the handler for an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception or whenFAULTMASKis enabled. Setting theHFNMIENAbit enables the MPU when operating with these two priorities. MPU Control (MPUCTRL) Base 0xE000.E000 Offset 0xD94 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ENABLEHFNMIENAPRIVDEFENreserved RWRWRWROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:3 June 12, 2014180 Texas Instruments-Production Data Cortex-M4 Peripherals

DescriptionResetTypeNameBit/Field MPU Default Region This bit enables privileged software access to the default memory map. DescriptionValue If the MPU is enabled, this bit disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. If the MPU is enabled, this bit enables use of the default memory map as a background region for privileged software accesses. When this bit is set, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. If the MPU is disabled, the processor ignores this bit. 0RWPRIVDEFEN2 MPU Enabled During Faults This bit controls the operation of the MPU during hard fault, NMI, and FAULTMASKhandlers. DescriptionValue The MPU is disabled during hard fault, NMI, andFAULTMASK handlers, regardless of the value of theENABLEbit. The MPU is enabled during hard fault, NMI, andFAULTMASK handlers. When the MPU is disabled and this bit is set, the resulting behavior is unpredictable. 0RWHFNMIENA1 MPU Enable DescriptionValue The MPU is disabled.0 The MPU is enabled.1 When the MPU is disabled and theHFNMIENAbit is set, the resulting behavior is unpredictable. 0RWENABLE0 181June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register82:MPURegionNumber(MPUNUMBER),offset0xD98 Note: This register can only be accessed from privileged mode. The MPUNUMBERregister selects which memory region is referenced by theMPURegionBase Address(MPUBASE) and MPURegionAttributeandSize(MPUATTR) registers. Normally, the required region number should be written to this register before accessing theMPUBASEor the MPUATTRregister. However, the region number can be changed by writing to theMPUBASE register with theVALIDbit set (see page 183). This write updates the value of theREGIONfield. MPU Region Number (MPUNUMBER) Base 0xE000.E000 Offset 0xD98 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 NUMBERreserved RWRWRWROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:3 MPU Region to Access This field indicates the MPU region referenced by theMPUBASEand MPUATTRregisters. The MPU supports eight memory regions. 0x0RWNUMBER2:0 June 12, 2014182 Texas Instruments-Production Data Cortex-M4 Peripherals

Register83:MPURegionBaseAddress(MPUBASE),offset0xD9C Register84:MPURegionBaseAddressAlias1(MPUBASE1),offset0xDA4 Register85:MPURegionBaseAddressAlias2(MPUBASE2),offset0xDAC Register86:MPURegionBaseAddressAlias3(MPUBASE3),offset0xDB4 Note: This register can only be accessed from privileged mode. The MPUBASEregister defines the base address of the MPU region selected by theMPURegion Number(MPUNUMBER) register and can update the value of theMPUNUMBERregister. To change the current region number and update theMPUNUMBERregister, write theMPUBASE register with theVALIDbit set. The ADDRfield is bits 31:N of theMPUBASEregister. Bits (N-1):5 are reserved. The region size, as specified by theSIZEfield in theMPURegionAttributeandSize(MPUATTR) register, defines the value ofN where: N = Log2(Region size in bytes) If the region size is configured to 4 GB in theMPUATTRregister, there is no validADDRfield. In this case, the region occupies the complete memory map, and the base address is 0x0000.0000. The base address is aligned to the size of the region. For example, a 64-KB region must be aligned on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000. MPU Region Base Address (MPUBASE) Base 0xE000.E000 Offset 0xD9C Type RW, reset 0x0000.0000 16171819202122232425262728293031 ADDR RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset 0123456789101112131415 REGIONreservedVALIDADDR RWRWRWROWORWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Base Address Mask Bits 31:N in this field contain the region base address. The value ofN depends on the region size, as shown above. The remaining bits (N-1):5 are reserved. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000RWADDR31:5 183June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Region Number Valid DescriptionValue The MPUNUMBERregister is not changed and the processor updates the base address for the region specified in the MPUNUMBERregister and ignores the value of theREGION field. The MPUNUMBERregister is updated with the value of the REGIONfield and the base address is updated for the region specified in theREGIONfield. This bit is always read as 0. 0WOVALID4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 Region Number On a write, contains the value to be written to theMPUNUMBERregister. On a read, returns the current region number in theMPUNUMBER register. 0x0RWREGION2:0 June 12, 2014184 Texas Instruments-Production Data Cortex-M4 Peripherals

Register87:MPURegionAttributeandSize(MPUATTR),offset0xDA0 Register88:MPURegionAttributeandSizeAlias1(MPUATTR1),offset0xDA8 Register89:MPURegionAttributeandSizeAlias2(MPUATTR2),offset0xDB0 Register90:MPURegionAttributeandSizeAlias3(MPUATTR3),offset0xDB8 Note: This register can only be accessed from privileged mode. The MPUATTRregister defines the region size and memory attributes of the MPU region specified by theMPURegionNumber(MPUNUMBER) register and enables that region and any subregions. The MPUATTRregister is accessible using word or halfword accesses with the most-significant halfword holding the region attributes and the least-significant halfword holds the region size and the region and subregion enable bits. The MPU access permission attribute bits,XN, AP, TEX, S, C, andB, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. The SIZEfield defines the size of the MPU memory region specified by theMPUNUMBERregister as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32 bytes, corresponding to aSIZEvalue of 4. Table 3-10 on page 185 gives exampleSIZEvalues with the corresponding region size and value of N in the MPURegionBaseAddress(MPUBASE) register. Table3-10.ExampleSIZEFieldValues NoteValueofN aRegionSizeSIZE Encoding Minimum permitted size532 B00100b (0x4) -101 KB01001b (0x9) -201 MB10011b (0x13) -301 GB11101b (0x1D) Maximum possible sizeNo validADDRfield inMPUBASE; the region occupies the complete memory map.

4 GB11111b (0x1F)

a. Refers to the N parameter in theMPUBASEregister (see page 183). MPU Region Attribute and Size (MPUATTR) Base 0xE000.E000 Offset 0xDA0 Type RW, reset 0x0000.0000 16171819202122232425262728293031 BCSTEXreservedAPreservedXNreserved RWRWRWRWRWRWRORORWRWRWRORWROROROType 0000000000000000Reset 0123456789101112131415 ENABLESIZEreservedSRD RWRWRWRWRWRWRORORWRWRWRWRWRWRWRWType 0000000000000000Reset 185June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:29 Instruction Access Disable DescriptionValue Instruction fetches are enabled.0 Instruction fetches are disabled.1 0RWXN28 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27 Access Privilege For information on using this bit field, see Table 3-5 on page 122. 0RWAP26:24 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved23:22 Type Extension Mask For information on using this bit field, see Table 3-3 on page 121. 0x0RWTEX21:19 Shareable For information on using this bit, see Table 3-3 on page 121. 0RWS18 Cacheable For information on using this bit, see Table 3-3 on page 121. 0RWC17 Bufferable For information on using this bit, see Table 3-3 on page 121. 0RWB16 Subregion Disable Bits DescriptionValue The corresponding subregion is enabled.0 The corresponding subregion is disabled.1 Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, configure theSRDfield as 0x00. See the section called “Subregions” on page 121 for more information. 0x00RWSRD15:8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved7:6 Region Size Mask The SIZEfield defines the size of the MPU memory region specified by the MPUNUMBERregister. Refer to Table 3-10 on page 185 for more information. 0x0RWSIZE5:1 June 12, 2014186 Texas Instruments-Production Data Cortex-M4 Peripherals

DescriptionResetTypeNameBit/Field Region Enable DescriptionValue The region is disabled.0 The region is enabled.1 0RWENABLE0

3.7 Floating-PointUnit(FPU)RegisterDescriptions

This section lists and describes the Floating-Point Unit (FPU) registers, in numerical order by address offset. 187June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register91:CoprocessorAccessControl(CPAC),offset0xD88 The CPACregister specifies the access privileges for coprocessors. Coprocessor Access Control (CPAC) Base 0xE000.E000 Offset 0xD88 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reservedCP10CP11reserved RORORORORWRWRWRWROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:24 CP11 Coprocessor Access Privilege DescriptionValue Access Denied Any attempted access generates a NOCP Usage Fault. 0x0 Privileged Access Only An unprivileged access generates a NOCP fault. 0x1 Reserved The result of any access is unpredictable. 0x2 Full Access0x3 0x00RWCP1123:22 CP10 Coprocessor Access Privilege DescriptionValue Access Denied Any attempted access generates a NOCP Usage Fault. 0x0 Privileged Access Only An unprivileged access generates a NOCP fault. 0x1 Reserved The result of any access is unpredictable. 0x2 Full Access0x3 0x00RWCP1021:20 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved19:0 June 12, 2014188 Texas Instruments-Production Data Cortex-M4 Peripherals

Register92:Floating-PointContextControl(FPCC),offset0xF34 The FPCCregister sets or returns FPU control data. Floating-Point Context Control (FPCC) Base 0xE000.E000 Offset 0xF34 Type RW, reset 0xC000.0000 16171819202122232425262728293031 reservedLSPENASPEN RORORORORORORORORORORORORORORWRWType 0000000000000011Reset 0123456789101112131415 LSPACTUSERreservedTHREADHFRDYMMRDYBFRDYreservedMONRDYreserved RWRWRORWRWRWRWRORWROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Automatic State Preservation Enable When set, enables the use of theFRACTVbit in theCONTROLregister on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit. Important: Two bits control whenFPCAcan be enabled: theASPEN bit in theFloating-PointContextControl(FPCC) register and theDISFPCAbit in theAuxiliaryControl (ACTLR)register. 1RWASPEN31 Lazy State Preservation Enable When set, enables automatic lazy state preservation for floating-point context. 1RWLSPEN30 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved29:9 Monitor Ready When set, DebugMonitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated. 0RWMONRDY8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved7 Bus Fault Ready When set, BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated. 0RWBFRDY6 Memory Management Fault Ready When set, MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated. 0RWMMRDY5 189June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Hard Fault Ready When set, priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated. 0RWHFRDY4 Thread Mode When set, mode was Thread Mode when the floating-point stack frame was allocated. 0RWTHREAD3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2 User Privilege Level When set, privilege level was user when the floating-point stack frame was allocated. 0RWUSER1 Lazy State Preservation Active When set, Lazy State preservation is active. Floating-point stack frame has been allocated but saving state to it has been deferred. 0RWLSPACT0 June 12, 2014190 Texas Instruments-Production Data Cortex-M4 Peripherals

Register93:Floating-PointContextAddress(FPCA),offset0xF38 The FPCAregister holds the location of the unpopulated floating-point register space allocated on an exception stack frame. Floating-Point Context Address (FPCA) Base 0xE000.E000 Offset 0xF38 Type RW, reset - 16171819202122232425262728293031 ADDRESS RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0123456789101112131415 reservedADDRESS RORORORWRWRWRWRWRWRWRWRWRWRWRWRWType DescriptionResetTypeNameBit/Field Address The location of the unpopulated floating-point register space allocated on an exception stack frame. -RWADDRESS31:3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved2:0 191June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register94:Floating-PointDefaultStatusControl(FPDSC),offset0xF3C The FPDSCregister holds the default values for theFloating-PointStatusControl(FPSC) register. Floating-Point Default Status Control (FPDSC) Base 0xE000.E000 Offset 0xF3C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reservedRMODEFZDNAHPreserved RORORORORORORWRWRWRWRWROROROROROType 000000-----00000Reset 0123456789101112131415 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:27 AHP Bit Default This bit holds the default value for theAHPbit in theFPSCregister. -RWAHP26 DN Bit Default This bit holds the default value for theDNbit in theFPSCregister. -RWDN25 FZ Bit Default This bit holds the default value for theFZbit in theFPSCregister. -RWFZ24 RMODE Bit Default This bit holds the default value for theRMODEbit field in theFPSC register. DescriptionValue Round to Nearest (RN) mode0x0 Round towards Plus Infinity (RP) mode0x1 Round towards Minus Infinity (RM) mode0x2 Round towards Zero (RZ) mode0x3 -RWRMODE23:22 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved21:0 June 12, 2014192 Texas Instruments-Production Data Cortex-M4 Peripherals

4 JTAGInterface

The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of four pins:TCK, TMS, TDI, andTDO. Data is transmitted serially into the controller onTDIand out of the controller onTDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to theIEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The TM4C1233D5PZ JTAG controller works with the ARM JTAG controller built into the Cortex-M4F core by multiplexing theTDOoutputs from both JTAG controllers. ARM JTAG instructions select the ARM TDOoutput while JTAG instructions select theTDOoutput. The multiplexer is controlled by the JTAG controller, which has comprehensive programming for the ARM, Tiva™ C Series microcontroller, and unimplemented JTAG instructions. The TM4C1233D5PZ JTAG module has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Embedded Trace Macrocell (ETM) for instruction trace capture – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer See theARM® Debug Interface V5 Architecture Specification for more information on the ARM JTAG controller. 193June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

4.1 BlockDiagram

Figure4-1.JTAGModuleBlockDiagram Instruction Register (IR) T AP Controller BYP ASS Data Register Boundary Scan Data Register IDCODE Data Register ABOR T Data Register DP ACC Data Register AP ACC Data Register TCK TMS TDI TDO Cortex-M4F Debug Port

4.2 SignalDescription

The following table lists the external signals of the JTAG/SWD controller and describes the function of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals, however note that the reset state of the pins is for the JTAG/SWD function. The JTAG/SWD controller signals are under commit protection and require a special process to be configured as GPIOs, see “Commit Control” on page 639. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for the JTAG/SWD controller signals. TheAFSELbit in theGPIOAlternateFunction Select(GPIOAFSEL) register (page 656) is set to choose the JTAG/SWD function. The number in parentheses is the encoding that must be programmed into thePMCnfield in theGPIOPortControl (GPIOPCTL)register (page 674) to assign the JTAG/SWD controller signals to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 631. Table4-1.JTAG_SWD_SWOSignals(100LQFP) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName JTAG/SWD CLK.TTLIPC0 (1)85SWCLK JTAG TMS and SWDIO.TTLI/OPC1 (1)84SWDIO JTAG TDO and SWO.TTLOPC3 (1)82SWO JTAG/SWD CLK.TTLIPC0 (1)85TCK JTAG TDI.TTLIPC2 (1)83TDI JTAG TDO and SWO.TTLOPC3 (1)82TDO June 12, 2014194 Texas Instruments-Production Data JTAG Interface

Table4-1.JTAG_SWD_SWOSignals(100LQFP) (continued) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName JTAG TMS and SWDIO.TTLIPC1 (1)84TMS a. The TTL designation indicates the pin has TTL-compatible voltage levels.

4.3 FunctionalDescription

A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 194. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by theTCKand TMSinputs. The current state of the TAP controller depends on the sequence of values captured onTMSat the rising edge ofTCK. The TAP controller determines when the serial shift chains capture new data, shift data fromTDItowards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path betweenTDIand TDOis always connected (see Table 4-3 on page 201 for a list of implemented instructions). See “JTAG and Boundary Scan” on page 1196 for JTAG timing diagrams. Note: Of all the possible reset sources, only Power-On reset (POR) and the assertion of theRST input have any effect on the JTAG module. The pin configurations are reset by both the RSTinput and POR, whereas the internal JTAG logic is only reset with POR. See “Reset Sources” on page 206 for more information on reset.

4.3.1 JTAGInterfacePins

The JTAG interface consists of four standard pins:TCK, TMS, TDI, andTDO. These pins and their associated state after a power-on reset or reset caused by theRSTinput are given in Table 4-2. Detailed information on each pin follows. Note: The following pins are configured as JTAG port pins out of reset. Refer to “General-Purpose Input/Outputs (GPIOs)” on page 631 for information on how to reprogram the configuration of these pins. Table4-2.JTAGPortPinsStateafterPower-OnResetorRST assertion DriveValueDriveStrengthInternalPull-DownInternalPull-UpDataDirectionPinName N/AN/ADisabledEnabledInputTCK N/AN/ADisabledEnabledInputTMS N/AN/ADisabledEnabledInputTDI High-Z2-mA driverDisabledEnabledOutputTDO 195June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

4.3.1.1 TestClockInput(TCK)

The TCKpin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks and to ensure that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation,TCKis driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCKcan be stopped at 0 or 1 for extended periods of time. WhileTCKis stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on theTCKpin is enabled after reset, assuring that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as theTCKpin is constantly being driven by an external source (see page 662 and page 664).

4.3.1.2 TestModeSelect(TMS)

The TMSpin selects the next state of the JTAG TAP controller.TMSis sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value ofTMS, the next state may be entered. Because theTMSpin is sampled on the rising edge ofTCK, theIEEE Standard 1149.1 expects the value onTMSto change on the falling edge ofTCK. Holding TMShigh for five consecutiveTCKcycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG module and associated registers are reset to their default values. This procedure should be performed to initialize the JTAG controller. The JTAG Test Access Port state machine can be seen in its entirety in Figure 4-2 on page 197. By default, the internal pull-up resistor on theTMSpin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost (see page 662).

4.3.1.3 TestDataInput(TDI)

The TDIpin provides a stream of serial information to the IR chain and the DR chains.TDIis sampled on the rising edge ofTCKand, depending on the current TAP state and the current instruction, may present this data to the proper shift register chain. Because theTDIpin is sampled on the rising edge ofTCK, theIEEE Standard 1149.1 expects the value onTDIto change on the falling edge ofTCK. By default, the internal pull-up resistor on theTDIpin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost (see page 662).

4.3.1.4 TestDataOutput(TDO)

The TDOpin provides an output stream of serial information from the IR chain or the DR chains. The value ofTDOdepends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, theTDOpin is placed in an inactive drive state when not actively shifting out data. BecauseTDOcan be connected to theTDIof another controller in a daisy-chain configuration, theIEEE Standard 1149.1 expects the value onTDOto change on the falling edge ofTCK. By default, the internal pull-up resistor on theTDOpin is enabled after reset, assuring that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and June 12, 2014196 Texas Instruments-Production Data JTAG Interface

pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states (see page 662 and page 664).

4.3.2 JTAGTAPController

The JTAG TAP controller state machine is shown in Figure 4-2. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR). In order to reset the JTAG module after the microcontroller has been powered on, theTMSinput must be held HIGH for five TCK clock cycles, resetting the TAP controller and all associated JTAG chains. Asserting the correct sequence on theTMSpin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer toIEEE Standard 1149.1. Figure4-2.TestAccessPortStateMachine T est Logic Reset Run T est Idle Select DR Scan Select IR Scan Capture DR Capture IR Shift DR Shift IR Exit 1 DR Exit 1 IR Exit 2 DR Exit 2 IR Pause DR Pause IR Update DR Update IR 1 11 1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0

4.3.3 ShiftRegisters

The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller's CAPTURE states and allows this information to be shifted out onTDOduring the TAP controller's SHIFT states. While the sampled data is being shifted out of the chain onTDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller's UPDATE states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 201. 197June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

4.3.4 OperationalConsiderations

Certain operational parameters must be considered when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below.

4.3.4.1 GPIOFunctionality

When the microcontroller is reset with either a POR orRST , the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (DEN[3:0] set in thePortCGPIODigitalEnable(GPIODEN) register), enabling the pull-up resistors (PUE[3:0] set in thePortCGPIOPull-UpSelect(GPIOPUR) register), disabling the pull-down resistors (PDE[3:0]cleared in thePortCGPIOPull-DownSelect(GPIOPDR) register) and enabling the alternate hardware function (AFSEL[3:0]set in thePortCGPIOAlternateFunctionSelect (GPIOAFSEL)register) on the JTAG/SWD pins. See page 656, page 662, page 664, and page 667. It is possible for software to configure these pins as GPIOs after reset by clearingAFSEL[3:0]in the PortCGPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides four more GPIOs for use in the design. Caution – It is possible to create a software sequence that prevents the debugger from connecting to the TM4C1233D5PZ microcontroller . If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger . In the case that the software routine is not implemented and the device is locked out of the part, this issue can be solved by using the TM4C1233D5PZ Flash Programmer "Unlock" feature. Please refer to LMFLASHPROGRAMMER on the TI web for more information. The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the GPIO pins that can be used as the four JTAG/SWD pins and theNMIpin (see “Signal Tables” on page 1161 for pin numbers). Writes to protected bits of theGPIOAlternateFunctionSelect(GPIOAFSEL) register (see page 656),GPIO PullUpSelect(GPIOPUR) register (see page 662),GPIOPull-DownSelect(GPIOPDR) register (see page 664), andGPIODigitalEnable(GPIODEN) register (see page 667) are not committed to storage unless theGPIOLock(GPIOLOCK) register (see page 669) has been unlocked and the appropriate bits of theGPIOCommit(GPIOCR) register (see page 670) have been set.

4.3.4.2 CommunicationwithJTAG/SWD

Because the debug clock and the system clock can be running at different frequencies, care must be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state, the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software should check the ACK response to see if the previous operation has completed before initiating a new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock (TCKor SWCLK), the previous operation has enough time to complete and the ACK bits do not have to be checked.

4.3.4.3 Recoveringa"Locked"Microcontroller

Note: Performing the sequence below restores the non-volatile registers discussed in “Non-Volatile Register Programming” on page 515 to their factory default values. The mass erase of the Flash memory caused by the sequence below occurs prior to the non-volatile registers being restored. June 12, 2014198 Texas Instruments-Production Data JTAG Interface

In addition, the EEPROM is erased and its wear-leveling counters are returned to factory default values when performing the sequence below. If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug port unlock sequence that can be used to recover the microcontroller. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the microcontroller in reset mass erases the Flash memory. The debug port unlock sequence is: 1. Assert and hold theRST signal. 2. Apply power to the device. 3. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence on the section called “JTAG-to-SWD Switching” on page 200. 4. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence on the section called “SWD-to-JTAG Switching” on page 200. 5. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 6. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 7. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 8. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 9. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 10. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 11. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence. 12. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence. 13. Release theRST signal. 14. Wait 400 ms. 15. Power-cycle the microcontroller.

4.3.4.4 ARMSerialWireDebug(SWD)

In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M4F core without having to perform, or have any knowledge of, JTAG cycles. This integration is accomplished with a SWD preamble that is issued before the SWD session begins. The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. Stepping through this sequence of the TAP state machine enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see theARM® Debug Interface V5 Architecture Specification . 199June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to theIEEE Standard 1149.1. This instance is the only one where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occurring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. JTAG-to-SWD Switching To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the external debug hardware must send the switching preamble to the microcontroller. The 16-bit TMS/SWDIO command for switching to SWD mode is defined as b1110.0111.1001.1110, transmitted LSB first. This command can also be represented as 0xE79E when transmitted LSB first. The complete switch sequence should consist of the following transactions on theTCK/SWCLKand TMS/SWDIOsignals: 1. Send at least 50TCK/SWCLKcycles withTMS/SWDIOHigh to ensure that both JTAG and SWD are in their reset states. 2. Send the 16-bit JTAG-to-SWD switch command, 0xE79E, onTMS/SWDIO. 3. Send at least 50TCK/SWCLKcycles withTMS/SWDIOHigh to ensure that if SWJ-DP was already in SWD mode before sending the switch sequence, the SWD goes into the line reset state. To verify that the Debug Access Port (DAP) has switched to the Serial Wire Debug (SWD) operating mode, perform a SWD READID operation. The ID value can be compared against the device's known ID to verify the switch. SWD-to-JTAG Switching To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the external debug hardware must send a switch command to the microcontroller. The 16-bitTMS/SWDIO command for switching to JTAG mode is defined as b1110.0111.0011.1100, transmitted LSB first. This command can also be represented as 0xE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on theTCK/SWCLKand TMS/SWDIOsignals: 1. Send at least 50TCK/SWCLKcycles withTMS/SWDIOHigh to ensure that both JTAG and SWD are in their reset states. 2. Send the 16-bit SWD-to-JTAG switch command, 0xE73C, onTMS/SWDIO. 3. Send at least 50TCK/SWCLKcycles withTMS/SWDIOHigh to ensure that if SWJ-DP was already in JTAG mode before sending the switch sequence, the JTAG goes into the Test Logic Reset state. To verify that the Debug Access Port (DAP) has switched to the JTAG operating mode, set the JTAG Instruction Register (IR) to the IDCODE instruction and shift out the Data Register (DR). The DR value can be compared against the device's known IDCODE to verify the switch.

4.4 InitializationandConfiguration

After a Power-On-Reset or an external reset (RST ), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. To return the pins to their JTAG functions, enable the four JTAG pins (PC[3:0]) for their alternate function using theGPIOAFSELregister. June 12, 2014200 Texas Instruments-Production Data JTAG Interface

In addition to enabling the alternate functions, any other changes to the GPIO pad configurations on the four JTAG pins (PC[3:0]) should be returned to their default settings.

4.5 RegisterDescriptions

The registers in the JTAG TAP Controller or Shift Register chains are not memory mapped and are not accessible through the on-chip Advanced Peripheral Bus (APB). Instead, the registers within the JTAG controller are all accessed serially through the TAP Controller. These registers include the Instruction Register and the six Data Registers.

4.5.1 InstructionRegister(IR)

The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG TDIand TDOpins with a parallel load register. When the TAP Controller is placed in the correct states, bits can be shifted into the IR. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the IR bits is shown in Table 4-3. A detailed explanation of each instruction, along with its associated Data Register, follows. Table4-3.JTAGInstructionRegisterCommands DescriptionInstructionIR[3:0] Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. EXTEST0x0 Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. SAMPLE / PRELOAD0x2 Shifts data into the ARM Debug Port Abort Register.ABORT0x8 Shifts data into and out of the ARM DP Access Register.DPACC0xA Shifts data into and out of the ARM AC Access Register.APACC0xB Loads manufacturing information defined by theIEEE Standard 1149.1 into the IDCODE chain and shifts it out. IDCODE0xE Connects TDIto TDOthrough a single Shift Register chain.BYPASS0xF Defaults to the BYPASS instruction to ensure thatTDIis always connected to TDO. ReservedAll Others

4.5.1.1 EXTESTInstruction

The EXTEST instruction is not associated with its own Data Register chain. Instead, the EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. With tests that drive known values out of the controller, this instruction can be used to verify connectivity. While the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register.

4.5.1.2 SAMPLE/PRELOADInstruction

The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDIand TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out onTDOwhile 201June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register fromTDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST instruction to drive data into or out of the controller. See “Boundary Scan Data Register” on page 203 for more information.

4.5.1.3 ABORTInstruction

The ABORT instruction connects the associated ABORT Data Register chain betweenTDIand TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. See the “ABORT Data Register” on page 204 for more information.

4.5.1.4 DPACCInstruction

The DPACC instruction connects the associated DPACC Data Register chain betweenTDIand TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. See “DPACC Data Register” on page 204 for more information.

4.5.1.5 APACCInstruction

The APACC instruction connects the associated APACC Data Register chain betweenTDIand TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. See “APACC Data Register” on page 204 for more information.

4.5.1.6 IDCODEInstruction

The IDCODE instruction connects the associated IDCODE Data Register chain betweenTDIand TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure input and output data streams. IDCODE is the default instruction loaded into the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is entered. See “IDCODE Data Register” on page 203 for more information.

4.5.1.7 BYPASSInstruction

The BYPASS instruction connects the associated BYPASS Data Register chain betweenTDIand TDO. This instruction is used to create a minimum length serial path between theTDIand TDOports. The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. See “BYPASS Data Register” on page 203 for more information. June 12, 2014202 Texas Instruments-Production Data JTAG Interface

4.5.2 DataRegisters

The JTAG module contains six Data Registers. These serial Data Register chains include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT and are discussed in the following sections.

4.5.2.1 IDCODEDataRegister

The format for the 32-bit IDCODE Data Register defined by theIEEE Standard 1149.1 is shown in Figure 4-3. The standard requires that every JTAG-compliant microcontroller implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This definition allows auto-configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x4BA0.0477. This value allows the debuggers to automatically configure themselves to work correctly with the Cortex-M4F during debug. Figure4-3.IDCODERegisterFormat V ersion Part Number Manufacturer ID 1 31 28 27 12 1 1 1 0 TDOTDI

4.5.2.2 BYPASSDataRegister

The format for the 1-bit BYPASS Data Register defined by theIEEE Standard 1149.1 is shown in Figure 4-4. The standard requires that every JTAG-compliant microcontroller implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This definition allows auto-configuration test tools to determine which instruction is the default instruction. Figure4-4.BYPASSRegisterFormat

0 TDOTDI

4.5.2.3 BoundaryScanDataRegister

The format of the Boundary Scan Data Register is shown in Figure 4-5. Each GPIO pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as shown in the figure. When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge ofTCKin the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST instruction. The EXTEST instruction forces data out of the controller. 203June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Figure4-5.BoundaryScanRegisterFormat I N TDI st GPIO TDO... O U T O E I N m th GPIO O U T O E I N (m+1) th GPIO O U T O E ... I N GPIO n th O U T O E

4.5.2.4 APACCDataRegister

The format for the 35-bit APACC Data Register defined by ARM is described in theARM® Debug Interface V5 Architecture Specification .

4.5.2.5 DPACCDataRegister

The format for the 35-bit DPACC Data Register defined by ARM is described in theARM® Debug Interface V5 Architecture Specification .

4.5.2.6 ABORTDataRegister

The format for the 35-bit ABORT Data Register defined by ARM is described in theARM® Debug Interface V5 Architecture Specification . June 12, 2014204 Texas Instruments-Production Data JTAG Interface

5 SystemControl

System control configures the overall operation of the device and provides information about the device. Configurable features include reset control, NMI operation, power control, clock control, and low-power modes.

5.1 SignalDescription

The following table lists the external signals of the System Control module and describes the function of each. TheNMIsignal is the alternate function for two GPIO signals and functions as a GPIO after reset. TheNMIpins are under commit protection and require a special process to be configured as any alternate function or to subsequently return to the GPIO function, see “Commit Control” on page 639. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO pin placement for theNMIsignal. TheAFSELbit in theGPIOAlternateFunctionSelect (GPIOAFSEL)register (page 656) should be set to choose the NMI function. The number in parentheses is the encoding that must be programmed into thePMCnfield in theGPIOPortControl (GPIOPCTL)register (page 674) to assign theNMIsignal to the specified GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 631. The remaining signals (with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin assignment and function. Table5-1.SystemControl&ClocksSignals(100LQFP) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName Non-maskable interrupt.TTLIPF0 (8) PD7 (8) 100 NMI Main oscillator crystal input or an external clock reference input. AnalogIfixed65OSC0 Main oscillator crystal output. Leave unconnected when using a single-ended clock source. AnalogOfixed66OSC1 System reset input.TTLIfixed63RST a. The TTL designation indicates the pin has TTL-compatible voltage levels.

5.2 FunctionalDescription

The System Control module provides the following capabilities: ■ Device identification, see “Device Identification” on page 205 ■ Local control, such as reset (see “Reset Control” on page 206), power (see “Power Control” on page 211) and clock control (see “Clock Control” on page 212) ■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 219

5.2.1 DeviceIdentification

Several read-only registers provide software with information on the microcontroller, such as version, part number, memory sizes, and peripherals present on the device. TheDeviceIdentification0 (DID0)(page 230) andDeviceIdentification1(DID1) (page 232) registers provide details about the device's version, package, temperature range, and so on. The Peripheral Present registers starting at System Control offset 0x300, such as theWatchdogTimerPeripheralPresent(PPWD) register, provide information on how many of each type of module are included on the device. Finally, 205June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

information about the capabilities of the on-chip peripherals are provided at offset 0xFC0 in each peripheral's register space in the Peripheral Properties registers, such as theGPTMPeripheral Properties(GPTMPP)register. Previous devices used theDeviceCapabilities(DC0-DC9) registers for information about the peripherals and their capabilities. These registers are present on this device for backward software capability, but provide no information about peripherals that were not available on older devices.

5.2.2 ResetControl

This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence.

5.2.2.1 ResetSources

The TM4C1233D5PZ microcontroller has six sources of reset: 1. Power-on reset (POR) (see page 207). 2. External reset input pin (RST ) assertion (see page 208). 3. A brown-out detection that can be caused by any of the following events: (see page 209). ■ V DD under BOR0. The trigger value is the highest VDD voltage level for BOR0. ■ V DD under BOR1. The trigger value is the highest VDD voltage level for BOR1. 4. Software-initiated reset (with the software reset registers) (see page 210). 5. A watchdog timer reset condition violation (see page 210). 6. MOSC failure (see page 211). Table 5-2 provides a summary of results of the various reset operations. Table5-2.ResetSources On-ChipPeripheralsReset?JTAGReset?CoreReset?ResetSource YesYesYesPower-On Reset YesPin Config OnlyYesRST YesPin Config OnlyYesBrown-Out Reset YesPin Config OnlyYesSoftware System Request Reset using theSYSRESREQ bit in theAPINTregister. NoPin Config OnlyYesSoftware System Request Reset using theVECTRESET bit in theAPINTregister. YesaPin Config OnlyNoSoftware Peripheral Reset YesPin Config OnlyYesWatchdog Reset YesPin Config OnlyYesMOSC Failure Reset a. Programmable on a module-by-module basis using the Software Reset Control Registers. After a reset, theResetCause(RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR June 12, 2014206 Texas Instruments-Production Data System Control

is the cause, in which case, all the bits in theRESCregister are cleared except for the POR indicator. A bit in theRESCregister can be cleared by writing a 0. At any reset that resets the core, the user has the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal as configured in theBoot Configuration(BOOTCFG) register. At reset, the following sequence is performed: 1. The BOOTCFGregister is read. If theENbit is clear, the ROM Boot Loader is executed. 2. In the ROM Boot Loader, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 3. f thenENbit is set or the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004. The user application begins executing. Note: If the device fails the initialization phase, it toggles theTDOoutput pin as an indication the device is not executing. This feature is provided for debug purposes. For example, if theBOOTCFGregister is written and committed with the value of 0x0000.3C01, then PB7is examined at reset to determine if the ROM Boot Loader should be executed. IfPB7is Low, the core unconditionally begins executing the ROM boot loader. IfPB7is High, then the application in Flash memory is executed if the reset vector at location 0x0000.0004 is not 0xFFFF.FFFF. Otherwise, the ROM boot loader is executed.

5.2.2.2 Power-OnReset(POR)

Note: The JTAG controller can only be reset by the power-on reset. The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a threshold value (VVDD_POK). The microcontroller must be operating within the specified operating parameters when the on-chip power-on reset pulse is complete (see “Power and Brown-Out” on page 1198). For applications that require the use of an external reset signal to hold the microcontroller in reset longer than the internal POR, theRST input may be used as discussed in “External RSTPin” on page 208. The Power-On Reset sequence is as follows: 1. The microcontroller waits for internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The internal POR is only active on the initial power-up of the microcontroller and when the microcontroller wakes from hibernation. The Power-On Reset timing is shown in “Power and Brown-Out” on page 1198. 207June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

5.2.2.3 ExternalRST Pin

Note: It is recommended that the trace for theRSTsignal must be kept as short as possible. Be sure to place any components connected to theRSTsignal as close to the microcontroller as possible. If the application only uses the internal POR circuit, theRSTinput must be connected to the power supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 208. The RSTinput has filtering which requires a minimum pulse width in order for the reset pulse to be recognized, see Table 22-11 on page 1203. Figure5-1.BasicRST Configuration PU RST T iva™ Microcontroller R VDD RPU = 0 to 100 kΩ The external reset pin (RST) resets the microcontroller including the core and all the on-chip peripherals. The external reset sequence is as follows: 1. The external reset pin (RST) is asserted for the duration specified by TMIN and then deasserted (see “Reset” on page 1203). 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. To improve noise immunity and/or to delay reset at power up, theRST input may be connected to an RC network as shown in Figure 5-2 on page 208. Figure5-2.ExternalCircuitrytoExtendPower-OnReset PU C 1 RST R VDD T iva™ Microcontroller RPU = 1 kΩ to 100 kΩ C1 = 1 nF to 10 µF June 12, 2014208 Texas Instruments-Production Data System Control

If the application requires the use of an external reset switch, Figure 5-3 on page 209 shows the proper circuitry to use. Figure5-3.ResetCircuitControlledbySwitch PU C 1 R S RST R VDD T iva™ Microcontroller Typical RPU = 10 kΩ Typical RS = 470 Ω C1 = 10 nF The RPU and C1 components define the power-on delay. The external reset timing is shown in Figure 22-11 on page 1204.

5.2.2.4 Brown-OutReset(BOR)

The microcontroller provides a brown-out detection circuit that triggers if any of the following occur: ■ V DD under BOR0. The external VDD supply voltage is below the specified VDD BOR0 value. The trigger value is the highest VDD voltage level for BOR0. ■ V DD under BOR1. The external VDD supply voltage is below the specified VDD BOR1 value. The trigger value is the highest VDD voltage level for BOR1. The application can identify that a BOR event caused a reset by reading theResetCause(RESC) register. When a brown-out condition is detected, the default condition is to generate a reset. The BOR events can also be programmed to generate an interrupt by clearing theBOR0bit orBOR1bit in thePower-OnandBrown-OutResetControl(PBORCTL) register. The brown-out reset sequence is as follows: 1. When VDD drops below VBORnTH, an internal BOR condition is set. Please refer to “Power and Brown-Out” on page 1198 for VBORnTH value. 2. If the BOR condition exists, an internal reset is asserted. 3. The internal reset is released and the microcontroller fetches and loads the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. The result of a brown-out reset is equivalent to that of an assertion of the externalRST input, and the reset is held active until the proper VDD level is restored. TheRESCregister can be examined in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. 209June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

The internal Brown-Out Reset timing is shown in “Power and Brown-Out” on page 1198.

5.2.2.5 SoftwareReset

Software can reset a specific peripheral or generate a reset to the entire microcontroller. Peripherals can be individually reset by software via peripheral-specific reset registers available beginning at System Control offset 0x500 (for example theWatchdogTimerSoftwareReset (SRWD)register). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The entire microcontroller, including the core, can be reset by software by setting theSYSRESREQ bit in theApplicationInterruptandResetControl(APINT) register. The software-initiated system reset sequence is as follows: 1. A software microcontroller reset is initiated by setting theSYSRESREQbit. 2. An internal reset is asserted. 3. The internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The core only can be reset by software by setting theVECTRESETbit in theAPINTregister. The software-initiated core reset sequence is as follows: 1. A core reset is initiated by setting theVECTRESETbit. 2. An internal reset is asserted. 3. The internal reset is deasserted and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 22-12 on page 1204.

5.2.2.6 WatchdogTimerReset

The Watchdog Timer module's function is to prevent system hangs. The TM4C1233D5PZ microcontroller has two Watchdog Timer modules in case one watchdog clock source fails. One watchdog is run off the system clock and the other is run off the Precision Internal Oscillator (PIOSC). Each module operates in the same manner except that because the PIOSC watchdog timer module is in a different clock domain, register accesses must have a time delay between them. The watchdog timer can be configured to generate an interrupt or a non-maskable interrupt to the microcontroller on its first time-out and to generate a reset on its second time-out. After the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of the WatchdogTimerLoad(WDTLOAD) register and resumes counting down from that value. If the timer counts down to zero again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the microcontroller. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. June 12, 2014210 Texas Instruments-Production Data System Control

1. The internal reset is released and the microcontroller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. For more information on the Watchdog Timer module, see “Watchdog Timers” on page 760. The watchdog reset timing is shown in Figure 22-13 on page 1204.

5.2.3 Non-MaskableInterrupt

The microcontroller has four sources of non-maskable interrupt (NMI): ■ The assertion of theNMIsignal ■ A main oscillator verification error ■ The NMISETbit in theInterruptControlandState(INTCTRL) register in the Cortex™-M4F (see page 153). ■ The Watchdog module time-out interrupt when theINTTYPEbit in theWatchdogControl (WDTCTL)register is set (see page 766). Software must check the cause of the interrupt in order to distinguish among the sources.

5.2.3.1 NMIPin

The NMIsignal is an alternate function for either GPIO port pinPD7or PF0. The alternate function must be enabled in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose Input/Outputs (GPIOs)” on page 631. Note that enabling the NMI alternate function requires the use of the GPIO lock and commit function just like the GPIO port pins associated with JTAG/SWD functionality, see page 670. The active sense of theNMIsignal is High; asserting the enabled NMIsignal above VIH initiates the NMI interrupt sequence.

5.2.3.2 MainOscillatorVerificationFailure

The TM4C1233D5PZ microcontroller provides a main oscillator verification circuit that generates an error condition if the oscillator is running too fast or too slow. If the main oscillator verification circuit is enabled and a failure occurs, either a power-on reset is generated and control is transferred to the NMI handler, or an interrupt is generated. TheMOSCIMbit in theMOSCCTLregister determines which action occurs. In either case, the system clock source is automatically switched to the PIOSC. If a MOSC failure reset occurs, the NMI handler is used to address the main oscillator verification failure because the necessary code can be removed from the general reset handler, speeding up reset processing. The detection circuit is enabled by setting theCVALbit in theMainOscillator Control(MOSCCTL) register. The main oscillator verification error is indicated in the main oscillator fail status (MOSCFAIL) bit in theResetCause(RESC) register. The main oscillator verification circuit action is described in more detail in “Main Oscillator Verification Circuit” on page 219.

5.2.4 PowerControl

The TM4C1233D5PZ microcontroller provides an integrated LDO regulator that is used to provide power to the majority of the microcontroller's internal logic. Figure 5-4 shows the power architecture. An external LDO may not be used. Note: VDDAmust be supplied with a voltage that meets the specification in Table 22-5 on page 1193, or the microcontroller does not function properly.VDDAis the supply for all of the analog circuitry on the device, including the clock circuitry. 211June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Figure5-4.PowerArchitecture Analog Circuits I/O Buf fers LDO V oltage Regulator Internal Logic and PLL GND GNDA GNDA VDDA VDDA VDDC VDDC +3.3V GND GND GNDVDD VDD +3.3V

5.2.5 ClockControl

System control determines the control of clocks in this part.

5.2.5.1 FundamentalClockSources

There are multiple clock sources for use in the microcontroller: ■ PrecisionInternalOscillator(PIOSC). The precision internal oscillator is an on-chip clock source that is the clock source the microcontroller uses during and following POR. It does not require the use of any external components and provides a 16-MHz clock with ±1% accuracy with calibration and ±3% accuracy across temperature (see “PIOSC Specifications” on page 1208). The PIOSC allows for a reduced system cost in applications that require an accurate clock source. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. If the Hibernation Module clock source is a 32.768-kHz oscillator, the precision internal oscillator can be trimmed by software based on a reference clock for increased accuracy. Regardless of whether or not the PIOSC is the source for the system clock, the PIOSC can be configured to be the source for the ADC clock as well as the baud clock for the UART and SSI, see “System Control” on page 219. ■ MainOscillator(MOSC). The main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to theOSC0input pin, or an external crystal is connected across theOSC0input andOSC1output pins. If the PLL is being June 12, 2014212 Texas Instruments-Production Data System Control

used, the crystal value must be one of the supported frequencies between 5 MHz to 25 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies between 4 MHz to 25 MHz. The single-ended clock source range is as specified in Table 22-13 on page 1207. The supported crystals are listed in theXTALbit field in theRCCregister (see page 246). Note that the MOSC provides the clock source for the USB PLL and must be connected to a crystal or an oscillator. ■ Low-FrequencyInternalOscillator(LFIOSC). The low-frequency internal oscillator is intended for use during Deep-Sleep power-saving modes. The frequency can have wide variations; refer to “Low-Frequency Internal Oscillator (LFIOSC) Specifications” on page 1208 for more details. This power-savings mode benefits from reduced internal switching and also allows the MOSC to be powered down. In addition, the PIOSC can be powered down while in Deep-Sleep mode. ■ HibernationModuleClockSource. The Hibernation module is clocked by a 32.768-kHz oscillator connected to theXOSC0pin. The 32.768-kHz oscillator can be used for the system clock, thus eliminating the need for an additional crystal or oscillator. The Hibernation module clock source is intended to provide the system with a real-time clock source and may also provide an accurate source of Deep-Sleep or Hibernate mode power savings. The internal system clock (SysClk), is derived from any of the above sources plus two others: the output of the main internal PLL and the precision internal oscillator divided by four (4 MHz ± 1%). The frequency of the PLL clock reference must be in the range of 5 MHz to 25 MHz (inclusive). Table 5-3 on page 213 shows how the various clock sources can be used in a system. Table5-3.ClockSourceOptions UsedasSysClk?DrivePLL?ClockSource BYPASS= 1,OSCSRC= 0x1YesBYPASS= 0, OSCSRC= 0x1 YesPrecision Internal Oscillator BYPASS= 1,OSCSRC= 0x2Yes-NoPrecision Internal Oscillator divide by 4 (4 MHz ± 1%) BYPASS= 1,OSCSRC= 0x0YesBYPASS= 0, OSCSRC= 0x0 YesMain Oscillator BYPASS= 1,OSCSRC= 0x3Yes-NoLow-Frequency Internal Oscillator (LFIOSC) BYPASS= 1,OSCSRC2= 0x7Yes-NoHibernation Module 32.768-kHz Oscillator

5.2.5.2 ClockConfiguration

The Run-ModeClockConfiguration(RCC) and Run-ModeClockConfiguration2(RCC2) registers provide control for the system clock. TheRCC2register is provided to extend fields that offer additional encodings over theRCCregister. When used, theRCC2register field values are used by the logic over the corresponding field in theRCCregister. In particular,RCC2provides for a larger assortment of clock configuration options. These registers control the following clock functionality: ■ Source of clocks in sleep and deep-sleep modes ■ System clock derived from PLL or other clock source ■ Enabling/disabling of oscillators and PLL ■ Clock divisors 213June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

■ Crystal input selection Important: Write theRCCregister prior to writing theRCC2register. When transitioning the system clock configuration to use the MOSC as the fundamental clock source, theMOSCDISbit must be set prior to reselecting the MOSC or an undefined system clock configuration can sporadically occur. The configuration of the system clock must not be changed while an EEPROM operation is in process. Software must wait until theWORKINGbit in theEEPROMDoneStatus (EEDONE)register is clear before making any changes to the system clock. Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system clock signal and can be individually enabled/disabled. The ADC clock signal can be selected from the PIOSC, the system clock if the PLL is disabled, or the PLL output divided down to 16 MHz if the PLL is enabled. Note: If the ADC module is not using the PIOSC as the clock source, the system clock must be at least 16 MHz. When the USB module is in operation, MOSC must be the clock source, either with or without using the PLL, and the system clock must be at least 20 MHz. June 12, 2014214 Texas Instruments-Production Data System Control

Figure5-5.MainClockTree Main OSC Precision Internal OSC ( 16 MHz) Internal OSC ( 30 kHz) ÷ 4 ÷ 25 PWRDN System Clock MOSCDIS a IOSCDIS a ÷ SYSDIV e USESYSDIV a,d Hibernation OSC ( 32.768 kHz) OSCSRC b,d BYP ASS b,d XT AL a PWRDN b ÷ 2 USB PLL ( 480 MHz) ÷ 8 USB Clock XT AL a USBPWRDN c PLL ( 400 MHz) DIV400 c BYP ASS b,d UAR T Baud Clock CS f SSI Baud Clock CS f ADC Clock CS f Note: a. Control provided byRCCregister bit/field. b. Control provided byRCCregister bit/field orRCC2register bit/field, if overridden withRCC2register bit USERCC2. c. Control provided byRCC2register bit/field. d. Also may be controlled byDSLPCLKCFGwhen in deep sleep mode. e. Control provided byRCCregister SYSDIVfield, RCC2register SYSDIV2field if overridden withUSERCC2 bit, or [SYSDIV2,SYSDIV2LSB] if bothUSERCC2and DIV400bits are set. f. Control provided byUARTCC, SSICC, andADCCCregister field. Communication Clock Sources In addition to the main clock tree described above, the UART, and SSI modules all have a Clock Control register in the peripheral's register map at offset 0xFC8 that can be used to select the clock source for the module's baud clock. Users can choose between the system clock, which is the default source for the baud clock, and the PIOSC. Note that there may be special considerations when using the PIOSC as the baud clock. For more information, see the Clock Control register description in the chapter describing the operation of the module. Using the SYSDIV and SYSDIV2 Fields In theRCCregister, theSYSDIVfield specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how theBYPASSbit in this register is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. Table 5-4 shows how theSYSDIVencoding affects the system clock frequency, 215June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1). The divisor is equivalent to theSYSDIVencoding plus 1. For a list of possible clock sources, see Table 5-3 on page 213. Table5-4.PossibleSystemClockFrequenciesUsingtheSYSDIVField TivaWare™ ParameteraFrequency(BYPASS=1)Frequency(BYPASS=0)DivisorSYSDIV SYSCTL_SYSDIV_1Clock source frequency/1reserved/10x0 SYSCTL_SYSDIV_2Clock source frequency/2reserved/20x1 SYSCTL_SYSDIV_3Clock source frequency/366.67 MHz/30x2 SYSCTL_SYSDIV_4Clock source frequency/450 MHz/40x3 SYSCTL_SYSDIV_5Clock source frequency/540 MHz/50x4 SYSCTL_SYSDIV_6Clock source frequency/633.33 MHz/60x5 SYSCTL_SYSDIV_7Clock source frequency/728.57 MHz/70x6 SYSCTL_SYSDIV_8Clock source frequency/825 MHz/80x7 SYSCTL_SYSDIV_9Clock source frequency/922.22 MHz/90x8 SYSCTL_SYSDIV_10Clock source frequency/1020 MHz/100x9 SYSCTL_SYSDIV_11Clock source frequency/1118.18 MHz/110xA SYSCTL_SYSDIV_12Clock source frequency/1216.67 MHz/120xB SYSCTL_SYSDIV_13Clock source frequency/1315.38 MHz/130xC SYSCTL_SYSDIV_14Clock source frequency/1414.29 MHz/140xD SYSCTL_SYSDIV_15Clock source frequency/1513.33 MHz/150xE SYSCTL_SYSDIV_16Clock source frequency/1612.5 MHz (default)/160xF a. This parameter is used in functions such as SysCtlClockSet() in the TivaWare Peripheral Driver Library. The SYSDIV2field in theRCC2register is 2 bits wider than theSYSDIVfield in theRCCregister so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. The divisor is equivalent to theSYSDIV2encoding plus 1. Table 5-5 shows how theSYSDIV2encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list of possible clock sources, see Table 5-3 on page 213. Table5-5.ExamplesofPossibleSystemClockFrequenciesUsingtheSYSDIV2Field TivaWareParameteraFrequency(BYPASS2=1)Frequency (BYPASS2=0) DivisorSYSDIV2 SYSCTL_SYSDIV_1Clock source frequency/1reserved/10x00 SYSCTL_SYSDIV_2Clock source frequency/2reserved/20x01 SYSCTL_SYSDIV_3Clock source frequency/366.67 MHz/30x02 SYSCTL_SYSDIV_4Clock source frequency/450 MHz/40x03 SYSCTL_SYSDIV_5Clock source frequency/540 MHz/50x04 SYSCTL_SYSDIV_10Clock source frequency/1020 MHz/100x09 SYSCTL_SYSDIV_64Clock source frequency/643.125 MHz/640x3F a. This parameter is used in functions such as SysCtlClockSet() in the TivaWare Peripheral Driver Library. June 12, 2014216 Texas Instruments-Production Data System Control

To allow for additional frequency choices when using the PLL, theDIV400bit is provided along with theSYSDIV2LSBbit. When theDIV400bit is set, bit 22 becomes the LSB forSYSDIV2. In this situation, the divisor is equivalent to the (SYSDIV2encoding withSYSDIV2LSBappended) plus one. Table 5-6 shows the frequency choices whenDIV400is set. When theDIV400bit is clear, SYSDIV2LSBis ignored, and the system clock frequency is determined as shown in Table 5-5 on page 216. Table5-6.ExamplesofPossibleSystemClockFrequencieswithDIV400=1 TivaWareParameterbFrequency(BYPASS2=0)aDivisorSYSDIV2LSBSYSDIV2 -reserved/2reserved0x00 -reserved/30 0x01 -reserved/41 SYSCTL_SYSDIV_2_580 MHz/50 0x02 SYSCTL_SYSDIV_366.67 MHz/61 -reserved/70 0x03 SYSCTL_SYSDIV_450 MHz/81 SYSCTL_SYSDIV_4_544.44 MHz/90 0x04 SYSCTL_SYSDIV_540 MHz/101 SYSCTL_SYSDIV_63_53.15 MHz/1270 0x3F SYSCTL_SYSDIV_643.125 MHz/1281 a. Note thatDIV400and SYSDIV2LSBare only valid whenBYPASS2=0. b. This parameter is used in functions such as SysCtlClockSet() in the TivaWare Peripheral Driver Library.

5.2.5.3 PrecisionInternalOscillatorOperation(PIOSC)

The microcontroller powers up with the PIOSC running. If another clock source is desired, the PIOSC must remain enabled as it is used for internal functions. The PIOSC can only be disabled during Deep-Sleep mode. It can be powered down by setting thePIOSCPDbit in theDSLPCLKCFGregister. The PIOSC generates a 16-MHz clock with ±1% accuracy with calibration and ±3% accuracy across temperature (see “PIOSC Specifications” on page 1208). At the factory, the PIOSC is set to 16 MHz, however, the frequency can be trimmed for other voltage or temperature conditions using software in one of three ways: ■ Default calibration: clear theUTENbit and set theUPDATEbit in thePrecisionInternalOscillator Calibration(PIOSCCAL) register. ■ User-defined calibration: The user can program theUTvalue to adjust the PIOSC frequency. As the UTvalue increases, the generated period increases. To commit a newUTvalue, first set the UTENbit, then program theUTfield, and then set theUPDATEbit. The adjustment finishes within a few clock periods and is glitch free. ■ Automatic calibration using the Hibernation module with a functioning 32.768-kHz clock source: Set theCALbit in thePIOSCCALregister; the results of the calibration are shown in theRESULT field in thePrecisionInternalOscillatorStatistic(PIOSCSTAT) register. After calibration is complete, the PIOSC is trimmed using the trimmed value returned in theCTfield.

5.2.5.4 CrystalConfigurationfortheMainOscillator(MOSC)

The main oscillator supports the use of a select number of crystals from 4 to 25 MHz. 217June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

The XTALbit in theRCCregister (see page 246) describes the available crystal choices and default programming values. Software configures theRCCregister XTALfield with the crystal number. If the PLL is used in the design, theXTALfield value is internally translated to the PLL settings.

5.2.5.5 MainPLLFrequencyConfiguration

The main PLL is disabled by default during power-on reset and is enabled later by software if required. Software specifies the output divisor to set the system clock frequency and enables the main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor, unless theDIV400bit in theRCC2register is set. To configure the PIOSC to be the clock source for the main PLL, program theOSCRC2field in the Run-ModeClockConfiguration2(RCC2) register to be 0x1. If the main oscillator provides the clock reference to the main PLL, the translation provided by hardware and used to program the PLL is available for software in thePLLFrequencyn (PLLFREQn)registers (see page 264). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. Table 22-14 on page 1207 shows the actual PLL frequency and error for a given crystal choice. The Crystal Value field (XTAL) in theRun-ModeClockConfiguration(RCC) register (see page 246) describes the available crystal choices and default programming of thePLLFREQnregisters. Any time theXTALfield changes, the new settings are translated and the internal PLL settings are updated.

5.2.5.6 USBPLLFrequencyConfiguration

The USB PLL is disabled by default during power-on reset and is enabled later by software. The USB PLL must be enabled and running for proper USB function. The main oscillator is the only clock reference for the USB PLL. The USB PLL is enabled by clearing theUSBPWRDNbit of theRCC2 register. TheXTALbit field (Crystal Value) of theRCCregister describes the available crystal choices. The main oscillator must be connected to one of the following crystal values in order to correctly generate the USB clock: 5, 6, 8, 10, 12, 16, 18, 20, 24, or 25 MHz. Only these crystals provide the necessary USB PLL VCO frequency to conform with the USB timing specifications.

5.2.5.7 PLLModes

Both PLLs have two modes of operation: Normal and Power-Down ■ Normal: The PLL multiplies the input clock reference and drives the output. ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using theRCC/RCC2register fields (see page 246 and page 253).

5.2.5.8 PLLOperation

If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 22-13 on page 1207). During the relock time, the affected PLL is not usable as a clock reference. Software can poll theLOCKbit in thePLLStatus(PLLSTAT) register to determine when the PLL has locked. Either PLL is changed by one of the following: ■ Change to theXTALvalue in theRCCregister—writes of the same value do not cause a relock. June 12, 2014218 Texas Instruments-Production Data System Control

■ Change in the PLL from Power-Down to Normal mode. A counter clocked by the system clock is used to measure the TREADY requirement. The down counter is set to 0x200 if the PLL is powering up. If the M or N values in thePLLFREQnregisters are changed, the counter is set to 0xC0. Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before theRCC/RCC2register is switched to use the PLL. If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system control hardware continues to clock the microcontroller from the oscillator selected by theRCC/RCC2 register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software can use many methods to ensure that the system is clocked from the main PLL, including periodically polling thePLLLRISbit in theRawInterruptStatus(RIS) register, and enabling the PLL Lock interrupt. The USB PLL is not protected during the lock time (TREADY), and software should ensure that the USB PLL has locked before using the interface. Software can use many methods to ensure the TREADY period has passed, including periodically polling theUSBPLLLRISbit in theRawInterrupt Status(RIS) register, and enabling the USB PLL Lock interrupt.

5.2.5.9 MainOscillatorVerificationCircuit

The clock control includes circuitry to ensure that the main oscillator is running at the appropriate frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside of the allowable band of attached crystals. The detection circuit is enabled using theCVALbit in theMainOscillatorControl(MOSCCTL) register. If this circuit is enabled and detects an error, and if theMOSCIMbit in theMOSCCTLregister is clear, then the following sequence is performed by the hardware: 1. The MOSCFAILbit in theResetCause(RESC) register is set. 2. The system clock is switched from the main oscillator to the PIOSC. 3. An internal power-on reset is initiated. 4. Reset is deasserted and the processor is directed to the NMI handler during the reset sequence. if theMOSCIMbit in theMOSCCTLregister is set, then the following sequence is performed by the hardware: 1. The system clock is switched from the main oscillator to the PIOSC. 2. The MOFRISbit in theRISregister is set to indicate a MOSC failure.

5.2.6 SystemControl

For power-savings purposes, the peripheral-specificRCGCx, SCGCx, andDCGCxregisters (for example, RCGCWD) control the clock gating logic for that peripheral or block in the system while the microcontroller is in Run, Sleep, and Deep-Sleep mode, respectively. These registers are located in the System Control register map starting at offsets 0x600, 0x700, and 0x800, respectively. There must be a delay of 3 system clocks after a peripheral module clock is enabled in theRCGCregister before any module registers are accessed. 219June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Important: To support legacy software, theRCGCn, SCGCn, andDCGCnregisters are available at offsets 0x100 - 0x128. A write to any of these legacy registers also writes the corresponding bit in the peripheral-specificRCGCx, SCGCx, andDCGCxregisters. Software must use the peripheral-specific registers to support modules that are not present in the legacy registers. It is recommended that new software use the new registers and not rely on legacy operation. If software uses a peripheral-specific register to write a legacy peripheral (such as TIMER0), the write causes proper operation, but the value of that bit is not reflected in the legacy register. Any bits that are changed by writing to a legacy register can be read back correctly with a read of the legacy register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. There are four levels of operation for the microcontroller defined as: ■ Run mode ■ Sleep mode ■ Deep-Sleep mode ■ Hibernate mode The following sections describe the different modes in detail. Caution – If the Cortex-M4F Debug Access Port (DAP) has been enabled, and the device wakes from a low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals have been restored to their Run mode configuration. The DAP is usually enabled by software tools accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs, a Hard Fault is triggered when software accesses a peripheral with an invalid clock. A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses a peripheral register that might cause a fault. This loop can be removed for production software as the DAP is most likely not enabled during normal execution. Because the DAP is disabled by default (power on reset), the user can also power cycle the device. The DAP is not enabled unless it is enabled through the JTAG or SWD interface.

5.2.6.1 RunMode

In Run mode, the microcontroller actively executes code. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the peripheral-specificRCGC registers. The system clock can be any of the available clock sources including the PLL.

5.2.6.2 SleepMode

In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered by the Cortex-M4F core executing aWFI(Wait for Interrupt) instruction. Any properly configured interrupt event in the system brings the processor back into Run mode. See “Power Management” on page 107 for more details. June 12, 2014220 Texas Instruments-Production Data System Control

Peripherals are clocked that are enabled in the peripheral-specificSCGCregisters when auto-clock gating is enabled (see theRCCregister) or the peripheral-specificRCGCregisters when the auto-clock gating is disabled. The system clock has the same source and frequency as that during Run mode. Additional sleep modes are available that lower the power consumption of the SRAM and Flash memory. However, the lower power consumption modes have slower sleep and wake-up times, see “Dynamic Power Management” on page 222 for more information. Important: Before executing theWFIinstruction, software must confirm that the EEPROM is not busy by checking to see that theWORKINGbit in theEEPROMDoneStatus(EEDONE) register is clear.

5.2.6.3 Deep-SleepMode

In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the Deep-Sleep mode clock configuration) in addition to the processor clock being stopped. An interrupt returns the microcontroller to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Deep-Sleep mode is entered by first setting theSLEEPDEEPbit in the SystemControl(SYSCTRL) register (see page 159) and then executing a WFI instruction. Any properly configured interrupt event in the system brings the processor back into Run mode. See “Power Management” on page 107 for more details. The Cortex-M4F processor core and the memory subsystem are not clocked in Deep-Sleep mode. Peripherals are clocked that are enabled in the peripheral-specificDCGCregisters when auto-clock gating is enabled (see theRCCregister) or the peripheral-specificRCGCregisters when auto-clock gating is disabled. The system clock source is specified in theDSLPCLKCFGregister. When the DSLPCLKCFGregister is used, the internal oscillator source is powered up, if necessary, and other clocks are powered down. If the PLL is running at the time of the WFI instruction, hardware powers the PLL down and overrides theSYSDIVfield of the activeRCC/RCC2register, to be determined by theDSDIVORIDEsetting in theDSLPCLKCFGregister, up to /16 or /64 respectively. USB PLL is not powered down by execution of WFI instruction. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. If the PIOSC is used as the PLL reference clock source, it may continue to provide the clock during Deep-Sleep. See page 257. Important: Before executing theWFIinstruction, software must confirm that the EEPROM is not busy by checking to see that theWORKINGbit in theEEPROMDoneStatus(EEDONE) register is clear. To provide the lowest possible Deep-Sleep power consumption as well the ability to wake the processor from a peripheral without reconfiguring the peripheral for a change in clock, some of the communications modules have a Clock Control register at offset 0xFC8 in the module register space. The CSfield in the Clock Control register allows the user to select the PIOSC as the clock source for the module's baud clock. When the microcontroller enters Deep-Sleep mode, the PIOSC becomes the source for the module clock as well, which allows the transmit and receive FIFOs to continue operation while the part is in Deep-Sleep. Figure 5-6 on page 222 shows how the clocks are selected. 221June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Figure5-6.ModuleClockSelection Deep Sleep Module Clock System Clock Clock Control Register PIOSC Baud Clock Additional deep-sleep modes are available that lower the power consumption of the SRAM and Flash memory. However, the lower power consumption modes have slower deep-sleep and wake-up times, see “Dynamic Power Management” on page 222 for more information.

5.2.6.4 DynamicPowerManagement

In addition to the Sleep and Deep-Sleep modes and the clock gating for the on-chip modules, there are several additional power mode options that allow the LDO, Flash memory, and SRAM into different levels of power savings while in Sleep or Deep-Sleep modes. Note that these features may not be available on all devices; theSystemProperties(SYSPROP) register provides information on whether a mode is supported on a given MCU. The following registers provides these capabilities: ■ LDOSleepPowerControl(LDOSPCTL) : controls the LDO value in Sleep mode ■ LDODeep-SleepPowerControl(LDODPCTL) : controls the LDO value in Deep-Sleep mode ■ LDOSleepPowerCalibration(LDOSPCAL) : provides factory recommendations for the LDO value in Sleep mode ■ LDODeep-SleepPowerCalibration(LDODPCAL) : provides factory recommendations for the LDO value in Deep-Sleep mode ■ SleepPowerConfiguration(SLPPWRCFG): controls the power saving modes for Flash memory and SRAM in Sleep mode ■ Deep-SleepPowerConfiguration(DSLPPWRCFG) : controls the power saving modes for Flash memory and SRAM in Deep-Sleep mode ■ Deep-SleepClockConfiguration(DSLPCLKCFG) : controls the clocking in Deep-Sleep mode ■ Sleep/Deep-SleepPowerModeStatus(SDPMST) : provides status information on the various power saving events LDO Sleep/Deep-Sleep Power Control Note: While the device is connected through JTAG, the LDO control settings for Sleep or Deep-Sleep are not available and will not be applied. June 12, 2014222 Texas Instruments-Production Data System Control

The user can dynamically request to raise or lower the LDO voltage level to trade-off power/performance using either theLDOSPCTLregister (see page 271) or theLDODPCTLregister (see page 274). When lowering the LDO level, software must configure the system clock for the lower LDO value inRCC/RCC2for Sleep mode and inDSLPCLKCFGfor Deep-Sleep mode before requesting the LDO to lower. The LDO Power Calibration registers,LDOSPCALand LDODPCAL, provide suggested values for the LDO in the various modes. If software requests an LDO value that is too low or too high, the value is not accepted and an error is reported in theSDPMSTregister. The table below shows the maximum system clock frequency and PIOSC frequency with respect to the configured LDO voltage. PIOSCMaximumSystemClockFrequencyOperatingVoltage(LDO) 16 MHz80 MHz1.2 16 MHz20 MHz0.9 Flash Memory and SRAM Power Control During Sleep or Deep-Sleep mode, Flash memory can be in either the default active mode or the low power mode; SRAM can be in the default active mode, standby mode, or low power mode. The active mode in each case provides the fastest times to sleep and wake up, but consumes more power. Low power mode provides the lowest power consumption, but takes longer to sleep and wake up. The SRAM can be programmed to prohibit any power management by configuring theSRAMSMbit in theSystemProperties(SYSPROP) register. This configuration operates in the same way that legacy Stellaris® devices operate and provides the fastest sleep and wake-up times, but consumes the most power while in Sleep and Deep-Sleep mode. Other power options are retention mode, and retention mode with lower SRAM voltage. The SRAM retention mode with lower SRAM voltage provides the lowest power consumption, but has the longest sleep and wake-up times. These modes can be independently configured for Flash memory and SRAM using theSLPPWRCFGand DSLPPWRCFGregisters. The following power saving options are available in Sleep and Deep-Sleep modes: ■ The clocks can be gated according to the settings in the the peripheral-specificSCGCor DCGC registers. ■ In Deep-Sleep mode, the clock source can be changed and the PIOSC can be powered off (if no active peripheral requires it) using theDSLPCLKCFGregister. These options are not available for Sleep mode. ■ The LDO voltage can be changed using theLDOSPCTLor LDODPCTLregister. ■ The Flash memory can be put into low power mode. Refer to Table 22-24 on page 1214 for wake times from Sleep and Deep-Sleep. ■ The SRAM can be put into standby or low power mode. Refer to Table 22-24 on page 1214 for wake times from Sleep and Deep-Sleep. The SDPMSTregister provides results on the Dynamic Power Management command issued. It also has some real time status that can be viewed by a debugger or the core if it is running. These events do not trigger an interrupt and are meant to provide information to help tune software for power management. The status register gets written at the beginning of every Dynamic Power 223June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Management event request that provides error checking. There is no mechanism to clear the bits; they are overwritten on the next event. The real time data is real time and there is no event to register that information.

5.2.6.5 HibernateMode

In this mode, the power supplies are turned off to the main part of the microcontroller and only the Hibernation module's circuitry is active. An external wake event or RTC event is required to bring the microcontroller back to Run mode. The Cortex-M4F processor and peripherals outside of the Hibernation module see a normal "power on" sequence and the processor starts running code. Software can determine if the microcontroller has been restarted from Hibernate mode by inspecting the Hibernation module registers. For more information on the operation of Hibernate mode, see “Hibernation Module” on page 476.

5.3 InitializationandConfiguration

The PLL is configured using direct register writes to theRCC/RCC2register. If theRCC2register is being used, theUSERCC2bit must be set and the appropriateRCC2bit/field is used. The steps required to successfully change the PLL-based system clock are: 1. Bypass the PLL and system clock divider by setting theBYPASSbit and clearing theUSESYS bit in theRCCregister, thereby configuring the microcontroller to run off a "raw" clock source and allowing for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear thePWRDNbit in RCC/RCC2. Setting theXTALfield automatically pulls valid PLL configuration data for the appropriate crystal, and clearing thePWRDNbit powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) inRCC/RCC2and set theUSESYSbit inRCC. The SYSDIVfield determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling thePLLLRISbit in theRawInterruptStatus(RIS ) register. 5. Enable use of the PLL by clearing theBYPASSbit inRCC/RCC2.

5.4 RegisterMap

Table 5-7 on page 224 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register's address, relative to the System Control base address of 0x400F.E000. Note: Spaces in the System Control register space that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Additional Flash and ROM registers defined in the System Control register space are described in the “Internal Memory” on page 507. Table5-7.SystemControlRegisterMap See pageDescriptionResetTypeNameOffset SystemControlRegisters 230Device Identification 0-RODID00x000 June 12, 2014224 Texas Instruments-Production Data System Control

Table5-7.SystemControlRegisterMap (continued) See pageDescriptionResetTypeNameOffset 232Device Identification 10x10D0.442ERODID10x004 235Brown-Out Reset Control0x0000.7FFFRWPBORCTL0x030 236Raw Interrupt Status0x0000.0000RORIS0x050 239Interrupt Mask Control0x0000.0000RWIMC0x054 241Masked Interrupt Status and Clear0x0000.0000RW1CMISC0x058 244Reset Cause-RWRESC0x05C 246Run-Mode Clock Configuration0x0780.3AD1RWRCC0x060 250GPIO High-Performance Bus Control0x0000.7E00RWGPIOHBCTL0x06C 253Run-Mode Clock Configuration 20x07C0.6810RWRCC20x070 256Main Oscillator Control0x0000.0000RWMOSCCTL0x07C 257Deep Sleep Clock Configuration0x0780.0000RWDSLPCLKCFG0x144 259System Properties0x0000.1D31ROSYSPROP0x14C 261Precision Internal Oscillator Calibration0x0000.0000RWPIOSCCAL0x150 263Precision Internal Oscillator Statistics0x0000.0040ROPIOSCSTAT0x154 264PLL Frequency 00x0000.0032ROPLLFREQ00x160 265PLL Frequency 10x0000.0001ROPLLFREQ10x164 266PLL Status0x0000.0000ROPLLSTAT0x168 267Sleep Power Configuration0x0000.0000RWSLPPWRCFG0x188 269Deep-Sleep Power Configuration0x0000.0000RWDSLPPWRCFG0x18C 271LDO Sleep Power Control0x0000.0018RWLDOSPCTL0x1B4 273LDO Sleep Power Calibration0x0000.1818ROLDOSPCAL0x1B8 274LDO Deep-Sleep Power Control0x0000.0012RWLDODPCTL0x1BC 276LDO Deep-Sleep Power Calibration0x0000.1212ROLDODPCAL0x1C0 277Sleep / Deep-Sleep Power Mode Status0x0000.0000ROSDPMST0x1CC 280Watchdog Timer Peripheral Present0x0000.0003ROPPWD0x300 28116/32-Bit General-Purpose Timer Peripheral Present0x0000.003FROPPTIMER0x304 283General-Purpose Input/Output Peripheral Present0x0000.03FFROPPGPIO0x308 286Micro Direct Memory Access Peripheral Present0x0000.0001ROPPDMA0x30C 287Hibernation Peripheral Present0x0000.0001ROPPHIB0x314 288Universal Asynchronous Receiver/Transmitter Peripheral Present0x0000.00FFROPPUART0x318 290Synchronous Serial Interface Peripheral Present0x0000.000FROPPSSI0x31C 225June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table5-7.SystemControlRegisterMap (continued) See pageDescriptionResetTypeNameOffset 292Inter-Integrated Circuit Peripheral Present0x0000.003FROPPI2C0x320 294Universal Serial Bus Peripheral Present0x0000.0001ROPPUSB0x328 295Controller Area Network Peripheral Present0x0000.0001ROPPCAN0x334 296Analog-to-Digital Converter Peripheral Present0x0000.0003ROPPADC0x338 297Analog Comparator Peripheral Present0x0000.0001ROPPACMP0x33C 298Pulse Width Modulator Peripheral Present0x0000.0000ROPPPWM0x340 299Quadrature Encoder Interface Peripheral Present0x0000.0000ROPPQEI0x344 300EEPROM Peripheral Present0x0000.0001ROPPEEPROM0x358 30132/64-Bit Wide General-Purpose Timer Peripheral Present0x0000.003FROPPWTIMER0x35C 303Watchdog Timer Software Reset0x0000.0000RWSRWD0x500 30516/32-Bit General-Purpose Timer Software Reset0x0000.0000RWSRTIMER0x504 307General-Purpose Input/Output Software Reset0x0000.0000RWSRGPIO0x508 310Micro Direct Memory Access Software Reset0x0000.0000RWSRDMA0x50C 311Hibernation Software Reset0x0000.0000RWSRHIB0x514 312Universal Asynchronous Receiver/Transmitter Software Reset0x0000.0000RWSRUART0x518 314Synchronous Serial Interface Software Reset0x0000.0000RWSRSSI0x51C 316Inter-Integrated Circuit Software Reset0x0000.0000RWSRI2C0x520 318Universal Serial Bus Software Reset0x0000.0000RWSRUSB0x528 319Controller Area Network Software Reset0x0000.0000RWSRCAN0x534 320Analog-to-Digital Converter Software Reset0x0000.0000RWSRADC0x538 322Analog Comparator Software Reset0x0000.0000RWSRACMP0x53C 323EEPROM Software Reset0x0000.0000RWSREEPROM0x558 32432/64-Bit Wide General-Purpose Timer Software Reset0x0000.0000RWSRWTIMER0x55C 326Watchdog Timer Run Mode Clock Gating Control0x0000.0000RWRCGCWD0x600 32716/32-Bit General-Purpose Timer Run Mode Clock Gating Control0x0000.0000RWRCGCTIMER0x604 329General-Purpose Input/Output Run Mode Clock Gating Control0x0000.0000RWRCGCGPIO0x608 332Micro Direct Memory Access Run Mode Clock Gating Control0x0000.0000RWRCGCDMA0x60C 333Hibernation Run Mode Clock Gating Control0x0000.0001RWRCGCHIB0x614 334Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control0x0000.0000RWRCGCUART0x618 June 12, 2014226 Texas Instruments-Production Data System Control

Table5-7.SystemControlRegisterMap (continued) See pageDescriptionResetTypeNameOffset 336Synchronous Serial Interface Run Mode Clock Gating Control0x0000.0000RWRCGCSSI0x61C 338Inter-Integrated Circuit Run Mode Clock Gating Control0x0000.0000RWRCGCI2C0x620 340Universal Serial Bus Run Mode Clock Gating Control0x0000.0000RWRCGCUSB0x628 341Controller Area Network Run Mode Clock Gating Control0x0000.0000RWRCGCCAN0x634 342Analog-to-Digital Converter Run Mode Clock Gating Control0x0000.0000RWRCGCADC0x638 343Analog Comparator Run Mode Clock Gating Control0x0000.0000RWRCGCACMP0x63C 344EEPROM Run Mode Clock Gating Control0x0000.0000RWRCGCEEPROM0x658 34532/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control0x0000.0000RWRCGCWTIMER0x65C 347Watchdog Timer Sleep Mode Clock Gating Control0x0000.0000RWSCGCWD0x700 34816/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control0x0000.0000RWSCGCTIMER0x704 350General-Purpose Input/Output Sleep Mode Clock Gating Control0x0000.0000RWSCGCGPIO0x708 353Micro Direct Memory Access Sleep Mode Clock Gating Control0x0000.0000RWSCGCDMA0x70C 354Hibernation Sleep Mode Clock Gating Control0x0000.0001RWSCGCHIB0x714 355Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control0x0000.0000RWSCGCUART0x718 357Synchronous Serial Interface Sleep Mode Clock Gating Control0x0000.0000RWSCGCSSI0x71C 359Inter-Integrated Circuit Sleep Mode Clock Gating Control0x0000.0000RWSCGCI2C0x720 361Universal Serial Bus Sleep Mode Clock Gating Control0x0000.0000RWSCGCUSB0x728 362Controller Area Network Sleep Mode Clock Gating Control0x0000.0000RWSCGCCAN0x734 363Analog-to-Digital Converter Sleep Mode Clock Gating Control0x0000.0000RWSCGCADC0x738 364Analog Comparator Sleep Mode Clock Gating Control0x0000.0000RWSCGCACMP0x73C 365EEPROM Sleep Mode Clock Gating Control0x0000.0000RWSCGCEEPROM0x758 36632/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating Control0x0000.0000RWSCGCWTIMER0x75C 368Watchdog Timer Deep-Sleep Mode Clock Gating Control0x0000.0000RWDCGCWD0x800 36916/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control0x0000.0000RWDCGCTIMER0x804 371General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control0x0000.0000RWDCGCGPIO0x808 227June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table5-7.SystemControlRegisterMap (continued) See pageDescriptionResetTypeNameOffset 374Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control0x0000.0000RWDCGCDMA0x80C 375Hibernation Deep-Sleep Mode Clock Gating Control0x0000.0001RWDCGCHIB0x814 376Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control0x0000.0000RWDCGCUART0x818 378Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control0x0000.0000RWDCGCSSI0x81C 380Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control0x0000.0000RWDCGCI2C0x820 382Universal Serial Bus Deep-Sleep Mode Clock Gating Control0x0000.0000RWDCGCUSB0x828 383Controller Area Network Deep-Sleep Mode Clock Gating Control0x0000.0000RWDCGCCAN0x834 384Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control0x0000.0000RWDCGCADC0x838 385Analog Comparator Deep-Sleep Mode Clock Gating Control0x0000.0000RWDCGCACMP0x83C 386EEPROM Deep-Sleep Mode Clock Gating Control0x0000.0000RWDCGCEEPROM0x858 38732/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating Control0x0000.0000RWDCGCWTIMER0x85C 389Watchdog Timer Peripheral Ready0x0000.0000ROPRWD0xA00 39016/32-Bit General-Purpose Timer Peripheral Ready0x0000.0000ROPRTIMER0xA04 392General-Purpose Input/Output Peripheral Ready0x0000.0000ROPRGPIO0xA08 394Micro Direct Memory Access Peripheral Ready0x0000.0000ROPRDMA0xA0C 395Hibernation Peripheral Ready0x0000.0001ROPRHIB0xA14 396Universal Asynchronous Receiver/Transmitter Peripheral Ready0x0000.0000ROPRUART0xA18 398Synchronous Serial Interface Peripheral Ready0x0000.0000ROPRSSI0xA1C 400Inter-Integrated Circuit Peripheral Ready0x0000.0000ROPRI2C0xA20 402Universal Serial Bus Peripheral Ready0x0000.0000ROPRUSB0xA28 403Controller Area Network Peripheral Ready0x0000.0000ROPRCAN0xA34 404Analog-to-Digital Converter Peripheral Ready0x0000.0000ROPRADC0xA38 405Analog Comparator Peripheral Ready0x0000.0000ROPRACMP0xA3C 406EEPROM Peripheral Ready0x0000.0000ROPREEPROM0xA58 40732/64-Bit Wide General-Purpose Timer Peripheral Ready0x0000.0000ROPRWTIMER0xA5C June 12, 2014228 Texas Instruments-Production Data System Control

Table5-7.SystemControlRegisterMap (continued) See pageDescriptionResetTypeNameOffset SystemControlLegacyRegisters 409Device Capabilities 00x005F.001FRODC00x008 411Device Capabilities 10x1103.2FFFRODC10x010 414Device Capabilities 20x070F.F037RODC20x014 417Device Capabilities 30xBFFF.7FC0RODC30x018 421Device Capabilities 40x0004.F1FFRODC40x01C 424Device Capabilities 50x0000.0000RODC50x020 426Device Capabilities 60x0000.0011RODC60x024 427Device Capabilities 70xFFFF.FFFFRODC70x028 430Device Capabilities 80xFFFF.FFFFRODC80x02C 433Software Reset Control 00x0000.0000ROSRCR00x040 435Software Reset Control 10x0000.0000ROSRCR10x044 438Software Reset Control 20x0000.0000ROSRCR20x048 440Run Mode Clock Gating Control Register 00x0000.0040RORCGC00x100 443Run Mode Clock Gating Control Register 10x0000.0000RORCGC10x104 446Run Mode Clock Gating Control Register 20x0000.0000RORCGC20x108 449Sleep Mode Clock Gating Control Register 00x0000.0040ROSCGC00x110 451Sleep Mode Clock Gating Control Register 10x0000.0000ROSCGC10x114 454Sleep Mode Clock Gating Control Register 20x0000.0000ROSCGC20x118 457Deep Sleep Mode Clock Gating Control Register 00x0000.0040RODCGC00x120 459Deep-Sleep Mode Clock Gating Control Register 10x0000.0000RODCGC10x124 462Deep Sleep Mode Clock Gating Control Register 20x0000.0000RODCGC20x128 465Device Capabilities 90x00FF.00FFRODC90x190 467Non-Volatile Memory Information0x0000.0001RONVMSTAT0x1A0

5.5 SystemControlRegisterDescriptions

All addresses given are relative to the System Control base address of 0x400F.E000. Registers provided for legacy software support only are listed in “System Control Legacy Register Descriptions” on page 408. 229June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register1:DeviceIdentification0(DID0),offset0x000 This register identifies the version of the microcontroller. Each microcontroller is uniquely identified by the combined values of theCLASSfield in theDID0register and thePARTNOfield in theDID1 register. TheMAJORand MINORbit fields indicate the die revision number. Combined, theMAJOR and MINORbit fields indicate the part revision number. PartRevisionDieRevisionMINORBitfieldValueMAJORBitfieldValue 1A00x00x0 2A10x10x0 3A20x20x0 4A30x30x0 5B00x00x1 6B10x10x1 7B20x20x1 Device Identification 0 (DID0) Base 0x400F.E000 Offset 0x000 Type RO, reset - 16171819202122232425262728293031 CLASSreservedVERreserved ROROROROROROROROROROROROROROROROType 1010000000011000Reset 0123456789101112131415 MINORMAJOR ROROROROROROROROROROROROROROROROType DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 DID0 Version This field defines theDID0register format version. The version number is numeric. The value of theVERfield is encoded as follows (all other encodings are reserved): DescriptionValue Second version of theDID0register format.0x1 0x01ROVER30:28 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x08ROreserved27:24 June 12, 2014230 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field Device Class The CLASSfield value identifies the internal design from which all mask sets are generated for all microcontrollers in a particular product line. The CLASSfield value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJORor MINORfields require differentiation from prior microcontrollers. The value of theCLASSfield is encoded as follows (all other encodings are reserved): DescriptionValue Tiva™ TM4C123x microcontrollers0x05 0x05ROCLASS23:16 Major Die Revision This field specifies the major revision number of the microcontroller. The major revision reflects changes to base layers of the design. This field is encoded as follows: DescriptionValue Revision A (initial device)0x0 Revision B (first base layer revision)0x1 Revision C (second base layer revision)0x2 and so on. -ROMAJOR15:8 Minor Die Revision This field specifies the minor revision number of the microcontroller. The minor revision reflects changes to the metal layers of the design. The MINORfield value is reset when theMAJORfield is changed. This field is numeric and is encoded as follows: DescriptionValue Initial device, or a major revision update.0x0 First metal layer change.0x1 Second metal layer change.0x2 and so on. -ROMINOR7:0 231June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register2:DeviceIdentification1(DID1),offset0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Each microcontroller is uniquely identified by the combined values of theCLASSfield in the DID0register and thePARTNOfield in theDID1register. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset 0x10D0.442E 16171819202122232425262728293031 PARTNOFAMVER ROROROROROROROROROROROROROROROROType 0000101100001000Reset 0123456789101112131415 QUALROHSPKGTEMPreservedPINCOUNT ROROROROROROROROROROROROROROROROType 0111010000000010Reset DescriptionResetTypeNameBit/Field DID1 Version This field defines theDID1register format version. The version number is numeric. The value of theVERfield is encoded as follows (all other encodings are reserved): DescriptionValue Initial DID1register format definition, indicating a Stellaris LM3Snnn device. 0x0 Second version of theDID1register format.0x1 0x1ROVER31:28 Family This field provides the family identification of the device within the product portfolio. The value is encoded as follows (all other encodings are reserved): DescriptionValue Tiva™ C Series microcontrollers and legacy Stellaris microcontrollers, that is, all devices with external part numbers starting with TM4C, LM4F or LM3S. 0x0 0x0ROFAM27:24 Part Number This field provides the part number of the device within the family. The reset value shown indicates the TM4C1233D5PZ microcontroller. 0xD0ROPARTNO23:16 June 12, 2014232 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): DescriptionValue reserved0x0 reserved0x1 100-pin package0x2 64-pin package0x3 144-pin package0x4 157-pin package0x5 168-pin package0x6 0x2ROPINCOUNT15:13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12:8 Temperature Range This field specifies the temperature rating of the device. The value is encoded as follows (all other encodings are reserved): DescriptionValue Reserved0x0 Industrial temperature range (-40°C to 85°C)0x1 Extended temperature range (-40°C to 105°C)0x2 Available in both industrial temperature range (-40°C to 85°C) and extended temperature range (-40°C to 105°C) devices. See “Package Information” on page 1236 for specific order numbers. 0x3 0x1ROTEMP7:5 Package Type This field specifies the package type. The value is encoded as follows (all other encodings are reserved): DescriptionValue Reserved0x0 LQFP package0x1 BGA package0x2 0x1ROPKG4:3 RoHS-Compliance This bit specifies whether the device is RoHS-compliant. A 1 indicates the part is RoHS-compliant. 0x1ROROHS2 233June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): DescriptionValue Engineering Sample (unqualified)0x0 Pilot Production (unqualified)0x1 Fully Qualified0x2 0x2ROQUAL1:0 June 12, 2014234 Texas Instruments-Production Data System Control

Register3:Brown-OutResetControl(PBORCTL),offset0x030 This register is responsible for controlling reset conditions after initial power-on reset. Note: The BOR voltage values and center points are based on simulation only. These values are yet to be characterized and are subject to change. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type RW, reset 0x0000.7FFF 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedBOR1BOR0reserved RORWRWROROROROROROROROROROROROROType 0110000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:3 VDD under BOR0 Event Action The VDD BOR0 trip value is 3.02V +/- 90mv. DescriptionValue A BOR0 event causes an interrupt to be generated in the interrupt controller. A BOR0 event causes a reset of the microcontroller.1 1RWBOR02 VDD under BOR1 Event Action The VDD BOR1 trip value is 2.88V +/- 90mv. DescriptionValue A BOR1 event causes an interrupt to be generated to the interrupt controller. A BOR1 event causes a reset of the microcontroller.1 1RWBOR11 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved0 235June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register4:RawInterruptStatus(RIS),offset0x050 This register indicates the status for system control raw interrupts. An interrupt is sent to the interrupt controller if the corresponding bit in theInterruptMaskControl(IMC) register is set. Writing a 1 to the corresponding bit in theMaskedInterruptStatusandClear(MISC) register clears an interrupt status bit. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedBOR1RISreservedMOFRISreservedPLLLRISUSBPLLLRISMOSCPUPRISreservedVDDARISBOR0RISreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:12 VDD under BOR0 Raw Interrupt Status DescriptionValue A VDD BOR0 condition is not currently active.0 A VDD BOR0 condition is currently active.1 Note theBOR0bit in thePBORCTLregister must be cleared to cause an interrupt due to a BOR0 Event. This bit is cleared by writing a 1 to theBOR0MISbit in theMISCregister. 0ROBOR0RIS11 VDDA Power OK Event Raw Interrupt Status DescriptionValue VDDA power is not at its appropriate functional voltage.0 VDDA is at an appropriate functional voltage.1 This bit is cleared by writing a 1 to theVDDAMISbit in theMISCregister. 0ROVDDARIS10 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved9 June 12, 2014236 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field MOSC Power Up Raw Interrupt Status DescriptionValue Sufficient time has not passed for the MOSC to reach the expected frequency. Sufficient time has passed for the MOSC to reach the expected frequency. The value for this power-up time is indicated by TMOSC_START. This bit is cleared by writing a 1 to theMOSCPUPMISbit in theMISC register. 0ROMOSCPUPRIS8 USB PLL Lock Raw Interrupt Status DescriptionValue The USB PLL timer has not reached TREADY.0 The USB PLL timer has reached TREADY indicating that sufficient time has passed for the USB PLL to lock. This bit is cleared by writing a 1 to theUSBPLLLMISbit in theMISC register. 0ROUSBPLLLRIS7 PLL Lock Raw Interrupt Status DescriptionValue The PLL timer has not reached TREADY.0 The PLL timer has reached TREADY indicating that sufficient time has passed for the PLL to lock. This bit is cleared by writing a 1 to thePLLLMISbit in theMISCregister. 0ROPLLLRIS6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved5:4 Main Oscillator Failure Raw Interrupt Status DescriptionValue The main oscillator has not failed.0 The MOSCIMbit in theMOSCCTLregister is set and the main oscillator has failed. This bit is cleared by writing a 1 to theMOFMISbit in theMISCregister. 0ROMOFRIS3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2 237June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field VDD under BOR1 Raw Interrupt Status DescriptionValue A VDDS BOR1 condition is not currently active.0 A VDDS BOR1 condition is currently active.1 Note theBOR1bit in thePBORCTLregister must be cleared to cause an interrupt due to a BOR1 Event. This bit is cleared by writing a 1 to theBOR1MISbit in theMISCregister. 0ROBOR1RIS1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved0 June 12, 2014238 Texas Instruments-Production Data System Control

Register5:InterruptMaskControl(IMC),offset0x054 This register contains the mask bits for system control raw interrupts. A raw interrupt, indicated by a bit being set in theRawInterruptStatus(RIS) register, is sent to the interrupt controller if the corresponding bit in this register is set. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedBOR1IMreservedMOFIMreservedPLLLIMUSBPLLLIMMOSCPUPIMreservedVDDAIMBOR0IMreserved RORWRORWRORORWRWRWRORWRWROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:12 VDD under BOR0 Interrupt Mask DescriptionValue The BOR0RISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when theBOR0RIS bit in theRISregister is set. 0RWBOR0IM11 VDDA Power OK Interrupt Mask DescriptionValue The VDDARISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when theVDDARIS bit in theRISregister is set. 0RWVDDAIM10 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved9 MOSC Power Up Interrupt Mask DescriptionValue The MOSCPUPRISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when the MOSCPUPRISbit in theRISregister is set. 0RWMOSCPUPIM8 239June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field USB PLL Lock Interrupt Mask DescriptionValue The USBPLLLRISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when the USBPLLLRISbit in theRISregister is set. 0RWUSBPLLLIM7 PLL Lock Interrupt Mask DescriptionValue The PLLLRISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when thePLLLRIS bit in theRISregister is set. 0RWPLLLIM6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved5:4 Main Oscillator Failure Interrupt Mask DescriptionValue The MOFRISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when theMOFRIS bit in theRISregister is set. 0RWMOFIM3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2 VDD under BOR1 Interrupt Mask DescriptionValue The BOR1RISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when theBOR1RIS bit in theRISregister is set. 0RWBOR1IM1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved0 June 12, 2014240 Texas Instruments-Production Data System Control

Register6:MaskedInterruptStatusandClear(MISC),offset0x058 On a read, this register gives the current masked status value of the corresponding interrupt in the RawInterruptStatus(RIS) register. All of the bits are RW1C, thus writing a 1 to a bit clears the corresponding raw interrupt bit in theRISregister (see page 236). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type RW1C, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedBOR1MISreservedMOFMISreservedPLLLMISUSBPLLLMISMOSCPUPMISreservedVDDAMISBOR0MISreserved RORW1CRORORORORW1CRW1CRW1CRORW1CRW1CROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:12 VDD under BOR0 Masked Interrupt Status DescriptionValue When read, a 0 indicates that a BOR0 condition has not occurred. A write of 0 has no effect on the state of this bit. When read, a 1 indicates that an unmasked interrupt was signaled because of a BOR0 condition. Writing a 1 to this bit clears it and also theBOR0RISbit in the RISregister. 0RW1CBOR0MIS11 VDDA Power OK Masked Interrupt Status DescriptionValue When read, a 0 indicates that VDDA power is good. A write of 0 has no effect on the state of this bit. When read, a 1 indicates that an unmasked interrupt was signaled because VDDA was below the proper functioning voltage. Writing a 1 to this bit clears it and also theVDDARISbit in the RISregister. 0RW1CVDDAMIS10 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved9 241June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field MOSC Power Up Masked Interrupt Status DescriptionValue When read, a 0 indicates that sufficient time has not passed for the MOSC PLL to lock. A write of 0 has no effect on the state of this bit. When read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the MOSC PLL to lock. Writing a 1 to this bit clears it and also theMOSCPUPRISbit in the RISregister. 0RW1CMOSCPUPMIS8 USB PLL Lock Masked Interrupt Status DescriptionValue When read, a 0 indicates that sufficient time has not passed for the USB PLL to lock. A write of 0 has no effect on the state of this bit. When read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the USB PLL to lock. Writing a 1 to this bit clears it and also theUSBPLLLRISbit in the RISregister. 0RW1CUSBPLLLMIS7 PLL Lock Masked Interrupt Status DescriptionValue When read, a 0 indicates that sufficient time has not passed for the PLL to lock. A write of 0 has no effect on the state of this bit. When read, a 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the PLL to lock. Writing a 1 to this bit clears it and also thePLLLRISbit in the RISregister. 0RW1CPLLLMIS6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved5:4 Main Oscillator Failure Masked Interrupt Status DescriptionValue When read, a 0 indicates that the main oscillator has not failed. A write of 0 has no effect on the state of this bit. When read, a 1 indicates that an unmasked interrupt was signaled because the main oscillator failed. Writing a 1 to this bit clears it and also theMOFRISbit in the RISregister. 0ROMOFMIS3 June 12, 2014242 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2 VDD under BOR1 Masked Interrupt Status DescriptionValue When read, a 0 indicates that a BOR1 condition has not occurred. A write of 0 has no effect on the state of this bit. When read, a 1 indicates that an unmasked interrupt was signaled because of a BOR1 condition. Writing a 1 to this bit clears it and also theBOR1RISbit in the RISregister. 0RW1CBOR1MIS1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved0 243June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register7:ResetCause(RESC),offset0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an power-on reset is the cause, in which case, all bits other thanPORin theRESCregister are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type RW, reset - 16171819202122232425262728293031 MOSCFAILreserved RWROROROROROROROROROROROROROROROType -000000000000000Reset 0123456789101112131415 EXTPORBORWDT0SWWDT1reserved RWRWRWRWRWRWROROROROROROROROROROType DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved31:17 MOSC Failure Reset DescriptionValue When read, this bit indicates that a MOSC failure has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. When read, this bit indicates that the MOSC circuit was enabled for clock validation and failed while theMOSCIMbit in the MOSCCTLregister is clear, generating a reset event. -RWMOSCFAIL16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved15:6 Watchdog Timer 1 Reset DescriptionValue When read, this bit indicates that Watchdog Timer 1 has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. When read, this bit indicates that Watchdog Timer 1 timed out and generated a reset. -RWWDT15 June 12, 2014244 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field Software Reset DescriptionValue When read, this bit indicates that a software reset has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. When read, this bit indicates that a software reset has caused a reset event. -RWSW4 Watchdog Timer 0 Reset DescriptionValue When read, this bit indicates that Watchdog Timer 0 has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. When read, this bit indicates that Watchdog Timer 0 timed out and generated a reset. -RWWDT03 Brown-Out Reset DescriptionValue When read, this bit indicates that a brown-out (BOR0 or BOR1) reset has not generated a reset since the previous power-on reset. Writing a 0 to this bit clears it. When read, this bit indicates that a brown-out (BOR0 or BOR1) reset has caused a reset event. -RWBOR2 Power-On Reset DescriptionValue When read, this bit indicates that a power-on reset has not generated a reset. Writing a 0 to this bit clears it. When read, this bit indicates that a power-on reset has caused a reset event. -RWPOR1 External Reset DescriptionValue When read, this bit indicates that an external reset (RST assertion) has not caused a reset event since the previous power-on reset. Writing a 0 to this bit clears it. When read, this bit indicates that an external reset (RST assertion) has caused a reset event. -RWEXT0 245June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register8:Run-ModeClockConfiguration(RCC),offset0x060 The bits in this register configure the system clock and oscillators. Important: Write theRCCregister prior to writing theRCC2register. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type RW, reset 0x0780.3AD1 16171819202122232425262728293031 reservedUSESYSDIVSYSDIVACGreserved RORORORORORORWRWRWRWRWRWROROROROType 0000000111100000Reset 0123456789101112131415 MOSCDISreservedOSCSRCXTALBYPASSreservedPWRDNreserved RWRORORORWRWRWRWRWRWRWRWRORWROROType 1000101101011100Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:28 Auto Clock Gating This bit specifies whether the system uses theSleep-ModeClock GatingControl(SCGCn) registers andDeep-Sleep-ModeClock GatingControl(DCGCn) registers if the microcontroller enters a Sleep or Deep-Sleep mode (respectively). DescriptionValue The Run-ModeClockGatingControl(RCGCn) registers are used when the microcontroller enters a sleep mode. The SCGCnor DCGCnregisters are used to control the clocks distributed to the peripherals when the microcontroller is in a sleep mode. TheSCGCnand DCGCnregisters allow unused peripherals to consume less power when the microcontroller is in a sleep mode. The RCGCnregisters are always used to control the clocks in Run mode. 0RWACG27 System Clock Divisor Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how theBYPASS bit in this register is configured). See Table 5-4 on page 216 for bit encodings. If theSYSDIVvalue is less thanMINSYSDIV(see page 411), and the PLL is being used, then theMINSYSDIVvalue is used as the divisor. If the PLL is not being used, theSYSDIVvalue can be less than MINSYSDIV. 0xFRWSYSDIV26:23 June 12, 2014246 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field Enable System Clock Divider DescriptionValue The system clock is used undivided.0 The system clock divider is the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. If theUSERCC2bit in theRCC2register is set, then theSYSDIV2 field in theRCC2register is used as the system clock divider rather than theSYSDIVfield in this register. 0RWUSESYSDIV22 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved21:14 PLL Power Down DescriptionValue The PLL is operating normally.0 The PLL is powered down. Care must be taken to ensure that another clock source is functioning and that theBYPASSbit is set before setting this bit. 1RWPWRDN13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1ROreserved12 PLL Bypass DescriptionValue The system clock is the PLL output clock divided by the divisor specified bySYSDIV. The system clock is derived from the OSC source and divided by the divisor specified bySYSDIV. See Table 5-4 on page 216 for programming guidelines. Note: The ADC must be clocked from the PLL or directly from a 16-MHz clock source to operate properly. 1RWBYPASS11 247June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Frequencies that may be used with the USB interface are indicated in the table. To function within the clocking requirements of the USB specification, a crystal of 5, 6, 8, 10, 12, or 16 MHz must be used. Crystal Frequency (MHz) Using the PLL Crystal Frequency (MHz) Not Using the PLL Value reserved0x00-0x5 reserved4 MHz0x06 reserved4.096 MHz0x07 reserved4.9152 MHz0x08

5 MHz (USB)0x09

5.12 MHz0x0A

6 MHz (USB)0x0B

6.144 MHz0x0C

7.3728 MHz0x0D

8 MHz (USB)0x0E

8.192 MHz0x0F

10.0 MHz (USB)0x10

12.0 MHz (USB)0x11

12.288 MHz0x12

13.56 MHz0x13

14.31818 MHz0x14

16.0 MHz (USB)0x15

16.384 MHz0x16

18.0 MHz (USB)0x17

20.0 MHz (USB)0x18

24.0 MHz (USB)0x19

25.0 MHz (USB)0x1A

0x0BRWXTAL10:6 June 12, 2014248 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field Oscillator Source Selects the input source for the OSC. The values are: Input SourceValue MOSC Main oscillator 0x0 PIOSC Precision internal oscillator (default) 0x1 PIOSC/4 Precision internal oscillator / 4 0x2 LFIOSC Low-frequency internal oscillator 0x3 For additional oscillator sources, see theRCC2register. 0x1RWOSCSRC5:4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved3:1 Main Oscillator Disable DescriptionValue The main oscillator is enabled.0 The main oscillator is disabled (default).1 1RWMOSCDIS0 249June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register9:GPIOHigh-PerformanceBusControl(GPIOHBCTL),offset0x06C This register controls which internal bus is used to access each GPIO port. When a bit is clear, the corresponding GPIO port is accessed across the legacy Advanced Peripheral Bus (APB) bus and through the APB memory aperture. When a bit is set, the corresponding port is accessed across the Advanced High-Performance Bus (AHB) bus and through the AHB memory aperture. Each GPIO port can be individually configured to use AHB or APB, but may be accessed only through one aperture. The AHB bus provides better back-to-back access performance than the APB bus. The address aperture in the memory map changes for the ports that are enabled for AHB access (see Table 10-6 on page 643). Important: Ports K-N and P-Q are only available on the AHB bus, and therefore the corresponding bits reset to 1. If one of these bits is cleared, the corresponding port is disabled. If any of these ports is in use, read-modify-write operations should be used to change the value of this register so that these ports remain enabled. GPIO High-Performance Bus Control (GPIOHBCTL) Base 0x400F.E000 Offset 0x06C Type RW, reset 0x0000.7E00 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PORTAPORTBPORTCPORTDPORTEPORTFPORTGPORTHPORTJPORTKreserved RWRWRWRWRWRWRWRWRWRWROROROROROROType 0000000001000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0ROreserved31:10 Port K Advanced High-Performance Bus This bit defines the memory aperture for Port K. DescriptionValue Port K is disabled.0 Advanced High-Performance Bus (AHB)1 1RWPORTK9 Port J Advanced High-Performance Bus This bit defines the memory aperture for Port J. DescriptionValue Advanced Peripheral Bus (APB). This bus is the legacy bus.0 Advanced High-Performance Bus (AHB)1 0RWPORTJ8 June 12, 2014250 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field Port H Advanced High-Performance Bus This bit defines the memory aperture for Port H. DescriptionValue Advanced Peripheral Bus (APB). This bus is the legacy bus.0 Advanced High-Performance Bus (AHB)1 0RWPORTH7 Port G Advanced High-Performance Bus This bit defines the memory aperture for Port G. DescriptionValue Advanced Peripheral Bus (APB). This bus is the legacy bus.0 Advanced High-Performance Bus (AHB)1 0RWPORTG6 Port F Advanced High-Performance Bus This bit defines the memory aperture for Port F. DescriptionValue Advanced Peripheral Bus (APB). This bus is the legacy bus.0 Advanced High-Performance Bus (AHB)1 0RWPORTF5 Port E Advanced High-Performance Bus This bit defines the memory aperture for Port E. DescriptionValue Advanced Peripheral Bus (APB). This bus is the legacy bus.0 Advanced High-Performance Bus (AHB)1 0RWPORTE4 Port D Advanced High-Performance Bus This bit defines the memory aperture for Port D. DescriptionValue Advanced Peripheral Bus (APB). This bus is the legacy bus.0 Advanced High-Performance Bus (AHB)1 0RWPORTD3 Port C Advanced High-Performance Bus This bit defines the memory aperture for Port C. DescriptionValue Advanced Peripheral Bus (APB). This bus is the legacy bus.0 Advanced High-Performance Bus (AHB)1 0RWPORTC2 251June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Port B Advanced High-Performance Bus This bit defines the memory aperture for Port B. DescriptionValue Advanced Peripheral Bus (APB). This bus is the legacy bus.0 Advanced High-Performance Bus (AHB)1 0RWPORTB1 Port A Advanced High-Performance Bus This bit defines the memory aperture for Port A. DescriptionValue Advanced Peripheral Bus (APB). This bus is the legacy bus.0 Advanced High-Performance Bus (AHB)1 0RWPORTA0 June 12, 2014252 Texas Instruments-Production Data System Control

Register10:Run-ModeClockConfiguration2(RCC2),offset0x070 This register overrides theRCCequivalent register fields, as shown in Table 5-8, when theUSERCC2 bit is set, allowing the extended capabilities of theRCC2register to be used while also providing a means to be backward-compatible to previous parts. EachRCC2field that supersedes anRCC field is located at the same LSB bit position; however, someRCC2fields are larger than the corresponding RCCfield. Table5-8.RCC2FieldsthatOverrideRCCFields OverridesRCCFieldRCC2Field... SYSDIV, bits[26:23]SYSDIV2, bits[28:23] PWRDN, bit[13]PWRDN2, bit[13] BYPASS, bit[11]BYPASS2, bit[11] OSCSRC, bits[5:4]OSCSRC2, bits[6:4] Important: Write theRCCregister prior to writing theRCC2register. Run-Mode Clock Configuration 2 (RCC2) Base 0x400F.E000 Offset 0x070 Type RW, reset 0x07C0.6810 16171819202122232425262728293031 reservedSYSDIV2LSBSYSDIV2reservedDIV400USERCC2 RORORORORORORWRWRWRWRWRWRWRORWRWType 0000001111100000Reset 0123456789101112131415 reservedOSCSRC2reservedBYPASS2reservedPWRDN2USBPWRDNreserved RORORORORWRWRWRORORORORWRORWRWROType 0000100000010110Reset DescriptionResetTypeNameBit/Field Use RCC2 DescriptionValue The RCCregister fields are used, and the fields inRCC2are ignored. The RCC2register fields override theRCCregister fields.1 0RWUSERCC231 Divide PLL as 400 MHz versus 200 MHz This bit, along with theSYSDIV2LSBbit, allows additional frequency choices. DescriptionValue Use SYSDIV2as is and apply to 200 MHz predivided PLL output. See Table 5-5 on page 216 for programming guidelines. Append theSYSDIV2LSBbit to theSYSDIV2field to create a 7 bit divisor using the 400 MHz PLL output, see Table 5-6 on page 217. 0RWDIV40030 253June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved29 System Clock Divisor 2 Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how theBYPASS2 bit is configured).SYSDIV2is used for the divisor when both the USESYSDIVbit in theRCCregister and theUSERCC2bit in this register are set. See Table 5-5 on page 216 for programming guidelines. 0x0FRWSYSDIV228:23 Additional LSB forSYSDIV2 When DIV400is set, this bit becomes the LSB ofSYSDIV2. IfDIV400 is clear, this bit is not used. See Table 5-5 on page 216 for programming guidelines. This bit can only be set or cleared whenDIV400is set. 1RWSYSDIV2LSB22 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved21:15 Power-Down USB PLL DescriptionValue The USB PLL operates normally.0 The USB PLL is powered down.1 1RWUSBPWRDN14 Power-Down PLL 2 DescriptionValue The PLL operates normally.0 The PLL is powered down.1 1RWPWRDN213 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12 PLL Bypass 2 DescriptionValue The system clock is the PLL output clock divided by the divisor specified bySYSDIV2. The system clock is derived from the OSC source and divided by the divisor specified bySYSDIV2. See Table 5-5 on page 216 for programming guidelines. Note: The ADC must be clocked from the PLL or directly from a 16-MHz clock source to operate properly. 1RWBYPASS211 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved10:7 June 12, 2014254 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field Oscillator Source 2 Selects the input source for the OSC. The values are: DescriptionValue MOSC Main oscillator 0x0 PIOSC Precision internal oscillator 0x1 PIOSC/4 Precision internal oscillator / 4 0x2 LFIOSC Low-frequency internal oscillator 0x3 Reserved0x4-0x6 32.768 kHz 32.768-kHz external oscillator 0x7 0x1RWOSCSRC26:4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved3:0 255June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register11:MainOscillatorControl(MOSCCTL),offset0x07C This register provides control over the features of the main oscillator, including the ability to enable the MOSC clock verification circuit, what action to take when the MOSC fails, and whether or not a crystal is connected. When enabled, this circuit monitors the frequency of the MOSC to verify that the oscillator is operating within specified limits. If the clock goes invalid after being enabled, the microcontroller issues a power-on reset and reboots to the NMI handler or generates an interrupt. Main Oscillator Control (MOSCCTL) Base 0x400F.E000 Offset 0x07C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 CVALMOSCIMNOXTALreserved RWRWRWROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:3 No Crystal Connected DescriptionValue This bit should be cleared when a crystal or oscillator is connected to theOSC0and OSC1inputs, regardless of whether or not the MOSC is used or powered down. This bit should be set when a crystal or external oscillator is not connected to theOSC0and OSC1inputs to reduce power consumption. 0RWNOXTAL2 MOSC Failure Action DescriptionValue If the MOSC fails, a MOSC failure reset is generated and reboots to the NMI handler. If the MOSC fails, an interrupt is generated as indicated by the MOFRISbit in theRISregister.. Regardless of the action taken, if the MOSC fails, the oscillator source is switched to the PIOSC automatically. 0RWMOSCIM1 Clock Validation for MOSC DescriptionValue The MOSC monitor circuit is disabled.0 The MOSC monitor circuit is enabled.1 0RWCVAL0 June 12, 2014256 Texas Instruments-Production Data System Control

Register12:DeepSleepClockConfiguration(DSLPCLKCFG),offset0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type RW, reset 0x0780.0000 16171819202122232425262728293031 reservedDSDIVORIDEreserved RORORORORORORORWRWRWRWRWRWROROROType 0000000111100000Reset 0123456789101112131415 reservedPIOSCPDreservedDSOSCSRCreserved RORWRORORWRWRWROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:29 Divider Field Override If Deep-Sleep mode is enabled when the PLL is running, the PLL is disabled. This 6-bit field contains a system divider field that overrides the SYSDIVfield in theRCCregister or theSYSDIV2field in theRCC2 register during Deep Sleep. This divider is applied to the source selected by theDSOSCSRCfield. DescriptionValue /1 0x0 /2 0x1 /3 0x2 /4 0x3 /64 0x3F 0x0FRWDSDIVORIDE28:23 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved22:7 257June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Clock Source Specifies the clock source during Deep-Sleep mode. DescriptionValue MOSC Use the main oscillator as the source. To use the MOSC as the Deep-Sleep mode clock source, the MOSC must also be configured as the Run mode clock source in theRun-Mode ClockConfiguration(RCC) register. 0x0 Note: If the PIOSC is being used as the clock reference for the PLL, the PIOSC is the clock source instead of MOSC in Deep-Sleep mode. PIOSC Use the precision internal 16-MHz oscillator as the source. 0x1 Reserved0x2 LFIOSC Use the low-frequency internal oscillator as the source. 0x3 Reserved0x4-0x6 32.768 kHz Use the Hibernation module 32.768-kHz external oscillator as the source. 0x7 0x0RWDSOSCSRC6:4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved3:2 PIOSC Power Down Request Allows software to request the PIOSC to be powered-down in Deep-Sleep mode. If the PIOSC is needed by an enabled peripheral during Deep-Sleep, the PIOSC is powered down, but a warning is generated using thePPDWbit in theSDPMSTregister. If it is not possible to power down the PIOSC, an error is reported using thePPDERRbit in the SDPMSTregister. This bit can only be used to power down the PIOSC when thePIOSCPDE bit in theSYSPROPregister is set. DescriptionValue No action.0 Software requests that the PIOSC is powered down during Deep-Sleep mode. 0RWPIOSCPD1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved0 June 12, 2014258 Texas Instruments-Production Data System Control

Register13:SystemProperties(SYSPROP),offset0x14C This register provides information on whether certain System Control properties are present on the microcontroller. System Properties (SYSPROP) Base 0x400F.E000 Offset 0x14C Type RO, reset 0x0000.1D31 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 FPUreservedreservedreservedFLASHLPMreservedSRAMLPMSRAMSMPIOSCPDEreserved ROROROROROROROROROROROROROROROROType 1000110010111000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:13 PIOSC Power Down Present This bit determines whether thePIOSCPDbit in theDSLPCLKCFG register can be set to power down the PIOSC in Deep-Sleep mode. DescriptionValue The status of thePIOSCPDbit is ignored.0 The PIOSCPDbit can be set to power down the PIOSC in Deep-Sleep mode. 0x1ROPIOSCPDE12 SRAM Sleep/Deep-Sleep Standby Mode Present This bit determines whether theSRAMPMfield in theSLPPWRCFGand DSLPPWRCFGregisters can be configured to put the SRAM into Standby mode while in Sleep or Deep-Sleep mode. DescriptionValue A value of 0x1 in theSRAMPMfields is ignored.0 The SRAMPMfields can be configured to put the SRAM into Standby mode while in Sleep or Deep-Sleep mode. 0x1ROSRAMSM11 SRAM Sleep/Deep-Sleep Low Power Mode Present This bit determines whether theSRAMPMfield in theSLPPWRCFGand DSLPPWRCFGregisters can be configured to put the SRAM into Low Power mode while in Sleep or Deep-Sleep mode. DescriptionValue A value of 0x3 in theSRAMPMfields is ignored.0 The SRAMPMfields can be configured to put the SRAM into Low Power mode while in Sleep or Deep-Sleep mode. 0x1ROSRAMLPM10 259June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved9 Flash Memory Sleep/Deep-Sleep Low Power Mode Present This bit determines whether theFLASHPMfield in theSLPPWRCFG and DSLPPWRCFGregisters can be configured to put the Flash memory into Low Power mode while in Sleep or Deep-Sleep mode. DescriptionValue A value of 0x2 in theFLASHPMfields is ignored.0 The FLASHPMfields can be configured to put the Flash memory into Low Power mode while in Sleep or Deep-Sleep mode. 0x1ROFLASHLPM8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved7:6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x3ROreserved5:4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3:1 FPU Present This bit indicates if the FPU is present in the Cortex-M4 core. DescriptionValue FPU is not present.0 FPU is present.1 0x1ROFPU0 June 12, 2014260 Texas Instruments-Production Data System Control

Register14:PrecisionInternalOscillatorCalibration(PIOSCCAL),offset0x150 This register provides the ability to update or recalibrate the precision internal oscillator. Note that a 32.768-kHz oscillator must be used as the Hibernation module clock source for the user to be able to calibrate the PIOSC. Precision Internal Oscillator Calibration (PIOSCCAL) Base 0x400F.E000 Offset 0x150 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reservedUTEN RORORORORORORORORORORORORORORORWType 0000000000000000Reset 0123456789101112131415 UTreservedUPDATECALreserved RWRWRWRWRWRWRWRORWRWROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Use User Trim Value DescriptionValue The factory calibration value is used for an update trim operation.0 The trim value in bits[6:0] of this register are used for any update trim operation. 0RWUTEN31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000ROreserved30:10 Start Calibration DescriptionValue No action.0 Starts a new calibration of the PIOSC. Results are in the PIOSCSTATregister. The resulting trim value from the operation is active in the PIOSC after the calibration completes. The result overrides any previous update trim operation whether the calibration passes or fails. This bit is auto-cleared after it is set. 0RWCAL9 Update Trim DescriptionValue No action.0 Updates the PIOSC trim value with theUTbit or theDTbit in the PIOSCSTATregister. Used withUTEN. This bit is auto-cleared after the update. 0RWUPDATE8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved7 261June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field User Trim Value User trim value that can be loaded into the PIOSC. Refer to “Precision Internal Oscillator Operation (PIOSC)” on page 217 for more information on calibrating the PIOSC. 0x0RWUT6:0 June 12, 2014262 Texas Instruments-Production Data System Control

Register15:PrecisionInternalOscillatorStatistics(PIOSCSTAT),offset0x154 This register provides the user information on the PIOSC calibration. Note that a 32.768-kHz oscillator must be used as the Hibernation module clock source for the user to be able to calibrate the PIOSC. Precision Internal Oscillator Statistics (PIOSCSTAT) Base 0x400F.E000 Offset 0x154 Type RO, reset 0x0000.0040 16171819202122232425262728293031 DTreserved ROROROROROROROROROROROROROROROROType 0123456789101112131415 CTreservedRESULTreserved ROROROROROROROROROROROROROROROROType 0000001000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved31:23 Default Trim Value This field contains the default trim value. This value is loaded into the PIOSC after every full power-up. -RODT22:16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved15:10 Calibration Result DescriptionValue Calibration has not been attempted.0x0 The last calibration operation completed to meet 1% accuracy.0x1 The last calibration operation failed to meet 1% accuracy.0x2 Reserved0x3 0RORESULT9:8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved7 Calibration Trim Value This field contains the trim value from the last calibration operation. After factory calibrationCTand DTare the same. 0x40ROCT6:0 263June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register16:PLLFrequency0(PLLFREQ0),offset0x160 This register always contains the current M value presented to the system PLL. The PLL frequency can be calculated using the following equation: PLL frequency = (XTAL frequency * MDIV) / ((Q + 1) * (N + 1)) where MDIV = MINT + (MFRAC / 1024) The Q and N values are shown in thePLLFREQ1register. Table 22-14 on page 1207 shows the M, Q, and N values as well as the resulting PLL frequency for the variousXTALconfigurations. PLL Frequency 0 (PLLFREQ0) Base 0x400F.E000 Offset 0x160 Type RO, reset 0x0000.0032 16171819202122232425262728293031 MFRACreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 MINTMFRAC ROROROROROROROROROROROROROROROROType 0000000000010011Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved31:20 PLL M Fractional Value This field contains the integer value of the PLL M value. 0x32ROMFRAC19:10 PLL M Integer Value This field contains the integer value of the PLL M value. 0x00ROMINT9:0 June 12, 2014264 Texas Instruments-Production Data System Control

Register17:PLLFrequency1(PLLFREQ1),offset0x164 This register always contains the current Q and N values presented to the system PLL. The M value is shown in thePLLFREQ0register. Table 22-14 on page 1207 shows the M, Q, and N values as well as the resulting PLL frequency for the variousXTALconfigurations. PLL Frequency 1 (PLLFREQ1) Base 0x400F.E000 Offset 0x164 Type RO, reset 0x0000.0001 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 NreservedQreserved ROROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.0ROreserved31:13 PLL Q Value This field contains the PLL Q value. 0x0ROQ12:8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved7:5 PLL N Value This field contains the PLL N value. 0x1RON4:0 265June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register18:PLLStatus(PLLSTAT),offset0x168 This register shows the direct status of the PLL lock. PLL Status (PLLSTAT) Base 0x400F.E000 Offset 0x168 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 LOCKreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:1 PLL Lock DescriptionValue The PLL is unpowered or is not yet locked.0 The PLL is powered and locked.1 0x0ROLOCK0 June 12, 2014266 Texas Instruments-Production Data System Control

Register19:SleepPowerConfiguration(SLPPWRCFG),offset0x188 This register provides configuration information for the power control of the SRAM and Flash memory while in Sleep mode. Sleep Power Configuration (SLPPWRCFG) Base 0x400F.E000 Offset 0x188 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 SRAMPMreservedFLASHPMreserved RWRWRORORWRWROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:6 Flash Power Modes DescriptionValue Active Mode Flash memory is not placed in a lower power mode. This mode provides the fastest time to sleep and wakeup but the highest power consumption while the microcontroller is in Sleep mode. 0x0 Reserved0x1 Low Power Mode Flash memory is placed in low power mode. This mode provides the lowers power consumption but requires more time to come out of Sleep mode. 0x2 Reserved0x3 0x0RWFLASHPM5:4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved3:2 267June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field SRAM Power Modes This field controls the low power modes of the on-chip SRAM , including the USB SRAM while the microcontroller is in Deep-Sleep mode. DescriptionValue Active Mode SRAM is not placed in a lower power mode. This mode provides the fastest time to sleep and wakeup but the highest power consumption while the microcontroller is in Sleep mode. 0x0 Standby Mode SRAM is place in standby mode while in Sleep mode. 0x1 Reserved0x2 Low Power Mode SRAM is placed in low power mode. This mode provides the slowest time to sleep and wakeup but the lowest power consumption while in Sleep mode. 0x3 0x0RWSRAMPM1:0 June 12, 2014268 Texas Instruments-Production Data System Control

Register20:Deep-SleepPowerConfiguration(DSLPPWRCFG),offset0x18C This register provides configuration information for the power control of the SRAM and Flash memory while in Deep-Sleep mode. Deep-Sleep Power Configuration (DSLPPWRCFG) Base 0x400F.E000 Offset 0x18C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 SRAMPMreservedFLASHPMreserved RWRWRORORWRWROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:6 Flash Power Modes DescriptionValue Active Mode Flash memory is not placed in a lower power mode. This mode provides the fastest time to sleep and wakeup but the highest power consumption while the microcontroller is in Deep-Sleep mode. 0x0 Reserved0x1 Low Power Mode Flash memory is placed in low power mode. This mode provides the lowers power consumption but requires more time to come out of Deep-Sleep mode. 0x2 Reserved0x3 0x0RWFLASHPM5:4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved3:2 269June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field SRAM Power Modes This field controls the low power modes of the on-chip SRAM , including the USB SRAM while the microcontroller is in Deep-Sleep mode. DescriptionValue Active Mode SRAM is not placed in a lower power mode. This mode provides the fastest time to sleep and wakeup but the highest power consumption while the microcontroller is in Deep-Sleep mode. 0x0 Standby Mode SRAM is place in standby mode while in Deep-Sleep mode. 0x1 Reserved0x2 Low Power Mode SRAM is placed in low power mode. This mode provides the slowest time to sleep and wakeup but the lowest power consumption while in Deep-Sleep mode. 0x3 0x0RWSRAMPM1:0 June 12, 2014270 Texas Instruments-Production Data System Control

Register21:LDOSleepPowerControl(LDOSPCTL),offset0x1B4 This register specifies the LDO output voltage while in Sleep mode. Writes to theVLDObit field have no effect on the LDO output voltage, regardless of what is specified for theVADJENbit. The LDO output voltage is fixed at the recommended factory reset value. The table below shows the maximum system clock frequency and PIOSC frequency with respect to the configured LDO voltage. PIOSCMaximumSystemClockFrequencyOperatingVoltage(LDO) 16 MHz80 MHz1.2 16 MHz20 MHz0.9 Note: The LDO will not automatically adjust in Sleep/Deepsleep mode if a debugger has been connected since the last power-on reset. ■ If the LDO voltage is adjusted, it will take an extra 4 us to wake up from Sleep or Deep-Sleep mode. LDO Sleep Power Control (LDOSPCTL) Base 0x400F.E000 Offset 0x1B4 Type RW, reset 0x0000.0018 16171819202122232425262728293031 reservedVADJEN RORORORORORORORORORORORORORORORWType 0000000000000000Reset 0123456789101112131415 VLDOreserved RWRWRWRWRWRWRWRWROROROROROROROROType 0001100000000000Reset DescriptionResetTypeNameBit/Field Voltage Adjust Enable This bit enables the value of theVLDOfield to be used to specify the output voltage of the LDO in Sleep mode. DescriptionValue The LDO output voltage is set to the factory default value in Sleep mode. The value of theVLDOfield does not affect the LDO operation. The LDO output value in Sleep mode is configured by the value in theVLDOfield. 0RWVADJEN31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000.00ROreserved30:8 271June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field LDO Output Voltage This field provides program control of the LDO output voltage in Run mode. The value of the field is only used for the LDO voltage when the VADJENbit is set. For lowest power in Sleep mode, it is recommended to configure an LDO output voltage that is equal to or lower than the default value of 1.2 V. DescriptionValue

0.90 V0x12

0.95 V0x13

1.00 V0x14

1.05 V0x15

1.10 V0x16

1.15 V0x17

1.20 V0x18

0x18RWVLDO7:0 June 12, 2014272 Texas Instruments-Production Data System Control

Register22:LDOSleepPowerCalibration(LDOSPCAL),offset0x1B8 This register provides factory determined values that are recommended for theVLDOfield in the LDOSPCTLregister while in Sleep mode. LDO Sleep Power Calibration (LDOSPCAL) Base 0x400F.E000 Offset 0x1B8 Type RO, reset 0x0000.1818 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 NOPLLWITHPLL ROROROROROROROROROROROROROROROROType 0001100000011000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:16 Sleep with PLL The value in this field is the suggested value for theVLDOfield in the LDOSPCTLregister when using the PLL. This value provides the lowest recommended LDO output voltage for use with the PLL at the maximum specified value. 0x18ROWITHPLL15:8 Sleep without PLL The value in this field is the suggested value for theVLDOfield in the LDOSPCTLregister when not using the PLL. This value provides the lowest recommended LDO output voltage for use without the PLL. 0x18RONOPLL7:0 273June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register23:LDODeep-SleepPowerControl(LDODPCTL),offset0x1BC This register specifies the LDO output voltage while in Deep-Sleep mode. This register must be configured in Run mode before entering Deep-Sleep. Writes to theVLDObit field have no effect on the LDO output voltage, regardless of what is specified for theVADJENbit. The LDO output voltage is fixed at the recommended factory reset value. The table below shows the maximum system clock frequency and PIOSC frequency with respect to the configured LDO voltage. PIOSCMaximumSystemClockFrequencyOperatingVoltage(LDO) 16 MHz80 MHz1.2 16 MHz20 MHz0.9 Note: The LDO will not automatically adjust in Sleep/Deepsleep mode if a debugger has been connected since the last power-on reset. ■ If the LDO voltage is adjusted, it will take an extra 4 us to wake up from Sleep or Deep-Sleep mode. LDO Deep-Sleep Power Control (LDODPCTL) Base 0x400F.E000 Offset 0x1BC Type RW, reset 0x0000.0012 16171819202122232425262728293031 reservedVADJEN RORORORORORORORORORORORORORORORWType 0000000000000000Reset 0123456789101112131415 VLDOreserved RWRWRWRWRWRWRWRWROROROROROROROROType 0100100000000000Reset DescriptionResetTypeNameBit/Field Voltage Adjust Enable This bit enables the value of theVLDOfield to be used to specify the output voltage of the LDO in Deep-Sleep mode. DescriptionValue The LDO output voltage is set to the factory default value in Deep-Sleep mode. The value of theVLDOfield does not affect the LDO operation. The LDO output value in Deep-Sleep mode is configured by the value in theVLDOfield. 0RWVADJEN31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000.00ROreserved30:8 June 12, 2014274 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field LDO Output Voltage This field provides program control of the LDO output voltage in Run mode. The value of the field is only used for the LDO voltage when the VADJENbit is set. For lowest power in Deep-Sleep mode, it is recommended to configure the LDO output voltage to the default value of 0.90 V. DescriptionValue 0x12RWVLDO7:0 275June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register24:LDODeep-SleepPowerCalibration(LDODPCAL),offset0x1C0 This register provides factory determined values that are recommended for theVLDOfield in the LDODPCTLregister while in Deep-Sleep mode. LDO Deep-Sleep Power Calibration (LDODPCAL) Base 0x400F.E000 Offset 0x1C0 Type RO, reset 0x0000.1212 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 30KHZNOPLL ROROROROROROROROROROROROROROROROType 0100100001001000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:16 Deep-Sleep without PLL The value in this field is the suggested value for theVLDOfield in the LDODPCTLregister when not using the PLL. This value provides the lowest recommended LDO output voltage for use with the system clock. 0x12RONOPLL15:8 Deep-Sleep with IOSC The value in this field is the suggested value for theVLDOfield in the LDODPCTLregister when not using the PLL. This value provides the lowest recommended LDO output voltage for use with the low-frequency internal oscillator. 0x12RO30KHZ7:0 June 12, 2014276 Texas Instruments-Production Data System Control

Register25:Sleep/Deep-SleepPowerModeStatus(SDPMST),offset0x1CC This register provides status information on the Sleep and Deep-Sleep power modes as well as some real time status that can be viewed by a debugger or the core if it is running. These events do not trigger an interrupt and are meant to provide information that can help tune software for power management. The status register gets written at the beginning of every Dynamic Power Management event request with the results of any error checking. There is no mechanism to clear the bits; they are overwritten on the next event. TheLDOUA, FLASHLP, LOWPWR, PRACTbits provide real time data and there are no events to register that information. Sleep / Deep-Sleep Power Mode Status (SDPMST) Base 0x400F.E000 Offset 0x1CC Type RO, reset 0x0000.0000 16171819202122232425262728293031 PRACTLOWPWRFLASHLPLDOUAreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 SPDERRFPDERRPPDERRLDMINERRLSMINERRreservedLMAXERRPPDWreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved31:20 LDO Update Active DescriptionValue The LDO voltage level is not changing.0 The LDO voltage level is changing.1 0ROLDOUA19 Flash Memory in Low Power State DescriptionValue The Flash memory is currently in the active state.0 The Flash memory is currently in the low power state as programmed in theSLPPWRCFGor DSLPPWRCFGregister. 0ROFLASHLP18 Sleep or Deep-Sleep Mode DescriptionValue The microcontroller is currently in Run mode.0 The microcontroller is currently in Sleep or Deep-Sleep mode and is waiting for an interrupt or is in the process of powering up. The status of this bit is not affected by the power state of the Flash memory or SRAM. 0ROLOWPWR17 277June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Sleep or Deep-Sleep Power Request Active DescriptionValue A power request is not active.0 The microcontroller is currently in Deep-Sleep mode or is in Sleep mode and a request to put the SRAM and/or Flash memory into a lower power mode is currently active as configured by theSLPPWRCFGregister. 0ROPRACT16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved15:8 PIOSC Power Down Request Warning DescriptionValue No error.0 A warning has occurred because software has requested that the PIOSC be powered down during Deep-Sleep using the PIOSCPDbit in theDSLPCLKCFGregister and a peripheral requires that it be active in Deep-Sleep. The PIOSC is powered down regardless of the warning. 0ROPPDW7 VLDOValue Above Maximum Error DescriptionValue No error.0 An error has occurred because software has requested that the LDO voltage be above the maximum value allowed using the VLDObit in theLDOSPCTLor LDODPCTLregister. In this situation, the LDO is set to the factory default value. 0ROLMAXERR6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved5 VLDOValue Below Minimum Error in Sleep Mode DescriptionValue No error.0 An error has occurred because software has requested that the LDO voltage be below the minimum value allowed using the VLDObit in theLDOSPCTLregister. In this situation, the LDO voltage is not changed when entering Sleep mode. 0ROLSMINERR4 June 12, 2014278 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field VLDOValue Below Minimum Error in Deep-Sleep Mode DescriptionValue No error.0 An error has occurred because software has requested that the LDO voltage be below the minimum value allowed using the VLDObit in theLDODPCTLregister. In this situation, the LDO voltage is not changed when entering Deep-Sleep mode. 0ROLDMINERR3 PIOSC Power Down Request Error DescriptionValue No error.0 An error has occurred because software has requested that the PIOSC be powered down during Deep-Sleep and it is not possible to power down the PIOSC. In this situation, the PIOSC is not powered down when entering Deep-Sleep mode. 0ROPPDERR2 Flash Memory Power Down Request Error DescriptionValue No error.0 An error has occurred because software has requested a Flash memory power down mode that is not available using the FLASHPMfield in theSLPPWRCFGor theDSLPPWRCFG register. 0ROFPDERR1 SRAM Power Down Request Error DescriptionValue No error.0 An error has occurred because software has requested an SRAM power down mode that is not available using theSRAMPM field in theSLPPWRCFGor theDSLPPWRCFGregister. 0ROSPDERR0 279June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register26:WatchdogTimerPeripheralPresent(PPWD),offset0x300 The PPWDregister provides software information regarding the watchdog modules. Important: This register should be used to determine which watchdog timers are implemented on this microcontroller. However, to support legacy software, theDC1register is available. A read of theDC1register correctly identifies if a legacy module is present. Watchdog Timer Peripheral Present (PPWD) Base 0x400F.E000 Offset 0x300 Type RO, reset 0x0000.0003 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0P1reserved ROROROROROROROROROROROROROROROROType 1100000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 Watchdog Timer 1 Present DescriptionValue Watchdog module 1 is not present.0 Watchdog module 1 is present.1 0x1ROP11 Watchdog Timer 0 Present DescriptionValue Watchdog module 0 is not present.0 Watchdog module 0 is present.1 0x1ROP00 June 12, 2014280 Texas Instruments-Production Data System Control

Register27:16/32-BitGeneral-PurposeTimerPeripheralPresent(PPTIMER), offset0x304 The PPTIMERregister provides software information regarding the 16/32-bit general-purpose timer modules. Important: This register should be used to determine which timers are implemented on this microcontroller. However, to support legacy software, theDC2register is available. A read of theDC2register correctly identifies if a legacy module is present. Software must use this register to determine if a module that is not supported by theDC2register is present. 16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER) Base 0x400F.E000 Offset 0x304 Type RO, reset 0x0000.003F 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0P1P2P3P4P5reserved ROROROROROROROROROROROROROROROROType 1111110000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 16/32-Bit General-Purpose Timer 5 Present DescriptionValue 16/32-bit general-purpose timer module 6 is not present.0 16/32-bit general-purpose timer module 5 is present.1 0x1ROP55 16/32-Bit General-Purpose Timer 4 Present DescriptionValue 16/32-bit general-purpose timer module 4 is not present.0 16/32-bit general-purpose timer module 4 is present.1 0x1ROP44 16/32-Bit General-Purpose Timer 3 Present DescriptionValue 16/32-bit general-purpose timer module 3 is not present.0 16/32-bit general-purpose timer module 3 is present.1 0x1ROP33 281June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field 16/32-Bit General-Purpose Timer 2 Present DescriptionValue 16/32-bit general-purpose timer module 2 is not present.0 16/32-bit general-purpose timer module 2 is present.1 0x1ROP22 16/32-Bit General-Purpose Timer 1 Present DescriptionValue 16/32-bit general-purpose timer module 1 is not present.0 16/32-bit general-purpose timer module 1 is present.1 0x1ROP11 16/32-Bit General-Purpose Timer 0 Present DescriptionValue 16/32-bit general-purpose timer module 0 is not present.0 16/32-bit general-purpose timer module 0 is present.1 0x1ROP00 June 12, 2014282 Texas Instruments-Production Data System Control

Register28:General-PurposeInput/OutputPeripheralPresent(PPGPIO), offset0x308 The PPGPIOregister provides software information regarding the general-purpose input/output modules. Important: This register should be used to determine which GPIO ports are implemented on this microcontroller. However, to support legacy software, theDC4register is available. A read of theDC4register correctly identifies if a legacy module is present. Software must use this register to determine if a module that is not supported by theDC4register is present. General-Purpose Input/Output Peripheral Present (PPGPIO) Base 0x400F.E000 Offset 0x308 Type RO, reset 0x0000.03FF 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0P1P2P3P4P5P6P7P8P9P10P11P12P13P14reserved ROROROROROROROROROROROROROROROROType 1111111111000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:15 GPIO Port Q Present DescriptionValue GPIO Port Q is not present.0 GPIO Port Q is present.1 0x0ROP1414 GPIO Port P Present DescriptionValue GPIO Port P is not present.0 GPIO Port P is present.1 0x0ROP1313 GPIO Port N Present DescriptionValue GPIO Port N is not present.0 GPIO Port N is present.1 0x0ROP1212 283June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field GPIO Port M Present DescriptionValue GPIO Port M is not present.0 GPIO Port M is present.1 0x0ROP1111 GPIO Port L Present DescriptionValue GPIO Port L is not present.0 GPIO Port L is present.1 0x0ROP1010 GPIO Port K Present DescriptionValue GPIO Port K is not present.0 GPIO Port K is present.1 0x1ROP99 GPIO Port J Present DescriptionValue GPIO Port J is not present.0 GPIO Port J is present.1 0x1ROP88 GPIO Port H Present DescriptionValue GPIO Port H is not present.0 GPIO Port H is present.1 0x1ROP77 GPIO Port G Present DescriptionValue GPIO Port G is not present.0 GPIO Port G is present.1 0x1ROP66 GPIO Port F Present DescriptionValue GPIO Port F is not present.0 GPIO Port F is present.1 0x1ROP55 June 12, 2014284 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field GPIO Port E Present DescriptionValue GPIO Port E is not present.0 GPIO Port E is present.1 0x1ROP44 GPIO Port D Present DescriptionValue GPIO Port D is not present.0 GPIO Port D is present.1 0x1ROP33 GPIO Port C Present DescriptionValue GPIO Port C is not present.0 GPIO Port C is present.1 0x1ROP22 GPIO Port B Present DescriptionValue GPIO Port B is not present.0 GPIO Port B is present.1 0x1ROP11 GPIO Port A Present DescriptionValue GPIO Port A is not present.0 GPIO Port A is present.1 0x1ROP00 285June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register29:MicroDirectMemoryAccessPeripheralPresent(PPDMA),offset 0x30C The PPDMAregister provides software information regarding the μDMA module. Important: This register should be used to determine if the μDMA module is implemented on this microcontroller. However, to support legacy software, theDC7register is available. A read of theDC7register correctly identifies if the μDMA module is present. Micro Direct Memory Access Peripheral Present (PPDMA) Base 0x400F.E000 Offset 0x30C Type RO, reset 0x0000.0001 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0reserved ROROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 μDMA Module Present DescriptionValue μDMA module is not present.0 μDMA module is present.1 0x1ROP00 June 12, 2014286 Texas Instruments-Production Data System Control

Register30:HibernationPeripheralPresent(PPHIB),offset0x314 The PPHIBregister provides software information regarding the Hibernation module. Important: This register should be used to determine if the Hibernation module is implemented on this microcontroller. However, to support legacy software, theDC1register is available. A read of theDC1register correctly identifies if the Hibernation module is present. Hibernation Peripheral Present (PPHIB) Base 0x400F.E000 Offset 0x314 Type RO, reset 0x0000.0001 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0reserved ROROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 Hibernation Module Present DescriptionValue Hibernation module is not present.0 Hibernation module is present.1 0x1ROP00 287June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register31:UniversalAsynchronousReceiver/TransmitterPeripheralPresent (PPUART),offset0x318 The PPUARTregister provides software information regarding the UART modules. Important: This register should be used to determine which UART modules are implemented on this microcontroller. However, to support legacy software, theDC2register is available. A read of theDC2register correctly identifies if a legacy UART module is present. Software must use this register to determine if a module that is not supported by the DC2register is present. Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART) Base 0x400F.E000 Offset 0x318 Type RO, reset 0x0000.00FF 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0P1P2P3P4P5P6P7reserved ROROROROROROROROROROROROROROROROType 1111111100000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:8 UART Module 7 Present DescriptionValue UART module 7 is not present.0 UART module 7 is present.1 0x1ROP77 UART Module 6 Present DescriptionValue UART module 6 is not present.0 UART module 6 is present.1 0x1ROP66 UART Module 5 Present DescriptionValue UART module 5 is not present.0 UART module 5 is present.1 0x1ROP55 June 12, 2014288 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field UART Module 4 Present DescriptionValue UART module 4 is not present.0 UART module 4 is present.1 0x1ROP44 UART Module 3 Present DescriptionValue UART module 3 is not present.0 UART module 3 is present.1 0x1ROP33 UART Module 2 Present DescriptionValue UART module 2 is not present.0 UART module 2 is present.1 0x1ROP22 UART Module 1 Present DescriptionValue UART module 1 is not present.0 UART module 1 is present.1 0x1ROP11 UART Module 0 Present DescriptionValue UART module 0 is not present.0 UART module 0 is present.1 0x1ROP00 289June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register32:SynchronousSerialInterfacePeripheralPresent(PPSSI),offset 0x31C The PPSSIregister provides software information regarding the SSI modules. Important: This register should be used to determine which SSI modules are implemented on this microcontroller. However, to support legacy software, theDC2register is available. A read of theDC2register correctly identifies if a legacy SSI module is present. Software must use this register to determine if a module that is not supported by theDC2register is present. Synchronous Serial Interface Peripheral Present (PPSSI) Base 0x400F.E000 Offset 0x31C Type RO, reset 0x0000.000F 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0P1P2P3reserved ROROROROROROROROROROROROROROROROType 1111000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:4 SSI Module 3 Present DescriptionValue SSI module 3 is not present.0 SSI module 3 is present.1 0x1ROP33 SSI Module 2 Present DescriptionValue SSI module 2 is not present.0 SSI module 2 is present.1 0x1ROP22 SSI Module 1 Present DescriptionValue SSI module 1 is not present.0 SSI module 1 is present.1 0x1ROP11 June 12, 2014290 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field SSI Module 0 Present DescriptionValue SSI module 0 is not present.0 SSI module 0 is present.1 0x1ROP00 291June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register33:Inter-IntegratedCircuitPeripheralPresent(PPI2C),offset0x320 The PPI2Cregister provides software information regarding the I2C modules. Important: This register should be used to determine which I2C modules are implemented on this microcontroller. However, to support legacy software, theDC2register is available. A read of theDC2register correctly identifies if a legacy I2C module is present. Software must use this register to determine if a module that is not supported by theDC2register is present. Inter-Integrated Circuit Peripheral Present (PPI2C) Base 0x400F.E000 Offset 0x320 Type RO, reset 0x0000.003F 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0P1P2P3P4P5reserved ROROROROROROROROROROROROROROROROType 1111110000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 I2C Module 5 Present DescriptionValue I2C module 5 is not present.0 I2C module 5 is present.1 0x1ROP55 I2C Module 4 Present DescriptionValue I2C module 4 is not present.0 I2C module 4 is present.1 0x1ROP44 I2C Module 3 Present DescriptionValue I2C module 3 is not present.0 I2C module 3 is present.1 0x1ROP33 June 12, 2014292 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field I2C Module 2 Present DescriptionValue I2C module 2 is not present.0 I2C module 2 is present.1 0x1ROP22 I2C Module 1 Present DescriptionValue I2C module 1 is not present.0 I2C module 1 is present.1 0x1ROP11 I2C Module 0 Present DescriptionValue I2C module 0 is not present.0 I2C module 0 is present.1 0x1ROP00 293June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register34:UniversalSerialBusPeripheralPresent(PPUSB),offset0x328 The PPUSBregister provides software information regarding the USB module. Important: This register should be used to determine if the USB module is implemented on this microcontroller. However, to support legacy software, theDC6register is available. A read of theDC6register correctly identifies if the USB module is present. Universal Serial Bus Peripheral Present (PPUSB) Base 0x400F.E000 Offset 0x328 Type RO, reset 0x0000.0001 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0reserved ROROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 USB Module Present DescriptionValue USB module is not present.0 USB module is present.1 0x1ROP00 June 12, 2014294 Texas Instruments-Production Data System Control

Register35:ControllerAreaNetworkPeripheralPresent(PPCAN),offset0x334 The PPCANregister provides software information regarding the CAN modules. Important: This register should be used to determine which CAN modules are implemented on this microcontroller. However, to support legacy software, theDC1register is available. A read of theDC1register correctly identifies if a legacy CAN module is present. Controller Area Network Peripheral Present (PPCAN) Base 0x400F.E000 Offset 0x334 Type RO, reset 0x0000.0001 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0P1reserved ROROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 CAN Module 1 Present DescriptionValue CAN module 1 is not present.0 CAN module 1 is present.1 0x0ROP11 CAN Module 0 Present DescriptionValue CAN module 0 is not present.0 CAN module 0 is present.1 0x1ROP00 295June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register36:Analog-to-DigitalConverterPeripheralPresent(PPADC),offset 0x338 The PPADCregister provides software information regarding the ADC modules. Important: This register should be used to determine which ADC modules are implemented on this microcontroller. However, to support legacy software, theDC1register is available. A read of theDC1register correctly identifies if a legacy ADC module is present. Analog-to-Digital Converter Peripheral Present (PPADC) Base 0x400F.E000 Offset 0x338 Type RO, reset 0x0000.0003 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0P1reserved ROROROROROROROROROROROROROROROROType 1100000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 ADC Module 1 Present DescriptionValue ADC module 1 is not present.0 ADC module 1 is present.1 0x1ROP11 ADC Module 0 Present DescriptionValue ADC module 0 is not present.0 ADC module 0 is present.1 0x1ROP00 June 12, 2014296 Texas Instruments-Production Data System Control

Register37:AnalogComparatorPeripheralPresent(PPACMP),offset0x33C The PPACMPregister provides software information regarding the analog comparator module. Important: This register should be used to determine if the analog comparator module is implemented on this microcontroller. However, to support legacy software, theDC2 register is available. A read of theDC2register correctly identifies if the analog comparator module is present. Note that theAnalogComparatorPeripheralProperties(ACMPPP) register indicates how many analog comparator blocks are included in the module. Analog Comparator Peripheral Present (PPACMP) Base 0x400F.E000 Offset 0x33C Type RO, reset 0x0000.0001 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0reserved ROROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 Analog Comparator Module Present DescriptionValue Analog comparator module is not present.0 Analog comparator module is present.1 0x1ROP00 297June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register38:PulseWidthModulatorPeripheralPresent(PPPWM),offset0x340 The PPPWMregister provides software information regarding the PWM modules. Important: This register should be used to determine which PWM modules are implemented on this microcontroller. However, to support legacy software, theDC1register is available. A read of theDC1register correctly identifies if the legacy PWM module is present. Software must use this register to determine if a module that is not supported by the DC1register is present. Pulse Width Modulator Peripheral Present (PPPWM) Base 0x400F.E000 Offset 0x340 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0P1reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 PWM Module 1 Present DescriptionValue PWM module 1 is not present.0 PWM module 1 is present.1 0x0ROP11 PWM Module 0 Present DescriptionValue PWM module 0 is not present.0 PWM module 0 is present.1 0x0ROP00 June 12, 2014298 Texas Instruments-Production Data System Control

Register39:QuadratureEncoderInterfacePeripheralPresent(PPQEI),offset 0x344 The PPQEIregister provides software information regarding the QEI modules. Important: This register should be used to determine which QEI modules are implemented on this microcontroller. However, to support legacy software, theDC2register is available. A read of theDC2register correctly identifies if a legacy QEI module is present. Quadrature Encoder Interface Peripheral Present (PPQEI) Base 0x400F.E000 Offset 0x344 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0P1reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 QEI Module 1 Present DescriptionValue QEI module 1 is not present.0 QEI module 1 is present.1 0x0ROP11 QEI Module 0 Present DescriptionValue QEI module 0 is not present.0 QEI module 0 is present.1 0x0ROP00 299June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register40:EEPROMPeripheralPresent(PPEEPROM),offset0x358 The PPEEPROMregister provides software information regarding the EEPROM module. EEPROM Peripheral Present (PPEEPROM) Base 0x400F.E000 Offset 0x358 Type RO, reset 0x0000.0001 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0reserved ROROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 EEPROM Module Present DescriptionValue EEPROM module is not present.0 EEPROM module is present.1 0x1ROP00 June 12, 2014300 Texas Instruments-Production Data System Control

Register41:32/64-BitWideGeneral-PurposeTimerPeripheralPresent (PPWTIMER),offset0x35C The PPWTIMERregister provides software information regarding the 32/64-bit wide general-purpose timer modules. 32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER) Base 0x400F.E000 Offset 0x35C Type RO, reset 0x0000.003F 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 P0P1P2P3P4P5reserved ROROROROROROROROROROROROROROROROType 1111110000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 32/64-Bit Wide General-Purpose Timer 5 Present DescriptionValue 32/64-bit wide general-purpose timer module 5 is not present.0 32/64-bit wide general-purpose timer module 5 is present.1 0x1ROP55 32/64-Bit Wide General-Purpose Timer 4 Present DescriptionValue 32/64-bit wide general-purpose timer module 4 is not present.0 32/64-bit wide general-purpose timer module 4 is present.1 0x1ROP44 32/64-Bit Wide General-Purpose Timer 3 Present DescriptionValue 32/64-bit wide general-purpose timer module 3 is not present.0 32/64-bit wide general-purpose timer module 3 is present.1 0x1ROP33 32/64-Bit Wide General-Purpose Timer 2 Present DescriptionValue 32/64-bit wide general-purpose timer module 2 is not present.0 32/64-bit wide general-purpose timer module 2 is present.1 0x1ROP22 301June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field 32/64-Bit Wide General-Purpose Timer 1 Present DescriptionValue 32/64-bit wide general-purpose timer module 1 is not present.0 32/64-bit wide general-purpose timer module 1 is present.1 0x1ROP11 32/64-Bit Wide General-Purpose Timer 0 Present DescriptionValue 32/64-bit wide general-purpose timer module 0 is not present.0 32/64-bit wide general-purpose timer module 0 is present.1 0x1ROP00 June 12, 2014302 Texas Instruments-Production Data System Control

Register42:WatchdogTimerSoftwareReset(SRWD),offset0x500 The SRWDregister provides software the capability to reset the available watchdog modules. This register provides the same capability as the legacySoftwareResetControlnSRCRn registers specifically for the watchdog modules and has the same bit polarity as the correspondingSRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in theSRWDregister. While theSRWDbit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing theSRWDbit. There may be latency from the clearing of theSRWDbit to when the peripheral is ready for use. Software can check the correspondingPRWDbit to be sure. Important: This register should be used to reset the watchdog modules. To support legacy software, the SRCR0register is available. Setting a bit in theSRCR0register also resets the corresponding module. Any bits that are changed by writing to theSRCR0register can be read back correctly when reading theSRCR0register. If software uses this register to reset a legacy peripheral (such as Watchdog 1), the write causes proper operation, but the value of that bit is not reflected in theSRCR0register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Watchdog Timer Software Reset (SRWD) Base 0x400F.E000 Offset 0x500 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1reserved RWRWROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 Watchdog Timer 1 Software Reset DescriptionValue Watchdog module 1 is not reset.0 Watchdog module 1 is reset.1 0RWR11 303June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Watchdog Timer 0 Software Reset DescriptionValue Watchdog module 0 is not reset.0 Watchdog module 0 is reset.1 0RWR00 June 12, 2014304 Texas Instruments-Production Data System Control

Register43:16/32-BitGeneral-PurposeTimerSoftwareReset(SRTIMER), offset0x504 The SRTIMERregister provides software the capability to reset the available 16/32-bit timer modules. This register provides the same capability as the legacySoftwareResetControlnSRCRn registers specifically for the timer modules and has the same bit polarity as the correspondingSRCRnbits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in theSRTIMERregister. While theSRTIMERbit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing theSRTIMERbit. There may be latency from the clearing of theSRTIMERbit to when the peripheral is ready for use. Software can check the correspondingPRTIMERbit to be sure. Important: This register should be used to reset the timer modules. To support legacy software, the SRCR1register is available. Setting a bit in theSRCR1register also resets the corresponding module. Any bits that are changed by writing to theSRCR1register can be read back correctly when reading theSRCR1register. Software must use this register to reset modules that are not present in the legacy registers. If software uses this register to reset a legacy peripheral (such as Timer 1), the write causes proper operation, but the value of that bit is not reflected in theSRCR1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. 16/32-Bit General-Purpose Timer Software Reset (SRTIMER) Base 0x400F.E000 Offset 0x504 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5reserved RWRWRWRWRWRWROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 16/32-Bit General-Purpose Timer 5 Software Reset DescriptionValue 16/32-bit general-purpose timer module 5 is not reset.0 16/32-bit general-purpose timer module 5 is reset.1 0RWR55 305June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field 16/32-Bit General-Purpose Timer 4 Software Reset DescriptionValue 16/32-bit general-purpose timer module 4 is not reset.0 16/32-bit general-purpose timer module 4 is reset.1 0RWR44 16/32-Bit General-Purpose Timer 3 Software Reset DescriptionValue 16/32-bit general-purpose timer module 3 is not reset.0 16/32-bit general-purpose timer module 3 is reset.1 0RWR33 16/32-Bit General-Purpose Timer 2 Software Reset DescriptionValue 16/32-bit general-purpose timer module 2 is not reset.0 16/32-bit general-purpose timer module 2 is reset.1 0RWR22 16/32-Bit General-Purpose Timer 1 Software Reset DescriptionValue 16/32-bit general-purpose timer module 1 is not reset.0 16/32-bit general-purpose timer module 1 is reset.1 0RWR11 16/32-Bit General-Purpose Timer 0 Software Reset DescriptionValue 16/32-bit general-purpose timer module 0 is not reset.0 16/32-bit general-purpose timer module 0 is reset.1 0RWR00 June 12, 2014306 Texas Instruments-Production Data System Control

Register44:General-PurposeInput/OutputSoftwareReset(SRGPIO),offset 0x508 The SRGPIOregister provides software the capability to reset the available GPIO modules. This register provides the same capability as the legacySoftwareResetControlnSRCRn registers specifically for the GPIO modules and has the same bit polarity as the correspondingSRCRnbits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in theSRGPIOregister. While theSRGPIObit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing theSRGPIObit. There may be latency from the clearing of theSRGPIObit to when the peripheral is ready for use. Software can check the correspondingPRGPIObit to be sure. Important: This register should be used to reset the GPIO modules. To support legacy software, the SRCR2register is available. Setting a bit in theSRCR2register also resets the corresponding module. Any bits that are changed by writing to theSRCR2register can be read back correctly when reading theSRCR2register. Software must use this register to reset modules that are not present in the legacy registers. If software uses this register to reset a legacy peripheral (such as GPIO A), the write causes proper operation, but the value of that bit is not reflected in theSRCR2register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. General-Purpose Input/Output Software Reset (SRGPIO) Base 0x400F.E000 Offset 0x508 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5R6R7R8R9reserved RWRWRWRWRWRWRWRWRWRWROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:10 GPIO Port K Software Reset DescriptionValue GPIO Port K is not reset.0 GPIO Port K is reset.1 0RWR99 307June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field GPIO Port J Software Reset DescriptionValue GPIO Port J is not reset.0 GPIO Port J is reset.1 0RWR88 GPIO Port H Software Reset DescriptionValue GPIO Port H is not reset.0 GPIO Port H is reset.1 0RWR77 GPIO Port G Software Reset DescriptionValue GPIO Port G is not reset.0 GPIO Port G is reset.1 0RWR66 GPIO Port F Software Reset DescriptionValue GPIO Port F is not reset.0 GPIO Port F is reset.1 0RWR55 GPIO Port E Software Reset DescriptionValue GPIO Port E is not reset.0 GPIO Port E is reset.1 0RWR44 GPIO Port D Software Reset DescriptionValue GPIO Port D is not reset.0 GPIO Port D is reset.1 0RWR33 GPIO Port C Software Reset DescriptionValue GPIO Port C is not reset.0 GPIO Port C is reset.1 0RWR22 June 12, 2014308 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field GPIO Port B Software Reset DescriptionValue GPIO Port B is not reset.0 GPIO Port B is reset.1 0RWR11 GPIO Port A Software Reset DescriptionValue GPIO Port A is not reset.0 GPIO Port A is reset.1 0RWR00 309June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register45:MicroDirectMemoryAccessSoftwareReset(SRDMA),offset 0x50C The SRDMAregister provides software the capability to reset the available μDMA module. This register provides the same capability as the legacySoftwareResetControlnSRCRn registers specifically for the μDMA module and has the same bit polarity as the correspondingSRCRnbits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in theSRDMAregister. While theSRDMAbit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing theSRDMAbit. There may be latency from the clearing of theSRDMAbit to when the peripheral is ready for use. Software can check the correspondingPRDMAbit to be sure. Important: This register should be used to reset the μDMA module. To support legacy software, the SRCR2register is available. Setting theUDMAbit in theSRCR2register also resets the μDMA module. If theUDMAbit is set by writing to theSRCR2register, it can be read back correctly when reading theSRCR2register. If software uses this register to reset the μDMA module, the write causes proper operation, but the value of theUDMAbit is not reflected in theSRCR2register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Micro Direct Memory Access Software Reset (SRDMA) Base 0x400F.E000 Offset 0x50C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 μDMA Module Software Reset DescriptionValue μDMA module is not reset.0 μDMA module is reset.1 0RWR00 June 12, 2014310 Texas Instruments-Production Data System Control

Register46:HibernationSoftwareReset(SRHIB),offset0x514 The SRHIBregister provides software the capability to reset the available Hibernation module. This register provides the same capability as the legacySoftwareResetControlnSRCRn registers specifically for the Hibernation module and has the same bit polarity as the correspondingSRCRn bits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in theSRHIBregister. While theSRHIBbit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing theSRHIBbit. There may be latency from the clearing of theSRHIBbit to when the peripheral is ready for use. Software can check the correspondingPRHIBbit to be sure. Important: This register should be used to reset the Hibernation module. To support legacy software, the SRCR0register is available. Setting theHIBbit in theSRCR0register also resets the Hibernation module. If theHIBbit is set by writing to theSRCR0register, it can be read back correctly when reading theSRCR0register. If software uses this register to reset the Hibernation module, the write causes proper operation, but the value of the HIBbit is not reflected in the SRCR0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Hibernation Software Reset (SRHIB) Base 0x400F.E000 Offset 0x514 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 Hibernation Module Software Reset DescriptionValue Hibernation module is not reset.0 Hibernation module is reset.1 0RWR00 311June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register47:UniversalAsynchronousReceiver/TransmitterSoftwareReset (SRUART),offset0x518 The SRUARTregister provides software the capability to reset the available UART modules. This register provides the same capability as the legacySoftwareResetControlnSRCRn registers specifically for the UART modules and has the same bit polarity as the correspondingSRCRnbits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in theSRUARTregister. While theSRUARTbit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing theSRUARTbit. There may be latency from the clearing of theSRUARTbit to when the peripheral is ready for use. Software can check the correspondingPRUARTbit to be sure. Important: This register should be used to reset the UART modules. To support legacy software, the SRCR1register is available. Setting a bit in theSRCR1register also resets the corresponding module. Any bits that are changed by writing to theSRCR1register can be read back correctly when reading theSRCR1register. Software must use this register to reset modules that are not present in the legacy registers. If software uses this register to reset a legacy peripheral (such as UART0), the write causes proper operation, but the value of that bit is not reflected in theSRCR1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Asynchronous Receiver/Transmitter Software Reset (SRUART) Base 0x400F.E000 Offset 0x518 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5R6R7reserved RWRWRWRWRWRWRWRWROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:8 UART Module 7 Software Reset DescriptionValue UART module 7 is not reset.0 UART module 7 is reset.1 0RWR77 June 12, 2014312 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field UART Module 6 Software Reset DescriptionValue UART module 6 is not reset.0 UART module 6 is reset.1 0RWR66 UART Module 5 Software Reset DescriptionValue UART module 5 is not reset.0 UART module 5 is reset.1 0RWR55 UART Module 4 Software Reset DescriptionValue UART module 4 is not reset.0 UART module 4 is reset.1 0RWR44 UART Module 3 Software Reset DescriptionValue UART module 3 is not reset.0 UART module 3 is reset.1 0RWR33 UART Module 2 Software Reset DescriptionValue UART module 2 is not reset.0 UART module 2 is reset.1 0RWR22 UART Module 1 Software Reset DescriptionValue UART module 1 is not reset.0 UART module 1 is reset.1 0RWR11 UART Module 0 Software Reset DescriptionValue UART module 0 is not reset.0 UART module 0 is reset.1 0RWR00 313June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register48:SynchronousSerialInterfaceSoftwareReset(SRSSI),offset 0x51C The SRSSIregister provides software the capability to reset the available SSI modules. This register provides the same capability as the legacySoftwareResetControlnSRCRn registers specifically for the SSI modules and has the same bit polarity as the correspondingSRCRnbits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in theSRSSIregister. While theSRSSIbit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing theSRSSIbit. There may be latency from the clearing of theSRSSIbit to when the peripheral is ready for use. Software can check the correspondingPRSSIbit to be sure. Important: This register should be used to reset the SSI modules. To support legacy software, the SRCR1register is available. Setting a bit in theSRCR1register also resets the corresponding module. Any bits that are changed by writing to theSRCR1register can be read back correctly when reading theSRCR1register. Software must use this register to reset modules that are not present in the legacy registers. If software uses this register to reset a legacy peripheral (such as SSI0), the write causes proper operation, but the value of that bit is not reflected in theSRCR1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Synchronous Serial Interface Software Reset (SRSSI) Base 0x400F.E000 Offset 0x51C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3reserved RWRWRWRWROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:4 SSI Module 3 Software Reset DescriptionValue SSI module 3 is not reset.0 SSI module 3 is reset.1 0RWR33 June 12, 2014314 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field SSI Module 2 Software Reset DescriptionValue SSI module 2 is not reset.0 SSI module 2 is reset.1 0RWR22 SSI Module 1 Software Reset DescriptionValue SSI module 1 is not reset.0 SSI module 1 is reset.1 0RWR11 SSI Module 0 Software Reset DescriptionValue SSI module 0 is not reset.0 SSI module 0 is reset.1 0RWR00 315June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register49:Inter-IntegratedCircuitSoftwareReset(SRI2C),offset0x520 The SRI2Cregister provides software the capability to reset the available I2C modules. This register provides the same capability as the legacySoftwareResetControlnSRCRn registers specifically for the I2C modules and has the same bit polarity as the correspondingSRCRnbits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in theSRI2Cregister. While theSRI2Cbit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing theSRI2Cbit. There may be latency from the clearing of theSRI2Cbit to when the peripheral is ready for use. Software can check the correspondingPRI2Cbit to be sure. Important: This register should be used to reset the I2C modules. To support legacy software, the SRCR1register is available. Setting a bit in theSRCR1register also resets the corresponding module. Any bits that are changed by writing to theSRCR1register can be read back correctly when reading theSRCR1register. Software must use this register to reset modules that are not present in the legacy registers. If software uses this register to reset a legacy peripheral (such as I2C0), the write causes proper operation, but the value of that bit is not reflected in theSRCR1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Inter-Integrated Circuit Software Reset (SRI2C) Base 0x400F.E000 Offset 0x520 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5reserved RWRWRWRWRWRWROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 I2C Module 5 Software Reset DescriptionValue I2C module 5 is not reset.0 I2C module 5 is reset.1 0RWR55 June 12, 2014316 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field I2C Module 4 Software Reset DescriptionValue I2C module 4 is not reset.0 I2C module 4 is reset.1 0RWR44 I2C Module 3 Software Reset DescriptionValue I2C module 3 is not reset.0 I2C module 3 is reset.1 0RWR33 I2C Module 2 Software Reset DescriptionValue I2C module 2 is not reset.0 I2C module 2 is reset.1 0RWR22 I2C Module 1 Software Reset DescriptionValue I2C module 1 is not reset.0 I2C module 1 is reset.1 0RWR11 I2C Module 0 Software Reset DescriptionValue I2C module 0 is not reset.0 I2C module 0 is reset.1 0RWR00 317June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register50:UniversalSerialBusSoftwareReset(SRUSB),offset0x528 The SRUSBregister provides software the capability to reset the available USB module. This register provides the same capability as the legacySoftwareResetControlnSRCRn registers specifically for the USB module and has the same bit polarity as the correspondingSRCRnbits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in theSRUSBregister. While theSRUSBbit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing theSRUSBbit. There may be latency from the clearing of theSRUSBbit to when the peripheral is ready for use. Software can check the correspondingPRUSBbit to be sure. Important: This register should be used to reset the USB module. To support legacy software, the SRCR2register is available. Setting theUSB0bit in theSRCR2register also resets the USB module. If theUSB0bit is set by writing to theSRCR2register, it can be read back correctly when reading theSRCR2register. If software uses this register to reset the USB module, the write causes proper operation, but the value of theUSB0bit is not reflected in theSRCR2register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Serial Bus Software Reset (SRUSB) Base 0x400F.E000 Offset 0x528 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 USB Module Software Reset DescriptionValue USB module is not reset.0 USB module is reset.1 0RWR00 June 12, 2014318 Texas Instruments-Production Data System Control

Register51:ControllerAreaNetworkSoftwareReset(SRCAN),offset0x534 The SRCANregister provides software the capability to reset the available CAN modules. This register provides the same capability as the legacySoftwareResetControlnSRCRn registers specifically for the CAN modules and has the same bit polarity as the correspondingSRCRnbits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in theSRCANregister. While theSRCANbit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing theSRCANbit. There may be latency from the clearing of theSRCANbit to when the peripheral is ready for use. Software can check the correspondingPRCANbit to be sure. Important: This register should be used to reset the CAN modules. To support legacy software, the SRCR0register is available. Setting a bit in theSRCR0register also resets the corresponding module. Any bits that are changed by writing to theSRCR0register can be read back correctly when reading the SRCR0 register. If software uses this register to reset a legacy peripheral (such as CAN0), the write causes proper operation, but the value of that bit is not reflected in theSRCR0register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Controller Area Network Software Reset (SRCAN) Base 0x400F.E000 Offset 0x534 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 CAN Module 0 Software Reset DescriptionValue CAN module 0 is not reset.0 CAN module 0 is reset.1 0RWR00 319June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register52:Analog-to-DigitalConverterSoftwareReset(SRADC),offset0x538 The SRADCregister provides software the capability to reset the available ADC modules. This register provides the same capability as the legacySoftwareResetControlnSRCRn registers specifically for the ADC modules and has the same bit polarity as the correspondingSRCRnbits. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in theSRADCregister. While theSRADCbit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing theSRADCbit. There may be latency from the clearing of theSRADCbit to when the peripheral is ready for use. Software can check the correspondingPRADCbit to be sure. Important: This register should be used to reset the ADC modules. To support legacy software, the SRCR0register is available. Setting a bit in theSRCR0register also resets the corresponding module. Any bits that are changed by writing to theSRCR0register can be read back correctly when reading theSRCR0register. If software uses this register to reset a legacy peripheral (such as ADC0), the write causes proper operation, but the value of that bit is not reflected in theSRCR0register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog-to-Digital Converter Software Reset (SRADC) Base 0x400F.E000 Offset 0x538 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1reserved RWRWROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 ADC Module 1 Software Reset DescriptionValue ADC module 1 is not reset.0 ADC module 1 is reset.1 0RWR11 June 12, 2014320 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field ADC Module 0 Software Reset DescriptionValue ADC module 0 is not reset.0 ADC module 0 is reset.1 0RWR00 321June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register53:AnalogComparatorSoftwareReset(SRACMP),offset0x53C The SRACMPregister provides software the capability to reset the available analog comparator module. This register provides the same capability as the legacySoftwareResetControlnSRCRn registers specifically for the analog comparator module and has the same bit polarity as the corresponding SRCRnbits. A block is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in theSRACMPregister. While theSRACMPbit is 1, the module is held in reset. 2. Software completes the reset process by clearing theSRACMPbit. There may be latency from the clearing of theSRACMPbit to when the module is ready for use. Software can check the correspondingPRACMPbit to be sure. Important: This register should be used to reset the analog comparator module. To support legacy software, theSRCR1register is available. Setting any of theCOMPnbits in theSRCR0 register also resets the analog comparator module. If any of theCOMPnbits are set by writing to theSRCR1register, it can be read back correctly when reading theSRCR0 register. If software uses this register to reset the analog comparator module, the write causes proper operation, but the value ofR0is not reflected by theCOMPnbits in the SRCR1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog Comparator Software Reset (SRACMP) Base 0x400F.E000 Offset 0x53C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 Analog Comparator Module 0 Software Reset DescriptionValue Analog comparator module is not reset.0 Analog comparator module is reset.1 0RWR00 June 12, 2014322 Texas Instruments-Production Data System Control

Register54:EEPROMSoftwareReset(SREEPROM),offset0x558 The SREEPROMregister provides software the capability to reset the available EEPROM module. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in theSREEPROMregister. While theSREEPROMbit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing theSREEPROMbit. There may be latency from the clearing of theSREEPROMbit to when the peripheral is ready for use. Software can check the correspondingPREEPROMbit to be sure. EEPROM Software Reset (SREEPROM) Base 0x400F.E000 Offset 0x558 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 EEPROM Module Software Reset DescriptionValue EEPROM module is not reset.0 EEPROM module is reset.1 0RWR00 323June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register55:32/64-BitWideGeneral-PurposeTimerSoftwareReset (SRWTIMER),offset0x55C The SRWTIMERregister provides software the capability to reset the available 32/64-bit wide timer modules. A peripheral is reset by software using a simple two-step process: 1. Software sets a bit (or bits) in theSRWTIMERregister. While theSRWTIMERbit is 1, the peripheral is held in reset. 2. Software completes the reset process by clearing theSRWTIMERbit. There may be latency from the clearing of theSRWTIMERbit to when the peripheral is ready for use. Software can check the correspondingPRWTIMERbit to be sure. 32/64-Bit Wide General-Purpose Timer Software Reset (SRWTIMER) Base 0x400F.E000 Offset 0x55C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5reserved RWRWRWRWRWRWROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 32/64-Bit Wide General-Purpose Timer 5 Software Reset DescriptionValue 32/64-bit wide general-purpose timer module 5 is not reset.0 32/64-bit wide general-purpose timer module 5 is reset.1 0RWR55 32/64-Bit Wide General-Purpose Timer 4 Software Reset DescriptionValue 32/64-bit wide general-purpose timer module 4 is not reset.0 32/64-bit wide general-purpose timer module 4 is reset.1 0RWR44 32/64-Bit Wide General-Purpose Timer 3 Software Reset DescriptionValue 32/64-bit wide general-purpose timer module 3 is not reset.0 32/64-bit wide general-purpose timer module 3 is reset.1 0RWR33 June 12, 2014324 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field 32/64-Bit Wide General-Purpose Timer 2 Software Reset DescriptionValue 32/64-bit wide general-purpose timer module 2 is not reset.0 32/64-bit wide general-purpose timer module 2 is reset.1 0RWR22 32/64-Bit Wide General-Purpose Timer 1 Software Reset DescriptionValue 32/64-bit wide general-purpose timer module 1 is not reset.0 32/64-bit wide general-purpose timer module 1 is reset.1 0RWR11 32/64-Bit Wide General-Purpose Timer 0 Software Reset DescriptionValue 32/64-bit wide general-purpose timer module 0 is not reset.0 32/64-bit wide general-purpose timer module 0 is reset.1 0RWR00 325June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register56:WatchdogTimerRunModeClockGatingControl(RCGCWD), offset0x600 The RCGCWDregister provides software the capability to enable and disable watchdog modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacyRunModeClock GatingControlRegisternRCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingRCGCnbits. Important: This register should be used to control the clocking for the watchdog modules. To support legacy software, theRCGC0register is available. A write to theRCGC0register also writes the corresponding bit in this register. Any bits that are changed by writing to theRCGC0register can be read back correctly with a read of theRCGC0register. If software uses this register to write a legacy peripheral (such as Watchdog 0), the write causes proper operation, but the value of that bit is not reflected in theRCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Watchdog Timer Run Mode Clock Gating Control (RCGCWD) Base 0x400F.E000 Offset 0x600 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1reserved RWRWROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 Watchdog Timer 1 Run Mode Clock Gating Control DescriptionValue Watchdog module 1 is disabled.0 Enable and provide a clock to Watchdog module 1 in Run mode.1 0RWR11 Watchdog Timer 0 Run Mode Clock Gating Control DescriptionValue Watchdog module 0 is disabled.0 Enable and provide a clock to Watchdog module 0 in Run mode.1 0RWR00 June 12, 2014326 Texas Instruments-Production Data System Control

Register57:16/32-BitGeneral-PurposeTimerRunModeClockGatingControl (RCGCTIMER),offset0x604 The RCGCTIMERregister provides software the capability to enable and disable 16/32-bit timer modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacyRunModeClock GatingControlRegisternRCGCn registers specifically for the timer modules and has the same bit polarity as the correspondingRCGCnbits. Important: This register should be used to control the clocking for the timer modules. To support legacy software, theRCGC1register is available. A write to theRCGC1register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC1register can be read back correctly with a read of theRCGC1register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as Timer 0), the write causes proper operation, but the value of that bit is not reflected in theRCGC1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER) Base 0x400F.E000 Offset 0x604 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5reserved RWRWRWRWRWRWROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 5 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 5 in Run mode. 0RWR55 327June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field 16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 4 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 4 in Run mode. 0RWR44 16/32-Bit General-Purpose Timer 3 Run Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 3 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 3 in Run mode. 0RWR33 16/32-Bit General-Purpose Timer 2 Run Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 2 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 2 in Run mode. 0RWR22 16/32-Bit General-Purpose Timer 1 Run Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 1 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 1 in Run mode. 0RWR11 16/32-Bit General-Purpose Timer 0 Run Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 0 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 0 in Run mode. 0RWR00 June 12, 2014328 Texas Instruments-Production Data System Control

Register58:General-PurposeInput/OutputRunModeClockGatingControl (RCGCGPIO),offset0x608 The RCGCGPIOregister provides software the capability to enable and disable GPIO modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacyRunModeClock GatingControlRegisternRCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingRCGCnbits. Important: This register should be used to control the clocking for the GPIO modules. To support legacy software, theRCGC2register is available. A write to theRCGC2register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC2register can be read back correctly with a read of theRCGC2register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as GPIO A), the write causes proper operation, but the value of that bit is not reflected in theRCGC2register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO) Base 0x400F.E000 Offset 0x608 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5R6R7R8R9reserved RWRWRWRWRWRWRWRWRWRWROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:10 GPIO Port K Run Mode Clock Gating Control DescriptionValue GPIO Port K is disabled.0 Enable and provide a clock to GPIO Port K in Run mode.1 0RWR99 GPIO Port J Run Mode Clock Gating Control DescriptionValue GPIO Port J is disabled.0 Enable and provide a clock to GPIO Port J in Run mode.1 0RWR88 329June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field GPIO Port H Run Mode Clock Gating Control DescriptionValue GPIO Port H is disabled.0 Enable and provide a clock to GPIO Port H in Run mode.1 0RWR77 GPIO Port G Run Mode Clock Gating Control DescriptionValue GPIO Port G is disabled.0 Enable and provide a clock to GPIO Port G in Run mode.1 0RWR66 GPIO Port F Run Mode Clock Gating Control DescriptionValue GPIO Port F is disabled.0 Enable and provide a clock to GPIO Port F in Run mode.1 0RWR55 GPIO Port E Run Mode Clock Gating Control DescriptionValue GPIO Port E is disabled.0 Enable and provide a clock to GPIO Port E in Run mode.1 0RWR44 GPIO Port D Run Mode Clock Gating Control DescriptionValue GPIO Port D is disabled.0 Enable and provide a clock to GPIO Port D in Run mode.1 0RWR33 GPIO Port C Run Mode Clock Gating Control DescriptionValue GPIO Port C is disabled.0 Enable and provide a clock to GPIO Port C in Run mode.1 0RWR22 GPIO Port B Run Mode Clock Gating Control DescriptionValue GPIO Port B is disabled.0 Enable and provide a clock to GPIO Port B in Run mode.1 0RWR11 June 12, 2014330 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field GPIO Port A Run Mode Clock Gating Control DescriptionValue GPIO Port A is disabled.0 Enable and provide a clock to GPIO Port A in Run mode.1 0RWR00 331June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register59:MicroDirectMemoryAccessRunModeClockGatingControl (RCGCDMA),offset0x60C The RCGCDMAregister provides software the capability to enable and disable the μDMA module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacyRunModeClock GatingControlRegisternRCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingRCGCnbits. Important: This register should be used to control the clocking for the μDMA module. To support legacy software, theRCGC2register is available. A write to theUDMAbit in theRCGC2 register also writes theR0bit in this register. If theUDMAbit is changed by writing to the RCGC2register, it can be read back correctly with a read of theRCGC2register. If software uses this register to control the clock for the μDMA module, the write causes proper operation, but theUDMAbit in theRCGC2register does not reflect the value of the R0bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA) Base 0x400F.E000 Offset 0x60C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 μDMA Module Run Mode Clock Gating Control DescriptionValue μDMA module is disabled.0 Enable and provide a clock to the μDMA module in Run mode.1 0RWR00 June 12, 2014332 Texas Instruments-Production Data System Control

Register60:HibernationRunModeClockGatingControl(RCGCHIB),offset 0x614 The RCGCHIBregister provides software the capability to enable and disable the Hibernation module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacyRunMode ClockGatingControlRegisternRCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingRCGCnbits. Important: This register should be used to control the clocking for the Hibernation module. To support legacy software, theRCGC0register is available. A write to theHIBbit in the RCGC0register also writes theR0bit in this register. If theHIBbit is changed by writing to theRCGC0register, it can be read back correctly with a read of theRCGC0register. If software uses this register to control the clock for the Hibernation module, the write causes proper operation, but theHIBbit in theRCGC0register does not reflect the value of theR0bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Hibernation Run Mode Clock Gating Control (RCGCHIB) Base 0x400F.E000 Offset 0x614 Type RW, reset 0x0000.0001 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved RWROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 Hibernation Module Run Mode Clock Gating Control DescriptionValue Hibernation module is disabled.0 Enable and provide a clock to the Hibernation module in Run mode. 1RWR00 333June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register61:UniversalAsynchronousReceiver/TransmitterRunModeClock GatingControl(RCGCUART),offset0x618 The RCGCUARTregister provides software the capability to enable and disable the UART modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacyRunModeClock GatingControlRegisternRCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingRCGCnbits. Important: This register should be used to control the clocking for the UART modules. To support legacy software, theRCGC1register is available. A write to theRCGC1register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC1register can be read back correctly with a read of theRCGC1register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as UART0), the write causes proper operation, but the value of that bit is not reflected in theRCGC1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART) Base 0x400F.E000 Offset 0x618 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5R6R7reserved RWRWRWRWRWRWRWRWROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:8 UART Module 7 Run Mode Clock Gating Control DescriptionValue UART module 7 is disabled.0 Enable and provide a clock to UART module 7 in Run mode.1 0RWR77 UART Module 6 Run Mode Clock Gating Control DescriptionValue UART module 6 is disabled.0 Enable and provide a clock to UART module 6 in Run mode.1 0RWR66 June 12, 2014334 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field UART Module 5 Run Mode Clock Gating Control DescriptionValue UART module 5 is disabled.0 Enable and provide a clock to UART module 5 in Run mode.1 0RWR55 UART Module 4 Run Mode Clock Gating Control DescriptionValue UART module 4 is disabled.0 Enable and provide a clock to UART module 4 in Run mode.1 0RWR44 UART Module 3 Run Mode Clock Gating Control DescriptionValue UART module 3 is disabled.0 Enable and provide a clock to UART module 3 in Run mode.1 0RWR33 UART Module 2 Run Mode Clock Gating Control DescriptionValue UART module 2 is disabled.0 Enable and provide a clock to UART module 2 in Run mode.1 0RWR22 UART Module 1 Run Mode Clock Gating Control DescriptionValue UART module 1 is disabled.0 Enable and provide a clock to UART module 1 in Run mode.1 0RWR11 UART Module 0 Run Mode Clock Gating Control DescriptionValue UART module 0 is disabled.0 Enable and provide a clock to UART module 0 in Run mode.1 0RWR00 335June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register62:SynchronousSerialInterfaceRunModeClockGatingControl (RCGCSSI),offset0x61C The RCGCSSIregister provides software the capability to enable and disable the SSI modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacyRunModeClock GatingControlRegisternRCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingRCGCnbits. Important: This register should be used to control the clocking for the SSI modules. To support legacy software, theRCGC1register is available. A write to theRCGC1register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC1register can be read back correctly with a read of theRCGC1register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as SSI0), the write causes proper operation, but the value of that bit is not reflected in theRCGC1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI) Base 0x400F.E000 Offset 0x61C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3reserved RWRWRWRWROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:4 SSI Module 3 Run Mode Clock Gating Control DescriptionValue SSI module 3 is disabled.0 Enable and provide a clock to SSI module 3 in Run mode.1 0RWR33 SSI Module 2 Run Mode Clock Gating Control DescriptionValue SSI module 2 is disabled.0 Enable and provide a clock to SSI module 2 in Run mode.1 0RWR22 June 12, 2014336 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field SSI Module 1 Run Mode Clock Gating Control DescriptionValue SSI module 1 is disabled.0 Enable and provide a clock to SSI module 1 in Run mode.1 0RWR11 SSI Module 0 Run Mode Clock Gating Control DescriptionValue SSI module 0 is disabled.0 Enable and provide a clock to SSI module 0 in Run mode.1 0RWR00 337June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register63:Inter-IntegratedCircuitRunModeClockGatingControl (RCGCI2C),offset0x620 The RCGCI2Cregister provides software the capability to enable and disable the I2C modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacyRunModeClock GatingControlRegisternRCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingRCGCnbits. Important: This register should be used to control the clocking for the I2C modules. To support legacy software, theRCGC1register is available. A write to theRCGC1register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC1register can be read back correctly with a read of theRCGC1register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as I2C0), the write causes proper operation, but the value of that bit is not reflected in theRCGC1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C) Base 0x400F.E000 Offset 0x620 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5reserved RWRWRWRWRWRWROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 I2C Module 5 Run Mode Clock Gating Control DescriptionValue I2C module 5 is disabled.0 Enable and provide a clock to I2C module 5 in Run mode.1 0RWR55 I2C Module 4 Run Mode Clock Gating Control DescriptionValue I2C module 4 is disabled.0 Enable and provide a clock to I2C module 4 in Run mode.1 0RWR44 June 12, 2014338 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field I2C Module 3 Run Mode Clock Gating Control DescriptionValue I2C module 3 is disabled.0 Enable and provide a clock to I2C module 3 in Run mode.1 0RWR33 I2C Module 2 Run Mode Clock Gating Control DescriptionValue I2C module 2 is disabled.0 Enable and provide a clock to I2C module 2 in Run mode.1 0RWR22 I2C Module 1 Run Mode Clock Gating Control DescriptionValue I2C module 1 is disabled.0 Enable and provide a clock to I2C module 1 in Run mode.1 0RWR11 I2C Module 0 Run Mode Clock Gating Control DescriptionValue I2C module 0 is disabled.0 Enable and provide a clock to I2C module 0 in Run mode.1 0RWR00 339June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register64:UniversalSerialBusRunModeClockGatingControl(RCGCUSB), offset0x628 The RCGCUSBregister provides software the capability to enable and disable the USB module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacyRunModeClock GatingControlRegisternRCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingRCGCnbits. Important: This register should be used to control the clocking for the USB module. To support legacy software, theRCGC2register is available. A write to theUSB0bit in theRCGC2 register also writes theR0bit in this register. If theUSB0bit is changed by writing to the RCGC2register, it can be read back correctly with a read of theRCGC2register. If software uses this register to control the clock for the USB module, the write causes proper operation, but theUSB0bit in theRCGC2register does not reflect the value of the R0bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Serial Bus Run Mode Clock Gating Control (RCGCUSB) Base 0x400F.E000 Offset 0x628 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 USB Module Run Mode Clock Gating Control DescriptionValue USB module is disabled.0 Enable and provide a clock to the USB module in Run mode.1 0RWR00 June 12, 2014340 Texas Instruments-Production Data System Control

Register65:ControllerAreaNetworkRunModeClockGatingControl (RCGCCAN),offset0x634 The RCGCCANregister provides software the capability to enable and disable the CAN modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacyRunModeClock GatingControlRegisternRCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingRCGCnbits. Important: This register should be used to control the clocking for the CAN modules. To support legacy software, the RCGC0 register is available. A write to the RCGC0 register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC0 register can be read back correctly with a read of the RCGC0 register. If software uses this register to write a legacy peripheral (such as CAN0), the write causes proper operation, but the value of that bit is not reflected in the RCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Controller Area Network Run Mode Clock Gating Control (RCGCCAN) Base 0x400F.E000 Offset 0x634 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 CAN Module 0 Run Mode Clock Gating Control DescriptionValue CAN module 0 is disabled.0 Enable and provide a clock to CAN module 0 in Run mode.1 0RWR00 341June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register66:Analog-to-DigitalConverterRunModeClockGatingControl (RCGCADC),offset0x638 The RCGCADCregister provides software the capability to enable and disable the ADC modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacyRunModeClock GatingControlRegisternRCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingRCGCnbits. Important: This register should be used to control the clocking for the ADC modules. To support legacy software, the RCGC0 register is available. A write to the RCGC0 register also writes the corresponding bit in this register. Any bits that are changed by writing to the RCGC0 register can be read back correctly with a read of the RCGC0 register. If software uses this register to write a legacy peripheral (such as ADC0), the write causes proper operation, but the value of that bit is not reflected in the RCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC) Base 0x400F.E000 Offset 0x638 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1reserved RWRWROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 ADC Module 1 Run Mode Clock Gating Control DescriptionValue ADC module 1 is disabled.0 Enable and provide a clock to ADC module 1 in Run mode.1 0RWR11 ADC Module 0 Run Mode Clock Gating Control DescriptionValue ADC module 0 is disabled.0 Enable and provide a clock to ADC module 0 in Run mode.1 0RWR00 June 12, 2014342 Texas Instruments-Production Data System Control

Register67:AnalogComparatorRunModeClockGatingControl (RCGCACMP),offset0x63C The RCGCACMPregister provides software the capability to enable and disable the analog comparator module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacyRun ModeClockGatingControlRegisternRCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingRCGCnbits. Important: This register should be used to control the clocking for the analog comparator module. To support legacy software, the RCGC1 register is available. Setting any of theCOMPn bits in the RCGC1 register also sets theR0bit in this register. If any of theCOMPnbits are set by writing to the RCGC1 register, it can be read back correctly when reading the RCGC1 register. If software uses this register to change the clocking for the analog comparator module, the write causes proper operation, but the valueR0is not reflected by theCOMPnbits in the RCGC1 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog Comparator Run Mode Clock Gating Control (RCGCACMP) Base 0x400F.E000 Offset 0x63C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 Analog Comparator Module 0 Run Mode Clock Gating Control DescriptionValue Analog comparator module is disabled.0 Enable and provide a clock to the analog comparator module in Run mode. 0RWR00 343June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register68:EEPROMRunModeClockGatingControl(RCGCEEPROM),offset 0x658 The RCGCEEPROMregister provides software the capability to enable and disable the EEPROM module in Run mode. When enabled, the module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. EEPROM Run Mode Clock Gating Control (RCGCEEPROM) Base 0x400F.E000 Offset 0x658 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 EEPROM Module Run Mode Clock Gating Control DescriptionValue EEPROM module is disabled.0 Enable and provide a clock to the EEPROM module in Run mode. 0RWR00 June 12, 2014344 Texas Instruments-Production Data System Control

Register69:32/64-BitWideGeneral-PurposeTimerRunModeClockGating Control(RCGCWTIMER),offset0x65C The RCGCWTIMERregister provides software the capability to enable and disable 3264-bit timer modules in Run mode. When enabled, a module is provided a clock and accesses to module registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. This register provides the same capability as the legacyRunModeClock GatingControlRegisternRCGCn registers specifically for the timer modules and has the same bit polarity as the correspondingRCGCnbits. 32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control (RCGCWTIMER) Base 0x400F.E000 Offset 0x65C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5reserved RWRWRWRWRWRWROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 32/64-Bit Wide General-Purpose Timer 5 Run Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 5 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 5 in Run mode. 0RWR55 32/64-Bit Wide General-Purpose Timer 4 Run Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 4 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 4 in Run mode. 0RWR44 32/64-Bit Wide General-Purpose Timer 3 Run Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 3 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 3 in Run mode. 0RWR33 345June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field 32/64-Bit Wide General-Purpose Timer 2 Run Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 2 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 2 in Run mode. 0RWR22 32/64-Bit Wide General-Purpose Timer 1 Run Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 1 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 1 in Run mode. 0RWR11 32/64-Bit Wide General-Purpose Timer 0 Run Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 0 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 0 in Run mode. 0RWR00 June 12, 2014346 Texas Instruments-Production Data System Control

Register70:WatchdogTimerSleepModeClockGatingControl(SCGCWD), offset0x700 The SCGCWDregister provides software the capability to enable and disable watchdog modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacySleepModeClockGating ControlRegisternSCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingSCGCnbits. Important: This register should be used to control the clocking for the watchdog modules. To support legacy software, theSCGC0register is available. A write to theSCGC0register also writes the corresponding bit in this register. Any bits that are changed by writing to theSCGC0register can be read back correctly with a read of theSCGC0register. If software uses this register to write a legacy peripheral (such as Watchdog 0), the write causes proper operation, but the value of that bit is not reflected in theSCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD) Base 0x400F.E000 Offset 0x700 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 S0S1reserved RWRWROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 Watchdog Timer 1 Sleep Mode Clock Gating Control DescriptionValue Watchdog module 1 is disabled.0 Enable and provide a clock to Watchdog module 1 in sleep mode. 0RWS11 Watchdog Timer 0 Sleep Mode Clock Gating Control DescriptionValue Watchdog module 0 is disabled.0 Enable and provide a clock to Watchdog module 0 in sleep mode. 0RWS00 347June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register71:16/32-BitGeneral-PurposeTimerSleepModeClockGatingControl (SCGCTIMER),offset0x704 The SCGCTIMERregister provides software the capability to enable and disable 16/32-bit timer modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacySleepModeClock GatingControlRegisternSCGCn registers specifically for the timer modules and has the same bit polarity as the correspondingSCGCnbits. Important: This register should be used to control the clocking for the timer modules. To support legacy software, theSCGC1register is available. A write to theSCGC1register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC1register can be read back correctly with a read of theSCGC1register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as Timer 0), the write causes proper operation, but the value of that bit is not reflected in theSCGC1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER) Base 0x400F.E000 Offset 0x704 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 S0S1S2S3S4S5reserved RWRWRWRWRWRWROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 16/32-Bit General-Purpose Timer 5 Sleep Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 5 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 5 in sleep mode. 0RWS55 16/32-Bit General-Purpose Timer 4 Sleep Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 4 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 4 in sleep mode. 0RWS44 June 12, 2014348 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field 16/32-Bit General-Purpose Timer 3 Sleep Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 3 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 3 in sleep mode. 0RWS33 16/32-Bit General-Purpose Timer 2 Sleep Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 2 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 2 in sleep mode. 0RWS22 16/32-Bit General-Purpose Timer 1 Sleep Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 1 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 1 in sleep mode. 0RWS11 16/32-Bit General-Purpose Timer 0 Sleep Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 0 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 0 in sleep mode. 0RWS00 349June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register72:General-PurposeInput/OutputSleepModeClockGatingControl (SCGCGPIO),offset0x708 The SCGCGPIOregister provides software the capability to enable and disable GPIO modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacySleepModeClockGating ControlRegisternSCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingSCGCnbits. Important: This register should be used to control the clocking for the GPIO modules. To support legacy software, theSCGC2register is available. A write to theSCGC2register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC2register can be read back correctly with a read of theSCGC2register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as GPIO A), the write causes proper operation, but the value of that bit is not reflected in theSCGC2register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO) Base 0x400F.E000 Offset 0x708 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 S0S1S2S3S4S5S6S7S8S9reserved RWRWRWRWRWRWRWRWRWRWROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:10 GPIO Port K Sleep Mode Clock Gating Control DescriptionValue GPIO Port K is disabled.0 Enable and provide a clock to GPIO Port K in sleep mode.1 0RWS99 GPIO Port J Sleep Mode Clock Gating Control DescriptionValue GPIO Port J is disabled.0 Enable and provide a clock to GPIO Port J in sleep mode.1 0RWS88 June 12, 2014350 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field GPIO Port H Sleep Mode Clock Gating Control DescriptionValue GPIO Port H is disabled.0 Enable and provide a clock to GPIO Port H in sleep mode.1 0RWS77 GPIO Port G Sleep Mode Clock Gating Control DescriptionValue GPIO Port G is disabled.0 Enable and provide a clock to GPIO Port G in sleep mode.1 0RWS66 GPIO Port F Sleep Mode Clock Gating Control DescriptionValue GPIO Port F is disabled.0 Enable and provide a clock to GPIO Port F in sleep mode.1 0RWS55 GPIO Port E Sleep Mode Clock Gating Control DescriptionValue GPIO Port E is disabled.0 Enable and provide a clock to GPIO Port E in sleep mode.1 0RWS44 GPIO Port D Sleep Mode Clock Gating Control DescriptionValue GPIO Port D is disabled.0 Enable and provide a clock to GPIO Port D in sleep mode.1 0RWS33 GPIO Port C Sleep Mode Clock Gating Control DescriptionValue GPIO Port C is disabled.0 Enable and provide a clock to GPIO Port C in sleep mode.1 0RWS22 GPIO Port B Sleep Mode Clock Gating Control DescriptionValue GPIO Port B is disabled.0 Enable and provide a clock to GPIO Port B in sleep mode.1 0RWS11 351June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field GPIO Port A Sleep Mode Clock Gating Control DescriptionValue GPIO Port A is disabled.0 Enable and provide a clock to GPIO Port A in sleep mode.1 0RWS00 June 12, 2014352 Texas Instruments-Production Data System Control

Register73:MicroDirectMemoryAccessSleepModeClockGatingControl (SCGCDMA),offset0x70C The SCGCDMAregister provides software the capability to enable and disable the μDMA module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacySleepModeClockGating ControlRegisternSCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingSCGCnbits. Important: This register should be used to control the clocking for the μDMA module. To support legacy software, theSCGC2register is available. A write to theUDMAbit in theSCGC2 register also writes theS0bit in this register. If theUDMAbit is changed by writing to the SCGC2register, it can be read back correctly with a read of theSCGC2register. If software uses this register to control the clock for the μDMA module, the write causes proper operation, but theUDMAbit in theSCGC2register does not reflect the value of the S0bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA) Base 0x400F.E000 Offset 0x70C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 S0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 μDMA Module Sleep Mode Clock Gating Control DescriptionValue μDMA module is disabled.0 Enable and provide a clock to the μDMA module in sleep mode.1 0RWS00 353June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register74:HibernationSleepModeClockGatingControl(SCGCHIB),offset 0x714 The SCGCHIBregister provides software the capability to enable and disable the Hibernation module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacySleepModeClockGating ControlRegisternSCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingSCGCnbits. Important: This register should be used to control the clocking for the Hibernation module. To support legacy software, theSCGC0register is available. A write to theHIBbit in the SCGC0register also writes theS0bit in this register. If theHIBbit is changed by writing to theSCGC0register, it can be read back correctly with a read of theSCGC0register. If software uses this register to control the clock for the Hibernation module, the write causes proper operation, but theHIBbit in theSCGC0register does not reflect the value of theS0bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Hibernation Sleep Mode Clock Gating Control (SCGCHIB) Base 0x400F.E000 Offset 0x714 Type RW, reset 0x0000.0001 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 S0reserved RWROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 Hibernation Module Sleep Mode Clock Gating Control DescriptionValue Hibernation module is disabled.0 Enable and provide a clock to the Hibernation module in sleep mode. 1RWS00 June 12, 2014354 Texas Instruments-Production Data System Control

Register75:UniversalAsynchronousReceiver/TransmitterSleepModeClock GatingControl(SCGCUART),offset0x718 The SCGCUARTregister provides software the capability to enable and disable the UART modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacySleepModeClockGating ControlRegisternSCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingSCGCnbits. Important: This register should be used to control the clocking for the UART modules. To support legacy software, theSCGC1register is available. A write to theSCGC1register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC1register can be read back correctly with a read of theSCGC1register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as UART0), the write causes proper operation, but the value of that bit is not reflected in theSCGC1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control (SCGCUART) Base 0x400F.E000 Offset 0x718 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 S0S1S2S3S4S5S6S7reserved RWRWRWRWRWRWRWRWROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:8 UART Module 7 Sleep Mode Clock Gating Control DescriptionValue UART module 7 is disabled.0 Enable and provide a clock to UART module 7 in sleep mode.1 0RWS77 UART Module 6 Sleep Mode Clock Gating Control DescriptionValue UART module 6 is disabled.0 Enable and provide a clock to UART module 6 in sleep mode.1 0RWS66 355June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field UART Module 5 Sleep Mode Clock Gating Control DescriptionValue UART module 5 is disabled.0 Enable and provide a clock to UART module 5 in sleep mode.1 0RWS55 UART Module 4 Sleep Mode Clock Gating Control DescriptionValue UART module 4 is disabled.0 Enable and provide a clock to UART module 4 in sleep mode.1 0RWS44 UART Module 3 Sleep Mode Clock Gating Control DescriptionValue UART module 3 is disabled.0 Enable and provide a clock to UART module 3 in sleep mode.1 0RWS33 UART Module 2 Sleep Mode Clock Gating Control DescriptionValue UART module 2 is disabled.0 Enable and provide a clock to UART module 2 in sleep mode.1 0RWS22 UART Module 1 Sleep Mode Clock Gating Control DescriptionValue UART module 1 is disabled.0 Enable and provide a clock to UART module 1 in sleep mode.1 0RWS11 UART Module 0 Sleep Mode Clock Gating Control DescriptionValue UART module 0 is disabled.0 Enable and provide a clock to UART module 0 in sleep mode.1 0RWS00 June 12, 2014356 Texas Instruments-Production Data System Control

Register76:SynchronousSerialInterfaceSleepModeClockGatingControl (SCGCSSI),offset0x71C The SCGCSSIregister provides software the capability to enable and disable the SSI modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacySleepModeClockGating ControlRegisternSCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingSCGCnbits. Important: This register should be used to control the clocking for the SSI modules. To support legacy software, theSCGC1register is available. A write to theSCGC1register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC1register can be read back correctly with a read of theSCGC1register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as SSI0), the write causes proper operation, but the value of that bit is not reflected in theSCGC1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI) Base 0x400F.E000 Offset 0x71C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 S0S1S2S3reserved RWRWRWRWROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:4 SSI Module 3 Sleep Mode Clock Gating Control DescriptionValue SSI module 3 is disabled.0 Enable and provide a clock to SSI module 3 in sleep mode.1 0RWS33 SSI Module 2 Sleep Mode Clock Gating Control DescriptionValue SSI module 2 is disabled.0 Enable and provide a clock to SSI module 2 in sleep mode.1 0RWS22 357June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field SSI Module 1 Sleep Mode Clock Gating Control DescriptionValue SSI module 1 is disabled.0 Enable and provide a clock to SSI module 1 in sleep mode.1 0RWS11 SSI Module 0 Sleep Mode Clock Gating Control DescriptionValue SSI module 0 is disabled.0 Enable and provide a clock to SSI module 0 in sleep mode.1 0RWS00 June 12, 2014358 Texas Instruments-Production Data System Control

Register77:Inter-IntegratedCircuitSleepModeClockGatingControl (SCGCI2C),offset0x720 The SCGCI2Cregister provides software the capability to enable and disable the I2C modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacySleepModeClockGating ControlRegisternSCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingSCGCnbits. Important: This register should be used to control the clocking for the I2C modules. To support legacy software, theSCGC1register is available. A write to theSCGC1register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC1register can be read back correctly with a read of theSCGC1register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as I2C0), the write causes proper operation, but the value of that bit is not reflected in theSCGC1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C) Base 0x400F.E000 Offset 0x720 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 S0S1S2S3S4S5reserved RWRWRWRWRWRWROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 I2C Module 5 Sleep Mode Clock Gating Control DescriptionValue I2C module 5 is disabled.0 Enable and provide a clock to I2C module 5 in sleep mode.1 0RWS55 I2C Module 4 Sleep Mode Clock Gating Control DescriptionValue I2C module 4 is disabled.0 Enable and provide a clock to I2C module 4 in sleep mode.1 0RWS44 359June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field I2C Module 3 Sleep Mode Clock Gating Control DescriptionValue I2C module 3 is disabled.0 Enable and provide a clock to I2C module 3 in sleep mode.1 0RWS33 I2C Module 2 Sleep Mode Clock Gating Control DescriptionValue I2C module 2 is disabled.0 Enable and provide a clock to I2C module 2 in sleep mode.1 0RWS22 I2C Module 1 Sleep Mode Clock Gating Control DescriptionValue I2C module 1 is disabled.0 Enable and provide a clock to I2C module 1 in sleep mode.1 0RWS11 I2C Module 0 Sleep Mode Clock Gating Control DescriptionValue I2C module 0 is disabled.0 Enable and provide a clock to I2C module 0 in sleep mode.1 0RWS00 June 12, 2014360 Texas Instruments-Production Data System Control

Register78:UniversalSerialBusSleepModeClockGatingControl (SCGCUSB),offset0x728 The SCGCUSBregister provides software the capability to enable and disable the USB module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacySleepModeClockGating ControlRegisternSCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingSCGCnbits. Important: This register should be used to control the clocking for the USB module. To support legacy software, theSCGC2register is available. A write to theUSB0bit in theSCGC2 register also writes theS0bit in this register. If theUSB0bit is changed by writing to the SCGC2register, it can be read back correctly with a read of theSCGC2register. If software uses this register to control the clock for the USB module, the write causes proper operation, but theUSB0bit in theSCGC2register does not reflect the value of the S0bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Serial Bus Sleep Mode Clock Gating Control (SCGCUSB) Base 0x400F.E000 Offset 0x728 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 S0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 USB Module Sleep Mode Clock Gating Control DescriptionValue USB module is disabled.0 Enable and provide a clock to the USB module in sleep mode.1 0RWS00 361June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register79:ControllerAreaNetworkSleepModeClockGatingControl (SCGCCAN),offset0x734 The SCGCCANregister provides software the capability to enable and disable the CAN modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacySleepModeClockGating ControlRegisternSCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingSCGCnbits. Important: This register should be used to control the clocking for the CAN modules. To support legacy software, theSCGC0register is available. A write to theSCGC0register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC0register can be read back correctly with a read of theSCGC0register. If software uses this register to write a legacy peripheral (such as CAN0), the write causes proper operation, but the value of that bit is not reflected in theSCGC0register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN) Base 0x400F.E000 Offset 0x734 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 S0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 CAN Module 0 Sleep Mode Clock Gating Control DescriptionValue CAN module 0 is disabled.0 Enable and provide a clock to CAN module 0 in sleep mode.1 0RWS00 June 12, 2014362 Texas Instruments-Production Data System Control

Register80:Analog-to-DigitalConverterSleepModeClockGatingControl (SCGCADC),offset0x738 The SCGCADCregister provides software the capability to enable and disable the ADC modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacySleepModeClockGating ControlRegisternSCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingSCGCnbits. Important: This register should be used to control the clocking for the ADC modules. To support legacy software, theSCGC0register is available. A write to theSCGC0register also writes the corresponding bit in this register. Any bits that are changed by writing to the SCGC0register can be read back correctly with a read of theSCGC0register. If software uses this register to write a legacy peripheral (such as ADC0), the write causes proper operation, but the value of that bit is not reflected in theSCGC0register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC) Base 0x400F.E000 Offset 0x738 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 S0S1reserved RWRWROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 ADC Module 1 Sleep Mode Clock Gating Control DescriptionValue ADC module 1 is disabled.0 Enable and provide a clock to ADC module 1 in sleep mode.1 0RWS11 ADC Module 0 Sleep Mode Clock Gating Control DescriptionValue ADC module 0 is disabled.0 Enable and provide a clock to ADC module 0 in sleep mode.1 0RWS00 363June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register81:AnalogComparatorSleepModeClockGatingControl (SCGCACMP),offset0x73C The SCGCACMPregister provides software the capability to enable and disable the analog comparator module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacySleep ModeClockGatingControlRegisternSCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingSCGCnbits. Important: This register should be used to control the clocking for the analog comparator module. To support legacy software, theSCGC1register is available. Setting any of theCOMPn bits in the SCGC1 register also sets theS0bit in this register. If any of theCOMPnbits are set by writing to theSCGC1register, it can be read back correctly when reading the SCGC1register. If software uses this register to change the clocking for the analog comparator module, the write causes proper operation, but the valueS0is not reflected by theCOMPnbits in theSCGC1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP) Base 0x400F.E000 Offset 0x73C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 S0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 Analog Comparator Module 0 Sleep Mode Clock Gating Control DescriptionValue Analog comparator module is disabled.0 Enable and provide a clock to the analog comparator module in sleep mode. 0RWS00 June 12, 2014364 Texas Instruments-Production Data System Control

Register82:EEPROMSleepModeClockGatingControl(SCGCEEPROM), offset0x758 The SCGCEEPROMregister provides software the capability to enable and disable the EEPROM module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM) Base 0x400F.E000 Offset 0x758 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 S0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 EEPROM Module Sleep Mode Clock Gating Control DescriptionValue EEPROM module is disabled.0 Enable and provide a clock to the EEPROM module in sleep mode. 0RWS00 365June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register83:32/64-BitWideGeneral-PurposeTimerSleepModeClockGating Control(SCGCWTIMER),offset0x75C The SCGCWTIMERregister provides software the capability to enable and disable 3264-bit timer modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacySleepModeClock GatingControlRegisternSCGCn registers specifically for the timer modules and has the same bit polarity as the correspondingSCGCnbits. 32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating Control (SCGCWTIMER) Base 0x400F.E000 Offset 0x75C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 S0S1S2S3S4S5reserved RWRWRWRWRWRWROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 32/64-Bit Wide General-Purpose Timer 5 Sleep Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 5 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 5 in sleep mode. 0RWS55 32/64-Bit Wide General-Purpose Timer 4 Sleep Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 4 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 4 in sleep mode. 0RWS44 32/64-Bit Wide General-Purpose Timer 3 Sleep Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 3 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 3 in sleep mode. 0RWS33 June 12, 2014366 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field 32/64-Bit Wide General-Purpose Timer 2 Sleep Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 2 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 2 in sleep mode. 0RWS22 32/64-Bit Wide General-Purpose Timer 1 Sleep Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 1 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 1 in sleep mode. 0RWS11 32/64-Bit Wide General-Purpose Timer 0 Sleep Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 0 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 0 in sleep mode. 0RWS00 367June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register84:WatchdogTimerDeep-SleepModeClockGatingControl (DCGCWD),offset0x800 The DCGCWDregister provides software the capability to enable and disable watchdog modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacyDeep-SleepMode ClockGatingControlRegisternDCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingDCGCnbits. Important: This register should be used to control the clocking for the watchdog modules. To support legacy software, theDCGC0register is available. A write to theDCGC0register also writes the corresponding bit in this register. Any bits that are changed by writing to theDCGC0register can be read back correctly with a read of theDCGC0register. If software uses this register to write a legacy peripheral (such as Watchdog 0), the write causes proper operation, but the value of that bit is not reflected in theDCGC0 register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD) Base 0x400F.E000 Offset 0x800 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 D0D1reserved RWRWROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control DescriptionValue Watchdog module 1 is disabled.0 Enable and provide a clock to Watchdog module 1 in deep-sleep mode. 0RWD11 Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control DescriptionValue Watchdog module 0 is disabled.0 Enable and provide a clock to Watchdog module 0 in deep-sleep mode. 0RWD00 June 12, 2014368 Texas Instruments-Production Data System Control

Register85:16/32-BitGeneral-PurposeTimerDeep-SleepModeClockGating Control(DCGCTIMER),offset0x804 The DCGCTIMERregister provides software the capability to enable and disable 16/32-bit timer modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacyDeep-Sleep ModeClockGatingControlRegisternDCGCn registers specifically for the timer modules and has the same bit polarity as the correspondingDCGCnbits. Important: This register should be used to control the clocking for the timer modules. To support legacy software, theDCGC1register is available. A write to theDCGC1register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC1register can be read back correctly with a read of theDCGC1register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as Timer 0), the write causes proper operation, but the value of that bit is not reflected in theDCGC1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER) Base 0x400F.E000 Offset 0x804 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 D0D1D2D3D4D5reserved RWRWRWRWRWRWROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 16/32-Bit General-Purpose Timer 5 Deep-Sleep Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 5 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 5 in deep-sleep mode. 0RWD55 369June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field 16/32-Bit General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 4 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 4 in deep-sleep mode. 0RWD44 16/32-Bit General-Purpose Timer 3 Deep-Sleep Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 3 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 3 in deep-sleep mode. 0RWD33 16/32-Bit General-Purpose Timer 2 Deep-Sleep Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 2 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 2 in deep-sleep mode. 0RWD22 16/32-Bit General-Purpose Timer 1 Deep-Sleep Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 1 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 1 in deep-sleep mode. 0RWD11 16/32-Bit General-Purpose Timer 0 Deep-Sleep Mode Clock Gating Control DescriptionValue 16/32-bit general-purpose timer module 0 is disabled.0 Enable and provide a clock to 16/32-bit general-purpose timer module 0 in deep-sleep mode. 0RWD00 June 12, 2014370 Texas Instruments-Production Data System Control

Register86:General-PurposeInput/OutputDeep-SleepModeClockGating Control(DCGCGPIO),offset0x808 The DCGCGPIOregister provides software the capability to enable and disable GPIO modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacyDeep-SleepModeClock GatingControlRegisternDCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingDCGCnbits. Important: This register should be used to control the clocking for the GPIO modules. To support legacy software, theDCGC2register is available. A write to theDCGC2register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC2register can be read back correctly with a read of theDCGC2register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as GPIO A), the write causes proper operation, but the value of that bit is not reflected in theDCGC2register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO) Base 0x400F.E000 Offset 0x808 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 D0D1D2D3D4D5D6D7D8D9reserved RWRWRWRWRWRWRWRWRWRWROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:10 GPIO Port K Deep-Sleep Mode Clock Gating Control DescriptionValue GPIO Port K is disabled.0 Enable and provide a clock to GPIO Port K in deep-sleep mode.1 0RWD99 GPIO Port J Deep-Sleep Mode Clock Gating Control DescriptionValue GPIO Port J is disabled.0 Enable and provide a clock to GPIO Port J in deep-sleep mode.1 0RWD88 371June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field GPIO Port H Deep-Sleep Mode Clock Gating Control DescriptionValue GPIO Port H is disabled.0 Enable and provide a clock to GPIO Port H in deep-sleep mode.1 0RWD77 GPIO Port G Deep-Sleep Mode Clock Gating Control DescriptionValue GPIO Port G is disabled.0 Enable and provide a clock to GPIO Port G in deep-sleep mode.1 0RWD66 GPIO Port F Deep-Sleep Mode Clock Gating Control DescriptionValue GPIO Port F is disabled.0 Enable and provide a clock to GPIO Port F in deep-sleep mode.1 0RWD55 GPIO Port E Deep-Sleep Mode Clock Gating Control DescriptionValue GPIO Port E is disabled.0 Enable and provide a clock to GPIO Port E in deep-sleep mode.1 0RWD44 GPIO Port D Deep-Sleep Mode Clock Gating Control DescriptionValue GPIO Port D is disabled.0 Enable and provide a clock to GPIO Port D in deep-sleep mode.1 0RWD33 GPIO Port C Deep-Sleep Mode Clock Gating Control DescriptionValue GPIO Port C is disabled.0 Enable and provide a clock to GPIO Port C in deep-sleep mode.1 0RWD22 GPIO Port B Deep-Sleep Mode Clock Gating Control DescriptionValue GPIO Port B is disabled.0 Enable and provide a clock to GPIO Port B in deep-sleep mode.1 0RWD11 June 12, 2014372 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field GPIO Port A Deep-Sleep Mode Clock Gating Control DescriptionValue GPIO Port A is disabled.0 Enable and provide a clock to GPIO Port A in deep-sleep mode.1 0RWD00 373June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register87:MicroDirectMemoryAccessDeep-SleepModeClockGating Control(DCGCDMA),offset0x80C The DCGCDMAregister provides software the capability to enable and disable the μDMA module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacyDeep-SleepMode ClockGatingControlRegisternDCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingDCGCnbits. Important: This register should be used to control the clocking for the μDMA module. To support legacy software, theDCGC2register is available. A write to theUDMAbit in theDCGC2 register also writes theD0bit in this register. If theUDMAbit is changed by writing to the DCGC2register, it can be read back correctly with a read of theDCGC2register. If software uses this register to control the clock for the μDMA module, the write causes proper operation, but theUDMAbit in theDCGC2register does not reflect the value of the D0bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA) Base 0x400F.E000 Offset 0x80C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 D0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 μDMA Module Deep-Sleep Mode Clock Gating Control DescriptionValue μDMA module is disabled.0 Enable and provide a clock to the μDMA module in deep-sleep mode. 0RWD00 June 12, 2014374 Texas Instruments-Production Data System Control

Register88:HibernationDeep-SleepModeClockGatingControl(DCGCHIB), offset0x814 The DCGCHIBregister provides software the capability to enable and disable the Hibernation module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacyDeep-Sleep ModeClockGatingControlRegisternDCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingDCGCnbits. Important: This register should be used to control the clocking for the Hibernation module. To support legacy software, theDCGC0register is available. A write to theHIBbit in the DCGC0register also writes theD0bit in this register. If theHIBbit is changed by writing to theDCGC0register, it can be read back correctly with a read of theDCGC0register. If software uses this register to control the clock for the Hibernation module, the write causes proper operation, but theHIBbit in theDCGC0register does not reflect the value of theD0bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Hibernation Deep-Sleep Mode Clock Gating Control (DCGCHIB) Base 0x400F.E000 Offset 0x814 Type RW, reset 0x0000.0001 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 D0reserved RWROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 Hibernation Module Deep-Sleep Mode Clock Gating Control DescriptionValue Hibernation module is disabled.0 Enable and provide a clock to the Hibernation module in deep-sleep mode. 1RWD00 375June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register89:UniversalAsynchronousReceiver/TransmitterDeep-SleepMode ClockGatingControl(DCGCUART),offset0x818 The DCGCUARTregister provides software the capability to enable and disable the UART modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacyDeep-SleepMode ClockGatingControlRegisternDCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingDCGCnbits. Important: This register should be used to control the clocking for the UART modules. To support legacy software, theDCGC1register is available. A write to theDCGC1register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC1register can be read back correctly with a read of theDCGC1register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as UART0), the write causes proper operation, but the value of that bit is not reflected in theDCGC1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control (DCGCUART) Base 0x400F.E000 Offset 0x818 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 D0D1D2D3D4D5D6D7reserved RWRWRWRWRWRWRWRWROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:8 UART Module 7 Deep-Sleep Mode Clock Gating Control DescriptionValue UART module 7 is disabled.0 Enable and provide a clock to UART module 7 in deep-sleep mode. 0RWD77 UART Module 6 Deep-Sleep Mode Clock Gating Control DescriptionValue UART module 6 is disabled.0 Enable and provide a clock to UART module 6 in deep-sleep mode. 0RWD66 June 12, 2014376 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field UART Module 5 Deep-Sleep Mode Clock Gating Control DescriptionValue UART module 5 is disabled.0 Enable and provide a clock to UART module 5 in deep-sleep mode. 0RWD55 UART Module 4 Deep-Sleep Mode Clock Gating Control DescriptionValue UART module 4 is disabled.0 Enable and provide a clock to UART module 4 in deep-sleep mode. 0RWD44 UART Module 3 Deep-Sleep Mode Clock Gating Control DescriptionValue UART module 3 is disabled.0 Enable and provide a clock to UART module 3 in deep-sleep mode. 0RWD33 UART Module 2 Deep-Sleep Mode Clock Gating Control DescriptionValue UART module 2 is disabled.0 Enable and provide a clock to UART module 2 in deep-sleep mode. 0RWD22 UART Module 1 Deep-Sleep Mode Clock Gating Control DescriptionValue UART module 1 is disabled.0 Enable and provide a clock to UART module 1 in deep-sleep mode. 0RWD11 UART Module 0 Deep-Sleep Mode Clock Gating Control DescriptionValue UART module 0 is disabled.0 Enable and provide a clock to UART module 0 in deep-sleep mode. 0RWD00 377June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register90:SynchronousSerialInterfaceDeep-SleepModeClockGating Control(DCGCSSI),offset0x81C The DCGCSSIregister provides software the capability to enable and disable the SSI modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacyDeep-SleepModeClock GatingControlRegisternDCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingDCGCnbits. Important: This register should be used to control the clocking for the SSI modules. To support legacy software, theDCGC1register is available. A write to theDCGC1register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC1register can be read back correctly with a read of theDCGC1register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as SSI0), the write causes proper operation, but the value of that bit is not reflected in theDCGC1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI) Base 0x400F.E000 Offset 0x81C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 D0D1D2D3reserved RWRWRWRWROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:4 SSI Module 3 Deep-Sleep Mode Clock Gating Control DescriptionValue SSI module 3 is disabled.0 Enable and provide a clock to SSI module 3 in deep-sleep mode.1 0RWD33 SSI Module 2 Deep-Sleep Mode Clock Gating Control DescriptionValue SSI module 2 is disabled.0 Enable and provide a clock to SSI module 2 in deep-sleep mode.1 0RWD22 June 12, 2014378 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field SSI Module 1 Deep-Sleep Mode Clock Gating Control DescriptionValue SSI module 1 is disabled.0 Enable and provide a clock to SSI module 1 in deep-sleep mode.1 0RWD11 SSI Module 0 Deep-Sleep Mode Clock Gating Control DescriptionValue SSI module 0 is disabled.0 Enable and provide a clock to SSI module 0 in deep-sleep mode.1 0RWD00 379June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register91:Inter-IntegratedCircuitDeep-SleepModeClockGatingControl (DCGCI2C),offset0x820 The DCGCI2Cregister provides software the capability to enable and disable the I2C modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacyDeep-SleepModeClock GatingControlRegisternDCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingDCGCnbits. Important: This register should be used to control the clocking for the I2C modules. To support legacy software, theDCGC1register is available. A write to theDCGC1register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC1register can be read back correctly with a read of theDCGC1register. Software must use this register to support modules that are not present in the legacy registers. If software uses this register to write a legacy peripheral (such as I2C0), the write causes proper operation, but the value of that bit is not reflected in theDCGC1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C) Base 0x400F.E000 Offset 0x820 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 D0D1D2D3D4D5reserved RWRWRWRWRWRWROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 I2C Module 5 Deep-Sleep Mode Clock Gating Control DescriptionValue I2C module 5 is disabled.0 Enable and provide a clock to I2C module 5 in deep-sleep mode.1 0RWD55 I2C Module 4 Deep-Sleep Mode Clock Gating Control DescriptionValue I2C module 4 is disabled.0 Enable and provide a clock to I2C module 4 in deep-sleep mode.1 0RWD44 June 12, 2014380 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field I2C Module 3 Deep-Sleep Mode Clock Gating Control DescriptionValue I2C module 3 is disabled.0 Enable and provide a clock to I2C module 3 in deep-sleep mode.1 0RWD33 I2C Module 2 Deep-Sleep Mode Clock Gating Control DescriptionValue I2C module 2 is disabled.0 Enable and provide a clock to I2C module 2 in deep-sleep mode.1 0RWD22 I2C Module 1 Deep-Sleep Mode Clock Gating Control DescriptionValue I2C module 1 is disabled.0 Enable and provide a clock to I2C module 1 in deep-sleep mode.1 0RWD11 I2C Module 0 Deep-Sleep Mode Clock Gating Control DescriptionValue I2C module 0 is disabled.0 Enable and provide a clock to I2C module 0 in deep-sleep mode.1 0RWD00 381June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register92:UniversalSerialBusDeep-SleepModeClockGatingControl (DCGCUSB),offset0x828 The DCGCUSBregister provides software the capability to enable and disable the USB module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacyDeep-SleepModeClock GatingControlRegisternDCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingDCGCnbits. Important: This register should be used to control the clocking for the USB module. To support legacy software, theDCGC2register is available. A write to theUSB0bit in theDCGC2 register also writes theD0bit in this register. If theUSB0bit is changed by writing to the DCGC2register, it can be read back correctly with a read of theDCGC2register. If software uses this register to control the clock for the USB module, the write causes proper operation, but theUSB0bit in theDCGC2register does not reflect the value of the D0bit. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Universal Serial Bus Deep-Sleep Mode Clock Gating Control (DCGCUSB) Base 0x400F.E000 Offset 0x828 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 D0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 USB Module Deep-Sleep Mode Clock Gating Control DescriptionValue USB module is disabled.0 Enable and provide a clock to the USB module in deep-sleep mode. 0RWD00 June 12, 2014382 Texas Instruments-Production Data System Control

Register93:ControllerAreaNetworkDeep-SleepModeClockGatingControl (DCGCCAN),offset0x834 The DCGCCANregister provides software the capability to enable and disable the CAN modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacyDeep-SleepMode ClockGatingControlRegisternDCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingDCGCnbits. Important: This register should be used to control the clocking for the CAN modules. To support legacy software, theDCGC0register is available. A write to theDCGC0register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC0register can be read back correctly with a read of theDCGC0register. If software uses this register to write a legacy peripheral (such as CAN0), the write causes proper operation, but the value of that bit is not reflected in theDCGC0register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN) Base 0x400F.E000 Offset 0x834 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 D0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 CAN Module 0 Deep-Sleep Mode Clock Gating Control DescriptionValue CAN module 0 is disabled.0 Enable and provide a clock to CAN module 0 in deep-sleep mode. 0RWD00 383June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register94:Analog-to-DigitalConverterDeep-SleepModeClockGating Control(DCGCADC),offset0x838 The DCGCADCregister provides software the capability to enable and disable the ADC modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacyDeep-SleepMode ClockGatingControlRegisternDCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingDCGCnbits. Important: This register should be used to control the clocking for the ADC modules. To support legacy software, theDCGC0register is available. A write to theDCGC0register also writes the corresponding bit in this register. Any bits that are changed by writing to the DCGC0register can be read back correctly with a read of theDCGC0register. If software uses this register to write a legacy peripheral (such as ADC0), the write causes proper operation, but the value of that bit is not reflected in theDCGC0register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC) Base 0x400F.E000 Offset 0x838 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 D0D1reserved RWRWROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 ADC Module 1 Deep-Sleep Mode Clock Gating Control DescriptionValue ADC module 1 is disabled.0 Enable and provide a clock to ADC module 1 in deep-sleep mode. 0RWD11 ADC Module 0 Deep-Sleep Mode Clock Gating Control DescriptionValue ADC module 0 is disabled.0 Enable and provide a clock to ADC module 0 in deep-sleep mode. 0RWD00 June 12, 2014384 Texas Instruments-Production Data System Control

Register95:AnalogComparatorDeep-SleepModeClockGatingControl (DCGCACMP),offset0x83C The DCGCACMPregister provides software the capability to enable and disable the analog comparator module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-SleepModeClockGatingControlRegisternDCGCn registers specifically for the watchdog modules and has the same bit polarity as the correspondingDCGCnbits. Important: This register should be used to control the clocking for the analog comparator module. To support legacy software, theDCGC1register is available. Setting any of theCOMPn bits in theDCGC1register also sets theD0bit in this register. If any of theCOMPnbits are set by writing to theDCGC1register, it can be read back correctly when reading the DCGC1register. If software uses this register to change the clocking for the analog comparator module, the write causes proper operation, but the valueD0is not reflected by theCOMPnbits in theDCGC1register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP) Base 0x400F.E000 Offset 0x83C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 D0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 Analog Comparator Module 0 Deep-Sleep Mode Clock Gating Control DescriptionValue Analog comparator module is disabled.0 Enable and provide a clock to the analog comparator module in deep-sleep mode. 0RWD00 385June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register96:EEPROMDeep-SleepModeClockGatingControl(DCGCEEPROM), offset0x858 The DCGCEEPROMregister provides software the capability to enable and disable the EEPROM module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM) Base 0x400F.E000 Offset 0x858 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 D0reserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 EEPROM Module Deep-Sleep Mode Clock Gating Control DescriptionValue EEPROM module is disabled.0 Enable and provide a clock to the EEPROM module in deep-sleep mode. 0RWD00 June 12, 2014386 Texas Instruments-Production Data System Control

Register97:32/64-BitWideGeneral-PurposeTimerDeep-SleepModeClock GatingControl(DCGCWTIMER),offset0x85C The DCGCWTIMERregister provides software the capability to enable and disable 32/64-bit wide timer modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power. This register provides the same capability as the legacy Deep-SleepModeClockGatingControlRegisternDCGCn registers specifically for the timer modules and has the same bit polarity as the correspondingDCGCnbits. 32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCWTIMER) Base 0x400F.E000 Offset 0x85C Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 D0D1D2D3D4D5reserved RWRWRWRWRWRWROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 32/64-Bit Wide General-Purpose Timer 5 Deep-Sleep Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 5 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 5 in deep-sleep mode. 0RWD55 32/64-Bit Wide General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 4 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 4 in deep-sleep mode. 0RWD44 32/64-Bit Wide General-Purpose Timer 3 Deep-Sleep Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 3 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 3 in deep-sleep mode. 0RWD33 387June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field 32/64-Bit Wide General-Purpose Timer 2 Deep-Sleep Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 2 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 2 in deep-sleep mode. 0RWD22 32/64-Bit Wide General-Purpose Timer 1 Deep-Sleep Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 1 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 1 in deep-sleep mode. 0RWD11 32/64-Bit Wide General-Purpose Timer 0 Deep-Sleep Mode Clock Gating Control DescriptionValue 32/64-bit wide general-purpose timer module 0 is disabled.0 Enable and provide a clock to 32/64-bit wide general-purpose timer module 0 in deep-sleep mode. 0RWD00 June 12, 2014388 Texas Instruments-Production Data System Control

Register98:WatchdogTimerPeripheralReady(PRWD),offset0xA00 The PRWDregister indicates whether the watchdog modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the correspondingRCGCWDbit is changed. A reset change is initiated if the corresponding SRWDbit is changed from 0 to 1. The PRWDbit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Watchdog Timer Peripheral Ready (PRWD) Base 0x400F.E000 Offset 0xA00 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 Watchdog Timer 1 Peripheral Ready DescriptionValue Watchdog module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. Watchdog module 1 is ready for access.1 0ROR11 Watchdog Timer 0 Peripheral Ready DescriptionValue Watchdog module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. Watchdog module 0 is ready for access.1 0ROR00 389June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register99:16/32-BitGeneral-PurposeTimerPeripheralReady(PRTIMER), offset0xA04 The PRTIMERregister indicates whether the timer modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the correspondingRCGCTIMERbit is changed. A reset change is initiated if the corresponding SRTIMERbit is changed from 0 to 1. The PRTIMERbit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. 16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER) Base 0x400F.E000 Offset 0xA04 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 16/32-Bit General-Purpose Timer 5 Peripheral Ready DescriptionValue 16/32-bit timer module 5 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 16/32-bit timer module 5 is ready for access.1 0ROR55 16/32-Bit General-Purpose Timer 4 Peripheral Ready DescriptionValue 16/32-bit timer module 4 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 16/32-bit timer module 4 is ready for access.1 0ROR44 16/32-Bit General-Purpose Timer 3 Peripheral Ready DescriptionValue 16/32-bit timer module 3 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 16/32-bit timer module 3 is ready for access.1 0ROR33 June 12, 2014390 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field 16/32-Bit General-Purpose Timer 2 Peripheral Ready DescriptionValue 16/32-bit timer module 2 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 16/32-bit timer module 2 is ready for access.1 0ROR22 16/32-Bit General-Purpose Timer 1 Peripheral Ready DescriptionValue 16/32-bit timer module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 16/32-bit timer module 1 is ready for access.1 0ROR11 16/32-Bit General-Purpose Timer 0 Peripheral Ready DescriptionValue 16/32-bit timer module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 16/32-bit timer module 0 is ready for access.1 0ROR00 391June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register100:General-PurposeInput/OutputPeripheralReady(PRGPIO), offset0xA08 The PRGPIOregister indicates whether the GPIO modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the correspondingRCGCGPIObit is changed. A reset change is initiated if the corresponding SRGPIObit is changed from 0 to 1. The PRGPIObit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. General-Purpose Input/Output Peripheral Ready (PRGPIO) Base 0x400F.E000 Offset 0xA08 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5R6R7R8R9reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:10 GPIO Port K Peripheral Ready DescriptionValue GPIO Port K is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. GPIO Port K is ready for access.1 0ROR99 GPIO Port J Peripheral Ready DescriptionValue GPIO Port J is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. GPIO Port J is ready for access.1 0ROR88 GPIO Port H Peripheral Ready DescriptionValue GPIO Port H is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. GPIO Port H is ready for access.1 0ROR77 June 12, 2014392 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field GPIO Port G Peripheral Ready DescriptionValue GPIO Port G is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. GPIO Port G is ready for access.1 0ROR66 GPIO Port F Peripheral Ready DescriptionValue GPIO Port F is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. GPIO Port F is ready for access.1 0ROR55 GPIO Port E Peripheral Ready DescriptionValue GPIO Port E is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. GPIO Port E is ready for access.1 0ROR44 GPIO Port D Peripheral Ready DescriptionValue GPIO Port D is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. GPIO Port D is ready for access.1 0ROR33 GPIO Port C Peripheral Ready DescriptionValue GPIO Port C is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. GPIO Port C is ready for access.1 0ROR22 GPIO Port B Peripheral Ready DescriptionValue GPIO Port B is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. GPIO Port B is ready for access.1 0ROR11 GPIO Port A Peripheral Ready DescriptionValue GPIO Port A is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. GPIO Port A is ready for access.1 0ROR00 393June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register101:MicroDirectMemoryAccessPeripheralReady(PRDMA),offset 0xA0C The PRDMAregister indicates whether the μDMA module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the correspondingRCGCDMAbit is changed. A reset change is initiated if the corresponding SRDMAbit is changed from 0 to 1. The PRDMAbit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Micro Direct Memory Access Peripheral Ready (PRDMA) Base 0x400F.E000 Offset 0xA0C Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 μDMA Module Peripheral Ready DescriptionValue The μDMA module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. The μDMA module is ready for access.1 0ROR00 June 12, 2014394 Texas Instruments-Production Data System Control

Register102:HibernationPeripheralReady(PRHIB),offset0xA14 The PRHIBregister indicates whether the Hibernation module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the correspondingRCGCHIBbit is changed. A reset change is initiated if the corresponding SRHIBbit is changed from 0 to 1. The PRHIBbit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Hibernation Peripheral Ready (PRHIB) Base 0x400F.E000 Offset 0xA14 Type RO, reset 0x0000.0001 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved ROROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 Hibernation Module Peripheral Ready DescriptionValue The Hibernation module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. The Hibernation module is ready for access.1 1ROR00 395June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register103:UniversalAsynchronousReceiver/TransmitterPeripheralReady (PRUART),offset0xA18 The PRUARTregister indicates whether the UART modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the correspondingRCGCUARTbit is changed. A reset change is initiated if the corresponding SRUARTbit is changed from 0 to 1. The PRUARTbit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART) Base 0x400F.E000 Offset 0xA18 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5R6R7reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:8 UART Module 7 Peripheral Ready DescriptionValue UART module 7 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. UART module 7 is ready for access.1 0ROR77 UART Module 6 Peripheral Ready DescriptionValue UART module 6 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. UART module 6 is ready for access.1 0ROR66 UART Module 5 Peripheral Ready DescriptionValue UART module 5 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. UART module 5 is ready for access.1 0ROR55 June 12, 2014396 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field UART Module 4 Peripheral Ready DescriptionValue UART module 4 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. UART module 4 is ready for access.1 0ROR44 UART Module 3 Peripheral Ready DescriptionValue UART module 3 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. UART module 3 is ready for access.1 0ROR33 UART Module 2 Peripheral Ready DescriptionValue UART module 2 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. UART module 2 is ready for access.1 0ROR22 UART Module 1 Peripheral Ready DescriptionValue UART module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. UART module 1 is ready for access.1 0ROR11 UART Module 0 Peripheral Ready DescriptionValue UART module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. UART module 0 is ready for access.1 0ROR00 397June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register104:SynchronousSerialInterfacePeripheralReady(PRSSI),offset 0xA1C The PRSSIregister indicates whether the SSI modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the correspondingRCGCSSIbit is changed. A reset change is initiated if the corresponding SRSSIbit is changed from 0 to 1. The PRSSIbit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Synchronous Serial Interface Peripheral Ready (PRSSI) Base 0x400F.E000 Offset 0xA1C Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:4 SSI Module 3 Peripheral Ready DescriptionValue SSI module 3 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. SSI module 3 is ready for access.1 0ROR33 SSI Module 2 Peripheral Ready DescriptionValue SSI module 2 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. SSI module 2 is ready for access.1 0ROR22 SSI Module 1 Peripheral Ready DescriptionValue SSI module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. SSI module 1 is ready for access.1 0ROR11 June 12, 2014398 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field SSI Module 0 Peripheral Ready DescriptionValue SSI module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. SSI module 0 is ready for access.1 0ROR00 399June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register105:Inter-IntegratedCircuitPeripheralReady(PRI2C),offset0xA20 The PRI2Cregister indicates whether the I2C modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the correspondingRCGCI2Cbit is changed. A reset change is initiated if the correspondingSRI2C bit is changed from 0 to 1. The PRI2Cbit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Inter-Integrated Circuit Peripheral Ready (PRI2C) Base 0x400F.E000 Offset 0xA20 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 I2C Module 5 Peripheral Ready DescriptionValue I2C module 5 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. I2C module 5 is ready for access.1 0ROR55 I2C Module 4 Peripheral Ready DescriptionValue I2C module 4 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. I2C module 4 is ready for access.1 0ROR44 I2C Module 3 Peripheral Ready DescriptionValue I2C module 3 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. I2C module 3 is ready for access.1 0ROR33 June 12, 2014400 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field I2C Module 2 Peripheral Ready DescriptionValue I2C module 2 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. I2C module 2 is ready for access.1 0ROR22 I2C Module 1 Peripheral Ready DescriptionValue I2C module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. I2C module 1 is ready for access.1 0ROR11 I2C Module 0 Peripheral Ready DescriptionValue I2C module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. I2C module 0 is ready for access.1 0ROR00 401June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register106:UniversalSerialBusPeripheralReady(PRUSB),offset0xA28 The PRUSBregister indicates whether the USB module is ready to be accessed by software following a change in Run mode clocking or reset. A Run mode clocking change is initiated if the corresponding RCGCUSBbit is changed. A reset change is initiated if the correspondingSRUSBbit is changed from 0 to 1. The PRUSBbit is cleared on either of the above events and is not set again until the module is completely powered, enabled, and internally reset. Universal Serial Bus Peripheral Ready (PRUSB) Base 0x400F.E000 Offset 0xA28 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 USB Module Peripheral Ready DescriptionValue The USB module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. The USB module is ready for access.1 0ROR00 June 12, 2014402 Texas Instruments-Production Data System Control

Register107:ControllerAreaNetworkPeripheralReady(PRCAN),offset 0xA34 The PRCANregister indicates whether the CAN modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the correspondingRCGCCANbit is changed. A reset change is initiated if the corresponding SRCANbit is changed from 0 to 1. The PRCANbit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Controller Area Network Peripheral Ready (PRCAN) Base 0x400F.E000 Offset 0xA34 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 CAN Module 0 Peripheral Ready DescriptionValue CAN module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. CAN module 0 is ready for access.1 0ROR00 403June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register108:Analog-to-DigitalConverterPeripheralReady(PRADC),offset 0xA38 The PRADCregister indicates whether the ADC modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the correspondingRCGCADCbit is changed. A reset change is initiated if the corresponding SRADCbit is changed from 0 to 1. The PRADCbit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Analog-to-Digital Converter Peripheral Ready (PRADC) Base 0x400F.E000 Offset 0xA38 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:2 ADC Module 1 Peripheral Ready DescriptionValue ADC module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. ADC module 1 is ready for access.1 0ROR11 ADC Module 0 Peripheral Ready DescriptionValue ADC module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. ADC module 0 is ready for access.1 0ROR00 June 12, 2014404 Texas Instruments-Production Data System Control

Register109:AnalogComparatorPeripheralReady(PRACMP),offset0xA3C The PRACMPregister indicates whether the analog comparator module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the correspondingRCGCACMPbit is changed. A reset change is initiated if the correspondingSRACMPbit is changed from 0 to 1. The PRACMPbit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. Analog Comparator Peripheral Ready (PRACMP) Base 0x400F.E000 Offset 0xA3C Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 Analog Comparator Module 0 Peripheral Ready DescriptionValue The analog comparator module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. The analog comparator module is ready for access.1 0ROR00 405June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register110:EEPROMPeripheralReady(PREEPROM),offset0xA58 The PREEPROMregister indicates whether the EEPROM module is ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the correspondingRCGCEEPROMbit is changed. A reset change is initiated if the correspondingSREEPROMbit is changed from 0 to 1. The PREEPROMbit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. EEPROM Peripheral Ready (PREEPROM) Base 0x400F.E000 Offset 0xA58 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1 EEPROM Module Peripheral Ready DescriptionValue The EEPROM module is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. The EEPROM module is ready for access.1 0ROR00 June 12, 2014406 Texas Instruments-Production Data System Control

Register111:32/64-BitWideGeneral-PurposeTimerPeripheralReady (PRWTIMER),offset0xA5C The PRWTIMERregister indicates whether the timer modules are ready to be accessed by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated if the correspondingRCGCWTIMERbit is changed. A reset change is initiated if the corresponding SRWTIMERbit is changed from 0 to 1. The PRWTIMERbit is cleared on any of the above events and is not set again until the module is completely powered, enabled, and internally reset. 32/64-Bit Wide General-Purpose Timer Peripheral Ready (PRWTIMER) Base 0x400F.E000 Offset 0xA5C Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 R0R1R2R3R4R5reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:6 32/64-Bit Wide General-Purpose Timer 5 Peripheral Ready DescriptionValue 32/64-bit wide timer module 5 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 32/64-bit wide timer module 5 is ready for access.1 0ROR55 32/64-Bit Wide General-Purpose Timer 4 Peripheral Ready DescriptionValue 32/64-bit wide timer module 4 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 32/64-bit wide timer module 4 is ready for access.1 0ROR44 32/64-Bit Wide General-Purpose Timer 3 Peripheral Ready DescriptionValue 32/64-bit wide timer module 3 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 32/64-bit wide timer module 3 is ready for access.1 0ROR33 407June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field 32/64-Bit Wide General-Purpose Timer 2 Peripheral Ready DescriptionValue 32/64-bit wide timer module 2 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 32/64-bit wide timer module 2 is ready for access.1 0ROR22 32/64-Bit Wide General-Purpose Timer 1 Peripheral Ready DescriptionValue 32/64-bit wide timer module 1 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 32/64-bit wide timer module 1 is ready for access.1 0ROR11 32/64-Bit Wide General-Purpose Timer 0 Peripheral Ready DescriptionValue 32/64-bit wide timer module 0 is not ready for access. It is unclocked, unpowered, or in the process of completing a reset sequence. 32/64-bit wide timer module 0 is ready for access.1 0ROR00

5.6 SystemControlLegacyRegisterDescriptions

All addresses given are relative to the System Control base address of 0x400F.E000. Important: Register in this section are provided for legacy software support only; registers in “System Control Register Descriptions” on page 229 should be used instead. June 12, 2014408 Texas Instruments-Production Data System Control

Register112:DeviceCapabilities0(DC0),offset0x008 This legacy register is predefined by the part and can be used to verify features. Important: This register is provided for legacy software support only. The FlashSize(FSIZE) and SRAMSize(SSIZE) registers should be used to determine this microcontroller's memory sizes. A read ofDC0correctly identifies legacy memory sizes but software must useFSIZEand SSIZEfor memory sizes that are not listed below. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x005F.001F 16171819202122232425262728293031 SRAMSZ ROROROROROROROROROROROROROROROROType 1111101000000000Reset 0123456789101112131415 FLASHSZ ROROROROROROROROROROROROROROROROType 1111100000000000Reset DescriptionResetTypeNameBit/Field SRAM Size Indicates the size of the on-chip SRAM. DescriptionValue

2 KB of SRAM0x7

4 KB of SRAM0xF

6 KB of SRAM0x17

8 KB of SRAM0x1F

12 KB of SRAM0x2F

16 KB of SRAM0x3F

20 KB of SRAM0x4F

24 KB of SRAM0x5F

32 KB of SRAM0x7F

0x5FROSRAMSZ31:16 409June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Flash Size Indicates the size of the on-chip Flash memory. DescriptionValue

8 KB of Flash0x3

16 KB of Flash0x7

32 KB of Flash0xF

64 KB of Flash0x1F

96 KB of Flash0x2F

128 KB of Flash0x3F

192 KB of Flash0x5F

256 KB of Flash0x7F

0x1FROFLASHSZ15:0 June 12, 2014410 Texas Instruments-Production Data System Control

Register113:DeviceCapabilities1(DC1),offset0x010 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in theRCGC0, SCGC0, DCGC0, and the peripheral-specific RCGC, SCGC, andDCGCregisters cannot be set. Important: This register is provided for legacy software support only. The Peripheral Present registers should be used to determine which modules are implemented on this microcontroller. A read ofDC1correctly identifies if a legacy module is present but software must use the Peripheral Present registers to determine if a module is present that is not supported by theDCnregisters. Likewise, theADCPeripheralProperties(ADCPP) register should be used to determine the maximum ADC sample rate and whether the temperature sensor is present. However, to support legacy software, theMAXADCnSPDfields and theTEMPSNSbit are available. A read ofDC1correctly identifies the maximum ADC sample rate for legacy rates and whether the temperature sensor is present. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset 0x1103.2FFF 16171819202122232425262728293031 ADC0ADC1reservedPWM0PWM1reservedCAN0CAN1reservedWDT1reserved ROROROROROROROROROROROROROROROROType 1100000010001000Reset 0123456789101112131415 JTAGSWDSWOWDT0PLLTEMPSNSHIBMPUMAXADC0SPDMAXADC1SPDMINSYSDIV ROROROROROROROROROROROROROROROROType 1111111111110100Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:29 Watchdog Timer1 Present When set, indicates that watchdog timer 1 is present. 0x1ROWDT128 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:26 CAN Module 1 Present When set, indicates that CAN unit 1 is present. 0x0ROCAN125 CAN Module 0 Present When set, indicates that CAN unit 0 is present. 0x1ROCAN024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:22 PWM Module 1 Present When set, indicates that the PWM module is present. 0x0ROPWM121 411June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field PWM Module 0 Present When set, indicates that the PWM module is present. 0x0ROPWM020 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved19:18 ADC Module 1 Present When set, indicates that ADC module 1 is present. 0x1ROADC117 ADC Module 0 Present When set, indicates that ADC module 0 is present 0x1ROADC016 System Clock Divider Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See theRCCregister for how to change the system clock divisor using theSYSDIVbit. DescriptionValue Reserved0x1 Specifies an 80-MHz CPU clock with a PLL divider of 2.5.0x2 Specifies a 50-MHz CPU clock with a PLL divider of 4.0x3 Specifies a 40-MHz CPU clock with a PLL divider of 5.0x4 Specifies a 25-MHz clock with a PLL divider of 8.0x7 Specifies a 20-MHz clock with a PLL divider of 10.0x9 0x2ROMINSYSDIV15:12 Max ADC1 Speed This field indicates the maximum rate at which the ADC samples data. DescriptionValue 1M samples/second0x3 500K samples/second0x2 250K samples/second0x1 125K samples/second0x0 0x3ROMAXADC1SPD11:10 Max ADC0 Speed This field indicates the maximum rate at which the ADC samples data. DescriptionValue 1M samples/second0x3 500K samples/second0x2 250K samples/second0x1 125K samples/second0x0 0x3ROMAXADC0SPD9:8 MPU Present When set, indicates that the Cortex-M4F Memory Protection Unit (MPU) module is present. See the "Cortex-M4F Peripherals" chapter for details on the MPU. 0x1ROMPU7 June 12, 2014412 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field Hibernation Module Present When set, indicates that the Hibernation module is present. 0x1ROHIB6 Temp Sensor Present When set, indicates that the on-chip temperature sensor is present. 0x1ROTEMPSNS5 PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present. 0x1ROPLL4 Watchdog Timer 0 Present When set, indicates that watchdog timer 0 is present. 0x1ROWDT03 SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present. 0x1ROSWO2 SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present. 0x1ROSWD1 JTAG Present When set, indicates that the JTAG debugger interface is present. 0x1ROJTAG0 413June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register114:DeviceCapabilities2(DC2),offset0x014 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in theRCGC1, SCGC1, DCGC1, and the peripheral-specific RCGC, SCGC, andDCGCregisters registers cannot be set. Important: This register is provided for legacy software support only. The Peripheral Present registers should be used to determine which modules are implemented on this microcontroller. A read ofDC2correctly identifies if a legacy module is present but software must use the Peripheral Present registers to determine if a module is present that is not supported by theDCnregisters. Note that theAnalogComparatorPeripheralPresent(PPACMP) register identifies whether the analog comparator module is present. TheAnalogComparatorPeripheral Properties(ACMPPP) register indicates how many analog comparator blocks are present in the module. Device Capabilities 2 (DC2) Base 0x400F.E000 Offset 0x014 Type RO, reset 0x070F.F037 16171819202122232425262728293031 TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reservedI2S0reservedEPI0reserved ROROROROROROROROROROROROROROROROType 1111000011100000Reset 0123456789101112131415 UART0UART1UART2reservedSSI0SSI1reservedQEI0QEI1reservedI2C0I2C0HSI2C1I2C1HS ROROROROROROROROROROROROROROROROType 1110110000001111Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 EPI Module 0 Present When set, indicates that EPI module 0 is present. 0x0ROEPI030 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved29 I2S Module 0 Present When set, indicates that I2S module 0 is present. 0x0ROI2S028 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27 Analog Comparator 2 Present When set, indicates that analog comparator 2 is present. 0x1ROCOMP226 Analog Comparator 1 Present When set, indicates that analog comparator 1 is present. 0x1ROCOMP125 June 12, 2014414 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field Analog Comparator 0 Present When set, indicates that analog comparator 0 is present. 0x1ROCOMP024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:20 Timer Module 3 Present When set, indicates that General-Purpose Timer module 3 is present. 0x1ROTIMER319 Timer Module 2 Present When set, indicates that General-Purpose Timer module 2 is present. 0x1ROTIMER218 Timer Module 1 Present When set, indicates that General-Purpose Timer module 1 is present. 0x1ROTIMER117 Timer Module 0 Present When set, indicates that General-Purpose Timer module 0 is present. 0x1ROTIMER016 I2C Module 1 Speed When set, indicates that I2C module 1 can operate in high-speed mode. 0x1ROI2C1HS15 I2C Module 1 Present When set, indicates that I2C module 1 is present. 0x1ROI2C114 I2C Module 0 Speed When set, indicates that I2C module 0 can operate in high-speed mode. 0x1ROI2C0HS13 I2C Module 0 Present When set, indicates that I2C module 0 is present. 0x1ROI2C012 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved11:10 QEI Module 1 Present When set, indicates that QEI module 1 is present. 0x0ROQEI19 QEI Module 0 Present When set, indicates that QEI module 0 is present. 0x0ROQEI08 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved7:6 SSI Module 1 Present When set, indicates that SSI module 1 is present. 0x1ROSSI15 SSI Module 0 Present When set, indicates that SSI module 0 is present. 0x1ROSSI04 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 415June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field UART Module 2 Present When set, indicates that UART module 2 is present. 0x1ROUART22 UART Module 1 Present When set, indicates that UART module 1 is present. 0x1ROUART11 UART Module 0 Present When set, indicates that UART module 0 is present. 0x1ROUART00 June 12, 2014416 Texas Instruments-Production Data System Control

Register115:DeviceCapabilities3(DC3),offset0x018 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the feature is not present. Important: This register is provided for legacy software support only. For some modules, the peripheral-resident Peripheral Properties registers should be used to determine which pins are available on this microcontroller. A read ofDC3 correctly identifies if a legacy pin is present but software must use the Peripheral Properties registers to determine if a pin is present that is not supported by theDCn registers. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0xBFFF.7FC0 16171819202122232425262728293031 ADC0AIN0ADC0AIN1ADC0AIN2ADC0AIN3ADC0AIN4ADC0AIN5ADC0AIN6ADC0AIN7CCP0CCP1CCP2CCP3CCP4CCP5reserved32KHZ ROROROROROROROROROROROROROROROROType 1111111111111101Reset 0123456789101112131415 PWM0PWM1PWM2PWM3PWM4PWM5C0MINUSC0PLUSC0OC1MINUSC1PLUSC1OC2MINUSC2PLUSC2OPWMFAULT ROROROROROROROROROROROROROROROROType 0000001111111110Reset DescriptionResetTypeNameBit/Field 32KHz Input Clock Available When set, indicates an even CCP pin is present and can be used as a 32-KHz input clock. Note: The GPTMPPregister does not provide this information. 0x1RO32KHZ31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved30 T2CCP1 Pin Present When set, indicates that Capture/Compare/PWM pinT2CCP1is present. Note: The GPTMPPregister does not provide this information. 0x1ROCCP529 T2CCP0 Pin Present When set, indicates that Capture/Compare/PWM pinT2CCP0is present. Note: The GPTMPPregister does not provide this information. 0x1ROCCP428 T1CCP1 Pin Present When set, indicates that Capture/Compare/PWM pinT1CCP1is present. Note: The GPTMPPregister does not provide this information. 0x1ROCCP327 T1CCP0 Pin Present When set, indicates that Capture/Compare/PWM pinT1CCP0is present. Note: The GPTMPPregister does not provide this information. 0x1ROCCP226 417June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field T0CCP1 Pin Present When set, indicates that Capture/Compare/PWM pinT0CCP1is present. Note: The GPTMPPregister does not provide this information. 0x1ROCCP125 T0CCP0 Pin Present When set, indicates that Capture/Compare/PWM pinT0CCP0is present. Note: The GPTMPPregister does not provide this information. 0x1ROCCP024 ADC Module 0 AIN7 Pin Present When set, indicates that ADC module 0 input pin 7 is present. Note: The CHfield in theADCPPregister provides this information. 0x1ROADC0AIN723 ADC Module 0 AIN6 Pin Present When set, indicates that ADC module 0 input pin 6 is present. Note: The CHfield in theADCPPregister provides this information. 0x1ROADC0AIN622 ADC Module 0 AIN5 Pin Present When set, indicates that ADC module 0 input pin 5 is present. Note: The CHfield in theADCPPregister provides this information. 0x1ROADC0AIN521 ADC Module 0 AIN4 Pin Present When set, indicates that ADC module 0 input pin 4 is present. Note: The CHfield in theADCPPregister provides this information. 0x1ROADC0AIN420 ADC Module 0 AIN3 Pin Present When set, indicates that ADC module 0 input pin 3 is present. Note: The CHfield in theADCPPregister provides this information. 0x1ROADC0AIN319 ADC Module 0 AIN2 Pin Present When set, indicates that ADC module 0 input pin 2 is present. Note: The CHfield in theADCPPregister provides this information. 0x1ROADC0AIN218 ADC Module 0 AIN1 Pin Present When set, indicates that ADC module 0 input pin 1 is present. Note: The CHfield in theADCPPregister provides this information. 0x1ROADC0AIN117 ADC Module 0 AIN0 Pin Present When set, indicates that ADC module 0 input pin 0 is present. Note: The CHfield in theADCPPregister provides this information. 0x1ROADC0AIN016 PWM Fault Pin Present When set, indicates that a PWM Fault pin is present. SeeDC5for specific Fault pins on this device. Note: The FCNTfield in thePWMPPregister provides this information. 0x0ROPWMFAULT15 C2o Pin Present When set, indicates that the analog comparator 2 output pin is present. Note: The C2Obit in theACMPPPregister provides this information. 0x1ROC2O14 June 12, 2014418 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field C2+ Pin Present When set, indicates that the analog comparator 2 (+) input pin is present. Note: This pin is present when analog comparator 2 is present. 0x1ROC2PLUS13 C2- Pin Present When set, indicates that the analog comparator 2 (-) input pin is present. Note: This pin is present when analog comparator 2 is present. 0x1ROC2MINUS12 C1o Pin Present When set, indicates that the analog comparator 1 output pin is present. Note: The C1Obit in theACMPPPregister provides this information. 0x1ROC1O11 C1+ Pin Present When set, indicates that the analog comparator 1 (+) input pin is present. Note: This pin is present when analog comparator 1 is present. 0x1ROC1PLUS10 C1- Pin Present When set, indicates that the analog comparator 1 (-) input pin is present. Note: This pin is present when analog comparator 1 is present. 0x1ROC1MINUS9 C0o Pin Present When set, indicates that the analog comparator 0 output pin is present. Note: The C0Obit in theACMPPPregister provides this information. 0x1ROC0O8 C0+ Pin Present When set, indicates that the analog comparator 0 (+) input pin is present. Note: This pin is present when analog comparator 0 is present. 0x1ROC0PLUS7 C0- Pin Present When set, indicates that the analog comparator 0 (-) input pin is present. Note: This pin is present when analog comparator 0 is present. 0x1ROC0MINUS6 PWM5 Pin Present When set, indicates that the PWM pin 5 is present. Note: The GCNTfield in thePWMPPregister provides this information. 0x0ROPWM55 PWM4 Pin Present When set, indicates that the PWM pin 4 is present. Note: The GCNTfield in thePWMPPregister provides this information. 0x0ROPWM44 PWM3 Pin Present When set, indicates that the PWM pin 3 is present. Note: The GCNTfield in thePWMPPregister provides this information. 0x0ROPWM33 419June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field PWM2 Pin Present When set, indicates that the PWM pin 2 is present. Note: The GCNTfield in thePWMPPregister provides this information. 0x0ROPWM22 PWM1 Pin Present When set, indicates that the PWM pin 1 is present. Note: The GCNTfield in thePWMPPregister provides this information. 0x0ROPWM11 PWM0 Pin Present When set, indicates that the PWM pin 0 is present. Note: The GCNTfield in thePWMPPregister provides this information. 0x0ROPWM00 June 12, 2014420 Texas Instruments-Production Data System Control

Register116:DeviceCapabilities4(DC4),offset0x01C This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in theRCGC2, SCGC2, DCGC2, and the peripheral-specific RCGC, SCGC, andDCGCregisters registers cannot be set. Important: This register is provided for legacy software support only. The Peripheral Present registers should be used to determine which modules are implemented on this microcontroller. A read ofDC4correctly identifies if a legacy module is present but software must use the Peripheral Present registers to determine if a module is present that is not supported by theDCnregisters. The peripheral-resident Peripheral Properties registers should be used to determine which pins and features are available on this microcontroller. A read ofDC4correctly identifies if a legacy pin or feature is present. Software must use the Peripheral Properties registers to determine if a pin or feature is present that is not supported by theDCn registers. Device Capabilities 4 (DC4) Base 0x400F.E000 Offset 0x01C Type RO, reset 0x0004.F1FF 16171819202122232425262728293031 reservedPICALreservedE1588reservedEMAC0reservedEPHY0reserved ROROROROROROROROROROROROROROROROType 0010000000000000Reset 0123456789101112131415 GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHGPIOJreservedROMUDMACCP6CCP7 ROROROROROROROROROROROROROROROROType 1111111110001111Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 Ethernet PHY Layer 0 Present When set, indicates that Ethernet PHY layer 0 is present. 0x0ROEPHY030 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved29 Ethernet MAC Layer 0 Present When set, indicates that Ethernet MAC layer 0 is present. 0x0ROEMAC028 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:25

1588 Capable

When set, indicates that Ethernet MAC layer 0 is 1588 capable. 0x0ROE158824 421June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:19 PIOSC Calibrate When set, indicates that the PIOSC can be calibrated by software. 0x1ROPICAL18 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved17:16 T3CCP1 Pin Present When set, indicates that Capture/Compare/PWM pinT3CCP1is present. Note: The GPTMPPregister does not provide this information. 0x1ROCCP715 T3CCP0 Pin Present When set, indicates that Capture/Compare/PWM pinT3CCP0is present. Note: The GPTMPPregister does not provide this information. 0x1ROCCP614 Micro-DMA Module Present When set, indicates that the micro-DMA module present. 0x1ROUDMA13 Internal Code ROM Present When set, indicates that internal code ROM is present. 0x1ROROM12 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved11:9 GPIO Port J Present When set, indicates that GPIO Port J is present. 0x1ROGPIOJ8 GPIO Port H Present When set, indicates that GPIO Port H is present. 0x1ROGPIOH7 GPIO Port G Present When set, indicates that GPIO Port G is present. 0x1ROGPIOG6 GPIO Port F Present When set, indicates that GPIO Port F is present. 0x1ROGPIOF5 GPIO Port E Present When set, indicates that GPIO Port E is present. 0x1ROGPIOE4 GPIO Port D Present When set, indicates that GPIO Port D is present. 0x1ROGPIOD3 GPIO Port C Present When set, indicates that GPIO Port C is present. 0x1ROGPIOC2 GPIO Port B Present When set, indicates that GPIO Port B is present. 0x1ROGPIOB1 June 12, 2014422 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field GPIO Port A Present When set, indicates that GPIO Port A is present. 0x1ROGPIOA0 423June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register117:DeviceCapabilities5(DC5),offset0x020 This register is predefined by the part and can be used to verify PWM features. If any bit is clear in this register, the module is not present. Important: This register is provided for legacy software support only. The PWMPeripheralProperties(PWMPP) register should be used to determine what pins and features are available on PWM modules. A read of this register correctly identifies if a legacy pin or feature is present. Software must use thePWMPPregister to determine if a pin or feature that is not supported by theDCnregisters is present. Device Capabilities 5 (DC5) Base 0x400F.E000 Offset 0x020 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reservedPWMESYNCPWMEFLTreservedPWMFAULT0PWMFAULT1PWMFAULT2PWMFAULT3reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PWM0PWM1PWM2PWM3PWM4PWM5PWM6PWM7reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:28 PWM Fault 3 Pin Present When set, indicates that the PWM Fault 3 pin is present. 0x0ROPWMFAULT327 PWM Fault 2 Pin Present When set, indicates that the PWM Fault 2 pin is present. 0x0ROPWMFAULT226 PWM Fault 1 Pin Present When set, indicates that the PWM Fault 1 pin is present. 0x0ROPWMFAULT125 PWM Fault 0 Pin Present When set, indicates that the PWM Fault 0 pin is present. 0x0ROPWMFAULT024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:22 PWM Extended Fault Active When set, indicates that the PWM Extended Fault feature is active. 0x0ROPWMEFLT21 PWM Extended SYNC Active When set, indicates that the PWM Extended SYNC feature is active. 0x0ROPWMESYNC20 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved19:8 June 12, 2014424 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field PWM7 Pin Present When set, indicates that the PWM pin 7 is present. 0x0ROPWM77 PWM6 Pin Present When set, indicates that the PWM pin 6 is present. 0x0ROPWM66 PWM5 Pin Present When set, indicates that the PWM pin 5 is present. 0x0ROPWM55 PWM4 Pin Present When set, indicates that the PWM pin 4 is present. 0x0ROPWM44 PWM3 Pin Present When set, indicates that the PWM pin 3 is present. 0x0ROPWM33 PWM2 Pin Present When set, indicates that the PWM pin 2 is present. 0x0ROPWM22 PWM1 Pin Present When set, indicates that the PWM pin 1 is present. 0x0ROPWM11 PWM0 Pin Present When set, indicates that the PWM pin 0 is present. 0x0ROPWM00 425June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register118:DeviceCapabilities6(DC6),offset0x024 This register is predefined by the part and can be used to verify features. If any bit is clear in this register, the module is not present. The corresponding bit in theRCGC0, SCGC0, andDCGC0 registers cannot be set. Important: This register is provided for legacy software support only. The USBPeripheralProperties(USBPP) register should be used to determine what features are available on the USB module. A read of this register correctly identifies if a legacy feature is present. Software must use theUSBPPregister to determine if a pin or feature that is not supported by theDCnregisters is present. Device Capabilities 6 (DC6) Base 0x400F.E000 Offset 0x024 Type RO, reset 0x0000.0011 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 USB0reservedUSB0PHYreserved ROROROROROROROROROROROROROROROROType 1000100000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:5 USB Module 0 PHY Present When set, indicates that the USB module 0 PHY is present. 0x1ROUSB0PHY4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3:2 USB Module 0 Present This field indicates that USB module 0 is present and specifies its capability. DescriptionsysValue NA USB0 is not present. 0x0 DEVICE USB0 is Device Only. 0x1 HOST USB0 is Device or Host. 0x2 OTG USB0 is OTG. 0x3 0x1ROUSB01:0 June 12, 2014426 Texas Instruments-Production Data System Control

Register119:DeviceCapabilities7(DC7),offset0x028 This register is predefined by the part and can be used to verify μDMA channel features. A 1 indicates the channel is available on this device; a 0 that the channel is only available on other devices in the family. Channels can have multiple assignments, see “Channel Assignments” on page 569 for more information. Important: This register is provided for legacy software support only. TheDMACHANSbit field in the DMAStatus(DMASTAT) register indicates the number of DMA channels. Device Capabilities 7 (DC7) Base 0x400F.E000 Offset 0x028 Type RO, reset 0xFFFF.FFFF 16171819202122232425262728293031 DMACH16DMACH17DMACH18DMACH19DMACH20DMACH21DMACH22DMACH23DMACH24DMACH25DMACH26DMACH27DMACH28DMACH29DMACH30reserved ROROROROROROROROROROROROROROROROType 1111111111111111Reset 0123456789101112131415 DMACH0DMACH1DMACH2DMACH3DMACH4DMACH5DMACH6DMACH7DMACH8DMACH9DMACH10DMACH11DMACH12DMACH13DMACH14DMACH15 ROROROROROROROROROROROROROROROROType 1111111111111111Reset DescriptionResetTypeNameBit/Field DMA Channel 31 When set, indicates μDMA channel 31 is available. 0x1ROreserved31 DMA Channel 30 When set, indicates μDMA channel 30 is available. 0x1RODMACH3030 DMA Channel 29 When set, indicates μDMA channel 29 is available. 0x1RODMACH2929 DMA Channel 28 When set, indicates μDMA channel 28 is available. 0x1RODMACH2828 DMA Channel 27 When set, indicates μDMA channel 27 is available. 0x1RODMACH2727 DMA Channel 26 When set, indicates μDMA channel 26 is available. 0x1RODMACH2626 DMA Channel 25 When set, indicates μDMA channel 25 is available. 0x1RODMACH2525 DMA Channel 24 When set, indicates μDMA channel 24 is available. 0x1RODMACH2424 DMA Channel 23 When set, indicates μDMA channel 23 is available. 0x1RODMACH2323 DMA Channel 22 When set, indicates μDMA channel 22 is available. 0x1RODMACH2222 427June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field DMA Channel 21 When set, indicates μDMA channel 21 is available. 0x1RODMACH2121 DMA Channel 20 When set, indicates μDMA channel 20 is available. 0x1RODMACH2020 DMA Channel 19 When set, indicates μDMA channel 19 is available. 0x1RODMACH1919 DMA Channel 18 When set, indicates μDMA channel 18 is available. 0x1RODMACH1818 DMA Channel 17 When set, indicates μDMA channel 17 is available. 0x1RODMACH1717 DMA Channel 16 When set, indicates μDMA channel 16 is available. 0x1RODMACH1616 DMA Channel 15 When set, indicates μDMA channel 15 is available. 0x1RODMACH1515 DMA Channel 14 When set, indicates μDMA channel 14 is available. 0x1RODMACH1414 DMA Channel 13 When set, indicates μDMA channel 13 is available. 0x1RODMACH1313 DMA Channel 12 When set, indicates μDMA channel 12 is available. 0x1RODMACH1212 DMA Channel 11 When set, indicates μDMA channel 11 is available. 0x1RODMACH1111 DMA Channel 10 When set, indicates μDMA channel 10 is available. 0x1RODMACH1010 DMA Channel 9 When set, indicates μDMA channel 9 is available. 0x1RODMACH99 DMA Channel 8 When set, indicates μDMA channel 8 is available. 0x1RODMACH88 DMA Channel 7 When set, indicates μDMA channel 7 is available. 0x1RODMACH77 DMA Channel 6 When set, indicates μDMA channel 6 is available. 0x1RODMACH66 DMA Channel 5 When set, indicates μDMA channel 5 is available. 0x1RODMACH55 DMA Channel 4 When set, indicates μDMA channel 4 is available. 0x1RODMACH44 June 12, 2014428 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field DMA Channel 3 When set, indicates μDMA channel 3 is available. 0x1RODMACH33 DMA Channel 2 When set, indicates μDMA channel 2 is available. 0x1RODMACH22 DMA Channel 1 When set, indicates μDMA channel 1 is available. 0x1RODMACH11 DMA Channel 0 When set, indicates μDMA channel 0 is available. 0x1RODMACH00 429June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register120:DeviceCapabilities8(DC8),offset0x02C This register is predefined by the part and can be used to verify features. Important: This register is provided for legacy software support only. The ADCPeripheralProperties(ADCPP) register should be used to determine how many input channels are available on the ADC module. A read of this register correctly identifies if legacy channels are present but software must use theADCPPregister to determine if a channel is present that is not supported by theDCnregisters. Device Capabilities 8 (DC8) Base 0x400F.E000 Offset 0x02C Type RO, reset 0xFFFF.FFFF 16171819202122232425262728293031 ADC1AIN0ADC1AIN1ADC1AIN2ADC1AIN3ADC1AIN4ADC1AIN5ADC1AIN6ADC1AIN7ADC1AIN8ADC1AIN9ADC1AIN10ADC1AIN11ADC1AIN12ADC1AIN13ADC1AIN14ADC1AIN15 ROROROROROROROROROROROROROROROROType 1111111111111111Reset 0123456789101112131415 ADC0AIN0ADC0AIN1ADC0AIN2ADC0AIN3ADC0AIN4ADC0AIN5ADC0AIN6ADC0AIN7ADC0AIN8ADC0AIN9ADC0AIN10ADC0AIN11ADC0AIN12ADC0AIN13ADC0AIN14ADC0AIN15 ROROROROROROROROROROROROROROROROType 1111111111111111Reset DescriptionResetTypeNameBit/Field ADC Module 1 AIN15 Pin Present When set, indicates that ADC module 1 input pin 15 is present. 0x1ROADC1AIN1531 ADC Module 1 AIN14 Pin Present When set, indicates that ADC module 1 input pin 14 is present. 0x1ROADC1AIN1430 ADC Module 1 AIN13 Pin Present When set, indicates that ADC module 1 input pin 13 is present. 0x1ROADC1AIN1329 ADC Module 1 AIN12 Pin Present When set, indicates that ADC module 1 input pin 12 is present. 0x1ROADC1AIN1228 ADC Module 1 AIN11 Pin Present When set, indicates that ADC module 1 input pin 11 is present. 0x1ROADC1AIN1127 ADC Module 1 AIN10 Pin Present When set, indicates that ADC module 1 input pin 10 is present. 0x1ROADC1AIN1026 ADC Module 1 AIN9 Pin Present When set, indicates that ADC module 1 input pin 9 is present. 0x1ROADC1AIN925 ADC Module 1 AIN8 Pin Present When set, indicates that ADC module 1 input pin 8 is present. 0x1ROADC1AIN824 ADC Module 1 AIN7 Pin Present When set, indicates that ADC module 1 input pin 7 is present. 0x1ROADC1AIN723 ADC Module 1 AIN6 Pin Present When set, indicates that ADC module 1 input pin 6 is present. 0x1ROADC1AIN622 June 12, 2014430 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field ADC Module 1 AIN5 Pin Present When set, indicates that ADC module 1 input pin 5 is present. 0x1ROADC1AIN521 ADC Module 1 AIN4 Pin Present When set, indicates that ADC module 1 input pin 4 is present. 0x1ROADC1AIN420 ADC Module 1 AIN3 Pin Present When set, indicates that ADC module 1 input pin 3 is present. 0x1ROADC1AIN319 ADC Module 1 AIN2 Pin Present When set, indicates that ADC module 1 input pin 2 is present. 0x1ROADC1AIN218 ADC Module 1 AIN1 Pin Present When set, indicates that ADC module 1 input pin 1 is present. 0x1ROADC1AIN117 ADC Module 1 AIN0 Pin Present When set, indicates that ADC module 1 input pin 0 is present. 0x1ROADC1AIN016 ADC Module 0 AIN15 Pin Present When set, indicates that ADC module 0 input pin 15 is present. 0x1ROADC0AIN1515 ADC Module 0 AIN14 Pin Present When set, indicates that ADC module 0 input pin 14 is present. 0x1ROADC0AIN1414 ADC Module 0 AIN13 Pin Present When set, indicates that ADC module 0 input pin 13 is present. 0x1ROADC0AIN1313 ADC Module 0 AIN12 Pin Present When set, indicates that ADC module 0 input pin 12 is present. 0x1ROADC0AIN1212 ADC Module 0 AIN11 Pin Present When set, indicates that ADC module 0 input pin 11 is present. 0x1ROADC0AIN1111 ADC Module 0 AIN10 Pin Present When set, indicates that ADC module 0 input pin 10 is present. 0x1ROADC0AIN1010 ADC Module 0 AIN9 Pin Present When set, indicates that ADC module 0 input pin 9 is present. 0x1ROADC0AIN99 ADC Module 0 AIN8 Pin Present When set, indicates that ADC module 0 input pin 8 is present. 0x1ROADC0AIN88 ADC Module 0 AIN7 Pin Present When set, indicates that ADC module 0 input pin 7 is present. 0x1ROADC0AIN77 ADC Module 0 AIN6 Pin Present When set, indicates that ADC module 0 input pin 6 is present. 0x1ROADC0AIN66 ADC Module 0 AIN5 Pin Present When set, indicates that ADC module 0 input pin 5 is present. 0x1ROADC0AIN55 ADC Module 0 AIN4 Pin Present When set, indicates that ADC module 0 input pin 4 is present. 0x1ROADC0AIN44 431June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field ADC Module 0 AIN3 Pin Present When set, indicates that ADC module 0 input pin 3 is present. 0x1ROADC0AIN33 ADC Module 0 AIN2 Pin Present When set, indicates that ADC module 0 input pin 2 is present. 0x1ROADC0AIN22 ADC Module 0 AIN1 Pin Present When set, indicates that ADC module 0 input pin 1 is present. 0x1ROADC0AIN11 ADC Module 0 AIN0 Pin Present When set, indicates that ADC module 0 input pin 0 is present. 0x1ROADC0AIN00 June 12, 2014432 Texas Instruments-Production Data System Control

Register121:SoftwareResetControl0(SRCR0),offset0x040 This register allows individual modules to be reset. Writes to this register are masked by the bits in the DeviceCapabilities1(DC1) register. Important: This register is provided for legacy software support only. The peripheral-specific Software Reset registers (such asSRWD) should be used to reset specific peripherals. A write to this legacy register also writes the corresponding bit in the peripheral-specific register. Any bits that are changed by writing to this legacy register can be read back correctly with a read of this register. Software must use the peripheral-specific registers to support modules that are not present in the legacy registers. If software uses a peripheral-specific register to write a legacy peripheral (such as Watchdog 1), the write causes proper operation, but the value of that bit is not reflected in this register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Software Reset Control 0 (SRCR0) Base 0x400F.E000 Offset 0x040 Type RO, reset 0x0000.0000 16171819202122232425262728293031 ADC0ADC1reservedCAN0reservedWDT1reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedWDT0reservedHIBreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:29 WDT1 Reset Control When this bit is set, Watchdog Timer module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROWDT128 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:25 CAN0 Reset Control When this bit is set, CAN module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROCAN024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:18 433June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field ADC1 Reset Control When this bit is set, ADC module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROADC117 ADC0 Reset Control When this bit is set, ADC module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROADC016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:7 HIB Reset Control When this bit is set, the Hibernation module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROHIB6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved5:4 WDT0 Reset Control When this bit is set, Watchdog Timer module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROWDT03 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2:0 June 12, 2014434 Texas Instruments-Production Data System Control

Register122:SoftwareResetControl1(SRCR1),offset0x044 This register allows individual modules to be reset. Writes to this register are masked by the bits in the DeviceCapabilities2(DC2) register. Important: This register is provided for legacy software support only. The peripheral-specific Software Reset registers (such asSRTIMER) should be used to reset specific peripherals. A write to this register also writes the corresponding bit in the peripheral-specific register. Any bits that are changed by writing to this register can be read back correctly with a read of this register. Software must use the peripheral-specific registers to support modules that are not present in the legacy registers. If software uses a peripheral-specific register to write a legacy peripheral (such as TIMER0), the write causes proper operation, but the value of that bit is not reflected in this register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Note that theSoftwareResetAnalogComparator(SRACMP) register has only one bit to set the analog comparator module. Resetting the module resets all the blocks. If any of theCOMPnbits are set, the entire analog comparator module is reset. It is not possible to reset the blocks individually. Software Reset Control 1 (SRCR1) Base 0x400F.E000 Offset 0x044 Type RO, reset 0x0000.0000 16171819202122232425262728293031 TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 UART0UART1UART2reservedSSI0SSI1reservedI2C0reservedI2C1reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:27 Analog Comp 2 Reset Control When this bit is set, Analog Comparator module 2 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROCOMP226 Analog Comp 1 Reset Control When this bit is set, Analog Comparator module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROCOMP125 435June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Analog Comp 0 Reset Control When this bit is set, Analog Comparator module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROCOMP024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:20 Timer 3 Reset Control Timer 3 Reset Control. When this bit is set, General-Purpose Timer module 3 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROTIMER319 Timer 2 Reset Control When this bit is set, General-Purpose Timer module 2 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROTIMER218 Timer 1 Reset Control When this bit is set, General-Purpose Timer module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROTIMER117 Timer 0 Reset Control When this bit is set, General-Purpose Timer module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROTIMER016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15 I2C1 Reset Control When this bit is set, I2C module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROI2C114 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved13 I2C0 Reset Control When this bit is set, I2C module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROI2C012 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved11:6 SSI1 Reset Control When this bit is set, SSI module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROSSI15 June 12, 2014436 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field SSI0 Reset Control When this bit is set, SSI module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROSSI04 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 UART2 Reset Control When this bit is set, UART module 2 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROUART22 UART1 Reset Control When this bit is set, UART module 1 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROUART11 UART0 Reset Control When this bit is set, UART module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROUART00 437June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register123:SoftwareResetControl2(SRCR2),offset0x048 This register allows individual modules to be reset. Writes to this register are masked by the bits in the DeviceCapabilities4(DC4) register. Important: This register is provided for legacy software support only. The peripheral-specific Software Reset registers (such asSRDMA) should be used to reset specific peripherals. A write to this legacy register also writes the corresponding bit in the peripheral-specific register. Any bits that are changed by writing to this register can be read back correctly with a read of this register. Software must use the peripheral-specific registers to support modules that are not present in the legacy registers. If software uses a peripheral-specific register to write a legacy peripheral (such as the μDMA), the write causes proper operation, but the value of that bit is not reflected in this register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Software Reset Control 2 (SRCR2) Base 0x400F.E000 Offset 0x048 Type RO, reset 0x0000.0000 16171819202122232425262728293031 USB0reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHGPIOJreservedUDMAreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:17 USB0 Reset Control When this bit is set, USB module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROUSB016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:14 Micro-DMA Reset Control When this bit is set, uDMA module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROUDMA13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12:9 June 12, 2014438 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field Port J Reset Control When this bit is set, Port J module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROGPIOJ8 Port H Reset Control When this bit is set, Port H module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROGPIOH7 Port G Reset Control When this bit is set, Port G module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROGPIOG6 Port F Reset Control When this bit is set, Port F module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROGPIOF5 Port E Reset Control When this bit is set, Port E module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROGPIOE4 Port D Reset Control When this bit is set, Port D module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROGPIOD3 Port C Reset Control When this bit is set, Port C module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROGPIOC2 Port B Reset Control When this bit is set, Port B module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROGPIOB1 Port A Reset Control When this bit is set, Port A module is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 0x0ROGPIOA0 439June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register124:RunModeClockGatingControlRegister0(RCGC0),offset 0x100 This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC0is the clock configuration register for running operation,SCGC0for Sleep operation, andDCGC0for Deep-Sleep operation. Setting the ACGbit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Note that there must be a delay of 3 system clocks after a module clock is enabled before any registers in that module are accessed. Important: This register is provided for legacy software support only. The peripheral-specific Run Mode Clock Gating Control registers (such asRCGCWD) should be used to reset specific peripherals. A write to this legacy register also writes the corresponding bit in the peripheral-specific register. Any bits that are changed by writing to this register can be read back correctly with a read of this register. Software must use the peripheral-specific registers to support modules that are not present in the legacy registers. If software uses a peripheral-specific register to write a legacy peripheral (such as Watchdog 1), the write causes proper operation, but the value of that bit is not reflected in this register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Likewise, theADCPeripheralConfiguration(ADCPC) register should be used to configure the ADC sample rate. However, to support legacy software, theMAXADCnSPD fields are available. A write to these legacy fields also writes the corresponding field in the peripheral-specific register. If a field is changed by writing to this register, it can be read back correctly with a read of this register. Software must use the peripheral-specific registers to support rates that are not available in this register. If software uses a peripheral-specific register to set the ADC rate, the write causes proper operation, but the value of that field is not reflected in this register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. June 12, 2014440 Texas Instruments-Production Data System Control

Run Mode Clock Gating Control Register 0 (RCGC0) Base 0x400F.E000 Offset 0x100 Type RO, reset 0x0000.0040 16171819202122232425262728293031 ADC0ADC1reservedCAN0reservedWDT1reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedWDT0reservedHIBreservedMAXADC0SPDMAXADC1SPDreserved ROROROROROROROROROROROROROROROROType 0000001000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:29 WDT1 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROWDT128 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:25 CAN0 Clock Gating Control This bit controls the clock gating for CAN module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROCAN024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:18 ADC1 Clock Gating Control This bit controls the clock gating for SAR ADC module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROADC117 ADC0 Clock Gating Control This bit controls the clock gating for ADC module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROADC016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:12 441June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field ADC1 Sample Speed This field sets the rate at which ADC module 1 samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting theMAXADC1SPDbit as follows (all other encodings are reserved): DescriptionValue 125K samples/second0x0 250K samples/second0x1 500K samples/second0x2 1M samples/second0x3 0x0ROMAXADC1SPD11:10 ADC0 Sample Speed This field sets the rate at which ADC0 samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting theMAXADC0SPDbit as follows (all other encodings are reserved): DescriptionValue 125K samples/second0x0 250K samples/second0x1 500K samples/second0x2 1M samples/second0x3 0x0ROMAXADC0SPD9:8 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved7 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x1ROHIB6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved5:4 WDT0 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROWDT03 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2:0 June 12, 2014442 Texas Instruments-Production Data System Control

Register125:RunModeClockGatingControlRegister1(RCGC1),offset 0x104 This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC1is the clock configuration register for running operation,SCGC1for Sleep operation, andDCGC1for Deep-Sleep operation. Setting the ACGbit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Note that there must be a delay of 3 system clocks after a module clock is enabled before any registers in that module are accessed. Important: This register is provided for legacy software support only. The peripheral-specific Run Mode Clock Gating Control registers (such asRCGCTIMER) should be used to reset specific peripherals. A write to this legacy register also writes the corresponding bit in the peripheral-specific register. Any bits that are changed by writing to this register can be read back correctly with a read of this register. Software must use the peripheral-specific registers to support modules that are not present in the legacy registers. If software uses a peripheral-specific register to write a legacy peripheral (such as Timer 0), the write causes proper operation, but the value of that bit is not reflected in this register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Run Mode Clock Gating Control Register 1 (RCGC1) Base 0x400F.E000 Offset 0x104 Type RO, reset 0x0000.0000 16171819202122232425262728293031 TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 UART0UART1UART2reservedSSI0SSI1reservedI2C0reservedI2C1reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:27 443June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROCOMP226 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROCOMP125 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROCOMP024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:20 Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROTIMER319 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROTIMER218 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROTIMER117 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROTIMER016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROI2C114 June 12, 2014444 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved13 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROI2C012 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved11:6 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROSSI15 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROSSI04 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUART22 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUART11 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUART00 445June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register126:RunModeClockGatingControlRegister2(RCGC2),offset 0x108 This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC2is the clock configuration register for running operation,SCGC2for Sleep operation, andDCGC2for Deep-Sleep operation. Setting the ACGbit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Note that there must be a delay of 3 system clocks after a module clock is enabled before any registers in that module are accessed. Important: This register is provided for legacy software support only. The peripheral-specific Run Mode Clock Gating Control registers (such asRCGCDMA) should be used to reset specific peripherals. A write to this legacy register also writes the corresponding bit in the peripheral-specific register. Any bits that are changed by writing to this register can be read back correctly with a read of this register. Software must use the peripheral-specific registers to support modules that are not present in the legacy registers. If software uses a peripheral-specific register to write a legacy peripheral (such as the μDMA), the write causes proper operation, but the value of that bit is not reflected in this register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Run Mode Clock Gating Control Register 2 (RCGC2) Base 0x400F.E000 Offset 0x108 Type RO, reset 0x0000.0000 16171819202122232425262728293031 USB0reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHGPIOJreservedUDMAreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:17 June 12, 2014446 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field USB0 Clock Gating Control This bit controls the clock gating for USB module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUSB016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:14 Micro-DMA Clock Gating Control This bit controls the clock gating for micro-DMA. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUDMA13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12:9 Port J Clock Gating Control This bit controls the clock gating for Port J. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOJ8 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOH7 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOG6 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOF5 Port E Clock Gating Control Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOE4 Port D Clock Gating Control Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOD3 447June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOC2 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOB1 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOA0 June 12, 2014448 Texas Instruments-Production Data System Control

Register127:SleepModeClockGatingControlRegister0(SCGC0),offset 0x110 This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC0is the clock configuration register for running operation,SCGC0for Sleep operation, andDCGC0for Deep-Sleep operation. Setting the ACGbit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Important: This register is provided for legacy software support only. The peripheral-specific Sleep Mode Clock Gating Control registers (such asSCGCWD) should be used to reset specific peripherals. A write to this legacy register also writes the corresponding bit in the peripheral-specific register. Any bits that are changed by writing to this register can be read back correctly with a read of this register. Software must use the peripheral-specific registers to support modules that are not present in the legacy registers. If software uses a peripheral-specific register to write a legacy peripheral (such as Watchdog 1), the write causes proper operation, but the value of that bit is not reflected in this register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Sleep Mode Clock Gating Control Register 0 (SCGC0) Base 0x400F.E000 Offset 0x110 Type RO, reset 0x0000.0040 16171819202122232425262728293031 ADC0ADC1reservedCAN0reservedWDT1reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedWDT0reservedHIBreserved ROROROROROROROROROROROROROROROROType 0000001000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:29 WDT1 Clock Gating Control This bit controls the clock gating for Watchdog Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROWDT128 449June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:25 CAN0 Clock Gating Control This bit controls the clock gating for CAN module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROCAN024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:18 ADC1 Clock Gating Control This bit controls the clock gating for ADC module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROADC117 ADC0 Clock Gating Control This bit controls the clock gating for ADC module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROADC016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:7 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x1ROHIB6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved5:4 WDT0 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROWDT03 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2:0 June 12, 2014450 Texas Instruments-Production Data System Control

Register128:SleepModeClockGatingControlRegister1(SCGC1),offset 0x114 This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC1is the clock configuration register for running operation,SCGC1for Sleep operation, andDCGC1for Deep-Sleep operation. Setting the ACGbit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Important: This register is provided for legacy software support only. The peripheral-specific Sleep Mode Clock Gating Control registers (such as SCGCTIMER) should be used to reset specific peripherals. A write to this legacy register also writes the corresponding bit in the peripheral-specific register. Any bits that are changed by writing to this register can be read back correctly with a read of this register. Software must use the peripheral-specific registers to support modules that are not present in the legacy registers. If software uses a peripheral-specific register to write a legacy peripheral (such as Timer 0), the write causes proper operation, but the value of that bit is not reflected in this register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Sleep Mode Clock Gating Control Register 1 (SCGC1) Base 0x400F.E000 Offset 0x114 Type RO, reset 0x0000.0000 16171819202122232425262728293031 TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 UART0UART1UART2reservedSSI0SSI1reservedI2C0reservedI2C1reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:27 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROCOMP226 451June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROCOMP125 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROCOMP024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:20 Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROTIMER319 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROTIMER218 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROTIMER117 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROTIMER016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROI2C114 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved13 June 12, 2014452 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROI2C012 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved11:6 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROSSI15 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROSSI04 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUART22 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUART11 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUART00 453June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register129:SleepModeClockGatingControlRegister2(SCGC2),offset 0x118 This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC2is the clock configuration register for running operation,SCGC2for Sleep operation, andDCGC2for Deep-Sleep operation. Setting the ACGbit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Important: This register is provided for legacy software support only. The peripheral-specific Sleep Mode Clock Gating Control registers (such asSCGCDMA) should be used to reset specific peripherals. A write to this legacy register also writes the corresponding bit in the peripheral-specific register. Any bits that are changed by writing to this register can be read back correctly with a read of this register. Software must use the peripheral-specific registers to support modules that are not present in the legacy registers. If software uses a peripheral-specific register to write a legacy peripheral (such as the μDMA), the write causes proper operation, but the value of that bit is not reflected in this register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Sleep Mode Clock Gating Control Register 2 (SCGC2) Base 0x400F.E000 Offset 0x118 Type RO, reset 0x0000.0000 16171819202122232425262728293031 USB0reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHGPIOJreservedUDMAreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:17 USB0 Clock Gating Control This bit controls the clock gating for USB module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUSB016 June 12, 2014454 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:14 Micro-DMA Clock Gating Control This bit controls the clock gating for micro-DMA. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUDMA13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12:9 Port J Clock Gating Control This bit controls the clock gating for Port J. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOJ8 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOH7 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOG6 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOF5 Port E Clock Gating Control Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOE4 Port D Clock Gating Control Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOD3 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOC2 455June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOB1 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOA0 June 12, 2014456 Texas Instruments-Production Data System Control

Register130:DeepSleepModeClockGatingControlRegister0(DCGC0), offset0x120 This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC0is the clock configuration register for running operation,SCGC0for Sleep operation, andDCGC0for Deep-Sleep operation. Setting the ACGbit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Important: This register is provided for legacy software support only. The peripheral-specific Deep Sleep Mode Clock Gating Control registers (such as DCGCWD) should be used to reset specific peripherals. A write to this legacy register also writes the corresponding bit in the peripheral-specific register. Any bits that are changed by writing to this register can be read back correctly with a read of this register. Software must use the peripheral-specific registers to support modules that are not present in the legacy registers. If software uses a peripheral-specific register to write a legacy peripheral (such as Watchdog 1), the write causes proper operation, but the value of that bit is not reflected in this register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Base 0x400F.E000 Offset 0x120 Type RO, reset 0x0000.0040 16171819202122232425262728293031 ADC0ADC1reservedCAN0reservedWDT1reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 reservedWDT0reservedHIBreserved ROROROROROROROROROROROROROROROROType 0000001000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:29 WDT1 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROWDT128 457June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved27:25 CAN0 Clock Gating Control This bit controls the clock gating for CAN module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROCAN024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:18 ADC1 Clock Gating Control This bit controls the clock gating for ADC module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROADC117 ADC0 Clock Gating Control This bit controls the clock gating for ADC module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROADC016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:7 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x1ROHIB6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved5:4 WDT0 Clock Gating Control This bit controls the clock gating for the Watchdog Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROWDT03 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2:0 June 12, 2014458 Texas Instruments-Production Data System Control

Register131:Deep-SleepModeClockGatingControlRegister1(DCGC1), offset0x124 This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC1is the clock configuration register for running operation,SCGC1for Sleep operation, andDCGC1for Deep-Sleep operation. Setting the ACGbit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Important: This register is provided for legacy software support only. The peripheral-specific Deep Sleep Mode Clock Gating Control registers (such as DCGCTIMER) should be used to reset specific peripherals. A write to this legacy register also writes the corresponding bit in the peripheral-specific register. Any bits that are changed by writing to this register can be read back correctly with a read of this register. Software must use the peripheral-specific registers to support modules that are not present in the legacy registers. If software uses a peripheral-specific register to write a legacy peripheral (such as Timer 0), the write causes proper operation, but the value of that bit is not reflected in this register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1) Base 0x400F.E000 Offset 0x124 Type RO, reset 0x0000.0000 16171819202122232425262728293031 TIMER0TIMER1TIMER2TIMER3reservedCOMP0COMP1COMP2reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 UART0UART1UART2reservedSSI0SSI1reservedI2C0reservedI2C1reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:27 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROCOMP226 459June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROCOMP125 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROCOMP024 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved23:20 Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROTIMER319 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROTIMER218 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROTIMER117 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROTIMER016 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROI2C114 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved13 June 12, 2014460 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROI2C012 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved11:6 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROSSI15 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROSSI04 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved3 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUART22 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUART11 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUART00 461June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register132:DeepSleepModeClockGatingControlRegister2(DCGC2), offset0x128 This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and future parts.RCGC2is the clock configuration register for running operation,SCGC2for Sleep operation, andDCGC2for Deep-Sleep operation. Setting the ACGbit in theRun-ModeClockConfiguration(RCC) register specifies that the system uses sleep modes. Important: This register is provided for legacy software support only. The peripheral-specific Deep Sleep Mode Clock Gating Control registers (such as DCGCDMA) should be used to reset specific peripherals. A write to this legacy register also writes the corresponding bit in the peripheral-specific register. Any bits that are changed by writing to this register can be read back correctly with a read of this register. Software must use the peripheral-specific registers to support modules that are not present in the legacy registers. If software uses a peripheral-specific register to write a legacy peripheral (such as the μDMA), the write causes proper operation, but the value of that bit is not reflected in this register. If software uses both legacy and peripheral-specific register accesses, the peripheral-specific registers must be accessed by read-modify-write operations that affect only peripherals that are not present in the legacy registers. In this manner, both the peripheral-specific and legacy registers have coherent information. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Base 0x400F.E000 Offset 0x128 Type RO, reset 0x0000.0000 16171819202122232425262728293031 USB0reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHGPIOJreservedUDMAreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:17 USB0 Clock Gating Control This bit controls the clock gating for USB module 0. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUSB016 June 12, 2014462 Texas Instruments-Production Data System Control

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:14 Micro-DMA Clock Gating Control This bit controls the clock gating for micro-DMA. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROUDMA13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12:9 Port J Clock Gating Control This bit controls the clock gating for Port J. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOJ8 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOH7 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOG6 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOF5 Port E Clock Gating Control Port E Clock Gating Control. This bit controls the clock gating for Port E. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOE4 Port D Clock Gating Control Port D Clock Gating Control. This bit controls the clock gating for Port D. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOD3 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOC2 463June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOB1 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled. If the module is unclocked, a read or write to the module generates a bus fault. 0x0ROGPIOA0 June 12, 2014464 Texas Instruments-Production Data System Control

Register133:DeviceCapabilities9(DC9),offset0x190 This register is predefined by the part and can be used to verify ADC digital comparator features. Important: This register is provided for legacy software support only. The ADCPeripheralProperties(ADCPP) register should be used to determine how many digital comparators are available on the ADC module. A read of this register correctly identifies if legacy comparators are present. Software must use theADCPP register to determine if a comparator that is not supported by theDCnregisters is present. Device Capabilities 9 (DC9) Base 0x400F.E000 Offset 0x190 Type RO, reset 0x00FF.00FF 16171819202122232425262728293031 ADC1DC0ADC1DC1ADC1DC2ADC1DC3ADC1DC4ADC1DC5ADC1DC6ADC1DC7reserved ROROROROROROROROROROROROROROROROType 1111111100000000Reset 0123456789101112131415 ADC0DC0ADC0DC1ADC0DC2ADC0DC3ADC0DC4ADC0DC5ADC0DC6ADC0DC7reserved ROROROROROROROROROROROROROROROROType 1111111100000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:24 ADC1 DC7 Present When set, indicates that ADC module 1 Digital Comparator 7 is present. 0x1ROADC1DC723 ADC1 DC6 Present When set, indicates that ADC module 1 Digital Comparator 6 is present. 0x1ROADC1DC622 ADC1 DC5 Present When set, indicates that ADC module 1 Digital Comparator 5 is present. 0x1ROADC1DC521 ADC1 DC4 Present When set, indicates that ADC module 1 Digital Comparator 4 is present. 0x1ROADC1DC420 ADC1 DC3 Present When set, indicates that ADC module 1 Digital Comparator 3 is present. 0x1ROADC1DC319 ADC1 DC2 Present When set, indicates that ADC module 1 Digital Comparator 2 is present. 0x1ROADC1DC218 ADC1 DC1 Present When set, indicates that ADC module 1 Digital Comparator 1 is present. 0x1ROADC1DC117 ADC1 DC0 Present When set, indicates that ADC module 1 Digital Comparator 0 is present. 0x1ROADC1DC016 465June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15:8 ADC0 DC7 Present When set, indicates that ADC module 0 Digital Comparator 7 is present. 0x1ROADC0DC77 ADC0 DC6 Present When set, indicates that ADC module 0 Digital Comparator 6 is present. 0x1ROADC0DC66 ADC0 DC5 Present When set, indicates that ADC module 0 Digital Comparator 5 is present. 0x1ROADC0DC55 ADC0 DC4 Present When set, indicates that ADC module 0 Digital Comparator 4 is present. 0x1ROADC0DC44 ADC0 DC3 Present When set, indicates that ADC module 0 Digital Comparator 3 is present. 0x1ROADC0DC33 ADC0 DC2 Present When set, indicates that ADC module 0 Digital Comparator 2 is present. 0x1ROADC0DC22 ADC0 DC1 Present When set, indicates that ADC module 0 Digital Comparator 1 is present. 0x1ROADC0DC11 ADC0 DC0 Present When set, indicates that ADC module 0 Digital Comparator 0 is present. 0x1ROADC0DC00 June 12, 2014466 Texas Instruments-Production Data System Control

Register134:Non-VolatileMemoryInformation(NVMSTAT),offset0x1A0 This register is predefined by the part and can be used to verify features. Important: This register is provided for legacy software support only. The ROMThird-PartySoftware(ROMSWMAP) register should be used to determine the presence of third-party software in the on-chip ROM on this microcontroller. A read of theTPSWbit in this register correctly identifies the presence of legacy third-party software. Software should use theROMSWMAPregister for software that is not on legacy devices. Non-Volatile Memory Information (NVMSTAT) Base 0x400F.E000 Offset 0x1A0 Type RO, reset 0x0000.0001 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 FWBreserved ROROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:1

32 Word Flash Write Buffer Available

When set, indicates that the 32 word Flash memory write buffer feature is available. 0x1ROFWB0 467June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

6 SystemExceptionModule

This module is an AHB peripheral that handles system-level Cortex-M4 FPU exceptions. For functions with registers mapped into this aperture, if the function is not available on a device, then all writes to the associated registers are ignored and reads return zeros.

6.1 FunctionalDescription

The System Exception module provides control and status of the system-level interrupts. All the interrupt events are ORed together before being sent to the interrupt controller, so the System Exception module can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the SystemExceptionMaskedInterruptStatus(SYSEXCMIS) register. The interrupt events that can trigger a controller-level interrupt are defined in theSystemExceptionInterruptMask(SYSEXCIM) register by setting the corresponding interrupt mask bits. If interrupts are not used, the raw interrupt status is always visible via theSystemExceptionRawInterruptStatus(SYSEXCRIS) register. Interrupts are always cleared (for both theSYSEXCMISand SYSEXCRISregisters) by writing a 1 to the corresponding bit in theSystemExceptionInterruptClear(SYSEXCIC) register.

6.2 RegisterMap

Table 6-1 on page 468 lists the System Exception module registers. The offset listed is a hexadecimal increment to the register's address, relative to the System Exception base address of 0x400F.9000. Note: Spaces in the System Exception register space that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Table6-1.SystemExceptionRegisterMap See pageDescriptionResetTypeNameOffset 469System Exception Raw Interrupt Status0x0000.0000ROSYSEXCRIS0x000 471System Exception Interrupt Mask0x0000.0000RWSYSEXCIM0x004 473System Exception Masked Interrupt Status0x0000.0000ROSYSEXCMIS0x008 475System Exception Interrupt Clear0x0000.0000W1CSYSEXCIC0x00C

6.3 RegisterDescriptions

All addresses given are relative to the System Exception base address of 0x400F.9000. June 12, 2014468 Texas Instruments-Production Data System Exception Module

Register1:SystemExceptionRawInterruptStatus(SYSEXCRIS),offset0x000 The SYSEXCRISregister is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect. System Exception Raw Interrupt Status (SYSEXCRIS) Base 0x400F.9000 Offset 0x000 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 FPIDCRISFPDZCRISFPIOCRISFPUFCRISFPOFCRISFPIXCRISreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:6 Floating-Point Inexact Exception Raw Interrupt Status DescriptionValue No interrupt0 A floating-point inexact exception has occurred.1 This bit is cleared by writing a 1 to theIXCICbit in theSYSEXCIC register. 0ROFPIXCRIS5 Floating-Point Overflow Exception Raw Interrupt Status DescriptionValue No interrupt0 A floating-point overflow exception has occurred.1 This bit is cleared by writing a 1 to theOFCICbit in theSYSEXCIC register. 0ROFPOFCRIS4 Floating-Point Underflow Exception Raw Interrupt Status DescriptionValue No interrupt0 A floating-point underflow exception has occurred.1 This bit is cleared by writing a 1 to theUFCICbit in theSYSEXCIC register. 0ROFPUFCRIS3 469June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Floating-Point Invalid Operation Raw Interrupt Status DescriptionValue No interrupt0 A floating-point invalid operation exception has occurred.1 This bit is cleared by writing a 1 to theIOCICbit in theSYSEXCIC register. 0ROFPIOCRIS2 Floating-Point Divide By 0 Exception Raw Interrupt Status DescriptionValue No interrupt0 A floating-point divide by 0 exception has occurred.1 This bit is cleared by writing a 1 to theDZCICbit in theSYSEXCIC register. 0ROFPDZCRIS1 Floating-Point Input Denormal Exception Raw Interrupt Status DescriptionValue No interrupt0 A floating-point input denormal exception has occurred.1 This bit is cleared by writing a 1 to theIDCICbit in theSYSEXCIC register. 0ROFPIDCRIS0 June 12, 2014470 Texas Instruments-Production Data System Exception Module

Register2:SystemExceptionInterruptMask(SYSEXCIM),offset0x004 The SYSEXCIMregister is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit prevents the raw interrupt signal from being sent to the interrupt controller. System Exception Interrupt Mask (SYSEXCIM) Base 0x400F.9000 Offset 0x004 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset 0123456789101112131415 FPIDCIMFPDZCIMFPIOCIMFPUFCIMFPOFCIMFPIXCIMreserved RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00RWreserved31:6 Floating-Point Inexact Exception Interrupt Mask DescriptionValue The FPIXCRISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when the FPISCRISbit in theSYSEXCRISregister is set. 0RWFPIXCIM5 Floating-Point Overflow Exception Interrupt Mask DescriptionValue The FPOFCISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when the FPOFCRISbit in theSYSEXCRISregister is set. 0RWFPOFCIM4 Floating-Point Underflow Exception Interrupt Mask DescriptionValue The FPUFCRISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when the FPUFCRISbit in theSYSEXCRISregister is set. 0RWFPUFCIM3 471June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Floating-Point Invalid Operation Interrupt Mask DescriptionValue The FPIOCRISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when the FPIOCRISbit in theSYSEXCRISregister is set. 0RWFPIOCIM2 Floating-Point Divide By 0 Exception Interrupt Mask DescriptionValue The FPDZCRISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when the FPDZCRISbit in theSYSEXCRISregister is set. 0RWFPDZCIM1 Floating-Point Input Denormal Exception Interrupt Mask DescriptionValue The FPIDCRISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when the FPIDCRISbit in theSYSEXCRISregister is set. 0RWFPIDCIM0 June 12, 2014472 Texas Instruments-Production Data System Exception Module

Register3:SystemExceptionMaskedInterruptStatus(SYSEXCMIS),offset 0x008 The SYSEXCMISregister is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. System Exception Masked Interrupt Status (SYSEXCMIS) Base 0x400F.9000 Offset 0x008 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 FPIDCMISFPDZCMISFPIOCMISFPUFCMISFPOFCMISFPIXCMISreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00ROreserved31:6 Floating-Point Inexact Exception Masked Interrupt Status DescriptionValue An interrupt has not occurred or is masked.0 An unmasked interrupt was signaled due to an inexact exception. This bit is cleared by writing a 1 to theFPIXCICbit in theSYSEXCIC register. 0ROFPIXCMIS5 Floating-Point Overflow Exception Masked Interrupt Status DescriptionValue An interrupt has not occurred or is masked.0 An unmasked interrupt was signaled due to an overflow exception. This bit is cleared by writing a 1 to theFPOFCICbit in theSYSEXCIC register. 0ROFPOFCMIS4 Floating-Point Underflow Exception Masked Interrupt Status DescriptionValue An interrupt has not occurred or is masked.0 An unmasked interrupt was signaled due to an underflow exception. This bit is cleared by writing a 1 to theFPUFCICbit in theSYSEXCIC register. 0ROFPUFCMIS3 473June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Floating-Point Invalid Operation Masked Interrupt Status DescriptionValue An interrupt has not occurred or is masked.0 An unmasked interrupt was signaled due to an invalid operation.1 This bit is cleared by writing a 1 to theFPIOCICbit in theSYSEXCIC register. 0ROFPIOCMIS2 Floating-Point Divide By 0 Exception Masked Interrupt Status DescriptionValue An interrupt has not occurred or is masked.0 An unmasked interrupt was signaled due to a divide by 0 exception. This bit is cleared by writing a 1 to theFPDZCICbit in theSYSEXCIC register. 0ROFPDZCMIS1 Floating-Point Input Denormal Exception Masked Interrupt Status DescriptionValue An interrupt has not occurred or is masked.0 An unmasked interrupt was signaled due to an input denormal exception. This bit is cleared by writing a 1 to theFPIDCICbit in theSYSEXCIC register. 0ROFPIDCMIS0 June 12, 2014474 Texas Instruments-Production Data System Exception Module

Register4:SystemExceptionInterruptClear(SYSEXCIC),offset0x00C The SYSEXCICregister is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. System Exception Interrupt Clear (SYSEXCIC) Base 0x400F.9000 Offset 0x00C Type W1C, reset 0x0000.0000 16171819202122232425262728293031 reserved W1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CType 0000000000000000Reset 0123456789101112131415 FPIDCICFPDZCICFPIOCICFPUFCICFPOFCICFPIXCICreserved W1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CW1CType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.00W1Creserved31:6 Floating-Point Inexact Exception Interrupt Clear Writing a 1 to this bit clears theFPIXCRISbit in theSYSEXCRISregister and theFPIXCMISbit in theSYSEXCMISregister. 0W1CFPIXCIC5 Floating-Point Overflow Exception Interrupt Clear Writing a 1 to this bit clears theFPOFCRISbit in theSYSEXCRISregister and theFPOFCMISbit in theSYSEXCMISregister. 0W1CFPOFCIC4 Floating-Point Underflow Exception Interrupt Clear Writing a 1 to this bit clears theFPUFCRISbit in theSYSEXCRISregister and theFPUFCMISbit in theSYSEXCMISregister. 0W1CFPUFCIC3 Floating-Point Invalid Operation Interrupt Clear Writing a 1 to this bit clears theFPIOCRISbit in theSYSEXCRISregister and theFPIOCMISbit in theSYSEXCMISregister. 0W1CFPIOCIC2 Floating-Point Divide By 0 Exception Interrupt Clear Writing a 1 to this bit clears theFPDZCRISbit in theSYSEXCRISregister and theFPDZCMISbit in theSYSEXCMISregister. 0W1CFPDZCIC1 Floating-Point Input Denormal Exception Interrupt Clear Writing a 1 to this bit clears theFPIDCRISbit in theSYSEXCRISregister and theFPIDCMISbit in theSYSEXCMISregister. 0W1CFPIDCIC0 475June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

7 HibernationModule

The Hibernation Module manages removal and restoration of power to provide a means for reducing system power consumption. When the processor and peripherals are idle, power can be completely removed with only the Hibernation module remaining powered. Power can be restored based on an external signal or at a certain time using the built-in Real-Time Clock (RTC). The Hibernation module can be independently supplied from an external battery or an auxiliary power supply. The Hibernation module has the following features: ■ 32-bit real-time seconds counter (RTC) with 1/32,768 second resolution and a 15-bit sub-seconds counter – 32-bit RTC seconds match register and a 15-bit sub seconds match for timed wake-up and interrupt generation with 1/32,768 second resolution – RTC predivider trim for making fine adjustments to the clock rate ■ Two mechanisms for power control – System power control using discrete external regulator – On-chip power control using internal switches under register control ■ Dedicated pin for waking using an external signal ■ RTC operational and hibernation memory valid as long as VDD or VBAT is valid ■ Low-battery detection, signaling, and interrupt generation, with optional wake on low battery ■ GPIO pin state can be retained during hibernation ■ Clock source from a 32.768-kHz external crystal or oscillator ■ Sixteen 32-bit words of battery-backed memory to save state during hibernation ■ Programmable interrupts for: – RTC match – External wake – Low battery June 12, 2014476 Texas Instruments-Production Data Hibernation Module

7.1 BlockDiagram

Figure7-1.HibernationModuleBlockDiagram HIBIM HIBRIS HIBMIS HIBIC HIBR TCT Pre-DividerXOSC0 XOSC1 HIBCTL.CLK32EN HIBR TCC HIBR TCLD HIBR TCM0 HIBR TCSS R TC Interrupts Power Sequence Logic Low Battery Detect LOWBA T V BA T HIBCTL.PINWEN HIBCTL.R TCWEN HIBCTL.V ABOR T Battery-Backed Memory 16 words HIBDA T A HIBCTL.HIBREQ W AKE HIB Clock Source for System Clock Interrupts to CPU HIBCTL.R TCEN MA TCH HIBCTL.BA TCHK HIBCTL.VBA TSEL HIBCTL.BA TWKEN

7.2 SignalDescription

The following table lists the external signals of the Hibernation module and describes the function of each. Table7-1.HibernateSignals(100LQFP) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName GND for the Hibernation oscillator. When using a crystal clock source, this pin should be connected to digital ground along with the crystal load capacitors. When using an external oscillator, this pin should be connected to digital ground. Power-fixed53GNDX An output that indicates the processor is in Hibernate mode. TTLOfixed51HIB Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply. Power-fixed55VBAT An external input that brings the processor out of Hibernate mode when asserted. TTLIfixed50WAKE 477June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table7-1.HibernateSignals(100LQFP) (continued) DescriptionBufferTypeaPinTypePinMux/Pin Assignment PinNumberPinName Hibernation module oscillator crystal input or an external clock reference input. Note that this is either a 32.768-kHz crystal or a 32.768-kHz oscillator for the Hibernation module RTC. AnalogIfixed52XOSC0 Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. AnalogOfixed54XOSC1 a. The TTL designation indicates the pin has TTL-compatible voltage levels.

7.3 FunctionalDescription

The Hibernation module provides two mechanisms for power control: ■ The first mechanism uses internal switches to control power to the Cortex-M4F as well as to most analog and digital functions while retaining I/O pin power (VDD3ON mode). ■ The second mechanism controls the power to the microcontroller with a control signal (HIB ) that signals an external voltage regulator to turn on or off. The Hibernation module power source is determined dynamically. The supply voltage of the Hibernation module is the larger of the main voltage source (VDD) or the battery/auxilliary voltage source (VBAT). The Hibernation module also has an independent clock source to maintain a real-time clock (RTC) when the system clock is powered down. Hibernate mode can be entered through one of two ways: ■ The user initiates hibernation by setting theHIBREQbit in theHibernationControl(HIBCTL) register ■ Power is arbitrarily removed from VDD while a valid VBAT is applied Once in hibernation, the module signals an external voltage regulator to turn the power back on when an external pin (WAKE ) is asserted or when the internal RTC reaches a certain value. The Hibernation module can also detect when the battery voltage is low and optionally prevent hibernation or wake from hibernation when the battery voltage falls below a certain threshold. When waking from hibernation, theHIB signal is deasserted. The return of VDD causes a POR to be executed. The time from when theWAKEsignal is asserted to when code begins execution is equal to the wake-up time (tWAKE_TO_HIB) plus the power-on reset time (TPOR).

7.3.1 RegisterAccessTiming

Because the Hibernation module has an independent clocking domain, hibernation registers must be written only with a timing gap between accesses. The delay time is tHIB_REG_ACCESS, therefore software must guarantee that this delay is inserted between back-to-back writes to Hibernation registers or between a write followed by a read. TheWCinterrupt in theHIBMISregister can be used to notify the application when the Hibernation modules registers can be accessed. Alternatively, software may make use of theWRCbit in theHibernationControl(HIBCTL) register to ensure that the required timing gap has elapsed. This bit is cleared on a write operation and set once the write completes, indicating to software that another write or read may be started safely. Software should poll HIBCTLfor WRC=1 prior to accessing any hibernation register. June 12, 2014478 Texas Instruments-Production Data Hibernation Module

Back-to-back reads from Hibernation module registers have no timing restrictions. Reads are performed at the full peripheral clock rate.

7.3.2 HibernationClockSource

In systems where the Hibernation module is used, the module must be clocked by an external source that is independent from the main system clock, even if the RTC feature is not used. An external oscillator or crystal is used for this purpose. To use a crystal, a 32.768-kHz crystal is connected to the XOSC0and XOSC1pins. Alternatively, a 32.768-kHz oscillator can be connected to theXOSC0 pin, leavingXOSC1unconnected. Care must be taken that the voltage amplitude of the 32.768-kHz oscillator is less than VBAT, otherwise, the Hibernation module may draw power from the oscillator and not VBAT during hibernation. See Figure 7-2 on page 479 and Figure 7-3 on page 480. The Hibernation clock source is enabled by setting theCLK32ENbit of theHIBCTLregister. The CLK32ENbit must be set before accessing any other Hibernation module register. If a crystal is used for the clock source, the software must leave a delay of tHIBOSC_START after writing to the CLK32ENbit and before any other accesses to the Hibernation module registers. The delay allows the crystal to power up and stabilize. If an external oscillator is used for the clock source, no delay is needed. When using an external clock source, theOSCBYPbit in theHIBCTLregister should be set. When using a crystal clock source, theGNDXpin should be connected to digital ground along with the crystal load capacitors, as shown in Figure 7-2 on page 479. When using an external clock source, theGNDXpin should be connected to digital ground. Note: In the figures below the parameters RBAT and CBAT have recommended values of 51Ω ±5% and 0.1µF ±5%, respectively. See “Hibernation Module” on page 1216 for more information. Figure7-2.UsingaCrystalastheHibernationClockSourcewithaSingleBatterySource Open drain external wake up circuit BatteryGND C 2C 1 X 1 VB A T EN Input V oltage Regulator or Switch XOSC1 XOSC0 VDD HIB W AKE OU TIN R PU GNDX R BA T C BA T T iva™ Microcontroller Note: Some devices may not supply theGNDXsignal. IfGNDXis absent, the crystal load capacitors can be tied to GND externally. See “Signal Tables” on page 1161 for pins specific to your device. X1 = Crystal frequency is fXOSC_XTAL. C1,2 = Capacitor value derived from crystal vendor load capacitance specifications. RPU = Pull-up resistor is 200 kΩ RBAT = 51Ω ±5% CBAT = 0.1µF ±20% See “Hibernation Clock Source Specifications” on page 1208 for specific parameter values. 479June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Figure7-3.UsingaDedicatedOscillatorastheHibernationClockSourcewithVDD3ONMode Open drain external wake up circuit GND Input V oltage Regulator Clock Source (f EXT_OSC ) N.C. XOSC1 XOSC0 VDD HIB W AKE VB A T OU TIN R PU GNDX Battery R BA T C BA T T iva™ Microcontroller Note: Some devices may not supply theGNDX, WAKEor HIBsignals. See “Signal Tables” on page 1161 for pins specific to your device. RPU = Pull-up resistor is 1 MΩ RBAT = 51Ω ±5% CBAT = 0.1µF ±20%

7.3.3 SystemImplementation

Several different system configurations are possible when using the Hibernation module: ■ Using a single battery source, where the battery provides both VDD and VBAT, as shown in Figure 7-2 on page 479. ■ Using the VDD3ON mode, where VDD continues to be powered in hibernation, allowing the GPIO pins to retain their states, as shown in Figure 7-3 on page 480. In this mode, VDDC is powered off internally. The GPIO retention will be released when power is reapplied and the GPIOs will be initialized to their default values. ■ Using separate sources for VDD and VBAT. In this mode, additional circuitry is required for system start-up without a battery or with a depleted battery. ■ Using a regulator to provide both VDD and VBAT with a switch enabled byHIBto remove VDD during hibernation as shown in Figure 7-4 on page 481. June 12, 2014480 Texas Instruments-Production Data Hibernation Module

Figure7-4.UsingaRegulatorforBothV DDandVBAT Open drain external wake up circuit GND C 2C 1 X 1 VB A T EN Input V oltage Switch XOSC1 XOSC0 VDD HIB W AKE OU TIN T iva™ Microcontroller R PU GNDX OU TIN Regulator Note: Some devices may not supply aGNDXsignal. See “Signal Tables” on page 1161 for pins specific to your device. Adding external capacitance to the VBAT supply reduces the accuracy of the low-battery measurement and should be avoided if possible. The diagrams referenced in this section only show the connection to the Hibernation pins and not to the full system. If the application does not require the use of the Hibernation module, refer to “Connections for Unused Signals” on page 1190. In this situation, theHIBbit in theRunModeClockGatingControl Register0(RCGC0) and theHibernationRunModeClockGatingControl(RCGCHIB) registers must be cleared, disabling the system clock to the Hibernation module and Hibernation module registers are not accessible.

7.3.4 BatteryManagement

Important: System-level factors may affect the accuracy of the low-battery detect circuit. The designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements. The Hibernation module can be independently powered by a battery or an auxiliary power source using theVBATpin. The module can monitor the voltage level of the battery and detect when the voltage drops below VLOWBAT. The voltage threshold can be between 1.9 V and 2.5 V and is configured using theVBATSELfield in theHIBCTLregister. The module can also be configured so that it does not go into Hibernate mode if the battery voltage drops below this threshold. In addition, battery voltage is monitored while in hibernation, and the microcontroller can be configured to wake from hibernation if the battery voltage goes below the threshold using theBATWKENbit in theHIBCTL register. The Hibernation module is designed to detect a low-battery condition and set theLOWBATbit of the HibernationRawInterruptStatus(HIBRIS) register when this occurs. If theVABORTbit in the HIBCTLregister is also set, then the module is prevented from entering Hibernate mode when a low-battery is detected. The module can also be configured to generate an interrupt for the low-battery condition (see “Interrupts and Status” on page 485). Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher voltage. Therefore, it is important to design the circuit to ensure that VDD is higher than VBAT under nominal conditions or else the Hibernation module draws power from the battery even when VDD is available. 481June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

7.3.5 Real-TimeClock

The RTC module is designed to keep wall time. The RTC can operate in seconds counter mode. A 32.768 kHz clock source along with a 15-bit predivider reduces the clock to 1 Hz. The 1 Hz clock is used to increment the 32-bit counter and keep track of seconds. A match register can be configured to interrupt or wake the system from hibernate. In addition, a software trim register is implemented to allow the user to compensate for oscillator inaccuracies using software.

7.3.5.1 RTCCounter-Seconds/SubsecondsMode

The clock signal to the RTC is provided by either of the 32.768-kHz clock sources available to the Hibernation module. TheHibernationRTCCounter(HIBRTCC) register displays the seconds value. TheHibernationRTCSubSecondsregister(HIBRTCSS) is provided for additional time resolution of an application requiring less than one-second divisions. The RTC is enabled by setting theRTCENbit of theHIBCTLregister. The RTC counter and sub-seconds counters begin counting immediately onceRTCENis set. Both counters count up. The RTC continues counting as long as the RTC is enabled and a valid VBAT is present, regardless of whether VDD is present or if the device is in hibernation. The HIBRTCCregister is set by writing theHibernationRTCLoad(HIBRTCLD) register. A write to theHIBRTCLDregister clears the 15-bit sub-seconds counter field,RTCSSC, in theHIBRTCSS register. To ensure a valid read of the RTC value, theHIBRTCCregister should be read first, followed by a read of theRTCSSCfield in theHIBRTCSSregister and then a re-read of theHIBRTCCregister. If the two values for theHIBRTCCare equal, the read is valid. By following this procedure, errors in the application caused by theHIBRTCCregister rolling over by a count of 1 during a read of the RTCSSCfield are prevented. The RTC can be configured to generate an alarm by setting theRTCAL0 bit in theHIBIMregister. When an RTC match occurs, an interrupt is generated and displayed in the HIBRISregister. Refer to “RTC Match - Seconds/Subseconds Mode” on page 482 for more information. If the RTC is enabled, only a cold POR, where both VBAT and VDD are removed, resets the RTC registers. If any other reset occurs while the RTC is enabled, such as an externalRST assertion or BOR reset, the RTC is not reset. The RTC registers can be reset under any type of system reset as long as the RTC and external wake pins are not enabled.

7.3.5.2 RTCMatch-Seconds/SubsecondsMode

The Hibernation module includes a 32-bit match register,HIBRTCM0, which is compared to the value of the RTC 32-bit counter,HIBRTCC. The match functionality also extends to the sub-seconds counter. The 15-bit field (RTCSSM) in theHIBRTCSSregister is compared to the value of the 15-bit sub-seconds counter. When a match occurs, theRTCALT0bit is set in theHIBRISregister. For applications using Hibernate mode, the processor can be programmed to wake from Hibernate mode by setting theRTCWENbit in theHIBCTLregister. The processor can also be programmed to generate an interrupt to the interrupt controller by setting theRTCALT0bit in theHIBIMregister. The match interrupt generation takes priority over an interrupt clear. Therefore, writes to theRTCALT0 bit in theHibernationInterruptClear(HIBIC) register do not clear theRTCALT0bit if theHIBRTCC value and theHIBRTCM0value are equal. There are several methodologies to avoid this occurrence, such as writing a new value to theHIBRTCLDregister prior to writing theHIBICto clear theRTCALT0. Another example, would be to disable the RTC and re-enable the RTC by clearing and setting the RTCENbit in theHIBCTLregister. Note: A Hibernate request made while a match event is valid causes the module to immediately wake up. This occurs when theRTCWENbit is set and theRTCALT0bit in theHIBRISregister is set at the same time theHIBREQbit in theHIBCTLregister is written to a 1. This can be June 12, 2014482 Texas Instruments-Production Data Hibernation Module

avoided by clearing theRTCAL0bit in theHIBRISregister by writing a 1 to the corresponding bit in theHIBICregister before setting theHIBREQbit. Another example would be to disable the RTC and re-enable the RTC by clearing and setting theRTCENbit in theHIBCTLregister.

7.3.5.3 RTCTrim

The RTC counting rate can be adjusted to compensate for inaccuracies in the clock source by using the predivider trim register,HIBRTCT. This register has a nominal value of 0x7FFF, and is used for one second out of every 64 seconds in RTC counter mode, when bits [5:0] in theHIBRTCCregister change from 0x00 to 0x01, to divide the input clock. This configuration allows the software to make fine corrections to the clock rate by adjusting the predivider trim register up or down from 0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC rate and down from 0x7FFF in order to speed up the RTC rate. Care must be taken when using trim values that are near to the sub seconds match value in the HIBRTCSSregister. It is possible when using trim values above 0x7FFF to receive two match interrupts for the same counter value. In addition, it is possible when using trim values below 0x7FFF to miss a match interrupt. In the case of a trim value above 0x7FFF, when theRTCSSCvalue in theHIBRTCSSregister reaches 0x7FFF, theRTCCvalue increments from 0x0 to 0x1 while theRTCSSCvalue is decreased by the trim amount. TheRTCSSCvalue is counted up again to 0x7FFF before rolling over to 0x0 to begin counting up again. If the match value is within this range, the match interrupt is triggered twice. For example, as shown in Figure 7-5 on page 483, if the match interrupt was configured withRTCM0=0x1 and RTCSSM=0x7FFD, two interrupts would be triggered. Figure7-5.CounterBehaviorwithaTRIMValueof0x8002 R T C C L K R TCC[6:0] R TCSSC 0 x 0 0 0 x 7 F F D 0 x 7 F F E 0 x 0 1 0 x 0 2 0 x 7 F F F 0 x 7 F F D 0 x 7 F F E 0 x 7 F F F 0 x 7 F F E 0 x 7 F F F 0 x 0 0 x 10 x 0 In the case of a trim value below 0x7FFF, theRTCSSCvalue is advanced from 0x7FFF to the trim value while theRTCCvalue is incremented from 0x0 to 0x1. If the match value is within that range, the match interrupt is not triggered. For example, as shown in Figure 7-6 on page 483, if the match interrupt was configured withRTCM0=0x1 andRTCSSM=0x2,an interrupt would never be triggered. Figure7-6.CounterBehaviorwithaTRIMValueof0x7FFC R T C C L K R TCC[6:0] R TCSSC 0 x 0 0 0 x 7 F F D 0 x 7 F F E 0 x 0 1 0 x 7 F F F 0 x 7 F F D 0 x 7 F F E 0 x 7 F F F 483June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

7.3.6 Battery-BackedMemory

The Hibernation module contains 16 32-bit words of memory that are powered from the battery or an auxiliary power supply and therefore retained during hibernation. The processor software can save state information in this memory prior to hibernation and recover the state upon waking. The battery-backed memory can be accessed through theHIBDATAregisters. If both VDD and VBAT are removed, the contents of theHIBDATAregisters are not retained.

7.3.7 PowerControlUsingHIB

Important: The Hibernation Module requires special system implementation considerations when using HIB to control power, as it is intended to power-down all other sections of the microcontroller. All system signals and power supplies that connect to the chip must be driven to 0 V or powered down with the same regulator controlled byHIB The Hibernation module controls power to the microcontroller through the use of theHIBpin which is intended to be connected to the enable signal of the external regulator(s) providing 3.3 V to the microcontroller and other circuits. When theHIB signal is asserted by the Hibernation module, the external regulator is turned off and no longer powers the microcontroller and any parts of the system that are powered by the regulator. The Hibernation module remains powered from the VBAT supply until a Wake event. Power to the microcontroller is restored by deasserting theHIB signal, which causes the external regulator to turn power back on to the chip.

7.3.8 PowerControlUsingVDD3ONMode

The Hibernation module may also be configured to cut power to all internal modules during Hibernate mode. While in this state, ifVDD3ONis set in theHIBCTLregister, all pins are held in the state they were in prior to entering hibernation. For example, inputs remain inputs; outputs driven high remain driven high, and so on. There are important procedural and functional items to note when in VDD3ON mode: ■ In the VDD3ON mode, the regulator should maintain 3.3 V power to the microcontroller during Hibernate. GPIO retention is disabled when theRETCLRbit is cleared in theHIBCTLregister.

7.3.9 InitiatingHibernate

Hibernate mode is initiated when theHIBREQbit of theHIBCTLregister is set. If a wake-up condition has not been configured using thePINWENor RTCWENbits in theHIBCTLregister, the hibernation request is ignored. If a Flash memory write operation is in progress when theHIBREQbit is set, an interlock feature holds off the transition into Hibernate mode until the write has completed. In addition, if the battery voltage is below the threshold voltage defined by theVBATSELfield in theHIBCTL register, the hibernation request is ignored.

7.3.10 WakingfromHibernate

The Hibernation module is configured to wake from the externalWAKE pin by setting thePINWEN bit of theHIBCTLregister. It is configured to wake from RTC match by setting theRTCWENbit. Note that theWAKEpin uses the Hibernation module's internal power supply as the logic 1 reference. The Hibernation module can also be configured to wake from hibernate when the following events occur: ■ RTC match wake event ■ Low Battery wake event June 12, 2014484 Texas Instruments-Production Data Hibernation Module

By setting theRTCWENbit in theHIBCTLregister a wake from hibernate can occur when the value of theHIBRTCCregister matches the value of theHIBRTCM0register and the value of theRTCSSC field matches theRTCSSMfield in theHIBRTCSSregister. To allow a wake from Hibernate on a low battery event, theBATWKENbit in theHIBCTLregister must be set. In this configuration, the battery voltage is checked every 512 seconds while in hibernation. If the voltage is below the level specified by theVBATSELfield, theLOWBATinterrupt is set in theHIBRISregister. Upon external wake-up, external reset, or RTC match, the Hibernation module delays coming out of hibernation until VDD is above the minimum specified voltage, see Table 22-5 on page 1193. When the Hibernation module wakes, the microcontroller performs a normal power-on reset. The normal power-on reset does not reset the Hibernation module, but does reset the rest of the microcontroller. Software can detect that the power-on was due to a wake from hibernation by examining the raw interrupt status register (see “Interrupts and Status” on page 485) and by looking for state data in the battery-backed memory (see “Battery-Backed Memory” on page 484).

7.3.11 ArbitraryPowerRemoval

The microcontroller goes into hibernation if VDD is arbitrarily removed when theCLK32ENbit is set and any of the following bits are set: ■ PINWENbit in theHIBCTLregister ■ RTCENbit in theHIBCTLregister The microcontroller wakes from hibernation when power is reapplied. If theCLK32ENbit is set but thePINWEN, andRTCENbits are all clear, the microcontroller still goes into hibernation if power is removed; however, when VDD is reapplied, the MCU executes a cold POR and the Hibernation module is reset. If theCLK32ENbit is not set and VDD is arbitrarily removed, the part is simply powered off and executes a cold POR when power is reapplied. If VDD is arbitrarily removed while a Flash memory orHIBDATAregister write operation is in progress, the write operation must be retried after VDD is reapplied.

7.3.12 InterruptsandStatus

The Hibernation module can generate interrupts when the following conditions occur: ■ Assertion of WAKE pin ■ RTC match ■ Low battery detected ■ Write complete/capable ■ Assertion of an externalRESET pin All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate module can only generate a single interrupt request to the controller at any given time. The software interrupt handler can service multiple interrupt events by reading theHibernationMaskedInterrupt Status(HIBMIS) register. Software can also read the status of the Hibernation module at any time by reading theHIBRISregister which shows all of the pending events. This register can be used 485June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

after waking from hibernation to see if a wake condition was caused by one of the events above or by a power loss. The WAKEpin can generate interrupts in Run, Sleep and Deep Sleep Mode. The events that can trigger an interrupt are configured by setting the appropriate bits in theHibernationInterruptMask (HIBIM)register. Pending interrupts can be cleared by writing the corresponding bit in theHibernation InterruptClear(HIBIC) register.

7.4 InitializationandConfiguration

The Hibernation module has several different configurations. The following sections show the recommended programming sequence for various scenarios. Because the Hibernation module runs at a low frequency and is asynchronous to the rest of the microcontroller, which is run off the system clock, software must allow a delay of tHIB_REG_ACCESS after writes to registers (see “Register Access Timing” on page 478). TheWCinterrupt in theHIBMISregister can be used to notify the application when the Hibernation modules registers can be accessed.

7.4.1 Initialization

The Hibernation module comes out of reset with the system clock enabled to the module, but if the system clock to the module has been disabled, then it must be re-enabled, even if the RTC feature is not used. See page 333. If a 32.768-kHz crystal is used as the Hibernation module clock source, perform the following steps: 1. Write 0x0000.0010 to theHIBIMregister to enable theWCinterrupt. 2. Write 0x40 to theHIBCTLregister at offset 0x10 to enable the oscillator input. 3. Wait until theWCinterrupt in theHIBMISregister has been triggered before performing any other operations with the Hibernation module. If a 32.768-kHz single-ended oscillator is used as the Hibernation module clock source, then perform the following steps: 1. Write 0x0000.0010 to theHIBIMregister to enable theWCinterrupt. 2. Write 0x0001.0040 to theHIBCTLregister at offset 0x10 to enable the oscillator input and bypass the on-chip oscillator. 3. Wait until theWCinterrupt in theHIBMISregister has been triggered before performing any other operations with the Hibernation module. The above steps are only necessary when the entire system is initialized for the first time. If the microcontroller has been in hibernation, then the Hibernation module has already been powered up and the above steps are not necessary. The software can detect that the Hibernation module and clock are already powered by examining theCLK32ENbit of theHIBCTLregister. Table 7-2 on page 486 illustrates how the clocks function with various bit setting both in normal operation and in hibernation. Table7-2.HibernationModuleClockOperation ResultHibernationResultNormalOperationRTCENRTCWENPINWENCLK32EN Hibernation module disabledHibernation module disabledXXX0 No hibernationRTC match capability enabled.1001 June 12, 2014486 Texas Instruments-Production Data Hibernation Module

Table7-2.HibernationModuleClockOperation (continued) ResultHibernationResultNormalOperationRTCENRTCWENPINWENCLK32EN RTC match for wake-up eventModule clocked1101 Clock is powered down during hibernation and powered up again on external wake-up event. Module clocked0011 Clock is powered up during hibernation for RTC. Wake up on external event. Module clocked1011 RTC match or external wake-up event, whichever occurs first. Module clocked1111

7.4.2 RTCMatchFunctionality(NoHibernation)

Use the following steps to implement the RTC match functionality of the Hibernation module: 1. Write 0x0000.0040 to theHIBCTLregister at offset 0x010 to enable 32.768-kHz Hibernation oscillator. 2. Write the required RTC match value to theHIBRTCM0register at offset 0x004 and theRTCSSM field in theHIBRTCSSregister at offset 0x028. 3. Write the required RTC load value to theHIBRTCLDregister at offset 0x00C. 4. Set the required RTC match interrupt mask in theRTCALT0in theHIBIMregister at offset 0x014. 5. Write 0x0000.0041 to theHIBCTLregister at offset 0x010 to enable the RTC to begin counting.

7.4.3 RTCMatch/Wake-UpfromHibernation

Use the following steps to implement the RTC match and wake-up functionality of the Hibernation module: 1. Write 0x0000.0040 to theHIBCTLregister at offset 0x010 to enable 32.768-kHz Hibernation oscillator. 2. Write the required RTC match value to theHIBRTCM0register at offset 0x004 and theRTCSSM field in theHIBRTCSSregister at offset 0x028. 3. Write the required RTC load value to theHIBRTCLDregister at offset 0x00C. This write causes the 15-bit sub seconds counter to be cleared. 4. Write any data to be retained during hibernation to theHIBDATAregister at offsets 0x030-0x06F. 5. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004B to the HIBCTLregister at offset 0x010.

7.4.4 ExternalWake-UpfromHibernation

Use the following steps to implement the Hibernation module with the externalWAKE pin as the wake-up source for the microcontroller: 1. Write 0x0000.0040 to theHIBCTLregister at offset 0x010 to enable 32.768-kHz Hibernation oscillator. 2. Write any data to be retained during hibernation to theHIBDATAregister at offsets 0x030-0x06F. 487June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

1. Enable the external wake and start the hibernation sequence by writing 0x0000.0052 to the HIBCTLregister at offset 0x010.

7.4.5 RTCorExternalWake-UpfromHibernation

1. Write 0x0000.0040 to theHIBCTLregister at offset 0x010 to enable 32.768-kHz Hibernation oscillator. 2. Write the required RTC match value to theHIBRTCM0register at offset 0x004 and theRTCSSM field in theHIBRTCSSregister at offset 0x028. 3. Write the required RTC load value to theHIBRTCLDregister at offset 0x00C. This write causes the 15-bit sub seconds counter to be cleared. 4. Write any data to be retained during hibernation to theHIBDATAregister at offsets 0x030-0x06F. 5. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005B to theHIBCTLregister at offset 0x010.

7.5 RegisterMap

Table 7-3 on page 488 lists the Hibernation registers. All addresses given are relative to the Hibernation Module base address at 0x400F.C000. Note that the system clock to the Hibernation module must be enabled before the registers can be programmed (see page 333). There must be a delay of 3 system clocks after the Hibernation module clock is enabled before any Hibernation module registers are accessed. In addition, theCLK32ENbit in theHIBCTLregister must be set before accessing any other Hibernation module register. Note: The Hibernation module registers are on the Hibernation module clock domain and have special timing requirements. Software should make use of theWRCbit in theHIBCTLregister to ensure that the required timing gap has elapsed. If theWRCbit is clear, any attempted write access is ignored. See “Register Access Timing” on page 478. Important: The Hibernation module registers are reset under two conditions: 1. Any type of system reset (if theRTCENand thePINWENbits in theHIBCTLregister are clear). 2. A cold POR occurs when both the VDD and VBAT supplies are removed. Any other reset condition is ignored by the Hibernation module. Table7-3.HibernationModuleRegisterMap See pageDescriptionResetTypeNameOffset 490Hibernation RTC Counter0x0000.0000ROHIBRTCC0x000 491Hibernation RTC Match 00xFFFF.FFFFRWHIBRTCM00x004 492Hibernation RTC Load0x0000.0000RWHIBRTCLD0x00C 493Hibernation Control0x8000.2000RWHIBCTL0x010 497Hibernation Interrupt Mask0x0000.0000RWHIBIM0x014 June 12, 2014488 Texas Instruments-Production Data Hibernation Module

Table7-3.HibernationModuleRegisterMap (continued) See pageDescriptionResetTypeNameOffset 499Hibernation Raw Interrupt Status0x0000.0000ROHIBRIS0x018 501Hibernation Masked Interrupt Status0x0000.0000ROHIBMIS0x01C 503Hibernation Interrupt Clear0x0000.0000RW1CHIBIC0x020 504Hibernation RTC Trim0x0000.7FFFRWHIBRTCT0x024 505Hibernation RTC Sub Seconds0x0000.0000RWHIBRTCSS0x028 506Hibernation Data-RWHIBDATA0x030- 0x06F

7.6 RegisterDescriptions

The remainder of this section lists and describes the Hibernation module registers, in numerical order by address offset. 489June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register1:HibernationRTCCounter(HIBRTCC),offset0x000 This register is the current 32-bit value of the RTC counter. The RTC counter consists of a 32-bit seconds counter and a 15-bit sub seconds counter. The RTC counters are reset by the Hibernation module reset. The RTC 32-bit seconds counter can be set by the user using theHIBRTCLDregister. When the 32-bit seconds counter is set, the 15-bit sub second counter is cleared. The RTC value can be read by first reading theHIBRTCCregister, reading theRTCSSCfield in the HIBRTCSSregister, and then rereading theHIBRTCCregister. If the two values forHIBRTCCare equal, the read is valid. Hibernation RTC Counter (HIBRTCC) Base 0x400F.C000 Offset 0x000 Type RO, reset 0x0000.0000 16171819202122232425262728293031 RTCC ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 RTCC ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field RTC Counter A read returns the 32-bit counter value, which represents the seconds elapsed since the RTC was enabled. This register is read-only. To change the value, use theHIBRTCLDregister. 0x0000.0000RORTCC31:0 June 12, 2014490 Texas Instruments-Production Data Hibernation Module

Register2:HibernationRTCMatch0(HIBRTCM0),offset0x004 This register is the 32-bit seconds match register for the RTC counter. The 15-bit sub second match value is stored in the reading theRTCSSCfield in theHIBRTCSSregister and can be used in conjunction with this register for a more precise time match. Note: The Hibernation module registers are on the Hibernation module clock domain and have special timing requirements. Software should make use of theWRCbit in theHIBCTLregister to ensure that the required timing gap has elapsed. If theWRCbit is clear, any attempted write access is ignored. See “Register Access Timing” on page 478. Hibernation RTC Match 0 (HIBRTCM0) Base 0x400F.C000 Offset 0x004 Type RW, reset 0xFFFF.FFFF 16171819202122232425262728293031 RTCM0 RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1111111111111111Reset 0123456789101112131415 RTCM0 RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1111111111111111Reset DescriptionResetTypeNameBit/Field RTC Match 0 A write loads the value into the RTC match register. A read returns the current match value. 0xFFFF.FFFFRWRTCM031:0 491June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register3:HibernationRTCLoad(HIBRTCLD),offset0x00C This register is used to load a 32-bit value loaded into the RTC counter. The load occurs immediately upon this register being written. When this register is written, the 15-bit sub seconds counter is also cleared. Note: The Hibernation module registers are on the Hibernation module clock domain and have special timing requirements. Software should make use of theWRCbit in theHIBCTLregister to ensure that the required timing gap has elapsed. If theWRCbit is clear, any attempted write access is ignored. See “Register Access Timing” on page 478. Hibernation RTC Load (HIBRTCLD) Base 0x400F.C000 Offset 0x00C Type RW, reset 0x0000.0000 16171819202122232425262728293031 RTCLD RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset 0123456789101112131415 RTCLD RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field RTC Load A write loads the current value into the RTC counter (RTCC). A read returns the 32-bit load value. 0x0000.0000RWRTCLD31:0 June 12, 2014492 Texas Instruments-Production Data Hibernation Module

Register4:HibernationControl(HIBCTL),offset0x010 This register is the control register for the Hibernation module. This register must be written last before a hibernate event is issued. Writes to other registers after theHIBREQbit is set are not guaranteed to complete before hibernation is entered. Note: Writes to this register have special timing requirements. Software should make use of the WRCbit in theHIBCTLregister to ensure that the required synchronization has elapsed. While theWRCbit is clear, any attempts to write this register are ignored. Reads may occur at any time. Hibernation Control (HIBCTL) Base 0x400F.C000 Offset 0x010 Type RW, reset 0x8000.2000 16171819202122232425262728293031 OSCBYPOSCDRVreservedWRC RWRWROROROROROROROROROROROROROROType 0000000000000001Reset 0123456789101112131415 RTCENHIBREQreservedRTCWENPINWENreservedCLK32ENVABORTVDD3ONBATWKENBATCHKreservedVBATSELreserved RWRWRORWRWRORWRWRWRWRWRORORWRWROType 0000000000000100Reset DescriptionResetTypeNameBit/Field Write Complete/Capable DescriptionValue The interface is processing a prior write and is busy. Any write operation that is attempted whileWRCis 0 results in undetermined behavior. The interface is ready to accept a write.1 Software must poll this bit between write requests and defer writes until WRC=1 to ensure proper operation. An interrupt can be configured to indicate the WRC has completed. The bit nameWRCmeans "Write Complete," which is the normal use of the bit (between write accesses). However, because the bit is set out-of-reset, the name can also mean "Write Capable" which simply indicates that the interface may be written to by software. This difference may be exploited by software at reset time to detect which method of programming is appropriate: 0 = software delay loops required; 1 =WRC paced available. 1ROWRC31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved30:18 493June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Oscillator Drive Capability This bit is used to compensate for larger or smaller filtering capacitors. Note: This bit is not meant to be changed once the Hibernation oscillator has started. Oscillator stability is not guaranteed if the user changes this value after the oscillator is running. DescriptionValue Low drive strength is enabled, 12 pF.0 High drive strength is enabled, 24 pF.1 0RWOSCDRV17 Oscillator Bypass DescriptionValue The internal 32.768-kHz Hibernation oscillator is enabled. This bit should be cleared when using an external 32.768-kHz crystal. The internal 32.768-kHz Hibernation oscillator is disabled and powered down. This bit should be set when using a single-ended oscillator attached toXOSC0. 0RWOSCBYP16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15 Select for Low-Battery Comparator This field selects the battery level that is used when checking the battery status. If the battery voltage is below the specified level, theLOWBAT interrupt bit in theHIBRISregister is set. DescriptionValue

1.9 Volts0x0

2.1 Volts (default)0x1

2.3 Volts0x2

2.5 Volts0x3

0x1RWVBATSEL14:13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved12:11 Check Battery Status DescriptionValue When read, indicates that the low-battery comparator cycle is not active. Writing a 0 has no effect. When read, indicates the low-battery comparator cycle has not completed. Setting this bit initiates a low-battery comparator cycle. If the battery voltage is below the level specified byVBATSELfield, the LOWBATinterrupt bit in theHIBRISregister is set. A hibernation request is held off if a battery check is in progress. 0RWBATCHK10 June 12, 2014494 Texas Instruments-Production Data Hibernation Module

DescriptionResetTypeNameBit/Field Wake on Low Battery DescriptionValue The battery voltage level is not automatically checked. Low battery voltage does not cause the microcontroller to wake from hibernation. When this bit is set, the battery voltage level is checked every 512 seconds while in hibernation. If the voltage is below the level specified byVBATSELfield, the microcontroller wakes from hibernation and theLOWBATinterrupt bit in theHIBRISregister is set. 0RWBATWKEN9 VDD Powered DescriptionValue The internal switches are not used. TheHIB signal should be used to control an external switch or regulator. The internal switches control the power to the on-chip modules (VDD3ON mode). Regardless of the status of theVDD3ONbit, theHIB signal is asserted during Hibernate mode. Thus, whenVDD3ONis set, theHIBsignal should not be connected to the 3.3V regulator, and the 3.3V power source should remain connected. When this bit is set while in hibernation, all pins are held in the state they were in prior to entering hibernation. For example, inputs remain inputs; outputs driven high remain driven high, and so on. 0RWVDD3ON8 Power Cut Abort Enable DescriptionValue The microcontroller goes into hibernation regardless of the voltage level of the battery. When this bit is set, the battery voltage level is checked before entering hibernation. If VBAT is less than the voltage specified byVBATSEL, the microcontroller does not go into hibernation. 0RWVABORT7 Clocking Enable This bit must be enabled to use the Hibernation module. DescriptionValue The Hibernation module clock source is disabled.0 The Hibernation module clock source is enabled.1 0RWCLK32EN6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved5 495June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field External Wake Pin Enable DescriptionValue The status of theWAKEpin has no effect on hibernation.0 An assertion of theWAKEpin takes the microcontroller out of hibernation. Note: The external I/O wake pad interrupt is set if theWAKEpin is asserted in Run, Sleep, or Deep Sleep mode regardless of whether thePINWENbit is 0x0 or 0x1. The interrupt may be forwarded to the processor by setting theEXTWbit in the HIBIMregister. 0RWPINWEN4 RTC Wake-up Enable DescriptionValue An RTC match event has no effect on hibernation.0 An RTC match event (the value theHIBRTCCregister matches the value of theHIBRTCM0register and the value of theRTCSSCfield matches theRTCSSMfield in the HIBRTCSSregister) takes the microcontroller out of hibernation. 0RWRTCWEN3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved2 Hibernation Request DescriptionValue No hibernation request.0 Set this bit to initiate hibernation.1 After a wake-up event, this bit is automatically cleared by hardware. A hibernation request is ignored if both thePINWENand RTCWENbits are clear. A hibernation request is held off if theBATCHKbit is set. 0RWHIBREQ1 RTC Timer Enable DescriptionValue The Hibernation module RTC is disabled.0 The Hibernation module RTC is enabled.1 0RWRTCEN0 June 12, 2014496 Texas Instruments-Production Data Hibernation Module

Register5:HibernationInterruptMask(HIBIM),offset0x014 This register is the interrupt mask register for the Hibernation module interrupt sources. Each bit in this register masks the corresponding bit in theHibernationRawInterruptStatus(HIBRIS) register. If a bit is unmasked, the interrupt is sent to the interrupt controller. If the bit is masked, the interrupt is not sent to the interrupt controller. TheWCbit of theHIBIMregister may be set before theCLK32EN bit of theHIBCTLregister is set. This allows software to use theWCinterrupt trigger to detect when the RTCOSC clock is stable, which may be in excess of one second. If theWCbit is set before the CLK32ENhas been set, the mask value is not preserved over a hibernate cycle unless the bit is written a second time. Note: The WCbit of this register is in the system clock domain such that a write to this bit is immediate and may be done before theCLK32ENbit is set in theHIBCTLregister. Hibernation Interrupt Mask (HIBIM) Base 0x400F.C000 Offset 0x014 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 RTCALT0reservedLOWBATEXTWWCreserved RWRORWRWRWROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:5 External Write Complete/Capable Interrupt Mask DescriptionValue The WCinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when theWCbit in the HIBRISregister is set. 0RWWC4 External Wake-Up Interrupt Mask DescriptionValue The EXTWinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when theEXTWbit in theHIBRISregister is set. 0RWEXTW3 497June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Low Battery Voltage Interrupt Mask DescriptionValue The LOWBATinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when theLOWBAT bit in theHIBRISregister is set. 0RWLOWBAT2 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved1 RTC Alert 0 Interrupt Mask DescriptionValue The RTCALT0interrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when theRTCALT0 bit in theHIBRISregister is set. 0RWRTCALT00 June 12, 2014498 Texas Instruments-Production Data Hibernation Module

Register6:HibernationRawInterruptStatus(HIBRIS),offset0x018 This register is the raw interrupt status for the Hibernation module interrupt sources. Each bit can be masked by clearing the corresponding bit in theHIBIMregister. When a bit is masked, the interrupt is not sent to the interrupt controller. Bits in this register are cleared by writing a 1 to the corresponding bit in theHibernationInterruptClear(HIBIC) register or by entering hibernation. Note: The bits in this register do not reflect hibernation due to an arbitrary power loss on VDD. If the LOWBATbit was set prior to the loss of power, it will still be set when power is reapplied. In addition, theEXTWbit is self-clearing when exiting from hibernation, so if it was set prior to the power loss, the event is lost after the power is reapplied. Hibernation Raw Interrupt Status (HIBRIS) Base 0x400F.C000 Offset 0x018 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 RTCALT0reservedLOWBATEXTWWCreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:5 Write Complete/Capable Raw Interrupt Status DescriptionValue The WRCbit in theHIBCTLhas not been set.0 The WRCbit in theHIBCTLhas been set.1 This bit is cleared by writing a 1 to theWCbit in theHIBICregister. 0ROWC4 External Wake-Up Raw Interrupt Status Note that theWAKE signal is cleared after the interrupt is registered in the Hibernation module. DescriptionValue The WAKEpin has not been asserted.0 The WAKEpin has been asserted.1 This bit is cleared by writing a 1 to theEXTWbit in theHIBICregister. Note: The EXTWbit is set if theWAKEpin is asserted in any mode of operation (Run, Sleep, Deep Sleep) regardless of whether the PINWENbit is set in theHIBCTLregister. 0ROEXTW3 499June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Low Battery Voltage Raw Interrupt Status DescriptionValue The battery voltage has not dropped below VLOWBAT.0 The battery voltage dropped below VLOWBAT.1 This bit is cleared by writing a 1 to theLOWBATbit in theHIBICregister. 0ROLOWBAT2 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved1 RTC Alert 0 Raw Interrupt Status DescriptionValue No match0 The value of theHIBRTCCregister matches the value in the HIBRTCM0register and the value of theRTCSSCfield matches the RTCSSMfield in theHIBRTCSSregister. This bit is cleared by writing a 1 to theRTCALT0bit in theHIBICregister. 0RORTCALT00 June 12, 2014500 Texas Instruments-Production Data Hibernation Module

Register7:HibernationMaskedInterruptStatus(HIBMIS),offset0x01C This register is the masked interrupt status for the Hibernation module interrupt sources. Bits in this register are the AND of the corresponding bits in theHIBRISand HIBIMregisters. When both corresponding bits are set, the bit in this register is set, and the interrupt is sent to the interrupt controller. Hibernation Masked Interrupt Status (HIBMIS) Base 0x400F.C000 Offset 0x01C Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 RTCALT0reservedLOWBATEXTWWCreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:5 Write Complete/Capable Masked Interrupt Status DescriptionValue The WRCbit has not been set or the interrupt is masked.0 An unmasked interrupt was signaled due to theWRCbit being set. This bit is cleared by writing a 1 to theWCbit in theHIBICregister. 0ROWC4 External Wake-Up Masked Interrupt Status DescriptionValue An external wake-up interrupt has not occurred or is masked.0 An unmasked interrupt was signaled due to aWAKE pin assertion. This bit is cleared by writing a 1 to theEXTWbit in theHIBICregister. 0ROEXTW3 Low Battery Voltage Masked Interrupt Status DescriptionValue A low-battery voltage interrupt has not occurred or is masked.0 An unmasked interrupt was signaled due to a low-battery voltage condition. This bit is cleared by writing a 1 to theLOWBATbit in theHIBICregister. 0ROLOWBAT2 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved1 501June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field RTC Alert 0 Masked Interrupt Status DescriptionValue An RTC match interrupt has not occurred or is masked.0 An unmasked interrupt was signaled due to an RTC match.1 This bit is cleared by writing a 1 to theRTCALT0bit in theHIBICregister. 0RORTCALT00 June 12, 2014502 Texas Instruments-Production Data Hibernation Module

Register8:HibernationInterruptClear(HIBIC),offset0x020 This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources. Writing a 1 to a bit clears the corresponding interrupt in theHIBRISregister. Hibernation Interrupt Clear (HIBIC) Base 0x400F.C000 Offset 0x020 Type RW1C, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 RTCALT0reservedLOWBATEXTWWCreserved RW1CRORW1CRW1CRW1CROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:5 Write Complete/Capable Interrupt Clear Writing a 1 to this bit clears theWCbit in theHIBRISand HIBMIS registers. Reads return the raw interrupt status. 0RW1CWC4 External Wake-Up Interrupt Clear Writing a 1 to this bit clears theEXTWbit in theHIBRISand HIBMIS registers. Reads return the raw interrupt status. 0RW1CEXTW3 Low Battery Voltage Interrupt Clear Writing a 1 to this bit clears theLOWBATbit in theHIBRISand HIBMIS registers. Reads return the raw interrupt status. 0RW1CLOWBAT2 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved1 RTC Alert0 Masked Interrupt Clear Writing a 1 to this bit clears theRTCALT0bit in theHIBRISand HIBMIS registers. Reads return the raw interrupt status. Note: The timer interrupt source cannot be cleared if the RTC value and theHIBRTCM0register /RTCMSSfield values are equal. The match interrupt takes priority over the interrupt clear. 0RW1CRTCALT00 503June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register9:HibernationRTCTrim(HIBRTCT),offset0x024 This register contains the value that is used to trim the RTC clock predivider. It represents the computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock cycles, where N is the number of clock cycles to add or subtract every 64 seconds in RTC mode. Note: The Hibernation module registers are on the Hibernation module clock domain and have special timing requirements. Software should make use of theWRCbit in theHIBCTLregister to ensure that the required timing gap has elapsed. If theWRCbit is clear, any attempted write access is ignored. See “Register Access Timing” on page 478. Hibernation RTC Trim (HIBRTCT) Base 0x400F.C000 Offset 0x024 Type RW, reset 0x0000.7FFF 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 TRIM RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1111111111111110Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000ROreserved31:16 RTC Trim Value This value is loaded into the RTC predivider every 64 seconds in RTC counter mode. It is used to adjust the RTC rate to account for drift and inaccuracy in the clock source. Compensation can be adjusted by software by moving the default value of 0x7FFF up or down. Moving the value up slows down the RTC and moving the value down speeds up the RTC. 0x7FFFRWTRIM15:0 June 12, 2014504 Texas Instruments-Production Data Hibernation Module

Register10:HibernationRTCSubSeconds(HIBRTCSS),offset0x028 This register contains the RTC sub seconds counter and match values. The RTC value can be read by first reading theHIBRTCCregister, reading theRTCSSCfield in theHIBRTCSSregister, and then rereading theHIBRTCCregister. If the two values forHIBRTCCare equal, the read is valid. Note: The Hibernation module registers are on the Hibernation module clock domain and have special timing requirements. Software should make use of theWRCbit in theHIBCTLregister to ensure that the required timing gap has elapsed. If theWRCbit is clear, any attempted write access is ignored. See “Register Access Timing” on page 478. Hibernation RTC Sub Seconds (HIBRTCSS) Base 0x400F.C000 Offset 0x028 Type RW, reset 0x0000.0000 16171819202122232425262728293031 RTCSSMreserved RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWROType 0000000000000000Reset 0123456789101112131415 RTCSSCreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31 RTC Sub Seconds Match A write loads the value into the RTC sub seconds match register in 1/32,768 of a second increments. A read returns the current 1/32,768 seconds match value. 0x0000RWRTCSSM30:16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved15 RTC Sub Seconds Count A read returns the sub second RTC count in 1/32,768 seconds. 0x0000RORTCSSC14:0 505June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register11:HibernationData(HIBDATA),offset0x030-0x06F This address space is implemented as a 16x32-bit memory (64 bytes). It can be loaded by the system processor in order to store state information and retains its state during a power cut operation as long as a battery is present. Note: The Hibernation module registers are on the Hibernation module clock domain and have special timing requirements. Software should make use of theWRCbit in theHIBCTLregister to ensure that the required timing gap has elapsed. If theWRCbit is clear, any attempted write access is ignored. See “Register Access Timing” on page 478. Note: If VDD is arbitrarily removed while aHIBDATAregister write operation is in progress, the write operation must be retried after VDD is reapplied. Hibernation Data (HIBDATA) Base 0x400F.C000 Offset 0x030-0x06F Type RW, reset - 16171819202122232425262728293031 RTD RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0123456789101112131415 RTD RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType DescriptionResetTypeNameBit/Field Hibernation Module NV Data-RWRTD31:0 June 12, 2014506 Texas Instruments-Production Data Hibernation Module

8 InternalMemory

The TM4C1233D5PZ microcontroller comes with 24 KB of bit-banded SRAM, internal ROM, 64 KB of Flash memory, and 2KB of EEPROM. The Flash memory controller provides a user-friendly interface, making Flash memory programming a simple task. Flash memory is organized in 1-KB independently erasable blocks and memory protection can be applied to the Flash memory on a 2-KB block basis. The EEPROM module provides a well-defined register interface to support accesses to the EEPROM with both a random access style of read and write as well as a rolling or sequential access scheme. A password model allows the application to lock one or more EEPROM blocks to control access on 16-word boundaries.

8.1 BlockDiagram

Figure 8-1 on page 507 illustrates the internal SRAM, ROM, and Flash memory blocks and control logic. The dashed boxes in the figure indicate registers residing in the System Control module. Figure8-1.InternalMemoryBlockDiagram ROM Control RMCTL ROM Array Flash Control FMA FMD FCIM FCMISC Flash Array Cortex-M4F Bridge SRAM Array System Bus Icode Bus Dcode Bus FMPRE FMPPE Flash Protection FMPREn FMPPEn User Registers BOOTCFG USER_REG0 USER_REG1 USER_REG2 USER_REG3 FMC FCRIS FMC2 FWBV AL FWBn 32 words FSIZE SSIZE Flash W rite Buffer ROMSWMAP 507June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Figure 8-2 on page 508 illustrates the internal EEPROM block and control logic. The EEPROM block is connected to the AHB bus. Figure8-2.EEPROMBlockDiagram Block 0 Block 1 Block 2 Block n ... EEBLOCK EEOFFSET EERDWR EERDWRINC Security Program EEPROM ArrayEEPROM Control EEDONE EESUPP EEUNLOCK EEPROT EEP ASS0 EEP ASS1 EEP ASS2 EEINT EEHIDE EEDBGME EESIZE Block 3 EEPROMPP

8.2 FunctionalDescription

This section describes the functionality of the SRAM, ROM, Flash, and EEPROM memories. Note: The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash memory and ROM are located on a separate internal bus, it is not possible to transfer data from the Flash memory or ROM with the μDMA controller.

8.2.1 SRAM

The internal SRAM of the TM4C1233D5PZ device is located at address 0x2000.0000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM provides bit-banding technology in the processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The bit-band base is located at address 0x2200.0000. The bit-band alias is calculated by using the formula: bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000. For details about bit-banding, see “Bit-Banding” on page 90. June 12, 2014508 Texas Instruments-Production Data Internal Memory

Note: The SRAM is implemented using two 32-bit wide SRAM banks (separate SRAM arrays). The banks are partitioned such that one bank contains all even words (the even bank) and the other contains all odd words (the odd bank). A write access that is followed immediately by a read access to the same bank incurs a stall of a single clock cycle. However, a write to one bank followed by a read of the other bank can occur in successive clock cycles without incurring any delay.

8.2.2 ROM

The internal ROM of the TM4C1233D5PZ device is located at address 0x0100.0000 of the device memory map. Detailed information on the ROM contents can be found in theTiva™ C Series TM4C123x ROM User’s Guide (literature number SPMU367). The ROM contains the following components: ■ TivaWare ™ Boot Loader and vector table ■ TivaWare Peripheral Driver Library (DriverLib) release for product-specific peripherals and interfaces ■ Advanced Encryption Standard (AES) cryptography tables ■ Cyclic Redundancy Check (CRC) error detection functionality The boot loader is used as an initial program loader (when the Flash memory is empty) as well as an application-initiated firmware upgrade mechanism (by calling back to the boot loader). The Peripheral Driver Library APIs in ROM can be called by applications, reducing Flash memory requirements and freeing the Flash memory to be used for other purposes (such as additional features in the application). Advance Encryption Standard (AES) is a publicly defined encryption standard used by the U.S. Government and Cyclic Redundancy Check (CRC) is a technique to validate if a block of data has the same contents as when previously checked.

8.2.2.1 BootLoaderOverview

The TivaWare Boot Loader is used to download code to the Flash memory of a device without the use of a debug interface. When the core is reset, the user has the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal in Ports A-H as configured in theBootConfiguration(BOOTCFG) register (see page 563). At reset, the following sequence is performed: 1. The BOOTCFGregister is read. If theENbit is clear, the ROM Boot Loader is executed. 2. In the ROM Boot Loader, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 3. If theENbit is set or the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004. The user application begins executing. 509June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

The boot loader uses a simple packet interface to provide synchronous communication with the device. The speed of the boot loader is determined by the internal oscillator (PIOSC) frequency as it does not enable the PLL. The following serial interfaces can be used: ■ UART0 ■ SSI0 ■ I 2C0 ■ USB The data format and communication protocol are identical for the UART0, SSI0, and I2C0 interfaces. Note: The Flash-memory-resident version of the boot loader also supports CAN. See theTivaWare™ Boot Loader for C Series User's Guide (literature number SPMU301) for information on the boot loader software. The USB boot loader uses the standard Device Firmware Upgrade USB device class. Considerations When Using the UART Boot Loader in ROM U0Txis not driven by the ROM boot loader until the auto-bauding process has completed. IfU0Tx is floating during this time, the receiver it is connected to may see transitions on the signal, which could be interpreted by its UART as valid characters. To handle this situation, put a pull-up or pull-down onU0Tx, providing a defined state for the signal until the ROM boot loader begins driving U0Tx. A pull-up is preferred as it indicates that the UART is idle, rather than a pull-down, which indicates a break condition.

8.2.2.2 TivaWarePeripheralDriverLibrary

The TivaWare Peripheral Driver Library contains a file calleddriverlib/rom.hthat assists with calling the peripheral driver library functions in the ROM. The detailed description of each function is available in theTiva™ C Series TM4C123x ROM User’s Guide (literature number SPMU367). See the "Using the ROM" chapter of theTivaWare™ Peripheral Driver Library for C Series User's Guide (literature number SPMU298) for more details on calling the ROM functions and using driverlib/rom.h. Thedriverlib/rom_map.hheader file is also provided to aid portability when using different Tiva™ C Series devices which might have a different subset of DriverLib functions in ROM. Thedriverlib/rom_map.hheader file uses build-time labels to route function calls to the ROM if those functions are available on a given device, otherwise, it routes to Flash-resident versions of the functions. A table at the beginning of the ROM points to the entry points for the APIs that are provided in the ROM. Accessing the API through these tables provides scalability; while the API locations may change in future versions of the ROM, the API tables will not. The tables are split into two levels; the main table contains one pointer per peripheral which points to a secondary table that contains one pointer per API that is associated with that peripheral. The main table is located at 0x0100.0010, right after the Cortex-M4F vector table in the ROM. DriverLib functions are described in detail in theTivaWare™ Peripheral Driver Library for C Series User's Guide (literature number SPMU298). Additional APIs are available for graphics and USB functions, but are not preloaded into ROM. The TivaWare Graphics Library provides a set of graphics primitives and a widget set for creating graphical user interfaces on Tiva™ C Series microcontroller-based boards that have a graphical display (for more information, see theTivaWare™ Graphics Library for C Series User's Guide (literature number SPMU300)). The TivaWare USB Library is a set of data types and functions for creating USB Device, June 12, 2014510 Texas Instruments-Production Data Internal Memory

Host or On-The-Go (OTG) applications on Tiva™ C Series microcontroller-based boards (for more information, see theTivaWare™ USB Library for C Series User's Guide (literature number SPMU297)).

8.2.2.3 AdvancedEncryptionStandard(AES)CryptographyTables

AES is a strong encryption method with reasonable performance and size. AES is fast in both hardware and software, is fairly easy to implement, and requires little memory. AES is ideal for applications that can use prearranged keys, such as setup during manufacturing or configuration. Four data tables used by the XySSL AES implementation are provided in the ROM. The first is the forward S-box substitution table, the second is the reverse S-box substitution table, the third is the forward polynomial table, and the final is the reverse polynomial table. See theTiva™ C Series TM4C123x ROM User’s Guide (literature number SPMU367) for more information on AES.

8.2.2.4 CyclicRedundancyCheck(CRC)ErrorDetection

The CRC technique can be used to validate correct receipt of messages (nothing lost or modified in transit), to validate data after decompression, to validate that Flash memory contents have not been changed, and for other cases where the data needs to be validated. A CRC is preferred over a simple checksum (for example, XOR all bits) because it catches changes more readily. See the Tiva™ C Series TM4C123x ROM User’s Guide (literature number SPMU367) for more information on CRC.

8.2.3 FlashMemory

At system clock speeds of 40 MHz and below, the Flash memory is read in a single cycle. The Flash memory is organized as a set of 1-KB blocks that can be individually erased. An individual 32-bit word can be programmed to change bits from 1 to 0. In addition, a write buffer provides the ability to program 32 continuous words in Flash memory in half the time of programming the words individually. Erasing a block causes the entire contents of the block to be reset to all 1s. The 1-KB blocks are paired into sets of 2-KB blocks that can be individually protected. The protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or a debugger.

8.2.3.1 PrefetchBuffer

The Flash memory controller has a prefetch buffer that is automatically used when the CPU frequency is greater than 40 MHz. In this mode, the Flash memory operates at half of the system clock. The prefetch buffer fetches two 32-bit words per clock allowing instructions to be fetched with no wait states while code is executing linearly. The fetch buffer includes a branch speculation mechanism that recognizes a branch and avoids extra wait states by not reading the next word pair. Also, short loop branches often stay in the buffer. As a result, some branches can be executed with no wait states. Other branches incur a single wait state.

8.2.3.2 FlashMemoryProtection

The user is provided two forms of Flash memory protection per 2-KB Flash memory block in one pair of 32-bit wide registers. The policy for each protection form is controlled by individual bits (per policy per block) in theFMPPEnand FMPREnregisters. 511June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

■ FlashMemoryProtectionProgramEnable(FMPPEn) : If a bit is set, the corresponding block may be programmed (written) or erased. If a bit is cleared, the corresponding block may not be changed. ■ FlashMemoryProtectionReadEnable(FMPREn) : If a bit is set, the corresponding block may be executed or read by software or debuggers. If a bit is cleared, the corresponding block may only be executed, and contents of the memory block are prohibited from being read as data. The policies may be combined as shown in Table 8-1 on page 512. Table8-1.FlashMemoryProtectionPolicyCombinations ProtectionFMPREnFMPPEn Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. The block may be written, erased or executed, but not read. This combination is unlikely to be used. Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. No protection. The block may be written, erased, executed or read.11 A Flash memory access that attempts to read a read-protected block (FMPREnbit is set) is prohibited and generates a bus fault. A Flash memory access that attempts to program or erase a program-protected block (FMPPEnbit is set) is prohibited and can optionally generate an interrupt (by setting theAMASKbit in theFlashControllerInterruptMask(FCIM) register) to alert software developers of poorly behaving software during the development and debug phases. The factory settings for theFMPREnand FMPPEnregisters are a value of 1 for all implemented banks. These settings create a policy of open access and programmability. The register bits may be changed by clearing the specific register bit. The changes are effective immediately, but are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The changes are committed using theFlashMemoryControl(FMC) register. Details on programming these bits are discussed in “Non-Volatile Register Programming” on page 515.

8.2.3.3 Execute-OnlyProtection

Execute-only protection prevents both modification and visibility to a protected flash block. This mode is intended to be used in situations where a device requires debug capability, yet portions of the application space must be protected from external access. An example of this is a company who wishes to sell Tiva™ C Series devices with their proprietary software preprogrammed, yet allow the end user to add custom code to an unprotected region of the flash (such as a motor control module with a customizable motor configuration section in flash). Literal data introduces a complication to the protection mechanism. When C code is compiled and linked, literal data (constants, and so on) is typically placed in the text section, between functions, by the compiler. The literal data is accessed at run time through the use of the LDR instruction, which loads the data from memory using a PC-relative memory address. The execution of the LDR instruction generates a read transaction across the Cortex-M3's DCode bus, which is subject to the execute-only protection mechanism. If the accessed block is marked as execute only, the transaction is blocked, and the processor is prevented from loading the constant data and, therefore, inhibiting correct execution. Therefore, using execute-only protection requires that literal data be handled differently. There are three ways to address this: June 12, 2014512 Texas Instruments-Production Data Internal Memory

1. Use a compiler that allows literal data to be collected into a separate section that is put into one or more read-enabled flash blocks. Note that the LDR instruction may use a PC-relative address–-in which case the literal pool cannot be located outside the span of the offset–-or the software may reserve a register to point to the base address of the literal pool and the LDR offset is relative to the beginning of the pool. 2. Use a compiler that generates literal data from arithmetic instruction immediate data and subsequent computation. 3. Use method 1 or 2, but in assembly language, if the compiler does not support either method.

8.2.3.4 Read-OnlyProtection

Read-only protection prevents the contents of the flash block from being re-programmed, while still allowing the content to be read by processor or the debug interface. Note that if aFMPREnbit is cleared, all read accesses to the Flash memory block are disallowed, including any data accesses. Care must be taken not to store required data in a Flash memory block that has the associated FMPREnbit cleared. The read-only mode does not prevent read access to the stored program, but it does provide protection against accidental (or malicious) erasure or programming. Read-only is especially useful for utilities like the boot loader when the debug interface is permanently disabled. In such combinations, the boot loader, which provides access control to the Flash memory, is protected from being erased or modified.

8.2.3.5 PermanentlyDisablingDebug

For extremely sensitive applications, the debug interface to the processor and peripherals can be permanently disabled, blocking all accesses to the device through the JTAG or SWD interfaces. With the debug interface disabled, it is still possible to perform standard IEEE instructions (such as boundary scan operations), but access to the processor and peripherals is blocked. The DBG0and DBG1bits of theBootConfiguration(BOOTCFG) register control whether the debug interface is turned on or off. The debug interface should not be permanently disabled without providing some mechanism–-such as the boot loader–-to provide customer-installable updates or bug fixes. Disabling the debug interface is permanent and cannot be reversed.

8.2.3.6 Interrupts

The Flash memory controller can generate interrupts when the following conditions are observed: ■ Programming Interrupt - signals when a program or erase action is complete. ■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block of memory that is protected by its correspondingFMPPEnbit. The interrupt events that can trigger a controller-level interrupt are defined in theFlashController MaskedInterruptStatus(FCMIS) register (see page 532) by setting the correspondingMASKbits. If interrupts are not used, the raw interrupt status is always visible via theFlashControllerRaw InterruptStatus(FCRIS) register (see page 529). Interrupts are always cleared (for both theFCMISand FCRISregisters) by writing a 1 to the corresponding bit in theFlashControllerMaskedInterruptStatusandClear(FCMISC) register (see page 534). 513June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

8.2.3.7 FlashMemoryProgramming

The Tiva™ C Series devices provide a user-friendly interface for Flash memory programming. All erase/program operations are handled via three registers:FlashMemoryAddress(FMA) , Flash MemoryData(FMD) , andFlashMemoryControl(FMC) . Note that if the debug capabilities of the microcontroller have been deactivated, resulting in a "locked" state, a recovery sequence must be performed in order to reactivate the debug module. See “Recovering a "Locked" Microcontroller” on page 198. During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation is complete. If instruction execution is required during a Flash memory operation, the code that is executing must be placed in SRAM and executed from there while the flash operation is in progress. Note: When programming Flash memory, the following characteristics of the memory must be considered: ■ Only an erase can change bits from 0 to 1. ■ A write can only change bits from 1 to 0. If the write attempts to change a 0 to a 1, the write fails and no bits are changed. ■ A flash operation can be started before entering the Sleep or Deep-Sleep mode (using the wait for interrupt instruction,WFI). It can also be completed while in Sleep or Deep-Sleep. If the Flash program/erase event comes in succession to EEPROM access, the Flash event gets completed after waking from Sleep/Deep-Sleep and is started after the wake-up.

8.2.3.8 BasicProgram/EraseOperations

1. Write source data to theFMDregister. 2. Write the target address to theFMAregister. 3. Write the Flash memory write key and theWRITEbit to theFMCregister. Depending on the value of theKEYbit in theBOOTCFGregister, the value 0xA442 or 0x71D5 must be written into theWRKEYfield for a Flash memory write to occur. 4. Poll theFMCregister until theWRITEbit is cleared. To perform an erase of a 1-KB page 1. Write the page address to theFMAregister. 2. Write the Flash memory write key and theERASEbit to theFMCregister. Depending on the value of theKEYbit in theBOOTCFGregister, the value 0xA442 or 0x71D5 must be written into theWRKEYfield for a Flash memory write to occur. 3. Poll theFMCregister until theERASEbit is cleared or, alternatively, enable the programming interrupt using thePMASKbit in theFCIMregister. June 12, 2014514 Texas Instruments-Production Data Internal Memory

To perform a mass erase of the Flash memory 1. Write the Flash memory write key and theMERASEbit to theFMCregister. Depending on the value of theKEYbit in theBOOTCFGregister, the value 0xA442 or 0x71D5 must be written into theWRKEYfield for a Flash memory write to occur. 2. Poll theFMCregister until theMERASEbit is cleared or, alternatively, enable the programming interrupt using thePMASKbit in theFCIMregister. 8.2.3.9 32-WordFlashMemoryWriteBuffer A 32-word write buffer provides the capability to perform faster write accesses to the Flash memory by programming 2 32-bit words at a time, allowing 32 words to be programmed in the same time as 16 would take using the method described above. The data for the buffered write is written to the FlashWriteBuffer(FWBn) registers. The registers are 32-word aligned with Flash memory, and therefore the registerFWB0corresponds with the address inFMAwhere bits [6:0] ofFMAare all 0.FWB1corresponds with the address in FMA+ 0x4 and so on. Only theFWBnregisters that have been updated since the previous buffered Flash memory write operation are written. TheFlashWriteBufferValid(FWBVAL) register shows which registers have been written since the last buffered Flash memory write operation. This register contains a bit for each of the 32FWBnregisters, where bit[n] ofFWBVALcorresponds toFWBn. The FWBnregister has been updated if the corresponding bit in theFWBVALregister is set. To program 32 words with a single buffered Flash memory write operation 1. Write the source data to theFWBnregisters. 2. Write the target address to theFMAregister. This must be a 32-word aligned address (that is, bits [6:0] inFMAmust be 0s). 3. Write the Flash memory write key and theWRBUFbit to theFMC2register. Depending on the value of theKEYbit in theBOOTCFGregister, the value 0xA442 or 0x71D5 must be written into theWRKEYfield for a Flash memory write to occur. 4. Poll theFMC2register until theWRBUFbit is cleared or wait for thePMISinterrupt to be signaled.

8.2.3.10 Non-VolatileRegisterProgramming

Note: The BootConfiguration(BOOTCFG) register requires a POR before the committed changes take effect. This section discusses how to update the registers shown in Table 8-2 on page 516 that are resident within the Flash memory itself. These registers exist in a separate space from the main Flash memory array and are not affected by an ERASE or MASS ERASE operation. With the exception of theBoot Configuration(BOOTCFG) register, the settings in these registers can be written, their functions verified, and their values read back before they are committed, at which point they become non-volatile. If a value in one of these registers has not been committed, a power-on reset restores the last committed value or the default value if the register has never been committed. Other types of reset have no effect. Once the register contents are committed, the only way to restore the factory default values is to perform the sequence described in “Recovering a "Locked" Microcontroller” on page 198. To write to a non-volatile register: ■ Bits can only be changed from 1 to 0. 515June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

■ For all registers except theBOOTCFGregister, write the data to the register address provided in the register description. For theBOOTCFGregister, write the data to theFMDregister. ■ The registers can be read to verify their contents. To verify what is to be stored in theBOOTCFG register, read theFMDregister. Reading theBOOTCFGregister returns the previously committed value or the default value if the register has never been committed. ■ The new values are effectively immediately for all registers exceptBOOTCFG, as the new value for the register is not stored in the register until it has been committed. ■ Prior to committing the register value, a power-on reset restores the last committed value or the default value if the register has never been committed. To commit a new value to a non-volatile register: ■ Write the data as described above. ■ Write to theFMAregister the value shown in Table 8-2 on page 516. ■ Write the Flash memory write key and set theCOMTbit in theFMCregister. These values must be written to theFMCregister at the same time. ■ Committing a non-volatile register has the same timing as a write to regular Flash memory, defined by TPROG64, as shown in Table 22-27 on page 1217. Software can poll theCOMTbit in the FMCregister to determine when the operation is complete, or an interrupt can be enabled by setting thePMASKbit in theFCIMregister. ■ When committing theBOOTCFGregister, theINVDRISbit in theFCRISregister is set if a bit that has already been committed as a 0 is attempted to be committed as a 1. ■ Once the value has been committed, a power-on reset has no effect on the register contents. ■ Changes to theBOOTCFGregister are effective after the next power-on reset. ■ Once theNWbit has been changed to 0 and committed, further changes to theBOOTCFGregister are not allowed. Important: After being committed, these registers can only be restored to their factory default values by performing the sequence described in “Recovering a "Locked" Microcontroller” on page 198. The mass erase of the main Flash memory array caused by the sequence is performed prior to restoring these registers. Table8-2.User-ProgrammableFlashMemoryResidentRegisters DataSourceFMAValueRegistertobeCommitted FMPRE00x0000.0000FMPRE0 FMPPE00x0000.0001FMPPE0 USER_REG00x8000.0000USER_REG0 USER_REG10x8000.0001USER_REG1 USER_REG20x8000.0002USER_REG2 USER_REG30x8000.0003USER_REG3 FMD0x7510.0000BOOTCFG June 12, 2014516 Texas Instruments-Production Data Internal Memory

8.2.4 EEPROM

The TM4C1233D5PZ microcontroller includes an EEPROM with the following features: ■ 2Kbytes of memory accessible as 512 32-bit words ■ 32 blocks of 16 words (64 bytes) each ■ Built-in wear leveling ■ Access protection per block ■ Lock protection option for the whole peripheral as well as per block using 32-bit to 96-bit unlock codes (application selectable) ■ Interrupt support for write completion to avoid polling ■ Endurance of 500K writes (when writing at fixed offset in every alternate page in circular fashion) to 15M operations (when cycling through two pages ) per each 2-page block.

8.2.4.1 FunctionalDescription

The EEPROM module provides a well-defined register interface to support accesses to the EEPROM with both a random access style of read and write as well as a rolling or sequential access scheme. A protection mechanism allows locking EEPROM blocks to prevent writes under a set of circumstances as well as reads under the same or different circumstances. The password model allows the application to lock one or more EEPROM blocks to control access on 16-word boundaries. Important: The configuration of the system clock must not be changed while an EEPROM operation is in process. Software must wait until theWORKINGbit in theEEPROMDoneStatus (EEDONE)register is clear before making any changes to the system clock. Blocks There are 32 blocks of 16 words each in the EEPROM. Bytes and half-words can be read, and these accesses do not have to occur on a word boundary. The entire word is read and any unneeded data is simply ignored. They are writable only on a word basis. To write a byte, it is necessary to read the word value, modify the appropriate byte, and write the word back. Each block is addressable as an offset within the EEPROM, using a block select register. Each word is offset addressable within the selected block. The current block is selected by theEEPROMCurrentBlock(EEBLOCK) register. The current offset is selected and checked for validity by theEEPROMCurrentOffset(EEOFFSET) register. The application may write theEEOFFSETregister any time, and it is also automatically incremented when theEEPROMRead-WritewithIncrement(EERDWRINC) register is accessed. However, the EERDWRINCregister does not increment the block number, but instead wraps within the block. Blocks are individually protectable. Attempts to read from a block for which the application does not have permission return 0xFFFF.FFFF. Attempts to write into a block for which the application does not have permission results in an error in theEEDONEregister. Timing Considerations After enabling or resetting the EEPROM module, software must wait until theWORKINGbit in the EEDONEregister is clear before accessing any EEPROM registers. 517June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

In the event that there are Flash memory writes or erases and EEPROM writes active, it is possible for the EEPROM process to be interrupted by the Flash memory write/erase and then continue after the Flash memory write is completed. This action may change the amount of time that the EEPROM operation takes. EEPROM operations must be completed before entering Sleep or Deep-Sleep mode. Ensure the EEPROM operations have completed by checking theEEPROMDoneStatus(EEDONE) register before issuing aWFIinstruction to enter Sleep or Deep-Sleep. Reads of words within a block are at direct speed, which means that wait states are automatically generated if the system clock is faster than the speed of the EEPROM. The read access time is specified in Table 22-28 on page 1217. Writing theEEOFFSETregister also does not incur any penalties. Writing theEEBLOCKregister is not delayed, but any attempt to access data within that block is delayed by 4 clocks after writingEEBLOCK. This time is used to load block specific information. Writes to words within a block are delayed by a variable amount of time. The application may use an interrupt to be notified when the write is done, or alternatively poll for the done status in the EEDONEregister. The variability ranges from the write timing of the EEPROM to the erase timing of EEPROM, where the erase timing is less than the write timing of most external EEPROMs. Locking and Passwords The EEPROM can be locked at both the module level and the block level. The lock is controlled by a password that is stored in theEEPROMPassword(EEPASSn) registers and can be any 32-bit to 96-bit value other than all 1s. Block 0 is the master block, the password for block 0 protects the control registers as well as all other blocks. Each block can be further protected with a password for that block. If a password is registered for block 0, then the whole module is locked at reset. The locking behavior is such that blocks 1 to 31 are inaccessible until block 0 is unlocked, and block 0 follows the rules defined by its protection bits. As a result, theEEBLOCKregister cannot be changed from 0 until block 0 is unlocked. A password registered with any block, including block 0, allows for protection rules that control access of that block based on whether it is locked or unlocked. Generally, the lock can be used to prevent write accesses when locked or can prevent read and write accesses when locked. All password-protected blocks are locked at reset. To unlock a block, the correct password value must be written to theEEPROMUnlock(EEUNLOCK) register by writing to it one to three times to form the 32-bit, 64-bit, or 96-bit password registered using theEEPASSnregister. The value used to configure theEEPASS0register must always be written last. For example, for a 96-bit password, the value used to configure theEEPASS2register must be written first, followed by the EEPASS1and theEEPASS0register values. A block or the module may be re-locked by writing 0xFFFF.FFFF to theEEUNLOCKregister because 0xFFFF.FFFF is not a valid password. Protection and Access Control The protection bits provide discrete control of read and write access for each block which allows various protection models per block, including: ■ Without password: Readable and writable at any time. This mode is the default when there is no password. ■ Without password: Readable but not writable. June 12, 2014518 Texas Instruments-Production Data Internal Memory

■ With password: Readable, but only writable when unlocked by the password. This mode is the default when there is a password. ■ With password: Readable or writable only when unlocked. ■ With password: Readable only when unlocked, not writable. Additionally, access protection may be applied based on the processor mode. This configuration allows for supervisor-only access or supervisor and user access, which is the default. Supervisor-only access mode also prevents access by the µDMA and Debugger. Additionally, the master block may be used to control access protection for the protection mechanism itself. If access control for block 0 is for supervisor only, then the whole module may only be accessed in supervisor mode. In addition, the protection level for block 0 sets the minimum protection level for the entire EEPROM. For example, if thePROTfield in theEEPROTregister is configured to 0x1 for block 0, then block 1 could be configured with thePROTfield to be 0x1, 0x2, or 0x3, but not 0x0. Note that for blocks 1 to 31, they are inaccessible for read or write if block 0 has a password and it is not unlocked. If block 0 has a master password, then the strictest protection defined for block 0 or an individual block is implemented on the remaining blocks. Hidden Blocks Hiding provides a temporary form of protection. Every block except block 0 can be hidden, which prevents all accesses until the next reset. This mechanism can allow a boot or initialization routine to access some data which is then made inaccessible to all further accesses. Because boot and initialization routines control the capabilities of the application, hidden blocks provide a powerful isolation of the data when debug is disabled. A typical use model would be to have the initialization code store passwords, keys, and/or hashes to use for verification of the rest of the application. Once performed, the block is then hidden and made inaccessible until the next reset which then re-enters the initialization code. Power and Reset Safety Once theEEDONEregister indicates that a location has been successfully written, the data is retained until that location is written again. There is no power or reset race after theEEDONEregister indicates a write has completed. Interrupt Control The EEPROM module allows for an interrupt when a write completes to eliminate the need for polling. The interrupt can be used to drive an application ISR which can then write more words or verify completion. The interrupt mechanism is used any time theEEDONEregister goes from working to done, whether because of an error or the successful completion of a program or erase operation. This interrupt mechanism works for data writes, writes to password and protection registers, forced erase by theEEPROMSupportControlandStatus(EESUPP) register, and mass erase using the EEPROMDebugMassErase(EEDGBME) register. The EEPROM interrupt is signaled to the core using the Flash memory interrupt vector. Software can determine that the source of the interrupt was the EEPROM by examining bit 2 of theFlashControllerMaskedInterruptStatusandClear (FCMISC)register. Theory of Operation The EEPROM operates using a traditional Flash bank model which implements EEPROM-type cells, but uses sector erase. Additionally, words are replicated in the pages to allow 500K+ erase 519June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

cycles when needed, which means that each word has a latest version. As a result, a write creates a new version of the word in a new location, making the previous value obsolete. Each sector contains two blocks. Each block contains locations for the active copy plus six redundant copies. Passwords, protection bits, and control data are all stored in the pages. When a page runs out of room to store the latest version of a word, a copy buffer is used. The copy buffer copies the latest words of each block. The original page is then erased. Finally, the copy buffer contents are copied back to the page. This mechanism ensures that data cannot be lost due to power down, even during an operation. The EEPROM mechanism properly tracks all state information to provide complete safety and protection. Although it should not normally be possible, errors during programming can occur in certain circumstances, for example, the voltage rail dropping during programming. In these cases, theEESUPPregister can be used to finish an operation as described in the section called “Error During Programming” on page 520. Manual Copy Buffer Erase The copy buffer is only used when a main block is full because a word has been written seven times and there is no more room to store its latest version. In this situation, the latest versions of all the words in the block are copied to the copy buffer, allowing the main block to be erased safely, providing power down safety. If the copy buffer itself is full, then it must first be erased, which adds extra time. By performing a manual erase of the copy buffer, this overhead does not occur during a future write access. TheEREQbit in theEESUPPregister is set if the copy buffer must be erased. If so, the STARTbit can be written by the application to force the erase at a more convenient time. The EEDONEand EEINTregisters can be used to detect completion. Debug Mass Erase The EEPROM debug mass erase allows the developer to mass erase the EEPROM. For the mass erase to occur correctly, there can be no active EEPROM operations. After the last EEPROM operation, the application must ensure that no EEPROM registers are updated, including modifying the EEBLOCKand theEEOFFSETregisters without doing an actual read or write operation. To hold off these operations, the application should reset the EEPROM module by setting theR0bit in the EEPROMSoftwareReset(SREEPROM ) register, wait untilWORKINGbit in theEEPROMDone Status(EEDONE) register is clear, and then enable the debug mass erase by setting theMEbit in the EEPROMDebugMassErase(EEDBGME) register. Error During Programming Operations such as data-write, password set, protection set, and copy buffer erase may perform multiple operations. For example, a normal write performs two underlying writes: the control word write and the data write. If the control word writes but the data fails (for example, due to a voltage drop), the overall write fails with indication provided in theEEDONEregister. Failure and the corrective action is broken down by the type of operation: ■ If a normal write fails such that the control word is written but the data fails to write, the safe course of action is to retry the operation once the system is otherwise stable, for example, when the voltage is stabilized. After the retry, the control word and write data are advanced to the next location. ■ If a password or protection write fails, the safe course of action is to retry the operation once the system is otherwise stable. In the event that multi-word passwords may be written outside of a manufacturing or bring-up mode, care must be taken to ensure all words are written in immediate succession. If not, then partial password unlock would need to be supported to recover. June 12, 2014520 Texas Instruments-Production Data Internal Memory

■ If the word write requires the block to be written to the copy buffer, then it is possible to fail or lose power during the subsequent operations. A control word mechanism is used to track what step the EEPROM was in if a failure occurs. If not completed, theEESUPPregister indicates the partial completion, and theEESUPPSTARTbit can be written to allow it to continue to completion. ■ If a copy buffer erase fails or power is lost while erasing, theEESUPPregister indicates it is not complete and allows it to be restarted After a reset and prior to writing any data to the EEPROM, software must read theEESUPPregister and check for the presence of any error condition which may indicate that a write or erase was in progress when the system was reset due to a voltage drop. If either thePRETRYor ERETRYbits are set, the peripheral should be reset by setting and then clearing theR0bit in theEEPROMSoftware Reset(SREEPROM) register and waiting for theWORKINGbit in theEEDONEregister to clear before again checking theEESUPPregister for error indicators. This procedure should allow the EEPROM to recover from the write or erase error. In very isolated cases, theEESUPPregister may continue to register an error after this operation, in which case the reset should be repeated. After recovery, the application should rewrite the data which was being programmed when the initial failure occurred. Soft Reset Handling The following soft resets should not be asserted during an EEPROM program or erase operation: ■ Software reset (SYSRESREQ) ■ Software peripheral reset ■ Watchdog reset ■ MOSC failure reset The WORKINGbit of theEEDONEregister can be checked before the reset is asserted to see if an EEPROM program or erase operation is occurring. Soft resets may occur when using a debugger and should be avoided during an EEPROM operation. A reset such as the Watchdog reset can be mapped to an external reset using a GPIO, or Hibernate can be entered, if time is not a concern. Endurance Endurance is per meta-block which is 2 blocks. Endurance is measured in two ways: 1. To the application, it is the number of writes that can be performed. 2. To the microcontroller, it is the number of erases that can be performed on the meta-block. Because of the second measure, the number of writes depends on how the writes are performed. For example: ■ One word can be written more than 500K times, but, these writes impact the meta-block that the word is within. As a result, writing one word 500K times, then trying to write a nearby word 500K times is not assured to work. To ensure success, the words should be written more in parallel. ■ All words can be written in a sweep with a total of more than 500K sweeps which updates all words more than 500K times. 521June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

■ Different words can be written such that any or all words can be written more than 500K times when write counts per word stay about the same. For example, offset 0 could be written 3 times, then offset 1 could be written 2 times, then offset 2 is written 4 times, then offset 1 is written twice, then offset 0 is written again. As a result, all 3 offsets would have 4 writes at the end of the sequence. This kind of balancing within 7 writes maximizes the endurance of different words within the same meta-block.

8.2.4.2 EEPROMInitializationandConfiguration

Before writing to any EEPROM registers, the clock to the EEPROM module must be enabled through the EEPROMRunModeClockGatingControl(RCGCEEPROM) register (see page 344) and the following initialization steps must be executed: 1. Insert delay (6 cycles plus function call overhead). 2. Poll theWORKINGbit in theEEPROMDoneStatus(EEDONE) register until it is clear, indicating that the EEPROM has completed its power-on initialization. WhenWORKING=0, continue. 3. Read thePRETRYand ERETRYbits in theEEPROMSupportControlandStatus(EESUPP) register. If either of the bits are set, return an error, else continue. 4. Reset the EEPROM module using theEEPROMSoftwareReset(SREEPROM) register at offset 0x558 in the System Control register space. 5. Insert delay (6 cycles plus function call overhead). 6. Poll theWORKINGbit in theEEPROMDoneStatus(EEDONE) register to determine when it is clear. WhenWORKING=0, continue. 7. Read thePRETRYand ERETRYbits in theEESUPPregister. If either of the bits are set, return an error, else the EEPROM initialization is complete and software may use the peripheral as normal. Important: Failure to perform these initialization steps after a reset may lead to incorrect operation or permanent data loss if the EEPROM is later written. If thePRETRYor ERETRYbits are set in theEESUPPregister, the EEPROM was unable to recover its state. If power is stable when this occurs, this indicates a fatal error and is likely an indication that the EEPROM memory has exceeded its specified lifetime write/erase specification. If the supply voltage is unstable when this return code is observed, retrying the operation once the voltage is stabilized may clear the error. The EEPROM initialization function code is named EEPROMinit( ) in TivaWare, which can be downloaded fromhttp://www.ti.com/tivaware.

8.3 RegisterMap

Table 8-3 on page 523 lists the ROM Controller register and the Flash memory and control registers. The offset listed is a hexadecimal increment to the particular memory controller's base address. The Flash memory register offsets are relative to the Flash memory control base address of 0x400F.D000. The EEPROM registers are relative to the EEPROM base address of 0x400A.F000. The ROM and Flash memory protection register offsets are relative to the System Control base address of 0x400F.E000. June 12, 2014522 Texas Instruments-Production Data Internal Memory

Table8-3.FlashRegisterMap See pageDescriptionResetTypeNameOffset FlashMemoryRegisters(FlashControlOffset) 525Flash Memory Address0x0000.0000RWFMA0x000 526Flash Memory Data0x0000.0000RWFMD0x004 527Flash Memory Control0x0000.0000RWFMC0x008 529Flash Controller Raw Interrupt Status0x0000.0000ROFCRIS0x00C 532Flash Controller Interrupt Mask0x0000.0000RWFCIM0x010 534Flash Controller Masked Interrupt Status and Clear0x0000.0000RW1CFCMISC0x014 537Flash Memory Control 20x0000.0000RWFMC20x020 538Flash Write Buffer Valid0x0000.0000RWFWBVAL0x030 539Flash Write Buffer n0x0000.0000RWFWBn0x100 - 0x17C 540Flash Size0x0000.001FROFSIZE0xFC0 541SRAM Size0x0000.005FROSSIZE0xFC4 542ROM Software Map0x0000.0000ROROMSWMAP0xFCC EEPROMRegisters(EEPROMControlOffset) 543EEPROM Size Information0x0020.0200ROEESIZE0x000 544EEPROM Current Block0x0000.0000RWEEBLOCK0x004 545EEPROM Current Offset0x0000.0000RWEEOFFSET0x008 546EEPROM Read-Write-RWEERDWR0x010 547EEPROM Read-Write with Increment-RWEERDWRINC0x014 548EEPROM Done Status0x0000.0000ROEEDONE0x018 550EEPROM Support Control and Status-RWEESUPP0x01C 552EEPROM Unlock-RWEEUNLOCK0x020 553EEPROM Protection0x0000.0000RWEEPROT0x030 555EEPROM Password-RWEEPASS00x034 555EEPROM Password-RWEEPASS10x038 555EEPROM Password-RWEEPASS20x03C 556EEPROM Interrupt0x0000.0000RWEEINT0x040 557EEPROM Block Hide0x0000.0000RWEEHIDE0x050 558EEPROM Debug Mass Erase0x0000.0000RWEEDBGME0x080 559EEPROM Peripheral Properties0x0000.001FROEEPROMPP0xFC0 523June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table8-3.FlashRegisterMap (continued) See pageDescriptionResetTypeNameOffset MemoryRegisters(SystemControlOffset) 560ROM Control-RW1CRMCTL0x0F0 561Flash Memory Protection Read Enable 00xFFFF.FFFFRWFMPRE00x130 561Flash Memory Protection Read Enable 00xFFFF.FFFFRWFMPRE00x200 562Flash Memory Protection Program Enable 00xFFFF.FFFFRWFMPPE00x134 562Flash Memory Protection Program Enable 00xFFFF.FFFFRWFMPPE00x400 563Boot Configuration0xFFFF.FFFEROBOOTCFG0x1D0 566User Register 00xFFFF.FFFFRWUSER_REG00x1E0 566User Register 10xFFFF.FFFFRWUSER_REG10x1E4 566User Register 20xFFFF.FFFFRWUSER_REG20x1E8 566User Register 30xFFFF.FFFFRWUSER_REG30x1EC

8.4 FlashMemoryRegisterDescriptions(FlashControlOffset)

This section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000. June 12, 2014524 Texas Instruments-Production Data Internal Memory

Register1:FlashMemoryAddress(FMA),offset0x000 During a single word write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During a write operation that uses the write buffer, this register contains a 128-byte (32-word) aligned address that specifies the start of the 32-word block to be written. During erase operations, this register contains a 1 KB-aligned CPU byte address and specifies which block is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Base 0x400F.D000 Offset 0x000 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 OFFSET RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:16 Address Offset Address offset in Flash memory where operation is performed, except for non-volatile registers (see “Non-Volatile Register Programming” on page 515 for details on values for this field). 0x0RWOFFSET15:0 525June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register2:FlashMemoryData(FMD),offset0x004 This register contains the data to be written during the programming cycle. This register is not used during erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type RW, reset 0x0000.0000 16171819202122232425262728293031 DATA RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset 0123456789101112131415 DATA RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Data Value Data value for write operation. 0x0000.0000RWDATA31:0 June 12, 2014526 Texas Instruments-Production Data Internal Memory

Register3:FlashMemoryControl(FMC),offset0x008 When this register is written, the Flash memory controller initiates the appropriate access cycle for the location specified by theFlashMemoryAddress(FMA) register (see page 525). If the access is a write access, the data contained in theFlashMemoryData(FMD) register (see page 526) is written to the specified address. This register must be the final register written and initiates the memory operation. The four control bits in the lower byte of this register are used to initiate memory operations. Care must be taken not to set multiple control bits as the results of such an operation are unpredictable. Flash Memory Control (FMC) Base 0x400F.D000 Offset 0x008 Type RW, reset 0x0000.0000 16171819202122232425262728293031 WRKEY WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType 0000000000000000Reset 0123456789101112131415 WRITEERASEMERASECOMTreserved RWRWRWRWROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Flash Memory Write Key This field contains a write key, which is used to minimize the incidence of accidental Flash memory writes. Depending on the value of theKEY bit in theBOOTCFGregister, the value 0xA442 or 0x71D5 must be written into this field for a Flash memory write to occur. Writes to the FMCregister without thisWRKEYvalue are ignored. A read of this field returns the value 0. 0x0000WOWRKEY31:16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00ROreserved15:4 Commit Register Value This bit is used to commit writes to Flash-memory-resident registers and to monitor the progress of that process. DescriptionValue A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous commit access is complete. Set this bit to commit (write) the register value to a Flash-memory-resident register. When read, a 1 indicates that the previous commit access is not complete. See “Non-Volatile Register Programming” on page 515 for more information on programming Flash-memory-resident registers. 0RWCOMT3 527June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Mass Erase Flash Memory This bit is used to mass erase the Flash main memory and to monitor the progress of that process. DescriptionValue A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous mass erase operation is complete. Set this bit to erase the Flash main memory. When read, a 1 indicates that the previous mass erase operation is not complete. For information on erase time, see “Flash Memory and EEPROM” on page 1217. 0RWMERASE2 Erase a Page of Flash Memory This bit is used to erase a page of Flash memory and to monitor the progress of that process. DescriptionValue A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous page erase operation is complete. Set this bit to erase the Flash memory page specified by the contents of theFMAregister. When read, a 1 indicates that the previous page erase operation is not complete. For information on erase time, see “Flash Memory and EEPROM” on page 1217. 0RWERASE1 Write a Word into Flash Memory This bit is used to write a word into Flash memory and to monitor the progress of that process. DescriptionValue A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous write update operation is complete. Set this bit to write the data stored in theFMDregister into the Flash memory location specified by the contents of theFMA register. When read, a 1 indicates that the write update operation is not complete. For information on programming time, see “Flash Memory and EEPROM” on page 1217. 0RWWRITE0 June 12, 2014528 Texas Instruments-Production Data Internal Memory

Register4:FlashControllerRawInterruptStatus(FCRIS),offset0x00C This register indicates that the Flash memory controller has an interrupt condition. An interrupt is sent to the interrupt controller only if the correspondingFCIMregister bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 ARISPRISERISreservedVOLTRISINVDRISERRISreservedPROGRISreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:14 Program Verify Error Raw Interrupt Status DescriptionValue An interrupt has not occurred.0 An interrupt is pending because the verify of a PROGRAM operation failed. If this error occurs when using the Flash write buffer, software must inspect the affected words to determine where the error occurred. This bit is cleared by writing a 1 to thePROGMISCbit in theFCMISC register. 0ROPROGRIS13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12 Erase Verify Error Raw Interrupt Status DescriptionValue An interrupt has not occurred.0 An interrupt is pending because the verify of an ERASE operation failed. If this error occurs when using the Flash write buffer, software must inspect the affected words to determine where the error occurred. This bit is cleared by writing a 1 to theERMISCbit in theFCMISC register. 0ROERRIS11 529June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Invalid Data Raw Interrupt Status DescriptionValue An interrupt has not occurred.0 An interrupt is pending because a bit that was previously programmed as a 0 is now being requested to be programmed as a 1. This bit is cleared by writing a 1 to theINVMISCbit in theFCMISC register. 0ROINVDRIS10 Pump Voltage Raw Interrupt Status DescriptionValue An interrupt has not occurred.0 An interrupt is pending because the regulated voltage of the pump went out of spec during the Flash operation and the operation was terminated. This bit is cleared by writing a 1 to theVOLTMISCbit in theFCMISC register. 0ROVOLTRIS9 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved8:3 EEPROM Raw Interrupt Status This bit provides status EEPROM operation. DescriptionValue An EEPROM interrupt has not occurred.0 An EEPROM interrupt has occurred.1 This bit is cleared by writing a 1 to theEMISCbit in theFCMISCregister. 0ROERIS2 Programming Raw Interrupt Status This bit provides status on programming cycles which are write or erase actions generated through theFMCor FMC2register bits (see page 527 and page 537). DescriptionValue The programming or erase cycle has not completed.0 The programming or erase cycle has completed.1 This status is sent to the interrupt controller when thePMASKbit in the FCIMregister is set. This bit is cleared by writing a 1 to thePMISCbit in theFCMISCregister. 0ROPRIS1 June 12, 2014530 Texas Instruments-Production Data Internal Memory

DescriptionResetTypeNameBit/Field Access Raw Interrupt Status DescriptionValue No access has tried to improperly program or erase the Flash memory. A program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in theFMPPEnregisters. This status is sent to the interrupt controller when theAMASKbit in the FCIMregister is set. This bit is cleared by writing a 1 to theAMISCbit in theFCMISCregister. 0ROARIS0 531June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register5:FlashControllerInterruptMask(FCIM),offset0x010 This register controls whether the Flash memory controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 AMASKPMASKEMASKreservedVOLTMASKINVDMASKERMASKreservedPROGMASKreserved RWRWRWRORORORORORORWRWRWRORWROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:14 PROGVER Interrupt Mask DescriptionValue The PROGRISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when thePROGRIS bit is set. 0RWPROGMASK13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12 ERVER Interrupt Mask DescriptionValue The ERRISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when theERRIS bit is set. 0RWERMASK11 Invalid Data Interrupt Mask DescriptionValue The INVDRISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when theINVDRIS bit is set. 0RWINVDMASK10 June 12, 2014532 Texas Instruments-Production Data Internal Memory

DescriptionResetTypeNameBit/Field VOLT Interrupt Mask DescriptionValue The VOLTRISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when theVOLTRIS bit is set. 0RWVOLTMASK9 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved8:3 EEPROM Interrupt Mask DescriptionValue The ERISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when theERISbit is set. 0RWEMASK2 Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the interrupt controller. DescriptionValue The PRISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when thePRISbit is set. 0RWPMASK1 Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the interrupt controller. DescriptionValue The ARISinterrupt is suppressed and not sent to the interrupt controller. An interrupt is sent to the interrupt controller when theARISbit is set. 0RWAMASK0 533June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register6:FlashControllerMaskedInterruptStatusandClear(FCMISC), offset0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type RW1C, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 AMISCPMISCEMISCreservedVOLTMISCINVDMISCERMISCreservedPROGMISCreserved RW1CRW1CRW1CRORORORORORORW1CRW1CRW1CRORW1CROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:14 PROGVER Masked Interrupt Status and Clear DescriptionValue When read, a 0 indicates that an interrupt has not occurred. A write of 0 has no effect on the state of this bit. When read, a 1 indicates that an unmasked interrupt was signaled. Writing a 1 to this bit clearsPROGMISCand also thePROGRIS bit in theFCRISregister (see page 529). 0RW1CPROGMISC13 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved12 ERVER Masked Interrupt Status and Clear DescriptionValue When read, a 0 indicates that an interrupt has not occurred. A write of 0 has no effect on the state of this bit. When read, a 1 indicates that an unmasked interrupt was signaled. Writing a 1 to this bit clearsERMISCand also theERRISbit in the FCRISregister (see page 529). 0RW1CERMISC11 June 12, 2014534 Texas Instruments-Production Data Internal Memory

DescriptionResetTypeNameBit/Field Invalid Data Masked Interrupt Status and Clear DescriptionValue When read, a 0 indicates that an interrupt has not occurred. A write of 0 has no effect on the state of this bit. When read, a 1 indicates that an unmasked interrupt was signaled. Writing a 1 to this bit clearsINVDMISCand also theINVDRIS bit in theFCRISregister (see page 529). 0RW1CINVDMISC10 VOLT Masked Interrupt Status and Clear DescriptionValue When read, a 0 indicates that an interrupt has not occurred. A write of 0 has no effect on the state of this bit. When read, a 1 indicates that an unmasked interrupt was signaled. Writing a 1 to this bit clearsVOLTMISCand also theVOLTRIS bit in theFCRISregister (see page 529). 0RW1CVOLTMISC9 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved8:3 EEPROM Masked Interrupt Status and Clear DescriptionValue When read, a 0 indicates that an interrupt has not occurred. A write of 0 has no effect on the state of this bit. When read, a 1 indicates that an unmasked interrupt was signaled. Writing a 1 to this bit clearsEMISCand also theERISbit in the FCRISregister (see page 529). 0RW1CEMISC2 Programming Masked Interrupt Status and Clear DescriptionValue When read, a 0 indicates that a programming cycle complete interrupt has not occurred. A write of 0 has no effect on the state of this bit. When read, a 1 indicates that an unmasked interrupt was signaled because a programming cycle completed. Writing a 1 to this bit clearsPMISCand also thePRISbit in the FCRISregister (see page 529). 0RW1CPMISC1 535June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Access Masked Interrupt Status and Clear DescriptionValue When read, a 0 indicates that no improper accesses have occurred. A write of 0 has no effect on the state of this bit. When read, a 1 indicates that an unmasked interrupt was signaled because a program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in theFMPPEnregisters. Writing a 1 to this bit clearsAMISCand also theARISbit in the FCRISregister (see page 529). 0RW1CAMISC0 June 12, 2014536 Texas Instruments-Production Data Internal Memory

Register7:FlashMemoryControl2(FMC2),offset0x020 When this register is written, the Flash memory controller initiates the appropriate access cycle for the location specified by theFlashMemoryAddress(FMA) register (see page 525). If the access is a write access, the data contained in theFlashWriteBuffer(FWB) registers is written. This register must be the final register written as it initiates the memory operation. Flash Memory Control 2 (FMC2) Base 0x400F.D000 Offset 0x020 Type RW, reset 0x0000.0000 16171819202122232425262728293031 WRKEY WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType 0000000000000000Reset 0123456789101112131415 WRBUFreserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Flash Memory Write Key This field contains a write key, which is used to minimize the incidence of accidental Flash memory writes. Depending on the value of theKEY bit in theBOOTCFGregister, the value 0xA442 or 0x71D5 must be written into this field for a Flash memory write to occur. Writes to the FMC2register without thisWRKEYvalue are ignored. A read of this field returns the value 0. 0x0000WOWRKEY31:16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved15:1 Buffered Flash Memory Write This bit is used to start a buffered write to Flash memory. DescriptionValue A write of 0 has no effect on the state of this bit. When read, a 0 indicates that the previous buffered Flash memory write access is complete. Set this bit to write the data stored in theFWBnregisters to the location specified by the contents of theFMAregister. When read, a 1 indicates that the previous buffered Flash memory write access is not complete. For information on programming time, see “Flash Memory and EEPROM” on page 1217. 0RWWRBUF0 537June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register8:FlashWriteBufferValid(FWBVAL),offset0x030 This register provides a bitwise status of whichFWBnregisters have been written by the processor since the last write of the Flash memory write buffer. The entries with a 1 are written on the next write of the Flash memory write buffer. This register is cleared after the write operation by hardware. A protection violation on the write operation also clears this status. Software can program the same 32 words to various Flash memory locations by setting theFWB[n] bits after they are cleared by the write operation. The next write operation then uses the same data as the previous one. In addition, if aFWBnregister change should not be written to Flash memory, software can clear the correspondingFWB[n]bit to preserve the existing data when the next write operation occurs. Flash Write Buffer Valid (FWBVAL) Base 0x400F.D000 Offset 0x030 Type RW, reset 0x0000.0000 16171819202122232425262728293031 FWB[n] RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset 0123456789101112131415 FWB[n] RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Flash Memory Write Buffer DescriptionValue The correspondingFWBnregister has no new data to be written.0 The correspondingFWBnregister has been updated since the last buffer write operation and is ready to be written to Flash memory. Bit 0 corresponds toFWB0, offset 0x100, and bit 31 corresponds to FWB31, offset 0x13C. 0x0RWFWB[n]31:0 June 12, 2014538 Texas Instruments-Production Data Internal Memory

Register9:FlashWriteBuffern(FWBn),offset0x100-0x17C These 32 registers hold the contents of the data to be written into the Flash memory on a buffered Flash memory write operation. The offset selects one of the 32-bit registers. OnlyFWBnregisters that have been updated since the preceding buffered Flash memory write operation are written into the Flash memory, so it is not necessary to write the entire bank of registers in order to write 1 or 2 words. TheFWBnregisters are written into the Flash memory with theFWB0register corresponding to the address contained inFMA. FWB1is written to the addressFMA+0x4 etc. Note that only data bits that are 0 result in the Flash memory being modified. A data bit that is 1 leaves the content of the Flash memory bit at its previous value. Flash Write Buffer n (FWBn) Base 0x400F.D000 Offset 0x100 - 0x17C Type RW, reset 0x0000.0000 16171819202122232425262728293031 DATA RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset 0123456789101112131415 DATA RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Data Data to be written into the Flash memory. 0x0000.0000RWDATA31:0 539June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register10:FlashSize(FSIZE),offset0xFC0 This register indicates the size of the on-chip Flash memory. Important: This register should be used to determine the size of the Flash memory that is implemented on this microcontroller. However, to support legacy software, theDC0 register is available. A read of theDC0register correctly identifies legacy memory sizes. Software must use theFSIZEregister for memory sizes that are not listed in theDC0 register description. Flash Size (FSIZE) Base 0x400F.D000 Offset 0xFC0 Type RO, reset 0x0000.001F 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 SIZE ROROROROROROROROROROROROROROROROType 1111100000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:16 Flash Size Indicates the size of the on-chip Flash memory. DescriptionValue

64 KB of Flash0x001F

0x1FROSIZE15:0 June 12, 2014540 Texas Instruments-Production Data Internal Memory

Register11:SRAMSize(SSIZE),offset0xFC4 This register indicates the size of the on-chip SRAM. Important: This register should be used to determine the size of the SRAM that is implemented on this microcontroller. However, to support legacy software, theDC0register is available. A read of theDC0register correctly identifies legacy memory sizes. Software must use theSSIZEregister for memory sizes that are not listed in theDC0register description. SRAM Size (SSIZE) Base 0x400F.D000 Offset 0xFC4 Type RO, reset 0x0000.005F 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 SIZE ROROROROROROROROROROROROROROROROType 1111101000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:16 SRAM Size Indicates the size of the on-chip SRAM. DescriptionValue

24 KB of SRAM0x005F

0x5FROSIZE15:0 541June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register12:ROMSoftwareMap(ROMSWMAP),offset0xFCC This register indicates the presence of third-party software in the on-chip ROM. Important: This register should be used to determine the presence of third-party software in the on-chip ROM on this microcontroller. However, to support legacy software, the NVMSTATregister is available. A read of theTPSWbit in theNVMSTATregister correctly identifies the presence of legacy third-party software. Software should use the ROMSWMAPregister for software that is not on legacy devices. ROM Software Map (ROMSWMAP) Base 0x400F.D000 Offset 0xFCC Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 SAFERTOSreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000ROreserved31:1 SafeRTOS Present DescriptionValue SafeRTOS is not in the on-chip ROM.0 SafeRTOS is in the on-chip ROM.1 0x0ROSAFERTOS0

8.5 EEPROMRegisterDescriptions(EEPROMOffset)

This section lists and describes the EEPROM registers, in numerical order by address offset. Registers in this section are relative to the EEPROM base address of 0x400A.F000. Note that the EEPROM module clock must be enabled before the registers can be programmed (see page 344). There must be a delay of 3 system clocks after the EEPROM module clock is enabled before any EEPROM module registers are accessed. In addition, after enabling or resetting the EEPROM module, software must wait until theWORKINGbit in theEEDONEregister is clear before accessing any EEPROM registers. June 12, 2014542 Texas Instruments-Production Data Internal Memory

Register13:EEPROMSizeInformation(EESIZE),offset0x000 The EESIZEregister indicates the number of 16-word blocks and 32-bit words in the EEPROM. EEPROM Size Information (EESIZE) Base 0x400A.F000 Offset 0x000 Type RO, reset 0x0020.0200 16171819202122232425262728293031 BLKCNTreserved ROROROROROROROROROROROROROROROROType 0000010000000000Reset 0123456789101112131415 WORDCNT ROROROROROROROROROROROROROROROROType 0000000001000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved31:27 Number of 16-Word Blocks This value encoded in this field describes the number of 16-word blocks in the EEPROM. 0x20ROBLKCNT26:16 Number of 32-Bit Words This value encoded in this field describes the number of 32-bit words in the EEPROM. 0x200ROWORDCNT15:0 543June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register14:EEPROMCurrentBlock(EEBLOCK),offset0x004 The EEBLOCKregister is used to select the EEPROM block for subsequent reads, writes, and protection control. The value is a block offset into the EEPROM, such that the first block is 0, then second block is 1, etc. Each block contains 16 words. Attempts to set an invalid block causes the BLOCKfield to be configured to 0. To verify that the intended block is being accessed, software can read theBLOCKfield after it has been written. An invalid block can be either a non-existent block or a block that has been hidden using theEEHIDEregister. Note that block 0 cannot be hidden. EEPROM Current Block (EEBLOCK) Base 0x400A.F000 Offset 0x004 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 BLOCK RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00000ROreserved31:16 Current Block This field specifies the block in the EEPROM that is selected for subsequent accesses. Once this field is configured, the read-write registers operate against the specified block, using theEEOFFSET register to select the word within the block. Additionally, the protection and unlock registers are used for the selected block. The maximum value that can be written into this register is determined by the block count, as indicated by theEESIZEregister. Attempts to write this field larger than the maximum number of blocks or to a locked block causes this field to be configured to 0. 0x0000RWBLOCK15:0 June 12, 2014544 Texas Instruments-Production Data Internal Memory

Register15:EEPROMCurrentOffset(EEOFFSET),offset0x008 The EEOFFSETregister is used to select the EEPROM word to read or write within the block selected by theEEBLOCKregister. The value is a word offset into the block. Because accesses to the EERDWRINCregister change the offset, software can read the contents of this register to determine the current offset. EEPROM Current Offset (EEOFFSET) Base 0x400A.F000 Offset 0x008 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 OFFSETreserved RWRWRWRWROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:4 Current Address Offset This value is the current address specified as an offset into the block selected by theEEBLOCKregister. Once configured, the read-write registers, EERDRWRand EERDWRINC, operate against that address. The offset is automatically incremented by theEERDWRINCregister, with wrap around within the block, which means the offset is incremented from 15 back to 0. 0x0RWOFFSET3:0 545June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register16:EEPROMRead-Write(EERDWR),offset0x010 The EERDWRregister is used to read or write the EEPROM word at the address pointed to by the EEBLOCKand EEOFFSETregisters. If the protection or access rules do not permit access, the operation is handled as follows: if reading is not allowed, the value 0xFFFF.FFFF is returned in all cases; if writing is not allowed, theEEDONEregister is configured to indicate an error. EEPROM Read-Write (EERDWR) Base 0x400A.F000 Offset 0x010 Type RW, reset - 16171819202122232425262728293031 VALUE RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0123456789101112131415 VALUE RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType DescriptionResetTypeNameBit/Field EEPROM Read or Write Data On a read, this field contains the value at the word pointed to by EEOFFSET. On a write, this field contains the data to be stored at the word pointed to byEEOFFSET. For writes, configuring this field starts the write process. If protection and access rules do not permit reads, all 1s are returned. If protection and access rules do not permit writes, the write fails and theEEDONEregister indicates failure. -RWVALUE31:0 June 12, 2014546 Texas Instruments-Production Data Internal Memory

Register17:EEPROMRead-WritewithIncrement(EERDWRINC),offset0x014 The EERDWRINCregister is used to read or write the EEPROM word at the address pointed to by the EEBLOCKand EEOFFSETregisters, and then increment theOFFSETfield in theEEOFFSET register. If the protection or access rules do not permit access, the operation is handled as follows: if reading is not allowed, the value 0xFFFF.FFFF is returned in all cases; if writing is not allowed, the EEDONEregister is configured to indicate an error. In all cases, theOFFSETfield is incremented. If the last value is reached,OFFSETwraps around to 0 and points to the first word. EEPROM Read-Write with Increment (EERDWRINC) Base 0x400A.F000 Offset 0x014 Type RW, reset - 16171819202122232425262728293031 VALUE RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0123456789101112131415 VALUE RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType DescriptionResetTypeNameBit/Field EEPROM Read or Write Data with Increment On a read, this field contains the value at the word pointed to by EEOFFSET. On a write, this field contains the data to be stored at the word pointed to byEEOFFSET. For writes, configuring this field starts the write process. If protection and access rules do not permit reads, all 1s are returned. If protection and access rules do not permit writes, the write fails and theEEDONEregister indicates failure. Regardless of error, theOFFSETfield in theEEOFFSETregister is incremented by 1, and the value wraps around if the last word is reached. -RWVALUE31:0 547June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register18:EEPROMDoneStatus(EEDONE),offset0x018 The EEDONEregister indicates the successful or failed completion of a write using theEERDWR or EERDWRINCregister, protection set using theEEPROTregister, password registered using the EEPASSregister, copy buffer erase or program retry using theEESUPPregister, or a debug mass erase using theEEDBGMEregister. TheEEDONEregister can be used with theEEINTregister to generate an interrupt to report the status. The normal usage is to poll theEEDONEregister or read the register after an interrupt is triggered. When theEEDONEbit 0 is set, then the operation is still in progress. When theEEDONEbit 0 is clear, then the value ofEEDONEindicates the completion status. IfEEDONE==0, then the write completed successfully. IfEEDONE!=0, then an error occurred and the source of the error is given by the set bit(s). If an error occurs, corrective action may be taken as explained on page 550. EEPROM Done Status (EEDONE) Base 0x400A.F000 Offset 0x018 Type RO, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 WORKINGreservedWKERASEWKCOPYNOPERMWRBUSYreserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:6 Write Busy DescriptionValue No error0 An attempt to access the EEPROM was made while a write was in progress. 0ROWRBUSY5 Write Without Permission DescriptionValue No error0 An attempt was made to write without permission. This error can result because the block is locked, the write violates the programmed access protection, or when an attempt is made to write a password when the password has already been written. 0RONOPERM4 June 12, 2014548 Texas Instruments-Production Data Internal Memory

DescriptionResetTypeNameBit/Field Working on a Copy DescriptionValue The EEPROM is not copying.0 A write is in progress and is waiting for the EEPROM to copy to or from the copy buffer. 0ROWKCOPY3 Working on an Erase DescriptionValue The EEPROM is not erasing.0 A write is in progress and the original block is being erased after being copied. 0ROWKERASE2 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved1 EEPROM Working DescriptionValue The EEPROM is not working.0 The EEPROM is performing the requested operation.1 0ROWORKING0 549June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register19:EEPROMSupportControlandStatus(EESUPP),offset0x01C The EESUPPregister indicates if internal operations are required because an internal copy buffer must be erased or a programming failure has occurred and the operation must be completed. These conditions are explained below as well as in more detail in the section called “Manual Copy Buffer Erase” on page 520 and the section called “Error During Programming” on page 520. ■ The EREQbit is set if the internal copy buffer must be erased the next time it is used because it is full. To avoid the delay of waiting for the copy buffer to be erased on the next write, it can be erased manually using this register by setting theSTARTbit. ■ If either PRETRYor ERETRYis set indicating that an operation must be completed, setting the STARTbit causes the operation to be performed again. ■ The PRETRYand ERETRYbits are cleared automatically after the failed operation has been successfully completed. These bits are not changed by reset, so any condition that occurred before a reset is still indicated after a reset. EEPROM Support Control and Status (EESUPP) Base 0x400A.F000 Offset 0x01C Type RW, reset - 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 STARTEREQERETRYPRETRYreserved RWROROROROROROROROROROROROROROROType 0---000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:4 Programming Must Be Retried DescriptionValue Programming has not failed.0 Programming from a copy in either direction failed to complete and must be restarted by setting theSTARTbit. -ROPRETRY3 Erase Must Be Retried DescriptionValue Erasing has not failed.0 Erasing failed to complete and must be restarted by setting the STARTbit. If the failed erase is due to the erase of a main buffer, the copy will be performed after the erase completes successfully. -ROERETRY2 June 12, 2014550 Texas Instruments-Production Data Internal Memory

DescriptionResetTypeNameBit/Field Erase Required DescriptionValue The copy buffer has available space.0 An erase of the copy buffer is required.1 -ROEREQ1 Start Erase Setting this bit starts error recovery if thePRETRYor ERETRYbit is set. If both thePRETRYand theERETRYbits are clear, setting this bit starts erasing the copy buffer ifEREQis set. If none of the other bits in this register are set, setting this bit is ignored. After this bit is set, the WORKINGbit in theEEDONEregister is set and is cleared when the operation is complete. In addition, theEEINTregister can be used to generate an interrupt on completion. If this bit is set while an operation is in progress, the write is ignored. The STARTbit is automatically cleared when the operation completes. 0RWSTART0 551June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register20:EEPROMUnlock(EEUNLOCK),offset0x020 The EEUNLOCKregister can be used to unlock the whole EEPROM or a single block using a password. Unlocking is only required if a password is registered using theEEPASSnregisters for the block that is selected by theEEBLOCKregister. If block 0 has a password, it locks the remaining blocks from any type of access, but uses its own protection mechanism, for example readable, but not writable when locked. In addition, if block 0 has a password, it must be unlocked before unlocking any other block. The EEUNLOCKregister is written between 1 and 3 times to form the 32-bit, 64-bit, or 96-bit password registered using theEEPASSnregisters. The value used to configure theEEPASS0 register must always be written last. For example, for a 96-bit password, the value used to configure the EEPASS2register must be written first followed by theEEPASS1and EEPASS0register values. The block or the whole EEPROM can be re-locked by writing 0xFFFF.FFFF to this register. In the event that an invalid value is written to this register, the block remains locked. The state of the EEPROM lock can be determined by reading back theEEUNLOCKregister. If a multi-word password is set and the number of words written is incorrect, writing 0xFFFF.FFFF to this register reverts the EEPROM lock to the locked state, and the proper unlock sequence can be retried. Note that the internal logic is balanced to prevent any electrical or time-based attack being used to find the correct password or its length. EEPROM Unlock (EEUNLOCK) Base 0x400A.F000 Offset 0x020 Type RW, reset - 16171819202122232425262728293031 UNLOCK RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0123456789101112131415 UNLOCK RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType DescriptionResetTypeNameBit/Field EEPROM Unlock DescriptionValue The EEPROM is locked.0 The EEPROM is unlocked.1 The EEPROM is locked if the block referenced by theEEBLOCKregister has a password registered, or if the master block (block 0) has a password. Unlocking is performed by writing the password to this register. The block or the EEPROM stays unlocked until it is locked again or until the next reset. It can be locked again by writing 0xFFFF.FFFF to this register. -RWUNLOCK31:0 June 12, 2014552 Texas Instruments-Production Data Internal Memory

Register21:EEPROMProtection(EEPROT),offset0x030 The EEPROTregister is used to set or read the protection for the current block, as selected by the EEBLOCKregister. Protection and access control is used to determine when a block's contents can be read or written. The protection level for block 0 sets the minimum protection level for the entire EEPROM. For example, if thePROTfield is configured to 0x1 for block 0, then block 1 could be configured with thePROTfield to be 0x1, 0x2, or 0x3, but not 0x0. EEPROM Protection (EEPROT) Base 0x400A.F000 Offset 0x030 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 PROTACCreserved RWRWRWRWROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:4 Access Control DescriptionValue Both user and supervisor code may access this block of the EEPROM. Only supervisor code may access this block of the EEPROM. μDMA and Debug are also prevented from accessing the EEPROM. If this bit is set for block 0, then the whole EEPROM may only be accessed by supervisor code. 0RWACC3 553June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Protection Control The Protection bits control what context is needed for reading and writing the block selected by theEEBLOCKregister, or if block 0 is selected, all blocks. The following values are allowed: DescriptionValue This setting is the default. If there is no password, the block is not protected and is readable and writable. If there is a password, the block is readable, but only writable when unlocked. 0x0 If there is a password, the block is readable or writable only when unlocked. This value has no meaning when there is no password. 0x1 If there is no password, the block is readable, not writable. If there is a password, the block is readable only when unlocked, but is not writable under any conditions. 0x2 Reserved0x3 0x0RWPROT2:0 June 12, 2014554 Texas Instruments-Production Data Internal Memory

Register22:EEPROMPassword(EEPASS0),offset0x034 Register23:EEPROMPassword(EEPASS1),offset0x038 Register24:EEPROMPassword(EEPASS2),offset0x03C The EEPASSnregisters are used to configure a password for a block. A password may only be set once and cannot be changed. The password may be 32-bits, 64-bits, or 96-bits. Each word of the password can be any 32-bit value other than 0xFFFF.FFFF (all 1s). To set a password, theEEPASS0 register is written to with a value other than 0xFFFF.FFFF. When the write completes, as indicated in theEEDONEregister, the application may choose to write to theEEPASS1register with a value other than 0xFFFF.FFFF. When that write completes, the application may choose to write to the EEPASS2register with a value other than 0xFFFF.FFFF to create a 96-bit password. The registers do not have to be written consecutively, and theEEPASS1and EEPASS2registers may be written at a later date. Based on whether 1, 2, or all 3 registers have been written, the unlock code also requires the same number of words to unlock. Note: Once the password is written, the block is not actually locked until either a reset occurs or 0xFFFF.FFFF is written toEEUNLOCK. EEPROM Password (EEPASSn) Base 0x400A.F000 Offset 0x034 Type RW, reset - 16171819202122232425262728293031 PASS RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0123456789101112131415 PASS RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType DescriptionResetTypeNameBit/Field Password This register reads as 0x1 if a password is registered for this block and 0x0 if no password is registered. A write to this register if it reads as 0x0 sets the password. If an attempt is made to write to this register when it reads as 0x1, the write is ignored and theNOPERMbit in theEEDONE register is set. -RWPASS31:0 555June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register25:EEPROMInterrupt(EEINT),offset0x040 The EEINTregister is used to control whether an interrupt should be generated when a write to EEPROM completes as indicated by theEEDONEregister value changing from 0x1 to any other value. If theINTbit in this register is set, theERISbit in theFlashControllerRawInterruptStatus (FCRIS)register is set whenever theEEDONEregister value changes from 0x1 as the Flash memory and the EEPROM share an interrupt vector. EEPROM Interrupt (EEINT) Base 0x400A.F000 Offset 0x040 Type RW, reset 0x0000.0000 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 INTreserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:1 Interrupt Enable DescriptionValue No interrupt is generated.0 An interrupt is generated when theEEDONEregister transitions from 1 to 0 or an error occurs. TheEEDONEregister provides status after a write to an offset location as well as a write to the password and protection bits. 0RWINT0 June 12, 2014556 Texas Instruments-Production Data Internal Memory

Register26:EEPROMBlockHide(EEHIDE),offset0x050 The EEHIDEregister is used to hide one or more blocks other than block 0. Once hidden, the block is not accessible until the next reset. This model allows initialization code to have access to data which is not visible to the rest of the application. This register also provides for additional security in that there is no password to search for in the code or data. EEPROM Block Hide (EEHIDE) Base 0x400A.F000 Offset 0x050 Type RW, reset 0x0000.0000 16171819202122232425262728293031 Hn RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset 0123456789101112131415 reservedHn RORWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 0000000000000000Reset DescriptionResetTypeNameBit/Field Hide Block DescriptionValue The corresponding block is not hidden.0 The block number that corresponds to the bit number is hidden. A hidden block cannot be accessed, and theOFFSETvalue in the EEBLOCKregister cannot be set to that block number. If an attempt is made to configure theOFFSETfield to a hidden block, theEEBLOCKregister is cleared. Any attempt to clear a bit in this register that is set is ignored. 0x0000.000RWHn31:1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0ROreserved0 557June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register27:EEPROMDebugMassErase(EEDBGME),offset0x080 The EEDBGMEregister is used to mass erase the EEPROM block back to its default state from the factory. This register is intended to be used only for debug and test purposes, not in production environments. The erase takes place in such a way as to be secure. It first erases all data and then erases the protection mechanism. This register can only be written from supervisor mode by the core, and can also be written by the TM4C1233D5PZ debug controller when enabled. A key is used to avoid accidental use of this mechanism. Note that if a power down takes place while erasing, the mechanism should be used again to complete the operation. Powering off prematurely does not expose secured data. To start a mass erase, the whole register must be written as 0xE37B.0001. The register reads back as 0x1 until the erase is fully completed at which time it reads as 0x0. TheEEDONEregister is set to 0x1 when the erase is started and changes to 0x0 or an error when the mass erase is complete. Note that mass erasing the EEPROM block means that the wear-leveling counters are also reset to the factory default. EEPROM Debug Mass Erase (EEDBGME) Base 0x400A.F000 Offset 0x080 Type RW, reset 0x0000.0000 16171819202122232425262728293031 KEY WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType 0000000000000000Reset 0123456789101112131415 MEreserved RWROROROROROROROROROROROROROROROType 0000000000000000Reset DescriptionResetTypeNameBit/Field Erase Key This field must be written with 0xE37B for theMEfield to be effective. 0x0000WOKEY31:16 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000ROreserved15:1 Mass Erase DescriptionValue No action.0 When written as a 1, the EEPROM is mass erased. This bit continues to read as 1 until the EEPROM is fully erased. 0RWME0 June 12, 2014558 Texas Instruments-Production Data Internal Memory

Register28:EEPROMPeripheralProperties(EEPROMPP),offset0xFC0 The EEPROMPPregister indicates the size of the EEPROM for this part. EEPROM Peripheral Properties (EEPROMPP) Base 0x400A.F000 Offset 0xFC0 Type RO, reset 0x0000.001F 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 SIZEreserved ROROROROROROROROROROROROROROROROType 1111100000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0ROreserved31:5 2-KB EEPROM Size0x1FROSIZE4:0

8.6 MemoryRegisterDescriptions(SystemControlOffset)

The remainder of this section lists and describes the registers that reside in the System Control address space, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000. 559June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register29:ROMControl(RMCTL),offset0x0F0 This register provides control of the ROM controller state. This register offset is relative to the System Control base address of 0x400F.E000. At reset, the following sequence is performed: 1. The BOOTCFGregister is read. If theENbit is clear, the ROM Boot Loader is executed. 2. In the ROM Boot Loader, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 3. If theENbit is set or the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004. The user application begins executing. ROM Control (RMCTL) Base 0x400F.E000 Offset 0x0F0 Type RW1C, reset - 16171819202122232425262728293031 reserved ROROROROROROROROROROROROROROROROType 0000000000000000Reset 0123456789101112131415 BAreserved RW1CROROROROROROROROROROROROROROROType 1000000000000000Reset DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000.000ROreserved31:1 Boot Alias DescriptionValue The Flash memory is at address 0x0.0 The microcontroller's ROM appears at address 0x0.1 This bit is cleared by writing a 1 to this bit position. 1RW1CBA0 June 12, 2014560 Texas Instruments-Production Data Internal Memory

Register30:FlashMemoryProtectionReadEnable0(FMPRE0),offset0x130 and0x200 Note: The FMPRE0register is aliased for backwards compatibility. Note: Offset is relative to System Control base address of 0x400F.E000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEnstores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for theFMPREn and FMPPEnregisters are a value of 1 for all implemented 2-KB blocks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is RW0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 198. Each FMPREnregister controls a 64-k block of Flash. For additional information, see “Flash Memory Protection” on page 511. ■ FMPRE0: 0 to 64 KB Flash Memory Protection Read Enable n (FMPREn) Base 0x400F.E000 Offset 0x130 and 0x200 Type RW, reset 0xFFFF.FFFF 16171819202122232425262728293031 READ_ENABLE RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1111111111111111Reset 0123456789101112131415 READ_ENABLE RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1111111111111111Reset DescriptionResetTypeNameBit/Field Flash Read Enable Each bit configures a 2-KB flash block to be read only. The policies may be combined as shown in Table 8-1 on page 512. 0xFFFF.FFFFRWREAD_ENABLE31:0 561June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register31:FlashMemoryProtectionProgramEnable0(FMPPE0),offset 0x134and0x400 Note: The FMPPE0register is aliased for backwards compatibility. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREnstores the read-only protection bits). This register is loaded during the power-on reset sequence. The factory settings for theFMPREn and FMPPEnregisters are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is RW0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 198. For additional information, see “Flash Memory Protection” on page 511. Each FMPPEnregister controls a 64-k block of Flash. For additional information, see “Flash Memory Protection” on page 511. ■ FMPPE0: 0 to 64 KB Flash Memory Protection Program Enable n (FMPPEn) Base 0x400F.E000 Offset 0x134 and 0x400 Type RW, reset 0xFFFF.FFFF 16171819202122232425262728293031 PROG_ENABLE RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1111111111111111Reset 0123456789101112131415 PROG_ENABLE RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1111111111111111Reset DescriptionResetTypeNameBit/Field Flash Programming Enable Each bit configures a 2-KB flash block to be execute only. The policies may be combined as shown in Table 8-1 on page 512. 0xFFFF.FFFFRWPROG_ENABLE31:0 June 12, 2014562 Texas Instruments-Production Data Internal Memory

Register32:BootConfiguration(BOOTCFG),offset0x1D0 Note: Offset is relative to System Control base address of 0x400F.E000. Note: The BootConfiguration(BOOTCFG) register requires a POR before the committed changes take effect. This register is not written directly, but instead uses theFMDregister as explained in “Non-Volatile Register Programming” on page 515. This register provides configuration of a GPIO pin to enable the ROM Boot Loader as well as a write-once mechanism to disable external debugger access to the device. At reset, the user has the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal from Ports A-Q as configured by the bits in this register. At reset, the following sequence is performed: 1. The BOOTCFGregister is read. If theENbit is clear, the ROM Boot Loader is executed. 2. In the ROM Boot Loader, the status of the specified GPIO pin is compared with the specified polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 3. If theENbit is set or the status doesn't match the specified polarity, the data at address 0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to address 0x0000.0000 and execution continues out of the ROM Boot Loader. 4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from address 0x0000.0004. The user application begins executing. The DBG0bit is cleared by the factory and theDBG1bit is set, which enables external debuggers. Clearing theDBG1bit disables any external debugger access to the device, starting with the next power-up cycle of the device. TheNWbit indicates that bits in the register can be changed from 1 to 0. By committing the register values using theCOMTbit in theFMCregister, the register contents become non-volatile and are therefore retained following power cycling. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset when the register is not yet committed; any other type of reset does not affect this register. Once committed, the register retains its value through power-on reset. Once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 198. Boot Configuration (BOOTCFG) Base 0x400F.E000 Offset 0x1D0 Type RO, reset 0xFFFF.FFFE 16171819202122232425262728293031 reservedNW ROROROROROROROROROROROROROROROROType 1111111111111111Reset 0123456789101112131415 DBG0DBG1reservedKEYreservedENPOLPINPORT ROROROROROROROROROROROROROROROROType 0111111111111111Reset 563June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

DescriptionResetTypeNameBit/Field Not Written When set, this bit indicates that the values in this register can be changed from 1 to 0. When clear, this bit specifies that the contents of this register cannot be changed. 1RONW31 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0xFFFFROreserved30:16 Boot GPIO Port This field selects the port of the GPIO port pin that enables the ROM boot loader at reset. DescriptionValue Port A0x0 Port B0x1 Port C0x2 Port D0x3 Port E0x4 Port F0x5 Port G0x6 Port H0x7 0x7ROPORT15:13 Boot GPIO Pin This field selects the pin number of the GPIO port pin that enables the ROM boot loader at reset. DescriptionValue Pin 00x0 Pin 10x1 Pin 20x2 Pin 30x3 Pin 40x4 Pin 50x5 Pin 60x6 Pin 70x7 0x7ROPIN12:10 Boot GPIO Polarity When set, this bit selects a high level for the GPIO port pin to enable the ROM boot loader at reset. When clear, this bit selects a low level for the GPIO port pin. 1ROPOL9 Boot GPIO Enable Clearing this bit enables the use of a GPIO pin to enable the ROM Boot Loader at reset. When this bit is set, the contents of address 0x0000.0004 are checked to see if the Flash memory has been programmed. If the contents are not 0xFFFF.FFFF, the core executes out of Flash memory. If the Flash has not been programmed, the core executes out of ROM. 1ROEN8 June 12, 2014564 Texas Instruments-Production Data Internal Memory

DescriptionResetTypeNameBit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x7ROreserved7:5 KEY Select This bit chooses between using the value 0xA442 or 0x71D5 as the WRKEYvalue in theFMC/FMC2register. DescriptionValue The value 0x71D5 is used as theWRKEYin theFMC/FMC2 register. Writes to theFMC/FMC2register with a 0xA442 key are ignored. 0xA442 is used as theWRKEYin theFMC/FMC2register. Writes to theFMC/FMC2register with a 0x71D5 key are ignored. 1ROKEY4 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x3ROreserved3:2 Debug Control 1 The DBG1bit must be 1 andDBG0must be 0 for debug to be available. 1RODBG11 Debug Control 0 The DBG1bit must be 1 andDBG0must be 0 for debug to be available. 0RODBG00 565June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Register33:UserRegister0(USER_REG0),offset0x1E0 Register34:UserRegister1(USER_REG1),offset0x1E4 Register35:UserRegister2(USER_REG2),offset0x1E8 Register36:UserRegister3(USER_REG3),offset0x1EC Note: Offset is relative to System Control base address of 0x400F.E000. These registers each provide 32 bits of user-defined data that is non-volatile. Bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset when the register is not yet committed; any other type of reset does not affect this register. Once committed, the register retains its value through power-on reset. Once committed, the only way to restore the factory default value of this register is to perform the sequence detailed in “Recovering a "Locked" Microcontroller” on page 198. User Register n (USER_REGn) Base 0x400F.E000 Offset 0x1E0 Type RW, reset 0xFFFF.FFFF 16171819202122232425262728293031 DATA RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1111111111111111Reset 0123456789101112131415 DATA RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType 1111111111111111Reset DescriptionResetTypeNameBit/Field User Data Contains the user data value. This field is initialized to all 1s and once committed, retains its value through power-on reset. 0xFFFF.FFFFRWDATA31:0 June 12, 2014566 Texas Instruments-Production Data Internal Memory

9 MicroDirectMemoryAccess(μDMA)

The TM4C1233D5PZ microcontroller includes a Direct Memory Access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex™-M4F processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. The μDMA controller provides the following features: ■ ARM ® PrimeCell® 32-channel configurable µDMA controller ■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes – Basic for simple transfer scenarios – Ping-pong for continuous data flow – Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single request ■ Highly flexible and configurable channel operation – Independently configured and operated channels – Dedicated channels for supported on-chip modules – Flexible channel assignments – One channel each for receive and transmit path for bidirectional modules – Dedicated channel for software-initiated transfers – Per-channel configurable priority scheme – Optional software-initiated requests for any channel ■ Two levels of priority ■ Design optimizations for improved bus access performance between µDMA controller and the processor core – µDMA controller access is subordinate to core access – RAM striping – Peripheral bus segmentation ■ Data sizes of 8, 16, and 32 bits ■ Transfer size is programmable in binary steps from 1 to 1024 ■ Source and destination address increment size of byte, half-word, word, or no increment 567June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

■ Maskable peripheral requests ■ Interrupt on transfer completion, with a separate interrupt per channel

9.1 BlockDiagram

Figure9-1.μDMABlockDiagram System Memory CH Control T able T ransfer Buf fers Used by µ DMA uDMA Controller DMASRCENDP DMADSTENDP DMACHCTL DMASRCENDP DMADSTENDP DMACHCTRL DMA error Peripheral DMA Channel 0 Peripheral DMA Channel N -1 DMAST A T DMACFG DMACTLBASE DMAAL TBASE DMA W AITST A T DMASWREQ DMAUSEBURSTSET DMAUSEBURSTCLR DMAREQMASKSET DMAREQMASKCLR DMAENASET DMAENACLR DMAAL TSET DMAAL TCLR DMAPRIOSET DMAPRIOCLR DMAERRCLR request done request done General Peripheral N Registers Nested V ectored Interrupt Controller ( NVIC) ARM Cortex -M4F IRQ request done DMACHASGN DMACHIS DMACHMAPn

9.2 FunctionalDescription

The μDMA controller is a flexible and highly configurable DMA controller designed to work efficiently with the microcontroller's Cortex-M4F processor core. It supports multiple data sizes and address increment schemes, multiple levels of priority among DMA channels, and several transfer modes to allow for sophisticated programmed data transfers. The μDMA controller's usage of the bus is always subordinate to the processor core, so it never holds up a bus transaction by the processor. Because the μDMA controller is only using otherwise-idle bus cycles, the data transfer bandwidth it provides is essentially free, with no impact on the rest of the system. The bus architecture has been optimized to greatly enhance the ability of the processor core and the μDMA controller to efficiently share the on-chip bus, thus improving performance. The optimizations include RAM striping and peripheral bus segmentation, which in many cases allow both the processor core and the μDMA controller to access the bus and perform simultaneous data transfers. The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash memory and ROM are located on a separate internal bus, it is not possible to transfer data from the Flash memory or ROM with the μDMA controller. Each peripheral function that is supported has a dedicated channel on the μDMA controller that can be configured independently. The μDMA controller implements a unique configuration method using channel control structures that are maintained in system memory by the processor. While simple transfer modes are supported, it is also possible to build up sophisticated "task" lists in memory that allow the μDMA controller to perform arbitrary-sized transfers to and from arbitrary locations as part of a single transfer request. The μDMA controller also supports the use of ping-pong buffering to accommodate constant streaming of data to or from a peripheral. June 12, 2014568 Texas Instruments-Production Data Micro Direct Memory Access (μDMA)

Each channel also has a configurable arbitration size. The arbitration size is the number of items that are transferred in a burst before the μDMA controller re-arbitrates for channel priority. Using the arbitration size, it is possible to control exactly how many items are transferred to or from a peripheral each time it makes a μDMA service request.

9.2.1 ChannelAssignments

Each DMA channel has up to five possible assignments which are selected using theDMAChannel MapSelectn(DMACHMAPn) registers with 4-bit assignment fields for each µDMA channel. Table 9-1 on page 569 shows the µDMA channel mapping. The Enc. column shows the encoding for the respectiveDMACHMAPnbit field. Encodings 0x5 - 0xF are all reserved. To support legacy software which uses theDMAChannelAssignment(DMACHASGN) register, Enc. 0 is equivalent to aDMACHASGNbit being clear, and Enc. 1 is equivalent to aDMACHASGNbit being set. If the DMACHASGNregister is read, bit fields return 0 if the correspondingDMACHMAPnregister field value are equal to 0, otherwise they return 1 if the correspondingDMACHMAPnregister field values are not equal to 0. The Type indication in the table indicates if a particular peripheral uses a single request (S), burst request (B) or either (SB). Note: Channels noted in the table as "Software" may be assigned to peripherals in the future. However, they are currently available for software use. Channel 30 is dedicated for software use. The USB endpoints mapped to μDMA channels 0-3 can be changed with theUSBDMASEL register (see page 1141). Table9-1.μDMAChannelAssignments 43210Enc. TypePeripheralTypePeripheralTypePeripheralTypePeripheralTypePeripheralCh# BSoftwareBGPTimer 4ABSoftwareSBUART2 RXSBUSB0 EP1 RX0 BSoftwareBGPTimer 4BBSoftwareSBUART2 TXBUSB0 EP1 TX1 BSoftwareBSoftwareBSoftwareBGPTimer 3ABUSB0 EP2 RX2 BSoftwareBSoftwareBSoftwareBGPTimer 3BBUSB0 EP2 TX3 BSoftwareBGPIO ABSoftwareBGPTimer 2ABUSB0 EP3 RX4 BSoftwareBGPIO BBSoftwareBGPTimer 2BBUSB0 EP3 TX5 BSoftwareBGPIO CSBUART5 RXBGPTimer 2ABSoftware6 BSoftwareBGPIO DSBUART5 TXBGPTimer 2BBSoftware7 BSoftwareBGPTimer 5ABSoftwareSBUART1 RXSBUART0 RX8 BSoftwareBGPTimer 5BBSoftwareSBUART1 TXSBUART0 TX9 BSoftwareBGPWideTimer 0ASBUART6 RXSBSSI1 RXSBSSI0 RX10 BSoftwareBGPWideTimer 0BSBUART6 TXSBSSI1 TXSBSSI0 TX11 BGPIO KBGPWideTimer 1ASBSSI2 RXSBUART2 RXBSoftware12 BSoftwareBGPWideTimer 1BSBSSI2 TXSBUART2 TXBSoftware13 BSoftwareBGPIO ESBSSI3 RXBGPTimer 2ABADC0 SS014 BSoftwareBGPIO FSBSSI3 TXBGPTimer 2BBADC0 SS115 BSoftwareBGPWideTimer 2ASBUART3 RXBSoftwareBADC0 SS216 BSoftwareBGPWideTimer 2BSBUART3 TXBSoftwareBADC0 SS317 BSoftwareBGPIO BSBUART4 RXBGPTimer 1ABGPTimer 0A18 BSoftwareBGPIO GSBUART4 TXBGPTimer 1BBGPTimer 0B19 BSoftwareBGPIO HSBUART7 RXBSoftwareBGPTimer 1A20 569June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Table9-1.μDMAChannelAssignments (continued) 43210Enc. TypePeripheralTypePeripheralTypePeripheralTypePeripheralTypePeripheralCh# BSoftwareBGPIO JSBUART7 TXBSoftwareBGPTimer 1B21 BSoftwareBSoftwareBSoftwareBSoftwareSBUART1 RX22 BSoftwareBSoftwareBSoftwareBSoftwareSBUART1 TX23 BSoftwareBGPWideTimer 3ABSoftwareBADC1 SS0SBSSI1 RX24 BSoftwareBGPWideTimer 3BBSoftwareBADC1 SS1SBSSI1 TX25 BSoftwareBGPWideTimer 4ABSoftwareBADC1 SS2BSoftware26 BSoftwareBGPWideTimer 4BBSoftwareBADC1 SS3BSoftware27 BSoftwareBGPWideTimer 5ABSoftwareBSoftwareBSoftware28 BSoftwareBGPWideTimer 5BBSoftwareBSoftwareBSoftware29 BSoftwareBSoftwareBSoftwareBSoftwareBSoftware30 BReservedBReservedBReservedBReservedBReserved31

9.2.2 Priority

The μDMA controller assigns priority to each channel based on the channel number and the priority level bit for the channel. Channel number 0 has the highest priority and as the channel number increases, the priority of a channel decreases. Each channel has a priority level bit to provide two levels of priority: default priority and high priority. If the priority level bit is set, then that channel has higher priority than all other channels at default priority. If multiple channels are set for high priority, then the channel number is used to determine relative priority among all the high priority channels. The priority bit for a channel can be set using theDMAChannelPrioritySet(DMAPRIOSET) register and cleared with theDMAChannelPriorityClear(DMAPRIOCLR) register.

9.2.3 ArbitrationSize

When a μDMA channel requests a transfer, the μDMA controller arbitrates among all the channels making a request and services the μDMA channel with the highest priority. Once a transfer begins, it continues for a selectable number of transfers before rearbitrating among the requesting channels again. The arbitration size can be configured for each channel, ranging from 1 to 1024 item transfers. After the μDMA controller transfers the number of items specified by the arbitration size, it then checks among all the channels making a request and services the channel with the highest priority. If a lower priority μDMA channel uses a large arbitration size, the latency for higher priority channels is increased because the μDMA controller completes the lower priority burst before checking for higher priority requests. Therefore, lower priority channels should not use a large arbitration size for best response on high priority channels. The arbitration size can also be thought of as a burst size. It is the maximum number of items that are transferred at any one time in a burst. Here, the term arbitration refers to determination of μDMA channel priority, not arbitration for the bus. When the μDMA controller arbitrates for the bus, the processor always takes priority. Furthermore, the μDMA controller is held off whenever the processor must perform a bus transaction on the same bus, even in the middle of a burst transfer.

9.2.4 RequestTypes

The μDMA controller responds to two types of requests from a peripheral: single or burst. Each peripheral may support either or both types of requests. A single request means that the peripheral June 12, 2014570 Texas Instruments-Production Data Micro Direct Memory Access (μDMA)

is ready to transfer one item, while a burst request means that the peripheral is ready to transfer multiple items. The μDMA controller responds differently depending on whether the peripheral is making a single request or a burst request. If both are asserted, and the μDMA channel has been set up for a burst transfer, then the burst request takes precedence. See Table 9-2 on page 571, which shows how each peripheral supports the two request types. Table9-2.RequestTypeSupport EventthatgeneratesBurstRequestEventthatgeneratesSingleRequestPeripheral FIFO half fullNoneADC Trigger eventNoneGeneral-Purpose Timer NoneRaw interrupt pulseGPIO TX FIFO Level (fixed at 4)TX FIFO Not FullSSI TX RX FIFO Level (fixed at 4)RX FIFO Not EmptySSI RX TX FIFO Level (configurable)TX FIFO Not FullUART TX RX FIFO Level (configurable)RX FIFO Not EmptyUART RX FIFO TXRDYNoneUSB TX FIFO RXRDYNoneUSB RX

9.2.4.1 SingleRequest

When a single request is detected, and not a burst request, the μDMA controller transfers one item and then stops to wait for another request.

9.2.4.2 BurstRequest

When a burst request is detected, the μDMA controller transfers the number of items that is the lesser of the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration size should be the same as the number of data items that the peripheral can accommodate when making a burst request. For example, the UART generates a burst request based on the FIFO trigger level. In this case, the arbitration size should be set to the amount of data that the FIFO can transfer when the trigger level is reached. A burst transfer runs to completion once it is started, and cannot be interrupted, even by a higher priority channel. Burst transfers complete in a shorter time than the same number of non-burst transfers. It may be desirable to use only burst transfers and not allow single transfers. For example, perhaps the nature of the data is such that it only makes sense when transferred together as a single unit rather than one piece at a time. The single request can be disabled by using theDMAChannel UseburstSet(DMAUSEBURSTSET) register. By setting the bit for a channel in this register, the μDMA controller only responds to burst requests for that channel.

9.2.5 ChannelConfiguration

The μDMA controller uses an area of system memory to store a set of channel control structures in a table. The control table may have one or two entries for each μDMA channel. Each entry in the table structure contains source and destination pointers, transfer size, and transfer mode. The control table can be located anywhere in system memory, but it must be contiguous and aligned on a 1024-byte boundary. Table 9-3 on page 572 shows the layout in memory of the channel control table. Each channel may have one or two control structures in the control table: a primary control structure and an optional alternate control structure. The table is organized so that all of the primary entries are in the first 571June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

half of the table, and all the alternate structures are in the second half of the table. The primary entry is used for simple transfer modes where transfers can be reconfigured and restarted after each transfer is complete. In this case, the alternate control structures are not used and therefore only the first half of the table must be allocated in memory; the second half of the control table is not necessary, and that memory can be used for something else. If a more complex transfer mode is used such as ping-pong or scatter-gather, then the alternate control structure is also used and memory space should be allocated for the entire table. Any unused memory in the control table may be used by the application. This includes the control structures for any channels that are unused by the application as well as the unused control word for each channel. Table9-3.ControlStructureMemoryMap ChannelOffset 0, Primary0x0 1, Primary0x10 31, Primary0x1F0 0, Alternate0x200 1, Alternate0x210 31, Alternate0x3F0 Table 9-4 shows an individual control structure entry in the control table. Each entry is aligned on a 16-byte boundary. The entry contains four long words: the source end pointer, the destination end pointer, the control word, and an unused entry. The end pointers point to the ending address of the transfer and are inclusive. If the source or destination is non-incrementing (as for a peripheral register), then the pointer should point to the transfer address. Table9-4.ChannelControlStructure DescriptionOffset Source End Pointer0x000 Destination End Pointer0x004 Control Word0x008 Unused0x00C The control word contains the following fields: ■ Source and destination data sizes ■ Source and destination address increment size ■ Number of transfers before bus arbitration ■ Total number of items to transfer ■ Useburst flag ■ Transfer mode June 12, 2014572 Texas Instruments-Production Data Micro Direct Memory Access (μDMA)

The control word and each field are described in detail in “μDMA Channel Control Structure” on page 590. The μDMA controller updates the transfer size and transfer mode fields as the transfer is performed. At the end of a transfer, the transfer size indicates 0, and the transfer mode indicates "stopped." Because the control word is modified by the μDMA controller, it must be reconfigured before each new transfer. The source and destination end pointers are not modified, so they can be left unchanged if the source or destination addresses remain the same. Prior to starting a transfer, a μDMA channel must be enabled by setting the appropriate bit in the DMAChannelEnableSet(DMAENASET) register. A channel can be disabled by setting the channel bit in theDMAChannelEnableClear(DMAENACLR) register. At the end of a complete μDMA transfer, the controller automatically disables the channel.

9.2.6 TransferModes

The μDMA controller supports several transfer modes. Two of the modes support simple one-time transfers. Several complex modes support a continuous flow of data.

9.2.6.1 StopMode

While Stop is not actually a transfer mode, it is a valid value for the mode field of the control word. When the mode field has this value, the μDMA controller does not perform any transfers and disables the channel if it is enabled. At the end of a transfer, the μDMA controller updates the control word to set the mode to Stop.

9.2.6.2 BasicMode

In Basic mode, the μDMA controller performs transfers as long as there are more items to transfer, and a transfer request is present. This mode is used with peripherals that assert a μDMA request signal whenever the peripheral is ready for a data transfer. Basic mode should not be used in any situation where the request is momentary even though the entire transfer should be completed. For example, a software-initiated transfer creates a momentary request, and in Basic mode, only the number of transfers specified by theARBSIZEfield in theDMAChannelControlWord(DMACHCTL) register is transferred on a software request, even if there is more data to transfer. When all of the items have been transferred using Basic mode, the μDMA controller sets the mode for that channel to Stop.

9.2.6.3 AutoMode

Auto mode is similar to Basic mode, except that once a transfer request is received, the transfer runs to completion, even if the μDMA request is removed. This mode is suitable for software-triggered transfers. Generally, Auto mode is not used with a peripheral. When all the items have been transferred using Auto mode, the μDMA controller sets the mode for that channel to Stop.

9.2.6.4 Ping-Pong

Ping-Pong mode is used to support a continuous data flow to or from a peripheral. To use Ping-Pong mode, both the primary and alternate data structures must be implemented. Both structures are set up by the processor for data transfer between memory and a peripheral. The transfer is started using the primary control structure. When the transfer using the primary control structure is complete, the μDMA controller reads the alternate control structure for that channel to continue the transfer. Each time this happens, an interrupt is generated, and the processor can reload the control structure for the just-completed transfer. Data flow can continue indefinitely this way, using the primary and alternate control structures to switch back and forth between buffers as the data flows to or from the peripheral. 573June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Refer to Figure 9-2 on page 574 for an example showing operation in Ping-Pong mode. Figure9-2.ExampleofPing-PongμDMATransaction Alternate Structure Primary Structure Primary Structure Alternate Structure transfer continues using alternate BUFFER B BUFFER A

• Process data in BUFFER A
• Reload primary structure transfers using BUFFER A BUFFER A transfers using BUFFER A transfers using BUFFER B transfer continues using alternatetransfer continues using primary BUFFER B transfers using BUFFER B Peripheral/ µ DMA Interrupt
• Process data in BUFFER B
• Reload alternate structure
• Process data in BUFFER B
• Reload alternate structure µ DMA Controller Cortex-M4F Processor T ime Peripheral/ µ DMA Interrupt Peripheral/ µ DMA Interrupt SOURCE DEST CONTROL Unused SOURCE DEST CONTROL Unused SOURCE DEST CONTROL Unused SOURCE DEST CONTROL Unused

9.2.6.5 MemoryScatter-Gather

Memory Scatter-Gather mode is a complex mode used when data must be transferred to or from varied locations in memory instead of a set of contiguous locations in a memory buffer. For example, June 12, 2014574 Texas Instruments-Production Data Micro Direct Memory Access (μDMA)

a gather μDMA operation could be used to selectively read the payload of several stored packets of a communication protocol and store them together in sequence in a memory buffer. In Memory Scatter-Gather mode, the primary control structure is used to program the alternate control structure from a table in memory. The table is set up by the processor software and contains a list of control structures, each containing the source and destination end pointers, and the control word for a specific transfer. The mode of each control word must be set to Scatter-Gather mode. Each entry in the table is copied in turn to the alternate structure where it is then executed. The μDMA controller alternates between using the primary control structure to copy the next transfer instruction from the list and then executing the new transfer instruction. The end of the list is marked by programming the control word for the last entry to use Auto transfer mode. Once the last transfer is performed using Auto mode, the μDMA controller stops. A completion interrupt is generated only after the last transfer. It is possible to loop the list by having the last entry copy the primary control structure to point back to the beginning of the list (or to a new list). It is also possible to trigger a set of other channels to perform a transfer, either directly, by programming a write to the software trigger for another channel, or indirectly, by causing a peripheral action that results in a μDMA request. By programming the μDMA controller using this method, a set of up to 256 arbitrary transfers can be performed based on a single μDMA request. Refer to Figure 9-3 on page 576 and Figure 9-4 on page 577, which show an example of operation in Memory Scatter-Gather mode. This example shows agather operation, where data in three separate buffers in memory is copied together into one buffer. Figure 9-3 on page 576 shows how the application sets up a μDMA task list in memory that is used by the controller to perform three sets of copy operations from different locations in memory. The primary control structure for the channel that is used for the operation is configured to copy from the task list to the alternate control structure. Figure 9-4 on page 577 shows the sequence as the μDMA controller performs the three sets of copy operations. First, using the primary control structure, the μDMA controller loads the alternate control structure with task A. It then performs the copy operation specified by task A, copying the data from the source buffer A to the destination buffer. Next, the μDMA controller again uses the primary control structure to load task B into the alternate control structure, and then performs the B operation with the alternate control structure. The process is repeated for task C. 575June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

Figure9-3.MemoryScatter-Gather,SetupandConfiguration NOTES: 1 . Application has a need to copy data items from three separate locations in memory into one combined buf fer . 2 . Application sets up µ DMA “task list” in memory , which contains the pointers and control configuration for three µ DMA copy “tasks.” 3 . Application sets up the channel primary control structure to copy each task configuration , one at a time, to the alternate control structure , where it is executed by the µ DMA controller . 4 . The SRC and DST pointers in the task list must point to the last location in the corresponding buf fer . C

4 WORDS (SRC A)

16 WORDS (SRC B)

ITEMS=16 Unused SRC DST ITEMS=1

1 WORD (SRC C)

4 (DEST A) 16 (DEST B) 1 (DEST C) DSTA B “T ASK” A “T ASK” B “T ASK” C SRC DST ITEMS=12 SRC DST ITEMS=n Task List in Memory 21 3 Source and Destination Buffer in Memory Channel Control Table in Memory Channel Primary Control Structure Channel Alternate Control Structure Unused ITEMS=4 SRC Unused June 12, 2014576 Texas Instruments-Production Data Micro Direct Memory Access (μDMA)

Figure9-4.MemoryScatter-Gather,μDMACopySequence SRC DST COPIED SRC DST COPIED PRI AL T SRC DST COPIED SRC DST COPIED SRC DST COPIED SRC DST COPIED Task List in Memory µ DMA Control Table in Memory Buffers in Memory T ASK B T ASK C PRI AL T SRC B SRC C DEST B DEST C Using the channel’ s primary control structure, the µ DMA controller copies task A configuration to the channel’ s alternate control structure . Then, using the channel’ s alternate control structure, the µ DMA controller copies data from the source buf fer A to the destination buf fer . Task List in Memory µ DMA Control Table in Memory Buffers in Memory Using the channel’ s primary control structure, the µ DMA controller copies task B configuration to the channel’ s alternate control structure . Then, using the channel’ s alternate control structure, the µ DMA controller copies data from the source buf fer B to the destination buf fer . µ DMA Control Table in Memory Buffers in Memory Using the channel’ s primary control structure, the µ DMA controller copies task C configuration to the channel’ s alternate control structure . Then, using the channel’ s alternate control structure, the µ DMA controller copies data from the source buf fer C to the destination buf fer . PRI AL T Task List in Memory T ASK A T ASK B T ASK A T ASK C SRC A SRC C DEST A DEST C SRC A SRC B DEST A DEST B T ASK A T ASK B SRC A T ASK C SRC C DEST C SRC B DEST B DEST A 577June 12, 2014 Texas Instruments-Production Data Tiva™ TM4C1233D5PZ Microcontroller

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