TM497MBM36A

TM893NBM36A TI1 | Alldatasheet

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TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES SMMS653B – MAY 1995 – REVISED JULY 1995 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization TM497MBM36A ...4 1 9 4 3 0 4 × 36 TM893NBM36A ...8 3 8 8608 × 36 /C0068Single 5-V Power Supply (±10% Tolerance) /C006872-Pin Leadless Single In-Line Memory Module (SIMM) for Use With Sockets /C0068TM497MBM36A – Utilizes Eight 16-Megabit and Four 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages /C0068TM893NBM36A – Utilizes Sixteen 16-Megabit and Eight 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages /C0068Long Refresh Period 32 ms (2048 Cycles) /C0068All Inputs, Outputs, Clocks Fully TTL-Compatible /C00683-State Output /C0068Common CAS Control for Nine Common Data-In and Data-Out Lines in Four Blocks /C0068Enhanced Page-Mode Operation With CAS -Before-RAS (CBR), RAS-Only, and Hidden Refresh /C0068Present Detect /C0068Operating Free-Air Temperature Range 0°C to 70°C /C0068Performance Ranges: ACCESS ACCESS ACCESS READ TIME TIME TIME OR tRAC tAA tCAC WRITE CYCLE (MAX) (MAX) (MAX) (MIN) ’497MBM36A-60 60 ns 30 ns 15 ns 110 ns ’497MBM36A-70 70 ns 35 ns 18 ns 130 ns ’497MBM36A-80 80 ns 40 ns 20 ns 150 ns ’893NBM36A-60 60 ns 30 ns 15 ns 110 ns ’893NBM36A-70 70 ns 35 ns 18 ns 130 ns ’893NBM36A-80 80 ns 40 ns 20 ns 150 ns /C0068Gold-Tabbed Versions Available:† TM497MBM36A TM893NBM36A /C0068Tin-Lead (Solder)-Tabbed Versions Available: TM497MBM36Q TM893NBM36Q

description

The TM497MBM36A is a 16-megabyte dynamic random-access memory (DRAM) organized as four times 4194304 × 9 (bit 9 is generally used for parity) in a 72-pin leadless single in-line memory module (SIMM). The SIMM is composed of eight TMS417400DJ 4194304 × 4-bit DRAMs, each in a 24/26-lead plastic small-outline J-lead (SOJ) package, and four TMS44100DJ 4194304 × 1-bit DRAMs, each in a 20/26-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS417400DJ and TMS44100DJ are described in the TMS417400 and TMS44100 data sheets, respectively. The TM497MBM36A SIMM is available in the single-sided, BM leadless module for use with sockets. TM893NBM36A The TM893NBM36A is a 32-megabyte DRAM organized as four times 8388608 × 9 (bit 9 is generally used for parity) in a 72-pin leadless SIMM. The SIMM is composed of sixteen TMS417400DJ 4194304 × 4-bit DRAMs, each in a 24/26-lead plastic SOJ package, and eight TMS44100DJ 4194304 × 1-bit DRAMs, each in a 20/26-lead plastic SOJ package, mounted on a substrate with decoupling capacitors. The TMS417400DJ and TMS44100DJ are described in the TMS417400 and TMS44100 data sheets, respectively. The TM893NBM36A SIMM is available in the double-sided, BM leadless module for use with sockets. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. † Part numbers in this data sheet refer only to the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. Copyright  1995, Texas Instruments Incorporated

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(RAS -only or CBR-refresh) cycle. Table 1. Connection Table † Side 2 applies to the TM893NBM36A.

TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES SMMS653B – MAY 1995 – REVISED JULY 1995 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Reference PRESENCE DETECT SIGNAL (PIN) PD1 (67) PD2 (68) PD3 (69) PD4 (70) 80 ns VSS NC NC VSS TM497MBM36A 70 ns VSS NC VSS NC 60 ns VSS NC NC NC 80 ns NC VSS NC VSS TM893NBM36A 70 ns NC VSS VSS NC 60 ns NC VSS NC NC DQ17 DQ35 CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 VCC DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC VSS BM SINGLE IN-LINE PACKAGE (TOP VIEW) TM497MBM36A (SIDE VIEW) PIN NOMENCLATURE A0–A10 Address Inputs CAS0 –CAS3 Column-Address Strobe DQ0–DQ35 Data In/Data Out NC No Connection PD1–PD4 Presence Detects RAS0 –RAS3 Row-Address Strobe VCC 5-V Supply VSS Ground W Write Enable TM893NBM36A (SIDE VIEW) VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 VCC NC A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 NC VCC RAS3 RAS2 DQ26 DQ8 VSS

TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES SMMS653 – MAY 1995 Temp late R elease D ate: 7–11–94

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functional block diagram (TM497MBM36A and TM893NBM36A, side 1) 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 DQ0– DQ3 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 DQ9– DQ12 DQ18– DQ21 DQ27– DQ30 DQ4– DQ7 DQ13– DQ16 DQ22– DQ25 DQ31– DQ34 W RAS0 CAS0 CAS1 CAS2 CAS3 RAS2 4M × 1 A0–A10 RAS W CAS DQ 4M × 1 A0–A10 RAS W CAS DQ 4M × 1 A0–A10 RAS W CAS DQ 4M × 1 A0–A10 RAS W CAS DQDQ8 DQ17 DQ26 DQ35 11 11 11 11 11 11 11 11 11 11 11 11

TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES SMMS653 – MAY 1995 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443• 5 functional block diagram (TM893NBM36A, side 2) 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 A0–A10 DQ0– DQ3 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 4M × 4 A0–A10 RAS W CAS OE DQ1– DQ4 DQ9– DQ12 DQ18– DQ21 DQ27– DQ30 DQ4– DQ7 DQ13– DQ16 DQ22– DQ25 DQ31– DQ34 W RAS1 CAS0 CAS1 CAS2 CAS3 RAS3 4M × 1 A0–A10 RAS W CAS DQ 4M × 1 A0–A10 RAS W CAS DQ 4M × 1 A0–A10 RAS W CAS DQ 4M × 1 A0–A10 RAS W CAS DQDQ8 DQ17 DQ26 DQ35 11 11 11 11 11 11 11 11 11 11 11 11

TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES SMMS653B – MAY 1995 – REVISED JULY 1995

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) – 1 0.8 V TA Operating free-air temperature 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ ’497MBM36A-60 ’497MBM36A-70 ’497MBM36A-80 UNITPARAMETER TEST CONDITIONS ‡ MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, V I = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, V O = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 Read- or write-cycle current VCC = 5.5 V, Minimum cycle 1300 1160 1040 mA ICC2 Standby current VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 24 24 24 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high 12 12 12 mA ICC3 Average refresh current (RAS -only refresh or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS-only refresh); RAS low after CAS low (CBR) 1300 1160 1040 mA ICC4 Average page current VCC = 5.5 V, t PC = MIN, RAS low, CAS cycling 920 800 680 mA ‡ For test conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.

TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES SMMS653B – MAY 1995 – REVISED JULY 1995 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS † ’893NBM36A-60 ’893NBM36A-70 ’893NBM36A-80 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, V I = 0 V to 6.5 V, All other pins = 0 V to VCC ± 20 ± 20 ± 20 µA IO Output current (leakage) VCC = 5.5 V, V O = 0 V to VCC , CAS high ± 20 ± 20 ± 20 µA ICC1 Read- or write-cycle current (one RAS active, see Note 3) VCC = 5.5 V, Minimum cycle 1324 1184 1064 mA ICC2 Standby current VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 48 48 48 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high 24 24 24 mA ICC3 Average refresh current (RAS only or CBR, see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS-only refresh); RAS low after CAS low (CBR) 1324 1184 1064 mA ICC4 Average page current (one RAS active, see Note 4) VCC = 5.5 V, t PC = MIN, RAS low, CAS cycling 944 824 704 mA † For test conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH capacitance over recommended supply voltage range and operating free-air temperature range, f = 1 MHz (see Note 5) PARAMETER ’497MBM36A ’893NMB36A UNITPARAMETER MIN MAX MIN MAX UNIT C i(A) Input capacitance, A0–A10 60 120 pF C i(R) Input capacitance, RAS inputs 42 42 pF C i(C) Input capacitance, CAS inputs 21 42 pF C i(W) Input capacitance, write-enable input 84 168 pF C (DQ) Output capacitance DQ pins 7 14 pF C o(DQ) O utput capacitance Parity pins 12 24 pF NOTE 5: V CC = 5 V ± 0.5 V, and the bias on pins under test is 0 V.

TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES SMMS653B – MAY 1995 – REVISED JULY 1995

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switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’497MBM36A-60 ’893NBM36A-60 ’497MBM36A-70 ’893NBM36A-70 ’497MBM36A-80 ’893NBM36A-80 UNIT MIN MAX MIN MAX MIN MAX tAA Access time from column address 30 35 40 ns tCAC Access time from CAS low 15 18 20 ns tRAC Access time from RAS low 60 70 80 ns tCPA Access time from column precharge 35 40 45 ns tCLZ CAS low to output in the low-impedance state 0 0 0 ns tOFF Output disable time after CAS high (see Note 6) 0 15 0 18 0 20 ns tOH Output disable time, start of CAS high 3 3 3 ns NOTE 6: tOFF is specified when the output is no longer driven. timing requirements over recommended ranges of supply voltage and operating free-air temperature ’497MBM36A-60 ’893NBM36A-60 ’497MBM36A-70 ’893NBM36A-70 ’497MBM36A-80 ’893NBM36A-80 UNIT MIN MAX MIN MAX MIN MAX tRC Cycle time, random read or write (see Note 7) 110 130 150 ns tPC Cycle time, page-mode read or write (see Notes 7 and 8)40 45 50 ns tRASP Pulse duration, page mode, RAS low 60 100 000 70 100 000 80 100 000 ns tRAS Pulse duration, nonpage mode, RAS low 60 10 000 70 10 000 80 10 000 ns tCAS Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns tCP Pulse duration, CAS high 10 10 10 ns tRP Pulse duration, RAS high (precharge) 40 50 60 ns tWP Pulse duration, W low 10 10 10 ns tASC Setup time, column address before CAS low 0 0 0 ns tASR Setup time, row address before RAS low 0 0 0 ns tDS Setup time, data before CAS low 0 0 0 ns tRCS Setup time, W high before CAS low 0 0 0 ns tCWL Setup time, W low before CAS high 15 18 20 ns tRWL Setup time, W low before RAS high 15 18 20 ns tWCS Setup time, W low before CAS low 0 0 0 ns tWRP Setup time, W high before RAS low (CBR refresh only) 10 10 10 ns tCAH Hold time, column address after CAS low 10 15 15 ns tRHCP Hold time, RAS high from CAS precharge 35 40 45 ns tDH Hold time, data after CAS low 10 15 15 ns tRAH Hold time, row address after RAS low 10 10 10 ns tRCH Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 9) 0 0 0 ns tWCH Hold time, W low after CAS low 10 15 15 ns tWRH Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns NOTES: 7. All cycle times assume tT = 5 ns. 8. To assure tPC min, tASC should be ≥ tCP . 9. Either tRRH or tRCH must be satisfied for a read cycle.

TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES SMMS653B – MAY 1995 – REVISED JULY 1995 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) ’497MBM36A-60 ’893NBM36A-60 ’497MBM36A-70 ’893NBM36A-70 ’497MBM36A-80 ’893NBM36A-80 UNIT MIN MAX MIN MAX MIN MAX tCHR Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns tCRP Delay time, CAS high to RAS low 5 5 5 ns tCSH Delay time, RAS low to CAS high 60 70 80 ns tCSR Delay time, CAS low to RAS low (CBR refresh only) 5 5 5 ns tRAD Delay time, RAS low to column address (see Note 10) 15 30 15 35 15 40 ns tRAL Delay time, column address to RAS high 30 35 40 ns tCAL Delay time, column address to CAS high 30 35 40 ns tRCD Delay time, RAS low to CAS low (see Note 10) 20 45 20 52 20 60 ns tRPC Delay time, RAS high to CAS low (CBR refresh only) 0 0 0 ns tRSH Delay time, CAS low to RAS high 15 18 20 ns tREF Refresh time interval 32 32 32 ms tT Transition time 3 30 3 30 3 30 ns NOTE 10: The maximum value is specified only to assure access time.

TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES SMMS653B – MAY 1995 – REVISED JULY 1995

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BM (R-PSIM-N72) SINGLE/DOUBLE-SIDED IN-LINE MEMORY MODULE 0.208 (5,28) MAX 1.305 (33,15) 0.010 (0,25) MAX 0.400 (10,16) TYP 0.047 (1,19) 1.295 (32,89) 0.054 (1,37) 0.360 (9,14) MAX 4088175/A 4/95 4.245 (107,82) 4.255 (108,08) 0.125 (3,18) TYP 0.040 (1,02) TYP 0.120 (3,05) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. device symbolization (TM497MBM36A illustrated) YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code TM497MBM36A –SS YYMMT NOTE: Location of symbolization may vary.

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