TM497MBK36H

TM497MBK36H TI1 | Alldatasheet

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TM497MBK36H, TM497MBK36I

4194304 BY 36-BIT

SMMS676 – MARCH 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068 Organization...41 9 43 0 4 × 36 /C0068 Single 5-V Power Supply (±10% Tolerance) /C0068 72-Pin Single-In-Line Memory Module (SIMM) for Use With Sockets /C0068 Uses Eight 16M-bit Dynamic RAMs (DRAMs) in Plastic Small-Outline J-Lead (SOJ) Packages and Four 4M-bit DRAMs in Plastic SOJ Packages /C0068 Long Refresh Period...3 2 m s (2 048 Cycles)† /C0068 All Inputs, Outputs, and Clocks are Fully TTL Compatible /C0068 Common CAS Control for Nine Common Data-In and Data-Out Lines in Four Blocks /C0068 Separate RAS Control for Eighteen Data-In and Data-Out Lines in Two Blocks /C0068 3-State Output /C0068 Performance Ranges: ACCESS ACCESS ACCESS READ TIME TIME TIME OR tRAC tCAC tAA WRITE CYCLE (MAX) (MAX) (MAX) (MIN) ’497MBK36H/I-60 60 ns 15 ns 30 ns 110 ns ’497MBK36H/I-70 70 ns 18 ns 35 ns 130 ns ’497MBK36H/I-80 80 ns 20 ns 40 ns 150 ns /C0068 Low Power Dissipation /C0068 Operating Free-Air Temperature Range ...0°C to 70°C /C0068 Presence Detect /C0068 Gold-Tabbed Version Available TM497MBK36H /C0068 Tin-Lead (Solder) Tabbed Version Available: TM497MBK36I

description

The TM497MBK36H/I is a 144M-bit dynamic random-access memory (DRAM) device organized as four times 4194304 × 9 (bit 9 generally is used for parity) in a 72-pin leadless single-in-line memory module (SIMM). The SIMM is composed of eight TMS417400ADJ, 4 194 304 × 4-bit DRAMs in 24/26-lead plastic SOJ packages, and four TMS44100DJ, 4 194 304 × 1-bit DRAMs in 20/26-lead plastic SOJ packages mounted on a substrate with decoupling capacitors. TMS417400ADJ and TMS44100DJ are described in the TMS417400A and TMS44100 data sheets (literature numbers SMKS889 and SMHS561, respectively). The TM497MBK36H/I is available in a double-sided, BK, leadless module for use with sockets. The TM497MBK36H/I features RAS access times of 60, 70, and 80 ns. This device is characterized for operation from 0°C to 70°C. operation The TM497MBK36H/I operates as eight TMS417400ADJs and four TMS44100DJs connected as shown in the functional block diagram and Table 1. See the TMS417400A and TMS44100 data sheets for details of operation. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. Table 1. Connection Table Copyright  1997, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † A0–A9 address lines must be refreshed every 16 ms.

(TOP VIEW) (SIDE VIEW) PIN NOMENCLATURE A0 –A10 Address Inputs CAS0 –CAS3 Column-Address Strobe DQ0 –DQ7, DQ9 –DQ16, Data Input/Output DQ18 –DQ25, DQ27 –DQ34 DQ8, DQ17, DQ26, DQ35 Parity NC No Connection PD1 –PD4 Presence Detect RAS0 , RAS2 Row-Address Strobe VCC 5-V Supply VSS Ground W Write Enable DQ17 DQ35 CAS0 CAS2 CAS3 CAS1 RAS0 NC NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 VCC DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC VSS VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 VCC NC A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 NC VCC NC RAS2 DQ26 DQ8 VSS TM497MBK36H, TM497MBK36I SMMS676 – MARCH 1997

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(PIN) PD1 (67) PD2 (68) PD3 (69) PD4 (70) 80 ns VSS NC NC VSS TM497MBK36H/I 70 ns VSS NC VSS NC 60 ns VSS NC NC NC

TM497MBK36H, TM497MBK36I SMMS676 – MARCH 1997 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 refresh The refresh period is extended to 32 ms and, during this period, each of the 2 048 rows must be strobed with RAS to retain data. Address line A10 must be used as the most significant refresh-address line (lowest frequency) to ensure correct refresh for both TMS417400A and TMS44100. A0–A9 address lines must be refreshed every 16 ms as required by the TMS44100 DRAM. CAS can remain high during the refresh sequence to conserve power. power up To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh (RAS -only or CAS-before-RAS [CBR]) cycle. single-in-line memory module and components PC substrate: 1,27± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM497MBK36H: Nickel plate and gold plate over copper Contact area for TM497MBK36I: Nickel plate and tin-lead over copper

TM497MBK36H, TM497MBK36I SMMS676 – MARCH 1997 Temp late R elease D ate: 7–11–94

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4M × 4 A0 –A10 RAS W CAS OE DQ1 – DQ4 A0 –A10 DQ0 – DQ3 4M × 4 A0 –A10 RAS W CAS OE DQ1 – DQ4 4M × 4 A0 –A10 RAS W CAS OE DQ1 – DQ4 4M × 4 A0 –A10 RAS W CAS OE DQ1 – DQ4 4M × 4 A0 –A10 RAS W CAS OE DQ1 – DQ4 4M × 4 A0 –A10 RAS W CAS OE DQ1 – DQ4 4M × 4 A0 –A10 RAS W CAS OE DQ1 – DQ4 4M × 4 A0 –A10 RAS W CAS OE DQ1 – DQ4 DQ9 – DQ12 DQ18 – DQ21 DQ27 – DQ30 DQ4 – DQ7 DQ13 – DQ16 DQ22 – DQ25 DQ31 – DQ34 W RAS0 CAS0 CAS1 CAS2 CAS3 RAS2 4M × 1 A0 –A10 RAS W CAS DQ 4M × 1 A0 –A10 RAS W CAS DQ 4M × 1 A0 –A10 RAS W CAS DQ 4M × 1 A0 –A10 RAS W CAS DQDQ8 DQ17 DQ26 DQ35 11 11 11 11 11 11 11 11 11 11 11 11

TM497MBK36H, TM497MBK36I SMMS676 – MARCH 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) – 1 0.8 V TA Operating free-air temperature 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS ’497MBK36H/I-60 ’497MBK36H/I-70 ’497MBK36H/I-80 UNITPARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 120 ± 120 ± 120 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 Read- or write-cycle current (see Note 3)VCC = 5.5 V, Minimum cycle 1300 1160 1040 mA ICC2 Standby current VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high 24 24 24 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and CAS high 12 12 12 mA ICC3 Average refresh current (RAS-only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS-only); CAS before RAS (CBR) 1300 1160 1040 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, tPC = MIN RAS low, CAS cycling 920 800 680 mA NOTES: 3. I CC3 is measured with a maximum of one address change while RAS = VIL. 4. ICC4 is measured with a maximum of one address change while CAS = VIH.

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capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5) PARAMETER MIN MAX UNIT C i(A) Input capacitance, address inputs 60 pF C i(C) Input capacitance, CAS inputs 21 pF C i(R) Input capacitance, RAS inputs 42 pF C i(W) Input capacitance, write-enable input 84 pF C Output capacitance DQ pins 7 pFC o Output capacitance Parity pins 12 pF NOTE 5: V CC = 5 V ± 0.5 V, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’497MBK36H/I-60 ’497MBK36H/I-70 ’497MBK36H/I-80 UNITPARAMETER MIN MAX MIN MAX MIN MAX UNIT tAA Access time from column address 30 35 40 ns tCAC Access time from CAS low 15 18 20 ns tCPA Access time from column precharge 35 40 45 ns tRAC Access time from RAS low 60 70 80 ns tCLZ CAS to output in low-impedance state 0 0 0 ns tOH Output disable time, start of CAS high 3 3 3 ns tOFF Output disable time after CAS high (see Note 6) 0 15 0 18 0 20 ns NOTE 6: tOFF is specified when the output is no longer driven. timing requirements over recommended ranges of supply voltage and operating free-air temperature ’497MBK36H/I-60 ’497MBK36H/I-70 ’497MBK36H/I-80 UNIT MIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, random read or write (see Note 7) 110 130 150 ns tPC Cycle time, page-mode read or write (see Notes 7 and 8) 40 45 50 ns tRASP Pulse duration, page-mode, RAS low 60 100 000 70 100 000 80 100 000 ns tRAS Pulse duration, nonpage-mode, RAS low 60 10 000 70 10 000 80 10 000 ns tCAS Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns tCP Pulse duration, CAS high 10 10 10 ns tRP Pulse duration, RAS high (precharge) 40 50 60 ns tWP Pulse duration, W low 10 10 10 ns tASC Setup time, column address before CAS low 0 0 0 ns tASR Setup time, row address before RAS low 0 0 0 ns tDS Setup time, data before CAS low 0 0 0 ns tRCS Setup time, W high before CAS low 0 0 0 ns tCWL Setup time, W low before CAS high 15 18 20 ns tRWL Setup time, W low before RAS high 15 18 20 ns tWCS Setup time, W low before CAS low 0 0 0 ns tWRP Setup time, W high before RAS low (CBR refresh only) 10 10 10 ns NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be ≥ tCP .

TM497MBK36H, TM497MBK36I SMMS676 – MARCH 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) ’497MBK36H/I-60 ’497MBK36H/I-70 ’497MBK36H/I-80 UNIT MIN MAX MIN MAX MIN MAX UNIT tCAH Hold time, column address after CAS low 10 15 15 ns tRHCP Hold time, RAS high from CAS precharge 35 40 45 ns tDH Hold time, data after CAS low 10 15 15 ns tRAH Hold time, row address after RAS low 10 10 10 ns tRCH Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 9) 0 0 0 ns tWCH Hold time, W low after CAS low 10 15 15 ns tWRH Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns tCHR Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns tCRP Delay time, CAS high to RAS low 5 5 5 ns tCSH Delay time, RAS low to CAS high 60 70 80 ns tCSR Delay time, CAS low to RAS low (CBR refresh only) 5 5 5 ns tRAD Delay time, RAS low to column address (see Note 10) 15 30 15 35 15 40 ns tRAL Delay time, column address to RAS high 30 35 40 ns tCAL Delay time, column address to CAS high 30 35 40 ns tRCD Delay time, RAS low to CAS low (see Note 10) 20 45 20 52 20 60 ns tRPC Delay time, RAS high to CAS low 5 5 5 ns tRSH Delay time, CAS low to RAS high 15 18 20 ns tREF Refresh time interval 32 32 32 ms tT Transition time 2 30 2 30 2 30 ns NOTES: 9. Either tRRH or tRCH must be satisfied for a read cycle. 10. The maximum value is specified only to ensure access time.

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BK –72 PIN SINGLE-IN-LINE MEMORY MODULE R –PSIP–N72 4.255 (108,08) 0.208 (5,28) MAX 0.400 (10,16) TYP 0.054 (1,37) 0.010 (0,254) MAX 0.125 (3,18) TYP 0.050 (1,27) TYP 0.040 (1,02) TYP 0.995 (25,27) 4.245 (107,82) 0.047 (1,19) 0.120 (3,05) 0.360 (9,14) MAX NOTE A: All linear dimensions are in inches (millimeters). device symbolization TM497MBK36I YYMMT YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE A: Location of symbolization may vary. -SS

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