TM497EU9-70

TM497EU9 TI | Alldatasheet

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SMMS499A – FEBRUARY 1994 – REVISED JUNE 1995 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization...4 1 9 4 3 0 4 × 9 /C0068Single 5-V Power Supply (±10% Tolerance) /C006830-Pin Single-In-Line Memory Module (SIMM) for Use With Sockets /C0068Utilizes One 4-Megabit and Two 16-Megabit Dynamic RAMs in Plastic Small-Outline J-Lead (SOJ) Packages /C0068Long Refresh Period 32 ms† (2048 Cycles) /C0068All Inputs, Outputs, and Clocks Fully TTL Compatible /C00683-State Outputs /C0068Performance Ranges: ACCESS ACCESS ACCESS READ OR TIME TIME TIME WRITE (tRAC )t (AA) (tCAC ) CYCLE (MAX) (MAX) (MAX) (MIN) ’497EU9-60 60 ns 30 ns 15 ns 110 ns ’497EU9-70 70 ns 35 ns 18 ns 130 ns ’497EU9-80 80 ns 40 ns 20 ns 150 ns /C0068Common CAS Control for Eight Common Data-In and Data-Out Lines /C0068Separate CAS Control for One Separate Pair of Data-In and Data-Out Lines /C0068Low Power Dissipation /C0068Operating Free-Air Temperature Range 0°C to 70°C /C0068Enhanced Page Mode Operation With CAS -Before-RAS (CBR), RAS-Only, and Hidden Refresh

description

The TM497EU9 is a 4M-byte dynamic random-access memory (RAM) organized as 4194304 × 9 bits [bit nine (D9, Q9) is generally used for parity and is controlled by CAS9 ] in a 30-pin leadless single-in-line memory module (SIMM). The SIMM is composed of two TMS417400DJ, 4194304 × 4-bit dynamic RAMs, each in a 24/26-lead plastic small-outline J-lead (SOJ) package, and one TMS44100DJ, 4194304 × 1-bit dynamic RAM in a 20/26-lead plastic SOJ package, mounted on a substrate with decoupling capacitors. The TM497EU9 is available in the U single-sided, leadless module for use with sockets and is characterized for operation from 0°C to 70°C. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. VCC 1 CAS 2 DQ1 3 A0 4 A1 5 DQ2 6 A2 7 A3 8 VSS 9 DQ3 10 A4 11 A5 12 DQ4 13 A6 14 A7 15 DQ5 16 A8 17 A9 18 A10 19 DQ6 20 W VSS 22 DQ7 23 NC 24 DQ8 25 Q9 26 RAS 27 CAS9 28 D9 29 VCC 30 U SINGLE-IN-LINE PACKAGE (TOP VIEW) A0–A10 CAS , CAS9 DQ1–DQ8 NC RAS VCC VSS W Address Inputs Column-Address Strobe Data In/Data Out Data In No Connection Data Out Row-Address Strobe 5-V Supply Ground Write Enable PIN NOMENCLATURE † A0–A9 address lines must be refreshed every 16 ms. Copyright  1995, Texas Instruments Incorporated

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The TM497EU9 operates as two TMS417400DJs and one TMS44100DJ connected as shown in the functional block diagram (refer to the TMS417400 and TMS44100 data sheets for details of their operation). The common I/O feature of the TM497EU9 dictates the use of early write cycles to prevent contention on D and Q. refresh The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power. In addition, the ten least significant row addresses (A0–A9) must be refreshed every 16 ms as required by the TMS44100. power up To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh (RAS -only or CBR) cycle. single-in-line memory module and components PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for socketable devices: Nickel plate and solder plate over copper functional block diagram A0–A10 RAS CAS W

11 A0–A10

W OE 4M × 4 A0–A10 RAS CAS W OE 4M × 4 A0–A10 RAS CAS W 4M × 1 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8CAS9 D Q 26 D9 DQ1 DQ2 DQ3 DQ4 DQ1 DQ2 DQ3 DQ4

SMMS499A – FEBRUARY 1994 – REVISED JUNE 1995 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) – 1 0.8 V TA Operating free-air temperature 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS ’497EU9-60 ’497EU9-70 ’497EU9-80 UNITPARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5 V, V I = 0 V to 6.5 V, All other pins = 0 V to VCC ±10 ±10 ±10 µA IO Output current (leakage) VCC = 5.5 V, V O = 0 V to VCC , CAS high ±10 ±10 ±10 µA ICC1 Read- or write-cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 325 290 260 mA ICC2 Standby current VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 6 6 6 mAICC2 Standby current VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high 3 3 3 mA ICC3 Average refresh current (RAS -only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS-only); RAS low after CAS low (CBR) 325 290 260 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, t PC = MIN, RAS low, CAS cycling 210 180 150 mA NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH

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capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5) PARAMETER MIN MAX UNIT C i(A) Input capacitance, A0–A10 15 pF C i(D) Input capacitance, data input (D9) 5 pF C i(R) Input capacitance, strobe input (RAS) 21 pF C i(C) Input capacitance strobe inputs CAS 14 pFC i(C) Input capacitance, strobe inputs CAS9 7 pF C i(W) Input capacitance, W 21 pF C o(DQ) Output capacitance (DQ1–DQ8) 7 pF C o(Q) Output capacitance (Q9) 7 pF NOTE 5: V CC = 5 V ± 0.5 V, and the bias on pin under test is 0 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’497EU9-60 ’497EU9-70 ’497EU9-80 UNITPARAMETER MIN MAX MIN MAX MIN MAX UNIT tAA Access time from column address 30 35 40 ns tCAC Access time from CAS low 15 18 20 ns tCPA Access time from column precharge 35 40 45 ns tRAC Access time from RAS low 60 70 80 ns tCLZ CAS to output in low-impedance state 0 0 0 ns tOH Output disable time, start of CAS high 3 3 3 ns tOFF Output disable time after CAS high (see Note 6) 0 15 0 18 0 20 ns NOTE 6: tOFF is specified when the output is no longer driven.

SMMS499A – FEBRUARY 1994 – REVISED JUNE 1995 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’497EU9-60 ’497EU9-70 ’497EU9-80 UNITPARAMETER MIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, random read or write (see Note 7) 110 130 150 ns tPC Cycle time, page mode read or write (see Notes 7 and 8) 40 45 50 ns tRASP Pulse duration, page mode, RAS low 60 100 000 70 100 000 80 100 000 ns tRAS Pulse duration, nonpage mode, RAS low 60 10 000 70 10 000 80 10 000 ns tCAS Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns tCP Pulse duration, CAS high 10 10 10 ns tRP Pulse duration, RAS high (precharge) 40 50 60 ns tWP Pulse duration, W low 10 10 10 ns tASC Setup time, column address before CAS low 0 0 0 ns tASR Setup time, row address before RAS low 0 0 0 ns tDS Setup time, data before CAS low 0 0 0 ns tRCS Setup time, W high before CAS low 0 0 0 ns tCWL Setup time, W low before CAS high 15 18 20 ns tRWL Setup time, W low before RAS high 15 18 20 ns tWCS Setup time, W low before CAS low 0 0 0 ns tWRP Setup time, W high before RAS low (CBR refresh only) 10 10 10 ns tCAH Hold time, column address after CAS low 10 15 15 ns tDH Hold time, data after CAS low 10 15 15 ns tRAH Hold time, row address after RAS low 10 10 10 ns tRCH Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 9) 0 0 0 ns tWCH Hold time, W low after CAS low 10 15 15 ns tWRH Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns tRHCP Hold time, RAS high from CAS precharge 35 40 45 ns tCHR Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns tCRP Delay time, CAS high to RAS low 5 5 5 ns tCSH Delay time, RAS low to CAS high 60 70 80 ns tCSR Delay time, CAS low to RAS low (CBR refresh only) 5 5 5 ns tRAD Delay time, RAS low to column address (see Note 10) 15 30 15 35 15 40 ns tRAL Delay time, column address to RAS high 30 35 40 ns tCAL Delay time, column address to CAS high 30 35 40 ns tRCD Delay time, RAS low to CAS low (see Note 10) 20 45 20 52 20 60 ns tRPC Delay time, RAS high to CAS low 0 0 0 ns tRSH Delay time, CAS low to RAS high 15 18 20 ns tREF Refresh time interval 32 32 32 ms tT Transition time 3 30 3 30 3 30 ns NOTES: 7. All cycle times assume tT = 5 ns. 8. To assure tPC min, tASC should be ≥ tCP . 9. Either tRRH or tRCH must be satisfied for a read cycle. 10. The maximum value is specified only to assure access time.

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-SS YYMMT NOTE: The location of the part number may vary. YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed

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