TM320LC203

TMS320C203 TI | Alldatasheet

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TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Based Upon the T320C2xLP Core CPU /C006816-Bit Fixed-Point DSP Architecture – Six Internal Buses for Increased Parallelism and Performance – 32-Bit ALU/Accumulator – 16 × 16-Bit Single-Cycle Multiplier With a 32-Bit Product – Block Moves for Data, Program, I/O Space – Hardware Repeat Instruction /C0068Instruction Cycle Time ’C203 ’LC203 ’C209 50 ns @ 5 V 50 ns @ 3.3 V 50 ns @ 5 V 35 ns @ 5 V 35 ns @ 5 V 25 ns @ 5 V /C0068Source Code Compatible With TMS320C25 /C0068Upwardly Code-Compatible With TMS320C5x Devices /C0068Four External Interrupts /C0068Boot-Loader Option (’C203 Only) /C0068TMS320C2xx Integrated Memory: – 544 × 16 Words of On-Chip Dual-Access Data RAM – 4K × 16 Words of On-Chip Single-Access Program/Data RAM (’C209 only) – 4K × 16 Words of On-Chip Program ROM (’C209 Only) /C0068224K × 16-Bit Total Addressable External Memory Space – 64K Program – 64K Data – 64K I/O – 32K Global /C0068TMS320C2xx Peripherals: – PLL With Various Clock Options – On-Chip Oscillator – One Wait State Software-Programmable to Each Space (’C209 Only) – 0 – 7 Wait States Software-Programmable to Each Space (’C203 Only) – Six General-Purpose I/O Pins – On-Chip 20-Bit Timer – Full-Duplex Asynchronous Serial Port (UART) (’C203 Only) – One Synchronous Serial Port With Four-Level-Deep FIFOs (’C203 Only) /C0068Supports Hardware Wait States /C0068Designed for Low-Power Consumption – Fully Static CMOS Technology – Power-Down IDLE Mode /C00681.1 mA/MIPS at 3.3 V /C0068’C203 is Pin-Compatible With TMS320F206 Flash DSP /C0068Up to 40-MIPS Performance at 5 V (’C203) /C006820-MIPS Performance at 3.3 V /C0068HOLD Mode for Multiprocessor

Applications

/C0068IEEE-1149.1†-Compatible Scan-Based Emulation /C006880- and 100-pin Small Thin Quad Flat Packages (TQFPs), (PN and PZ Suffixes)

description

The TMS320C2xx generation of digital signal processors (DSPs) combines strong performance and great flexibility to meet the needs of signal processing and control applications. The T320C2xLP core CPU that is the basis of all ’C2xx devices has been optimized for high speed, small size, and low-power, making it ideal for demanding applications in many markets. The CPU has an advanced, modified Harvard architecture with six internal buses that permits tremendous parallelism and data throughput. The powerful ’C2xx instruction set makes software development easy. And because the ’C2xx is code-compatible with the TMS320C2x and ’C5x generations, your code investment is preserved. Around this core, ’C2xx-generation devices feature various combinations of on-chip memory and peripherals. The serial ports provide easy communication with external devices such as codecs, A/D converters, and other processors. Other peripherals that facilitate the control of external devices include general-purpose I/O pins, a 20-bit timer, and a wait-state generator. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1998, Texas Instruments Incorporated † IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port.

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of package with total pin count. Table 1. Low Power Dissipation Table 2. Characteristics of the TMS320C2xx Processors

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C203 and TMS320LC203 Terminal Functions TERMINAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION DATA AND ADDRESS BUSES D15 D14 D13 D12 D11 D10 I/O/Z Parallel data bus D15 [most significant bit (MSB)] through D0 [least significant bit (LSB)]. D15–D0 are multiplexed to transfer data between the TMS320C2xx and external data/program memory or I/O devices. Placed in the high-impedance state when not outputting (R/W high) or RS when asserted. They go into the high-impedance state when OFF is active low. A15 A14 A13 A12 A11 A10 O/Z Parallel address bus A15 (MSB) through A0 (LSB). A15–A0 are multiplexed to address external data/program memory or I/O devices. These signals go into the high-impedance state when OFF is active low. MEMORY CONTROL SIGNALS PS 53 O/Z Program-select signal. PS is always high unless low-level asserted for communicating to off-chip program space. PS goes into the high-impedance state when OFF is active low. DS 51 O/Z Data-select signal. DS is always high unless low-level asserted for communicating to off-chip program space. DS goes into the high-impedance state when OFF is active low. IS 52 O/Z I/O space-select signal. IS is always high unless low-level asserted for communicating to I/O ports. IS goes into the high-impedance state when OFF is active low. READY 49 I Data-ready input. READY indicates that an external device is prepared for the bus transaction to be completed. If the external device is not ready (READY low), the TMS320C203 waits one cycle and checks READY again. If READY is not used, it should be pulled high. R/W 47 O/Z Read/write signal. R/W indicates transfer direction when communicating to an external device. R/W is normally in read mode (high), unless low level is asserted for performing a write operation. R/W goes into the high-impedance state when OFF is active low. RD 45 O/Z Read-select indicates an active, external read cycle and can connect directly to the output enable (OE) of external devices. RD is active on all external program, data, and I/O reads. RD goes into the high-impedance state when OFF is active low. WE 44 O/Z Write enable. The falling edge of WE indicates that the device is driving the external data bus (D15–D0). Data can be latched by an external device on the rising edge of WE. WE is active on all external program, data, and I/O writes. WE goes into the high-impedance state when OFF is active low. † I = input, O = output, Z = high impedance, PWR = power, GND = ground

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998

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TMS320C203 and TMS320LC203 Terminal Functions (Continued) TERMINAL TYPE † DESCRIPTION NAME NO. TYPE † DESCRIPTION MEMORY CONTROL SIGNALS (CONTINUED) STRB 46 O/Z Strobe signal. STRB is always high unless asserted low to indicate an external bus cycle. STRB goes into the high-impedance state when OFF is active low. MULTI-PROCESSING SIGNALS BR 43 O/Z Bus-request signal. BR is asserted when a global data-memory access is initiated. BR goes into the high-impedance state when OFF is active low. HOLDA 6 O/Z Hold-acknowledge signal. HOLDA indicates to the external circuitry that the processor is in a hold state and that the address, data, and memory control lines are in the high-impedance state so that they are available to the external circuitry for access of local memory. HOLDA goes into the high-impedance state when OFF is active low. XF 98 O/Z External flag output (latched software-programmable signal). XF is used for signalling other processors in multiprocessing configurations or as a general-purpose output pin. XF goes into the high-impedance state when OFF is active low. BIO 99 I Branch control input. When polled by the BIOZ instruction, if BIO is low, the TMS320C203 executes a branch. If BIO is not used, it should be pulled high. IO0 IO1 IO2 IO3 I/O/Z Software-controlled input/output pins by way of the asynchronous serial-port control register (ASPCR). At reset, IO0–IO3 are configured as inputs. These pins can be used as general-purpose input/output pins or as handshake control for the UART. IO0–IO3 go into the high-impedance state when OFF is active low. INITIALIZATION, INTERRUPTS, AND RESET OPERATIONS RS 100 I Reset input. RS causes the TMS320C203 to terminate execution and forces the program counter to zero. When RS is brought high, execution begins at location 0 of program memory after 16 cycles. RS affects various registers and status bits. TEST 1 I Reserved input pin. TEST is connected to VSS for normal operation. BOOT 2 I Microprocessor-mode-select pin. When BOOT is high, the device accesses off-chip memory. If BOOT is low, the on-chip boot-loader transfers data from external global data space to external RAM program space. NMI 17 I Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the interrupt-mode bit (INTM) or the interrupt mask register (IMR). When NMI is activated, the processor traps to the appropriate vector location. If NMI is not used, it should be pulled high. HOLD /INT1 18 I HOLD and INT1 share the same pin. Both are treated as interrupt signals. If the MODE bit is 0 in the interrupt-control register (ICR), hold logic can be implemented in combination with the IDLE instruction in software. At reset, the MODE bit in ICR is zero, enabling the HOLD mode for the pin. INT2 INT3 20 I External user interrupts. INT2 and INT3 are prioritized and maskable by the IMR and the INTM. INT2 and INT3 can be polled and reset by way of the interrupt flag register (IFR). If these signals are not used, they should be pulled high. OSCILLATOR, PLL, AND TIMER SIGNALS TOUT 92 O Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT1-cycle wide. TOUT goes into the high-impedance state when OFF is active low. CLKOUT1 15 O/Z Master clock ouput signal. The CLKOUT1 high pulse signifies the logic phase while the low pulse signifies the latch phase. CLKIN/X2 I O Input clock. CLKIN/X2 is the input clock to the device. As CLKIN, the pin operates as the external oscillator clock input, and as X2, the pin operates as the internal oscillator input with X1 being the internal oscillator output. DIV1 DIV2 I DIV1 and DIV2 provide clock-mode inputs. DIV1–DIV2 should not be changed unless the RS signal is active. † I = input, O = output, Z = high impedance, PWR = power, GND = ground

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C203 and TMS320LC203 Terminal Functions (Continued) TERMINAL TYPE † DESCRIPTION NAME NO. TYPE † DESCRIPTION OSCILLATOR, PLL, AND TIMER SIGNALS (CONTINUED) PLL5V 10 I PLL operating at 5 V. When the device is operating at 5 V, PLL5V should be tied high. When the device is operating at 3.3 V, PLL5V should be tied low. SERIAL PORT AND UART SIGNALS CLKX 87 I/O Transmit clock. CLKX is a clock signal for clocking data from the transmit shift register (XSR) to the DX data-transmit pin. The CLKX can be an input if the MCM bit in the synchronous serial-port control register (SSPCR) is set to 0. CLKX can also be driven by the device at one-half of the CLKOUT1 frequency when MCM = 1. If the serial port is not being used, CLKX goes into the high-impedance state when OFF is active low. Value at reset is as an input. CLKR 84 I/O Receive-clock input. External clock signal for clocking data from the DR (data-receive) pin into the serial-port receive shift register (RSR). CLKR must be present during serial-port transfers. If the serial port is not being used, CLKR can be sampled as an input by the IN0 bit of the SSPCR. FSR 85 I/O Frame synchronization pulse for receive input. The falling edge of the FSR pulse initiates the data-receive process, beginning the clocking of the RSR. FSR goes into the high-impedance state when OFF is active low. FSX 89 I/O Frame synchronization pulse for transmit input/ouput. The falling edge of the FSX pulse initiates the data-transmit process, beginning the clocking of the serial-port transmit shift register (XSR). Following reset, FSX is an input. FSX can be selected by software to be an output when the TXM bit in the SSPCR is set to 1. FSX goes into the high-impedance state when OFF is active low. DR 86 I Serial-data receive input. Serial data is received in the receive shift register (RSR) through the DR pin. DX 90 O Serial-port transmit output. Serial data is transmitted from the transmit shift register (XSR) through the DX pin. DX is in the high-impedance state when OFF is active low. TX 93 O Asynchronous transmit pin RX 95 I Asynchronous receive pin TEST SIGNALS TRST 79 I IEEE Standard 1149.1 (JTAG) test reset. TRST, when active high, gives the scan system control of the operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and the test signals are ignored. If the TRST pin is not driven, an external pulldown resistor must be used. TCK 78 I JTAG test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on the test-access port (TAP) input signals (TMS and TDI) are clocked into the TAP controller, instruction register, or selected test-data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. TMS 81 I JTAG test-mode select. TMS is clocked into the TAP controller on the rising edge of TCK. TDI 80 I JTAG test-data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO 82 O/Z JTAG test-data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. EMU0 76 I/O/Z Emulator pin 0. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as an input/output through the JTAG scan. EMU1/OFF 77 I/O/Z Emulator pin 1. Emulator pin 1 disables all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as an input/output through the JTAG scan. When TRST is driven low, this pin is configured as OFF. EMU1/OFF, when active low, puts all output drivers in the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following apply: TRST = 0 EMU0 = 1 EMU/OFF = 0 † I = input, O = output, Z = high impedance, PWR = power, GND = ground

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998

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TMS320C203 and TMS320LC203 Terminal Functions (Continued) TERMINAL TYPE † DESCRIPTION NAME NO. TYPE † DESCRIPTION SUPPLY PINS VDD PWR Power VSS GND Ground † I = input, O = output, Z = high impedance, PWR = power, GND = ground

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C209 Terminal Functions TERMINAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION ADDRESS AND DATA BUSES D15 D14 D13 D12 D11 D10 I/O/Z Parallel data bus D15 (MSB) through D0 (LSB). D15–D0 are multiplexed to transfer data between the core CPU and external data/program memory or I/O devices. D15–D0 are placed in the high-impedance state when not outputting or when RS is asserted. They also go into the high-impedance state when OFF is active low. A15 A14 A13 A12 A11 A10 O/Z Parallel address bus A15 (MSB) through A0 (LSB). A15–A0 are multiplexed to address external data/program memory or I/O devices. These signals go into the high-impedance state when OFF is active low. MEMORY CONTROL SIGNALS PS 65 O/Z Program-select signal. PS is always high unless low-level asserted for communicating to off-chip program space. PS goes into the high-impedance state when OFF is active low. DS 63 O/Z Data-select signal. DS is always high unless low-level asserted for communicating to off-chip program space. DS goes into the high-impedance state when OFF is active low. IS‡ 64 O/Z I/O-space-select signal. IS is always high unless low-level asserted for communicating to I/O ports. IS goes into the high-impedance state when OFF is active low. READY 7 I Data-ready input. READY indicates that an external device is prepared for the bus transaction to be completed. If READY is low, the TMS320C209 waits one cycle and checks READY again. If READY is not used, it should be pulled high. R/W ‡ 66 O/Z Read/write signal. R/W indicates transfer direction when communicating to an external device. R/W is normally in read mode (high), unless low level is asserted for performing a write operation. R/W goes into the high-impedance state when OFF is active low. STRB 67 O/Z Strobe signal. STRB is always high unless asserted low to indicate an external bus cycle. STRB goes into the high-impedance state when OFF is active low. RD 78 O/Z Read-select. RD indicates an active, external read cycle and can connect directly to the output enable (OE) of external devices. RD is active on all external program, data, and I/O reads. RD goes into the high-impedance state when OFF is active low. † I = input, O = output, Z = high impedance, PWR = power, GND = ground ‡ IS, R/W, and the data bus are visible at the pins, while accessing internal I/O-mapped registers (for ’C209 devices only).

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TMS320C209 Terminal Functions (Continued) TERMINAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION MEMORY CONTROL SIGNALS (CONTINUED) WE 62 O/Z Write enable. The falling edge of WE indicates that the device is driving the external data bus (D15–D0). Data can be latched by an external device on the rising edge of WE. WE is active on all external program, data, and I/O writes. WE goes into the high-impedance state when OFF is active low. RAMEN 37 I RAM enable. RAMEN enables the 4K × 16 words of on-chip RAM. MULTIPROCESSING SIGNALS BR 68 O/Z Bus-request signal. BR is asserted during access of external global data-memory space. BR can be used to extend the data memory address space by up to 32K words. BR goes into the high-impedance state when OFF is active low. BIO 9 I Branch control input. BIO is polled by BIOZ instruction. If BIO is low, the TMS320C209 executes a branch. If BIO is not used, it should be pulled high. XF 75 O/Z External flag output (latched software-programmable signal). XF is used for signaling other processors in multiprocessing configurations or as a general-purpose output pin. IACK 79 O/Z Interrupt-acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the interrupt vector location designated by A15–A0. IACK also goes into the high-impedance state when OFF is active low. INITIALIZATION, INTERRUPT, AND RESET OPERATIONS INT1 INT2 INT3 I External-user interrupts. INT1–INT3 are prioritized and maskable by the interrupt-mask register and the interrupt-mode bit. If INT1–INT3 are not used, they should be pulled high. NMI 36 I Nonmaskable interrupt. NMI is an external interrupt that cannot be masked through the INTM or the IMR. When NMI is activated, the processor traps to the appropriate vector location. If NMI is not used, it should be pulled high. RS RS I Reset input. RS and RS cause the TMS320C209 to terminate execution and force the program counter to 0. When RS is brought high, execution begins at location 0 of program memory after 16 cycles. RS affects various registers and status bits. MP/MC 10 I Microprocessor/microcontroller-mode-select pin. If MP/MC is low, the on-chip ROM is mapped into program space. When MP/MC is high, the device accesses off-chip memory. OSCILLATOR/TIMER SIGNALS CLKIN1/2 CLKOUT1 77 O/Z Master clock output signal. CLKOUT1 cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by the rising edges of CLKOUT1. CLKOUT1 goes into the high-impedance state when OFF is active low. CLKMOD 74 I Clock-input mode. CLKMOD (when high) enables the clock doubler and phase-locked loop (PLL) on the clock input signal. If the internal oscillator is not used, X1 should be left unconnected. CLKIN/X2 I O Input clock. CLKIN/X2 is the input clock to the device. As CLKIN, the pin operates as the external oscillator clock input, and as X2, the pin operates as the internal oscillator input with X1 being the internal oscillator output. TOUT 72 O Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT1-cycle wide. PLL5V 38 I PLL operating at 5 V. When PLL5V is operating at 5 V, PLL5V should be strapped high. RES1 40 I Reserved input pin. Do not connect to RES1. † I = input, O = output, Z = high impedance, PWR = power, GND = ground

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C209 Terminal Functions (Continued) TERMINAL TYPE † DESCRIPTIONNAME NO. TYPE † DESCRIPTION TEST SIGNALS TCK 8 I JTAG test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on test-access port (TAP) input signals (TMS and TDI) are clocked into the TAP controller, instruction register, or selected test-data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. TDI 5 I JTAG test data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO 71 O/Z JTAG test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when scanning of data is in progress. TDO goes into the high-impedance state when OFF is active low. TMS 32 I JTAG test mode-select. TMS is clocked into the TAP controller on the rising edge of TCK. TRST 80 I JTAG test reset. TRST, when active high, gives the JTAG scan system control of the operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and the JTAG signals are ignored. EMU0 EMU1/OFF I/O/Z Emulator pin 0. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as an input/output through the JTAG scan. Emulator pin 1. EMU1 disables all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output by way of JTAG scan. When TRST is driven low, this pin is configured as OFF. EMU1/OFF, when active low, puts all output drivers in the high-imped- ance state. SUPPLY PINS VDD PWR Power VSS GND Ground † I = input, O = output, Z = high impedance, PWR = power, GND = ground

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998

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functional block diagram of the ’C2xx internal hardware TCR Timer Data Bus OSCALE (0–7) D15–D0 A15–A0 1616 ACCL(16)ACCH(16)C CALU(32) 3232 MUX ISCALE (0–16) MUX PREG(32) Multiplier TREG0(16) MUX 1616 MUX B1 (256x16) B2 (32x16) DARAM B0 (256x16) DARAM MUX LSB from IR MUX DP(9) MUX SARAM † ARAU(16) MUX ARB(3) ARP(3) Program Bus AR7(16) AR6(16) AR5(16) AR3(16) AR2(16) AR1(16) AR0(16) Address Instruction Stack 8 x16 PC MUX NMI WE RD CLKIN/X2 CLKOUT1 INT[3:1] BOOT /MP/MC RS HOLDA † HOLD † XF BR READY STRB R/W PS DS IS DIV2 DIV1 Control Data Bus Program Bus Data Bus AR4(16) MUX MUX Data/Prog Data/Prog PSCALE (–6,0,1,4) Data ROM/FLASH † MUX MUX NPAR PAR MSTACK Program Control (PCTRL) PRD TIM ADTR ASP † SSPCR SSP † SDTR TOUT TX RX I/O PINS DX CLKX FSX DR FSR CLKR BRD IOSR Reserved Memory Map Register IMR (16) IFR (16) GREG (16) Program Bus I/O-Mapped Registers † Not available on all devices (see Table 2). NOTES: A. Symbol descriptions appear in Table 3. B. For clarity, the data and program buses are shown as single buses although they include address and data bits.

Table 3. Legend for the ’C2xx Internal Hardware Functional Block Diagram as an index value for AR updates of more than one and as a compare value to AR. memory address space by up to 32K words. provides status results to PCTRL. they are mapped to program space. GREG specifies the size of the global data memory space. IMR individually masks or enables the seven interrupts. INT# Interrupt Traps A total of 32 interrupts by way of hardware and/or software are available. output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations. signed or unsigned 2s-complement arithmetic multiply. address-generation logic is used to generate sequential addresses in data space. NPAR holds the program address to be driven out on the PAB on the next cycle. management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to DWEB. operations scheduled for the current machine cycle. PCTRL Program ControllerPCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations. 16-bit bus for program space read data. PRDB is driven by the memories or the logic interface.

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Table 3. Legend for the ’C2xx Internal Hardware Functional Block Diagram (Continued) PREG Product Register 32-bit register holds results of 16 × 16 multiply. for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction. SSPCR is the control register for selecting the serial port’s mode of operation. SDTR is the data-transmit and data-receive register. TCR contains the control bits that define the divide-down ratio, start/stop the timer, and reload the period. reload bit is activated. Reset initializes the PRD to 0xFFFF. TIM contains the current 16-bit count of the timer. Reset initializes the TIM to 0xFFFF. UART is the asynchronous serial port. ASPCR controls the asynchronous serial-port operation. IOSR detects current levels (and changes with inputs) on pins IO0–IO3 and the status of UART. loaded from data memory, thereby allowing the status of the machine to be saved and restored. routines, or for storing data. The ’C2xx stack is 16-bit wide and eight-level deep.

TMS320C2xx to execute most instructions in a single cycle. and restored for subroutines. (SST) is used to read from ST0 and ST1, except for the INTM bit, which is not affected by the LST instruction. and Table 5 show the organization of status registers ST0 and ST1, indicating all status bits contained in each. Table 4. Status and Control Register Zero Table 5. Status and Control Register One

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Table 6. Status Register Field Definitions† instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP. Carry bit. C is set to 1 if the result of an addition generates a carry; it is reset to 0 if the result of a subtraction generates a borrow. Otherwise, C is reset after an addition or set after a subtraction, except when the instruction is ADD or SUB with a 16-bit shift. provided to branch on the status of C. C is set to 1 on a reset. memory address of 16 bits. DP can be modified by the LST and LDP instructions. by reset. It is also set to 1 when a maskable interrupt trap is taken. OV remains set until a reset, BCND/D on OV/NOV, or LST instruction clears OV. instructions set and reset this bit, respectively. LST can also be used to modify the OVM. instruction, and can be loaded by the LST #1 instruction. SXM is set to 1 by reset. instructions can execute based on the condition of TC. the CLRC XF instructions. XF is set to 1 by reset. † See Table 3 for definitions of acronyms and Table 20 for descriptions of opcode instructions. functional block diagram shows the components of the CPU.

CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations. factor to be adaptable to the system’s performance. 32-bit product register (PREG) that holds the product. performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products. The PM field of status register ST1 specifies the PM shift mode, as shown in Table 7. Table 7. PSCALE Product-Shift Modes 128 consecutive multiply/accumulates without the possibility of overflow.

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998

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multiplier (continued) Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the multiplier, allowing both operands to be processed simultaneously. The data for these operations can be transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient addresses are generated by program address generation (PAGEN), while the data addresses are generated by data-address generation (DAGEN). This allows the repeated instruction to sequentially access the values from the coefficient table and step through the data in any of the indirect addressing modes. The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to throw away the oldest sample. The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed data memory location, with the result placed in PREG. This allows the operands of greater than 16 bits to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The SQRA (square/add) and SQRS (square/subtract) instructions pass the same value to both inputs of the multiplier for squaring a data-memory value. After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register (PREG). The product from PREG can be transferred to the CALU or to data memory by way of the SPH (store product-high register) and the SPL (store product-low register) instructions. Note: the transfer of PREG to either the CALU or data memory passes through the product-scaling shifter (PSCALE) and is therefore affected by the product-shift mode defined by PM bits in the ST1 register. This is important when saving PREG in an interrupt-service-routine-context save as the PSCALE shift effects cannot be modeled in the restore operation. PREG can be cleared by executing the MPY #0 instruction. The product register can be restored by loading the saved low half into TREG and executing the MPY #1 instruction. The high half is then loaded using the LPH instruction. central arithmetic logic unit The TMS320C2xx central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle. This arithmetic logic unit (ALU) is referred to as “central” to differentiate it from a second ALU used for indirect-address-generation (called the ARAU). Once an operation is performed in the CALU, the result is transferred to the accumulator (ACC), where additional operations, such as shifting, can occur. Data that is input to the CALU can be scaled by the input data-scaling shifter (ISCALE) when coming from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from the multiplier. The CALU is a general-purpose arithmetic/logic unit that operates on 16-bit words taken from data memory or derived from immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform Boolean operations, facilitating the bit manipulation ability required for a high-speed controller. One input to the CALU is always provided from the accumulator, and the other input can be provided from the product register (PREG) of the multiplier or the output of the scaling shifter (that has been read from data memory or from the ACC). After the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator. The TMS320C2xx supports floating-point operations for applications requiring a large dynamic range. The NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator by performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the LACT/ADDT/SUBT (load/add to/subtract from accumulator with shift specified by TREG) instructions. These instructions are useful in floating-point arithmetic where a number needs to be denormalized—that is, floating-point to fixed-point conversion. They are also useful in the execution of an automatic gain control (AGC) going into a filter. The BITT (bit-test) instruction provides testing of a single bit of a word in data memory based on the value contained in the four LSBs of TREG.

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 17POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 central arithmetic logic unit (continued) The CALU overflow-saturation mode can be enabled/disabled by setting/resetting the overflow mode (OVM) bit of ST0. When the CALU is in the overflow-saturation mode and an overflow occurs, the overflow flag is set and the accumulator is loaded with either the most positive or the most negative value representable in the accumulator, depending upon the direction of the overflow. The value of the accumulator upon saturation is 07FFFFFFFh (positive) or 080000000h (negative). If the OVM status register bit is reset and an overflow occurs, the overflowed results are loaded into the accumulator with modification. (Note that logical operations cannot result in overflow.) The CALU can execute a variety of branch instructions that depend on the status of the CALU and the accumulator. These instructions can be executed conditionally, based on any meaningful combination of these status bits. For overflow management, these conditions include the OV (branch on overflow) and EQ (branch on accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides the ability to branch to an address specified by the accumulator (computed goto). Bit-test instructions (BIT and BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory. The CALU also has a carry bit that is set or reset depending on various operations within the device. The carry bit allows more efficient computation of extended-precision products and additions or subtractions. It is also useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the single-bit shift and rotate instructions. It is not affected by accumulator loads, logical operations, or other such non-arithmetic or control instructions. /C0068Additions to and subtractions from the accumulator: C = 0: When the result of a subtraction generates a borrow. When the result of an addition does not generate a carry. (Exception: When the ADD instruction is used with a shift of 16 and no carry is generated, the ADD instruction has no effect on C.) C = 1: When the result of an addition generates a carry. When the result of a subtraction does not generate a borrow. (Exception: When the SUB instruction is used with a shift of 16 and no borrow is generated, the SUB instruction has no effect on C.) /C0068Single-bit shifts and rotations of the accumulator value. During a left shift or rotation, the most significant bit of the accumulator is passed to C; during a right shift or rotation, the least significant bit is passed to C. Note: the carry bit is set to “1” on a hardware reset. The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions provide the use of the previous value of carry in their addition/subtraction operation. The one exception to the operation of the carry bit is in the use of ADD with a shift count of 16 (add to high accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. This case of the ADD instruction can set the carry bit only if a carry is generated, and this case of the SUB instruction can reset the carry bit only if a borrow is generated; otherwise, neither instruction affects it. Two conditional operands, C and NC, are provided for branching, calling, returning, and conditionally executing based upon the status of the carry bit. The SETC, CLRC, and LST #1 instructions also can be used to load the carry bit. The carry bit is set to one on a hardware reset. accumulator The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage in data memory. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is performed while the data is being transferred to the data bus for storage. The contents of the accumulator remain unchanged. When the post-scaling shifter is used on the high word of the accumulator (bits 16–31), the MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0–15). When the post-scaling shifter is used on the low word, the LSBs are zero-filled.

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accumulator (continued) The SFL and SFR (in-place one-bit shift to the left/right) instructions and the ROL and ROR (rotate to the left/right) instructions implement shifting or rotating of the accumulator contents through the carry bit. The SXM status register bit affects the definition of the SFR (shift accumulator right) instruction. When SXM = 1, SFR performs an arithmetic right shift, maintaining the sign of the accumulator data. When SXM = 0, SFR performs a logical shift, shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. RPT (repeat) instructions can be used with the shift and rotate instructions for multiple-bit shifts. auxiliary registers and auxiliary-register arithmetic unit (ARAU) The ’C2xx provides a register file containing eight auxiliary registers (AR0–AR7). The auxiliary registers are used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register addressing allows placement of the data memory address of an instruction operand into one of the auxiliary registers. These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 0 through 7, designated AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded from data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The contents of these registers can also be stored in data memory or used as inputs to the CALU. The auxiliary register file is connected to the ARAU. The ARAU can autoindex the current auxiliary register while the data memory location is being addressed. Indexing either by ±1 or by the contents of AR0 can be performed. As a result, accessing tables of information does not require the CALU for address manipulation; therefore, the CALU is free for other operations in parallel. memory The ’C2xx implements three separate address spaces for program memory, data memory, and I/O. Each space accommodates a total of 64K 16-bit words. Within the 64K words of data space, the 256 to 32K words at the top of the address range can be defined to be external global memory in increments of powers of two, as specified by the contents of the global memory allocation register. Access to global memory is arbitrated using the global memory bus request (BR ) signal. On the ’C2xx, the first 96 (0–5Fh) data memory locations are allocated for memory-mapped registers or are reserved. This memory-mapped register space contains various control and status registers including those for the CPU. When using on-chip RAM, or high-speed external memory, the ’C2xx runs at full speed with no wait states. The ability of the DARAM to allow two accesses to be performed in one cycle, coupled with the parallel nature of the ’C2xx architecture, enables the device to perform three concurrent memory accesses in any given machine cycle. Externally, the READY line can be used to interface the ’C2xx to slower, less expensive external memory. Downloading programs from slow off-chip memory to on-chip RAM can speed processing while cutting system costs. The ’C2xx DARAM allows writes to and reads from the RAM in the same cycle without the address restrictions of the SARAM. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1), and block 2 (B2). Block 1 consists of 256 words in data memory and block 2 consists of 32 words in data memory. Block 0 is a 256-word block that can be configured as data or program memory. The SETC CNF (configure B0 as program memory) and CLRC CNF (configure B0 as data memory) instructions allow dynamic configuration of the memory maps through software. When using Block 0 as program memory, instructions can be downloaded from external program memory into on-chip RAM and then executed.

when enabled. When disabled, these addresses are located in the device’s external program memory space. The ’C209 devices provide two types of RAM: single-access RAM (SARAM) and dual-access RAM (DARAM). to improve code performance. internal I/O space. Figure 1, Table 6, and Table 7 describe these registers and show their respective addresses. respective memory spaces to on-chip or off-chip memory. RAMEN, and control bit CNF on the mapping of the respective memory spaces to on-chip or off-chip memory. Figure 1. TMS320C203/LC203 Memory Map

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Table 8. TMS320C203/LC203 Memory Map Configurations† † Internal I/O locations 0FFE0h–0FFFFh are dedicated to the timer, serial-port control, wait-state generator registers, and reserved space. ‡ FF00–FF0F are reserved for test purposes and should not be used. § When BOOT = 0, the on-chip boot-loader at 0xFF00h is enabled. During boot time, memory address FE00–FFFF is reserved. Table 9. TMS320C203/LC203 On-Chip Memory Map ¶ Each of these address pairs point to the same block of memory. to the 16-bit-wide destination. The maximum size for the EPROM, is 32K words × 8-bits. TMS320C2xx User’s Guide (literature number SPRU127). # The address range 8000h – FEFFh equals 32 512 words.

Figure 2. TMS320C209 Memory Map

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Table 10. TMS320C209 Memory Map Configurations† † Internal I/O locations 0FFF0h–0FFFFh are dedicated to the timer, wait-state generator registers, and reserved space. ‡ FF00–FF0F are reserved for test purposes and should not be used. Table 11. TMS320C209 On-Chip Memory Map § Both of the addresses in each of these address pairs point to the same block of memory.

internally mapped registers. Table 12. TMS320C203 Memory and I/O Internally Mapped Registers† TMS320C203. IMR is set to 0 at reset. the timer interrupt, TINT. Bits 3 and 4, RINT and XINT, respectively, are for the synchronous serial port, SSP. the CLKOUT1 pin is turned off. by the hold-generating circuit to determine if a HOLD or INT1 is active. ASPCR IS@FFF5 Asynchronous serial-port control register. ASPCR controls the asynchronous serial port operation. IOSR IS@FFF6 I/O status register. IOSR detects current levels (and changes with inputs) on pins IO0–IO3 and status of UART. divide-down ratio to 0 and starts the timer. borrows or when the reload bit is activated. Reset initializes the PRD to 0xFFFF. TIM IS@FFFA Timer-counter register. TIM contains the current 16-bit count of the timer. Reset initializes the TIM to 0xFFFF. I/O space. Reset initializes the WSGR to 0x0FFFh. † During on-chip I/O access, IS, RD, and WR are not visible at the pins (’C203 only).

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Table 13. TMS320C209 Memory-Mapped Registers three external interrupt pins (bit 0 ties to INT1, bit 1 to INT2, and bit 2 to INT3). Bit 3 ties to the timer interrupt. TMS320C209. IMR is set to 0 at reset. the respective pending interrupt. Writing a 1 to an inactive flag has no affect. IFR is set to 0 at reset. divide-down ratio to 0 and starts the timer. borrows or when the reload bit is activated. Reset initializes the PRD to 0xFFFF. TIM IS@FFFE Timer-counter register. TIM contains the current 16-bit count of the timer. Reset initializes the TIM to 0xFFFF. data, and I/O space as well as the address-visibility-enable bit. Reset initializes WSGR to 0xF. BR low (with timing similar to the address bus) (see Table 11).

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 25POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 external interface (continued) The ’C2xx external parallel interface provides various control signals to facilitate interfacing to the device. The R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal provides a timing reference for all external cycles. For convenience, the device also provides the RD and the WE output signals, which indicate a read and a write cycle, respectively, along with timing information for those cycles. The availability of these signals minimizes external gating necessary for interfacing external devices to the ’C2xx. Interface to memory and I/O devices of varying speeds is accomplished by using the READY line. When transactions are made with slower devices, the ’C2xx processor waits until the other device completes its function and signals the processor by way of the READY line. Once a ready indication is provided back to the ’C2xx from the external device, execution continues. On the ’C209 device, the READY line is required (active high) to complete reads or writes to internal I/O-mapped registers. On the ’C203 devices, the READY line is required to be active high during boot time. The bus-request (BR ) signal is used in conjunction with the other ’C2xx interface signals to arbitrate external global-memory accesses. Global memory is external data-memory space in which the BR signal is asserted at the beginning of the access. When an external global-memory device receives the bus request, it responds by asserting the READY signal after the global memory access is arbitrated and the global access is completed. The TMS320C2xx supports zero-wait-state reads on the external interface. However, to avoid bus conflicts, writes take two cycles. This allows the TMS320C2xx to buffer the transition of the data bus from input to output (or output to input) by a half cycle. In most systems, TMS320C2xx ratio of reads to writes is significantly large to minimize the overhead of the extra cycle on writes. Wait states can be generated when accessing slower external resources. The wait states operate on machine-cycle boundaries and are initiated either by using READY or by using the software wait-state generator. READY can be used to generate any number of wait states. interrupts and subroutines The ’C2xx implements three general-purpose interrupts, INT3–INT1, along with reset (RS) and the nonmaskable interrupt (NMI), which are available for external devices to request the attention of the processor. Internal interrupts are generated by the synchronous serial port (RINT and XINT) (’C203 only), the asynchronous serial port (TXRXINT) (’C203 only), the timer (TINT), the UART, and the software-interrupt (TRAP , INTR and NMI) instructions. Interrupts are prioritized with RS having the highest priority, followed by NMI , and timer (TINT) (for ’C209) or UART (for ’C203) having the lowest priority. Additionally, any interrupt, except RS and NMI, can be individually masked with a dedicated bit in the interrupt mask register (IMR) and can be cleared, set, or tested using its own dedicated bit in the interrupt flag register (IFR). The reset and NMI functions are not maskable. All interrupt vector locations are on two-word boundaries so that branch instructions can be accommodated in those locations if desired. A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle instruction, the interrupt is not processed until the instruction completes execution. This mechanism applies to instructions that are repeated (using the RPT instruction) and to instructions that become multicycle because of wait states. Each time an interrupt is serviced or a subroutine is entered, the program counter (PC) is pushed onto an internal hardware stack, providing a mechanism for returning to the previous context. The stack contains eight locations, allowing interrupts or subroutines to be nested up to eight-levels deep.

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The TMS320C203 provides an active-low reset (RS) only, while the TMS320C209 provides both an RS and an RS . RS and RS, the TMS320C209 resets, are not synchronized. A minimum pulse duration of six cycles ensures that an asynchronous reset signal resets the device. Either RS or RS can reset the device with RS being active high and RS being active low. The TMS320C2xx fetches its first instruction approximately sixteen cycles after the rising edge of RS (either ’C203 or ’C209) or falling edge of RS (’C209 only). Please note that the reset action halts all operations whether they are completed or not. Therefore, the state of the system and its data cannot be maintained through the reset operation. For example, if the device is writing to an external resource when the reset is initiated, the write is aborted. This can and will corrupt data in system resources. It is, therefore, necessary to reinitialize the system after a reset. power-down modes The ’C2xx implements several power-down modes in which the ’C2xx core enters a dormant state and dissipates considerably less power. A power-down mode is invoked either by executing the IDLE instruction or by driving the HOLD (’C203 only) input low and executing HOLD mode. When the HOLD signal initiates the power-down mode, on-chip peripherals continue to operate; this power-down mode is terminated when HOLD goes inactive (’C203 only). While the ’C2xx is in a power-down mode, all of its internal contents are maintained; this allows operation to continue unaltered when the power-down mode is terminated. All CPU activities are halted when the IDLE instruction is executed, but the CLKOUT1 pin remains active depending on the status of the interrupt-control (IC) register (’C203 only). The peripheral circuits continue to operate, allowing peripherals such as serial ports and timers to take the CPU out of its powered-down state. A power-down mode, when initiated by an IDLE instruction, is terminated upon receipt of an interrupt. software-controlled wait-state generator Due to the fast cycle time of the TMS320C2xx devices, it is often necessary to operate with wait states to interface with external logic and memory. For many systems, one wait state is adequate. TMS320C209 When operating the TMS320C209 at full speed, it is difficult to respond fast enough to provide a READY-based wait state for the first cycle. For this reason, the TMS320C209 includes a simple software-controlled wait-state generator to provide the first wait state. The software-controlled wait-state generator can be programmed to generate the first wait state for a given external space. The wait-state generator (WSGR) has four wait-state bits: AVIS, DATA (DSWS), PROG (PSWS), and I/O (ISWS). The wait-state generator inserts a wait state to a given memory space if the respective bit is set to 1, regardless of the condition of the READY signal. Then, READY can be used to further extend the wait states. The AVIS bit differs from the other WSGR bits because it does not generate a wait state but enables the address-visibility mode of the ’C209. This mode allows the internal program address to be presented to the address bus when this bus is not used for an external access. The WSGR bits are initially set to 1 by reset so that the device can operate from slow memory. After initialization, the AVIS bit should be set to 0 for production systems to reduce power and noise. The WSGR register (shown in Table 14 and Table 15) resides at I/O port 0xFFFFh.

Table 14. TMS320C209 Wait-State Generator Control Register (WSGR)

0 W–1 W–1 W–1 W–1

Table 15. Bit Functions of the TMS320C209 Wait-State Generator Control Register (WSGR)

0 PSWS

generated by PSWS. This bit is set to 1 (active) by reset (RS or RS).

1 DSWS

2 ISWS

3 AVIS

systems to reduce system power and noise. 15–4 Reserved Always read as zeros. and Table 18) resides at I/O port 0xFFFCh. Table 16. TMS320C203 Wait-State Generator Control Register (WSGR)

0 R/W–111 R/W–111 R/W–111 R/W–111

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Table 17. Bit Functions of the TMS320C203 Wait-State Generator Control Register (WSGR) extended using the READY signal. The READY signal does not override the wait states generated by PSLWS. Bits 2–0 are set to 1 (active) by reset (RS). extended using the READY signal. The READY signal does not override the wait states generated by PSUWS. signal does not override the wait states generated by ISWS. Bits 11–9 are set to 1 (active) by reset (RS). 15–12 Reserved Always read as zeros. Table 18. Bit Settings for TMS320C203 Wait-State(s) Programming disabled by specific status bits. mean of performing periodic I/O or other functions. The TMS320C209 includes two clock options. The first option (÷2) operates the CPU at half the input clock rate. ÷2 mode is enabled by tying the CLKMOD pin low. The ×2 mode is enabled by tying the CLKMOD pin high.

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 29POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C209 input clock options (continued) the processor is running because the internal clock generator can generate minimum clock pulse width specification violations. The RS or RS signals should be in their active state if the CLKMOD pin is changed. TMS320C203 input clock options The TMS320C203 provides multiple clock modes of: ÷2, ×1, ×2, ×4. The clock-mode configuration cannot be dynamically changed without executing another reset. The operation of the PLL circuit is affected by the operating voltage of the device. If the device is operating at 5 V, then the PLL5V signal should be tied high. For 3.3-V operation, PLL5V should be tied low. synchronous serial port (TMS320C203 only) A full-duplex, bidirectional, 16-bit on-chip synchronous serial port provides direct communication with serial devices such as CODECs, serial analog-to-digital converters (A/Ds), and other serial systems. The interface signals are compatible with CODECs and many other serial devices. The serial port can also be used for intercommunication between processors in multiprocessing applications. Both receive and transmit operations have a four-deep first-in-first-out (FIFO). The advantage of having a FIFO is to alleviate the CPU from being loaded with the task of servicing a transmit-data or receive-data on every interrupt, thereby, allowing a continuous communications stream of 16-bit data packets. The continuous mode provides operation that once initiated, requires no further frame synchronization pulses when transmitting at maximum packet frequency. The maximum transmission rate for both transmit and receive operations is CPU speed divided by two or CLKOUT1(frequency)/2. Therefore, the maximum rate is 20 Mbps at 25 ns and 14.28 Mbps at 35 ns. The serial port is fully static and functions at arbitrarily low clocking frequencies. When the serial ports are in reset, the device can be configured to shut off the serial port internal clocks, allowing the device to run in a lower-power mode of operation. Three signals are necessary to connect the transmit pins of the transmitting device with the receive pins of the receiving device for data transmission. The transmit-serial-data signal (DX) sends the actual data. The transmit-frame-synchronization signal (FSX) initiates the transfer (at the beginning of the packet), and the transmit-clock signal (CLKX) clocks the bit transfer. The corresponding pins on the receiving device are DR, FSR and CLKR, respectively. asynchronous serial port (TMS320C203 only) The universal asynchronous serial port (UART) is full-duplex, and transmits and receives 8-bit data only. For transmit and receive, there is one start bit and one or two configurable stop bits by way of the asynchronous serial-port control register (ASPCR). Double-buffering or transmit/receive data is used in all modes. Baud-rate generation uses the BRD (baud-rate divisor) register to obtain the baud rate. The maximum baud rate is 2.5 Mbps at 250000 characters per second (at 25-ns instruction cycle time). The asynchronous serial port contains an autobaud-detection feature that allows it to automatically lock to the incoming data rate. Autobaud detection is enabled by setting the CAD bit in the ASPCR to 1 and the ADC bit in the I/O status register (IOSR) to 0. See the TMS320C2xx User’s Guide (literature number SPRU127) for details. TMS320C2xx scan-based emulation TMS320C203 devices incorporate scan-based emulation logic for code-and hardware-development support. Scan-based emulation allows the emulator to control the processor in the system without the use of intrusive cables to the full pinout of the device. The scan-based emulator communicates with the ’C203 by way of the IEEE 1149.1 (JTAG) interface. Note: The TMS320C203, like other DSPs in the TMS320C20x/TMS320C24x families, does not include boundary scan. The scan chain of ’C203 device is useful for emulation functions only.

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multiprocessing (TMS320C203 only) The flexibility of the ’C2xx allows configurations to satisfy a wide range of system requirements; the device can be used in a variety of system configurations, including but not limited to the following: /C0068A standalone processor /C0068A multiprocessor with devices in parallel /C0068A slave/host multiprocessor with global memory space /C0068A peripheral processor interfaced by way of processor-controlled signals to another device For multiprocessing applications, the ’C2xx has the capability of allocating global memory space and communicating with that space by way of the BR and READY control signals. Global memory is data memory shared by more than one device. Global-memory access must be arbitrated. The 8-bit memory-mapped global-memory-allocation register (GREG) specifies part of the ’C2xx’s data memory as global external memory. The contents of the register determine the size of the global memory space. If the current instruction addresses an operand within that space, BR is asserted to request control of the bus. The length of the memory cycle is controlled by the READY line. The ’C203 supports direct-memory access (DMA) to its external program, data, and I/O spaces using the HOLD and HOLDA signals. Another device can take complete control of the ’C2xx’s external memory interface by asserting HOLD low and executing HOLD mode. This causes the ’C2xx to place its address, data, and memory-control signals in the high-impedance state and assert HOLDA. In ’C203, HOLD logic is not activated by hardware only. It is a combination of hardware interrupt (INT1 in MODE 0) and software instruction IDLE. See the TMS320C2xx User’s Guide (literature number SPRU127) for details. instruction set The ’C2xx microprocessor implements a comprehensive instruction set that supports both numeric-intensive signal-processing operations and general-purpose applications, such as multiprocessing and high-speed control. Source code for the ’C1x and ’C2x DSPs is upward-compatible with the ’C2xx. For maximum throughput, the next instruction is prefetched while the current one is being executed. Because the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an instruction requires to execute varies depending upon whether the next data-operand fetch is from internal or external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal or fast external program memory. addressing modes The ’C2xx instruction set provides four basic memory-addressing modes: direct, indirect, immediate and register. For direct addressing, the instruction word contains the lower seven bits of the data-memory address. This field is concatenated with the nine bits of the data-memory page pointer (DP) to form the 16-bit data-memory address. Therefore, in the direct-addressing mode, data memory is effectively paged with a total of 512 pages, with each page containing 128 words. Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers (AR0–AR7) provide flexible and powerful method of indirect addressing. To select a specific auxiliary register, the auxiliary register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 31POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 addressing modes (continued) There are seven types of indirect addressing: autoincrement or autodecrement, postindexing by either adding or subtracting the contents of AR0, single indirect addressing with no increment or decrement, and bit-reversed addressing [used in fast Fourier transforms (FFTs)] with increment or decrement. All operations are performed on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary register and ARP can be modified. In immediate addressing, the actual operand data is provided in a portion of the instruction word or words. There are two types of immediate addressing: long and short. In short immediate addressing, the data is contained in a portion of the bits in a single-word instruction. In long immediate addressing, the data is contained in the second word of a two-word instruction. The immediate-addressing mode is useful for data that does not need to be stored or used more than once during the course of program execution, such as initialization of values, constants, and so forth. The register-addressing mode uses operands in CPU registers either explicitly, such as with a direct reference to a specific register, or implicitly, with instructions that intrinsically reference certain registers. In either case, operand reference is simplified because 16-bit values can be used without specifying a full 16-bit operand address or immediate value. repeat feature The repeat function can be used with instructions (as defined in Table 20) such as multiply/accumulate (MAC and MACD), block move (BLDD and BLPD), I/O transfer (IN/OUT), and table read/write (TBLR/TBLW). These instructions, although normally multicycled, are pipelined when the repeat feature is used, and they effectively become single-cycle instructions. For example, the table-read (TBLR) instruction may take three or more cycles to execute, but when the instruction is repeated, a table location can be read every cycle. The repeat counter (RPTC) is loaded with the addressed data memory location if direct or indirect addressing mode is used, and with an 8-bit immediate value if short immediate addressing is used. The RPTC register is loaded by the RPT instruction. This results in a maximum of N + 1 executions of a given instruction. RPTC is cleared by reset. Once an RPT instruction is decoded, all interrupts including NMI (excluding reset) are masked until the completion of the repeat loop. instruction set summary This section summarizes the opcodes of the instruction set for the TMS320C2xx DSP devices. This instruction set is a superset of the ’C1x and ’C2x instruction sets. The instructions are alphabetized by the mnemonic. The symbols in Table 15 are used in the instruction set summary table (Table 20). The Texas Instruments ’C2xx assembler accepts ’C1x and ’C2x instructions. For detailed information on instruction operation (that is, mnemonic syntax, words, cycles, and opcodes), see the TMS320C2xx User’s Guide (literature number SPRU127).

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Table 19. Opcode Symbols Two bits used by the conditional execution instructions to represent the conditions TC, NTC, and BIO. is ANDed with the conditions. If any bits are set, the conditions are met.

Table 20. TMS320C2xx Instruction Set Summary

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Table 20. TMS320C2xx Instruction Set Summary (Continued) † In ’C2xx devices, the BLDD instruction does not work with memory-mapped registers IMR, IFR, and GREG.

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implementations, and fully integrate and debug software and hardware modules. the Literature Response Center at 800/477-8924. availability, contact the nearest TI field sales office or authorized distributor. TI is a trademark of Texas Instruments Incorporated.

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Table 21. TMS320C2xx Development Support Tools WIN and Windows are trademarks of Microsoft Corporation. Code Composer is a trademark of Go DSP Inc. SPARC is a trademark of SPARC International, Inc. PC-DOS and OS/2 are trademarks of International Business Machines Corp. HP is a trademark of Hewlett-Packard Company. XDS510XL and XDS510WS are trademarks of Texas Instruments Incorporated.

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 39POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 device and development support tool nomenclature To designate the stages in the product development cycle, Texas Instruments assigns prefixes to the part numbers of all TMS320 devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, and TMS. Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). This development flow is defined below. Device Development Evolutionary Flow: TMX Experimental device that is not necessarily representative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification TMS Fully-qualified production device Support Tool Development Evolutionary Flow: TMDX Development support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” TMS devices and TMDS development support tools have been fully characterized, and the quality and reliability of the device have been fully demonstrated. Texas Instruments standard warranty applies. Predictions show that prototype devices (TMX or TMP) will have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate is still undefined. Only qualified production devices are to be used.

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reading the complete device name for any TMS320 family member. ‡ The TMS320C203 is a boot-loader device without the B option. Figure 3. TMS320C2xx Device Nomenclature and hardware and software applications. Processing Applications With the TMS320 Family (literature numbers SPRA012, SPRA016, and SPRA017). code and object code for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323.

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 41POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C203/LC203 TIMINGS † absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (’320C203 only)‡ † For the ’C209 absolute maximum ratings, recommended operating conditions, electrical characteristics, and other timing parameters (i.e., switching characteristics and timing requirements), see the ’C209 timings in the back of this document. ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions for TMS320C203 @ 5 V TEST CONDITIONS MIN NOM MAX UNIT VDD Supply voltage 5-V operation 4.5 5 5.5 V VSS Supply voltage 0 V CLKIN/X2 3 VDD + 0.3 VIH High-level input voltage RS , CLKR, CLKX, RX 2.3 V All other inputs 2.2 VDD + 0.3 CLKIN/X2 – 0.3 0.7 VIL Low-level input voltage RS , CLKR, CLKX, RX 0.8 V All other inputs – 0.3 0.8 IOH High-level output current – 300 µA IOL Low-level output current 2 mA TA Operating free-air TMS320C203PZ 0 70 °C TA g temperature TMS320C203PZA – 40 85 °C electrical characteristics over recommended ranges of supply voltage and operating free-air temperature for TMS320C203 @ 5 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage 5-V operation, IOH = MAX 2.4 V VOL Low-level output voltage 5-V operation, IOL = MAX 0.7 V II Input current VI = VDD or 0 V – 10 10 µA IOZ Output current, high-impedance state (off-state)VO = VDD or 0 V ± 5 µA IDD Supply current, core CPU 5-V operation, 80 MHz 76 mA C i Input capacitance 15 pF C o Output capacitance 15 pF

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998

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TMS320C203/LC203 TIMINGS † (CONTINUED) absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (’320LC203 only)‡ † For the ’C209 absolute maximum ratings, recommended operating conditions, electrical characteristics, and other timing parameters (i.e., switching characteristics and timing requirements), see the ’C209 timings in the back of this document. ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions for TMS320LC203 @ 3.3 V TEST CONDITIONS MIN NOM MAX UNIT VDD Supply voltage 3.3-V operation 3 3.3 3.6 V VSS Supply voltage 0 V CLKIN/X2§ 2.5 VDD + 0.3 VIH High-level input voltage RS , CLKR, CLKX, RX 2 V All other inputs 1.8 VDD + 0.3 VIL Low-level input voltage CLKIN/X2, RS, READY, HOLD /INT1, INT2, INT3, NMI – 0.3 0.4 VIL g All other inputs – 0.3 0.4 IOH High-level output current – 300 µA IOL Low-level output current 2 mA TA Operating free-air temperature TMS320LC203PZA – 40 85 °C § Values derived from characterization data and not tested electrical characteristics over recommended ranges of supply voltage and operating free-air temperature for TMS320LC203 @ 3.3 V (TTL levels) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage 3.3-V operation, IOH = MAX 2.4 V VOL Low-level output voltage 3.3-V operation, IOL = MAX 0.4 V II Input current VI = VDD or 0 V – 10 10 µA IOZ Output current, high-impedance state (off-state)VO = VDD or 0 V ± 5 µA IDD Supply current, core CPU 3.3-V operation, 40 MHz 22 mA C i Input capacitance 15 pF C o Output capacitance 15 pF Ii CLKIN input current Vi = VDD or 0 V – 350 350 µA

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Figure 6 shows the TTL-level inputs. Figure 6. TTL-Level Inputs

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 45POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PARAMETER MEASUREMENT INFORMATION FOR ’C203/’LC203 timing parameter symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: A Address or A[15:0] MS Memory strobe pins IS , DS, or PS CI CLKIN/X2 R READY CO CLKOUT1 RD Read cycle or RD D Data or D[15:0] RS RESET pins RS or RS FS FSX S STRB H HOLD (’203 only) SCK Serial-port clock HA HOLDA (’203 only) W Write cycle or WE IN INTN; BIO , INT1–INT3, NMI Lowercase subscripts and their meanings are: The following letters and symbols and their meanings are: a access time H High c cycle time (period) L Low d delay time V Valid dis disable time Z High impedance en enable time X Unknown, changing, or don’t care level f fall time h hold time r rise time su setup time t transition time v valid time w pulse duration (width) general notes on timing parameters for ’C203/’LC203 All output signals from the TMS320C2xx devices (including CLKOUT1) are derived from an internal clock such that all output transitions for a given half cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, refer to the appropriate cycle description section of this data sheet.

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specified at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned-LC circuit. Figure 7 shows an external crystal (fundamental frequency) connected to the on-chip oscillator. Figure 7. Internal Clock Option

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 47POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing at VDD = 5 V with the PLL circuit disabled, divide-by-two mode for TMS320C203† PARAMETER TEST CONDITIONS MIN MAX UNIT fx Input clock frequency T A = – 40°C to 85°C, 5 V 0† 57.14 MHz 40.96 † This device is implemented in static logic and therefore can operate with tc(CI) approaching ∞ . The device is characterized at frequencies approaching 0 Hz, but is tested at fx = 6.7 MHz to meet device test time requirements. switching characteristics over recommended operating conditions for TMS320C203 (see Figure 8) PARAMETER ’320C203-40 ’320C203-57 ’320C203-80 UNITPARAMETER MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT tc(CO) Cycle time, CLKOUT1 48.8 2tc(CI) ‡ 35 2tc(CI) ‡ 25 2tc(CI) ‡ ns td(CIH-CO) Delay time, CLKIN high to CLKOUT1 high/low 1 11 20 1 11 20 1 9 18 ns tf(CO) Fall time, CLKOUT1 5§ 5 4 ns tr(CO) Rise time, CLKOUT1 5§ 5 4 ns tw(COL) Pulse duration, CLKOUT1 low H – 3 H H + 1 H – 3 H H + 1 H – 3 H H + 1 ns tw(COH) Pulse duration, CLKOUT1 high H – 1 H H + 3 H – 1 H H + 3 H – 1 H H + 3 ns ‡ This device is implemented in static logic and therefore can operate with tc(CI) approaching ∞ . The device is characterized at frequencies approaching 0 Hz, but is tested at tc(CI) = 300 ns to meet device test time requirements. § Values derived from characterization data and not tested timing requirements over recommended operating conditions for TMS320C203 (see Figure 8) ’320C203-40 ’320C203-57 ’320C203-80 UNIT MIN MAX MIN MAX MIN MAX UNIT tc(CI) Cycle time, CLKIN 25 ¶ 17.5 ¶ 12.5 ¶ ns tf(CI) Fall time, CLKIN§ 5 5 4 ns tr(CI) Rise time, CLKIN§ 5 5 4 ns tw(CIL) Pulse duration, CLKIN low 11 ¶ 8 ¶ 5 ¶ ns tw(CIH) Pulse duration, CLKIN high 11 ¶ 8 ¶ 5 ¶ ns § Values derived from characterization data and not tested ¶ This device is implemented in static logic and therefore can operate with tc(CI) approaching ∞ . The device is characterized at frequencies approaching 0 Hz, but is tested at a minimum tc(CI) = 150 ns to meet device test time requirements.

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approaching 0 Hz, but is tested at fx = 6.7 MHz to meet device test time requirements. approaching 0 Hz, but is tested at tc(CI) = 300 ns to meet device test time requirements. Figure 8. CLKIN-to-CLKOUT1 Timing Without PLL (using ÷2 clock option) for TMS320C203/LC203

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 49POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing @ VDD = 5 V with the PLL circuit enabled, multiply-by-two mode for TMS320C203 PARAMETER TEST CONDITIONS MIN MAX UNIT fx Input clock frequency TA = – 40°C to 85°C, 5 V 5 20 MHz switching characteristics over recommended operating conditions for TMS320C203 @ 5 V (see Figure 9) PARAMETER ’320C203-40 ’320C203-57 ’320C203-80 UNITPARAMETER MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT tc(CO) Cycle time, CLKOUT1 50 100 35 75 25 55 ns td(CIH-CO) Delay time, CLKIN high to CLKOUT1 high/low 3 8 18 3 8 18 1 8 16 ns tf(CO) Fall time, CLKOUT1† 5 5 4 ns tr(CO) Rise time, CLKOUT1† 5 5 4 ns tw(COL) Pulse duration, CLKOUT1 low H – 3 H H + 1 H – 3 H H + 1 H – 3 H H + 1 ns tw(COH) Pulse duration, CLKOUT1 high H – 1 H H + 3 H – 1 H H + 3 H – 1 H H + 3 ns tp Transition time, PLL synchronized after CLKIN supplied 2500 2500 2500 cycles † Values derived from characterization data and not tested timing requirements over recommended operating conditions for TMS320C203 @ 5 V (see Figure 9) ’320C203-40 ’320C203-57 ’320C203-80 UNIT MIN MAX MIN MAX MIN MAX UNIT t (CI) Cycle time, CLKIN multiply-by-one 50 100 35 75 25 75 ns tc(CI) Cycle time, CLKIN multiply-by-two 100 200 70 200 50 150 ns tf(CI) Fall time, CLKIN† 4 4 4 ns tr(CI) Rise time, CLKIN† 4 4 4 ns tw(CIL) Pulse duration, CLKIN low 16 95 14 95 11 95 ns tw(CIH) Pulse duration, CLKIN high 16 95 14 95 11 95 ns † Values derived from characterization data and not tested

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Figure 9. CLKIN-to-CLKOUT1 Timing With PLL (using ×2 clock option) for TMS320C203/LC203

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 51POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MEMORY AND PERIPHERAL INTERFACE TIMING FOR ’C203/’LC203 memory and parallel I/O interface read timing for TMS320C203 @ 5 V A15–A0, PS, DS, IS, R/W, and BR timings are all included in the timings referenced to A15–A0 except when in transition between read and write operations, where PS, DS, and IS pulse high [see tw(NSN) ]. switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 10) PARAMETER ALTERNATE SYMBOLS ’320C203-40 ’320C203-57 ’320C203-80 UNITSYMBOLS MIN MAX MIN MAX tsu(A-RD) Setup time, address valid before RD low tsu(A)RD H – 5 H – 5 ns th(RD-A) Hold time, address valid after RD high th(A)RD – 6 – 6 ns td(COL-A) Delay time, CLKOUT1 low to read address valid 5 4 ns th(COL-A)RD Hold time, read address valid after CLKOUT1 low th(A)COLRD – 4 – 3 ns td(CO-RD) Delay time, CLKOUT1 high/low to RD low/high – 1 6 – 1 5 ns td(COL-S) Delay time, CLKOUT1 low to STRB low/high† 0 9 0 9 ns tw(RDL) Pulse duration, RD low (no wait states) H – 3 H + 2 H – 3 H + 2 ns tw(RDH) Pulse duration, RD high H – 4 H + 3 H – 3 H + 3 ns † Values derived from characterization data and not tested timing requirements over recommended operating conditions [H = 0.5tc(CO)] (see Figure 10) ALTERNATE SYMBOLS ’320C203-40 ’320C203-57 ’320C203-80 UNITSYMBOLS MIN MAX MIN MAX ta(A) Access time, from address valid to read data 2H – 15 2H – 13 ns tsu(D-RD) Setup time, read data before RD high tsu(D)RD 13 13 ns th(RD-D) Hold time, read data after RD high th(D)RD – 2 – 2 ns th(AIV-D) Hold time, read data after address invalid th(D)A 0 0 ns tsu(D-COL)RD Setup time, read data before CLKOUT1 low tsu(DCOL)RD 9 10 ns th(COL-D)RD Hold time, read data after CLKOUT1 low th(DCOL)RD – 1 – 1 ns ta(RD) Access time, from RD low to read data H – 12 H – 13 ns ta(S) Access time, from STRB low to read data† 8 ns † Values derived from characterization data and not tested

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998

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memory and parallel I/O interface read timing for TMS320LC203 @ 3.3 V A15–A0, PS, DS, IS, R/W, and BR timings are all included in the timings referenced to A15–A0 except when in transition between read and write operations, where PS, DS, and IS pulse high [see tw(NSN) ]. switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 10) PARAMETER ALTERNATE ’320LC203-40 UNITPARAMETER SYMBOLS MIN MAX UNIT tsu(A-RD) Setup time, address valid before RD low tsu(A)RD H – 7 ns th(RD-A) Hold time, address valid after RD high th(A)RD – 8 ns td(COL-A) Delay time, CLKOUT1 low to read address valid 9 ns th(COL-A)RD Hold time, read address valid after CLKOUT1 low th(A)COLRD – 4 ns td(CO-RD) Delay time, CLKOUT1 high/low to RD low/high – 1 7 ns td(COL-S) Delay time, CLKOUT1 low to STRB low/high† 3 16 ns tw(RDL) Pulse duration, RD low (no wait states) H – 3 H + 2 ns tw(RDH) Pulse duration, RD high H – 4 H + 2 ns † Values derived from characterization data and not tested timing requirements over recommended operating conditions [H = 0.5tc(CO)] (see Figure 10) ALTERNATE ’320LC203-40 UNITSYMBOLS MIN MAX UNIT ta(A) Access time, from address valid to read data 2H – 23 ns tsu(D-RD) Setup time, read data before RD high tsu(D)RD 22 ns th(RD-D) Hold time, read data after RD high th(D)RD – 2 ns th(AIV-D) Hold time, read data after address invalid th(D)A 0 ns tsu(D-COL)RD Setup time, read data before CLKOUT1 low tsu(DCOL)RD 17 ns th(COL-D)RD Hold time, read data after CLKOUT1 low th(DCOL)RD – 1 ns ta(RD) Access time, from RD low to read data H – 20 ns

Figure 10. Memory Interface Read Timing for TMS320C203/LC203

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998

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memory and parallel I/O interface write timing for TMS320C203 @ 5 V A15–A0, PS, DS, IS, R/W, and BR timings are all included in the timings referenced to A15–A0 except when in transition between read and write operations, where PS, DS, and IS pulse high [see tw(NSN) ]. switching characteristics over recommended operating conditions @ 5 V [H = 0.5tc(CO)] (see Figure 11) PARAMETER ALTERNATE SYMBOLS ’320C203-40 ’320C203-57 ’320C203-80 UNITSYMBOLS MIN MAX MIN MAX tsu(A-W) Setup time, address valid before WE low tsu(A)W H – 7 H – 6 ns th(W-A) Hold time, address valid after WE high th(A)W H – 10 H – 8 ns tsu(A-COL) Setup time, write address valid before CLKOUT1 lowtsu(A)CO H – 9 H – 8 ns th(COL-A)W Hold time, write address valid after CLKOUT1 lowth(A)COLW H – 3 H – 5 ns tw(MS) Pulse duration, IS, DS, PS inactive high† tw(NSN) H – 9 H – 8 ns tw(WL) Pulse duration, WE low (no wait states) 2H – 3 2H + 2 2H – 4 2H + 2 ns tw(WH) Pulse duration, WE high 2H – 2 2H – 2 ns td(COL-W) Delay time, CLKOUT1 low to WE low/high – 1 6 – 1 4 ns td(RD-W) Delay time, RD high to WE low td(RDW) 2H – 8 2H – 7 ns td(W-RD) Delay time, WE high to RD low td(WRD) 3H – 8 3H – 8 ns tsu(D-W) Setup time, write data valid before WE high tsu(D)W 2H – 15 2H † 2H – 14 2H † ns th(W-D) Hold time, write data valid after WE high th(D)W H – 4 H + 7† H – 3 H + 7† ns tsu(D-COL)W Setup time, write data valid before CLKOUT1 lowtsu(DCOL)W 2H – 20 2H † 2H – 20 2H † ns th(COL-D)W Hold time, write data valid after CLKOUT1 low th(DCOL)W H – 4 H + 11† H – 5 H + 11† ns ten(D-W) Enable time, data bus driven from WE† ten(D)W – 4 – 3 ns † Values derived from characterization data and not tested

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 55POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory and parallel I/O interface write timing for TMS320LC203 @ 3.3 V A15–A0, PS, DS, IS, R/W, and BR timings are all included in the timings referenced to A15–A0 except when in transition between read and write operations, where PS, DS, and IS pulse high [see tw(NSN) ]. switching characteristics over recommended operating conditions @ 3.3 V [H = 0.5tc(CO)] (see Figure 11) PARAMETER ALTERNATE ’320LC203-40 UNITPARAMETER SYMBOLS MIN MAX UNIT tsu(A-W) Setup time, address valid before WE low tsu(A)W H – 5 ns th(W-A) Hold time, address valid after WE high th(A)W H – 10 ns tsu(A-COL) Setup time, write address valid before CLKOUT1 low tsu(A)CO H – 9 ns th(COL-A)W Hold time, write address valid after CLKOUT1 low th(A)COLW H – 5 ns tw(MS) Pulse duration, IS, DS, PS inactive high† tw(NSN) H – 9 ns tw(WL) Pulse duration, WE low (no wait states) 2H – 3 2H + 1 ns tw(WH) Pulse duration, WE high 2H – 2 ns td(COL-W) Delay time, CLKOUT1 low to WE low/high – 1 6 ns td(RD-W) Delay time, RD high to WE low td(RDW) 2H – 8 ns td(W-RD) Delay time, WE high to RD low td(WRD) 3H – 8 ns tsu(D-W) Setup time, write data valid before WE high tsu(D)W 2H – 15 2H † ns th(W-D) Hold time, write data valid after WE high th(D)W H – 4 H + 7† ns tsu(D-COL)W Setup time, write data valid before CLKOUT1 low tsu(DCOL)W 2H – 20 2H † ns th(COL-D)W Hold time, write data valid after CLKOUT1 low th(DCOL)W H – 4 H + 11† ns ten(D-W) Enable time, data bus driven from WE† ten(D)W – 4 ns † Values derived from characterization data and not tested

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Figure 11. Memory Interface Write Timing for TMS320C203/LC203

Figure 12. READY Timing for TMS320C203/LC203

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‡ This parameter assumes the CLKOUT1 to be stable before RS goes active. Figure 13. XF and TOUT Timing for TMS320C203/LC203

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 59POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 XF, TOUT, RS, INT1 – INT3, NMI, and BIO timing (continued) switching characteristics over recommended operating conditions for TMS320LC203 @ 3.3 V (see Figure 13) PARAMETER ALTERNATE ’320LC203-40 UNITPARAMETER SYMBOL MIN MAX UNIT td(COH-XF) Delay time, CLKOUT1 high to XF valid td(XF) 0† 12 ns td(COH-TOUT) Delay time, CLKOUT1 high to TOUT high/low td(TOUT) 0† 15 ns tw(TOUT) Pulse duration, TOUT high 2H – 12 ns † Values derived from characterization data and not tested timing requirements over recommended operating conditions for TMS320LC203 @ 3.3 V [H = 0.5tc(CO)] (see Figure 14 and Figure 15) ALTERNATE ’320LC203-40 UNITSYMBOL MIN MAX UNIT tsu(RS-CIL) Setup time, RS before CLKIN low tsu(RS)CIL 11 ns tsu(RS-COL) Setup time, RS before CLKOUT1 low tsu(RS)COL 15 ns tw(RSL) Pulse duration, RS low‡ 12H ns td(RS-RST) Delay time, RS high to reset-vector fetch td(EX) 34H ns tsu(IN-COLS) Setup time, INTN before CLKOUT1 low (synchronous) tsu(IN)COL 10 ns th(COLS-IN) Hold time, INTN after CLKOUT1 low (synchronous) th(IN)COL 1 ns tw(IN) Pulse duration, INTN low 2H + 18 ns td(IN-INT) Delay time, INTN low to interrupt-vector fetch td(IN) 12H ns ‡ This parameter assumes the CLKOUT1 to be stable before RS goes active.

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Figure 14. Reset Timing for TMS320C203/LC203 Figure 15. Interrupts and BIO Timing for TMS320C203/LC203

number SPRU127) for functional description of HOLD logic. ‡ This parameter includes all memory control lines. Figure 16. External DMA Timing for ’C203/’LC203

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Figure 17. Serial-Port Receive Timing for ’C203/’LC203

Figure 18. Serial-Port Transmit Timing of External Clocks and External Frames for ’C203/’LC203

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Figure 19. Serial-Port Transmit Timing of Internal Clocks and Internal Frames for ’C203/’LC203

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 65POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over case temperature range (unless otherwise noted) (’320C209 only)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions for TMS320C209 @ 5 V TEST CONDITIONS MIN NOM MAX UNIT VDD Supply voltage 5-V operation 4.5 5 5.5 V VSS Supply voltage 0 V CLKIN/X2 3 VDD +03 VIH High-level input voltage CLKIN/X2 3 VDD + 0.3 VVIH High-level in ut voltage Inputs 2.0 VDD + 0.3 V CLKIN/X2 – 0.3 0.7 VIL Low-level input voltage RS 0.8 V All other inputs – 0.3 0.8 IOH High-level output current – 300 µA IOL Low-level output current 2 mA TC Case temperature 0 85 °C electrical characteristics over recommended ranges of supply voltage and operating case temperature for TMS320C209 @ 5 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage 5-V operation, IOH = MAX 2.4 V VOL Low-level output voltage 5-V operation, IOL = MAX 0.6 V II Input current VI = VDD or 0 V – 10 10 µA IOZ Output current, high-impedance state (off-state)VO = VDD or 0 V ± 5 µA IDD Supply current, core CPU 5-V operation, 57 MHz 76 mA C i Input capacitance 15 pF C o Output capacitance 15 pF

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Figure 20. Test Load Circuit driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V. Figure 5 shows the TTL-level outputs. Figure 21. TTL-Level Outputs

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998

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PARAMETER MEASUREMENT INFORMATION FOR ’C209 timing parameter symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: A Address or A[15:0] R READY CI CLKIN/X2 RD Read cycle or RD CO CLKOUT1 RS RESET pins RS or RS D Data or D[15:0] S STRB FS FSX SCK Serial-port clock IN INTN; BIO , INT1–INT3, NMI W Write cycle or WE MS Memory strobe pins IS , DS, or PS Lowercase subscripts and their meanings are: The following letters and symbols and their meanings are: a access time H High c cycle time (period) L Low d delay time V Valid dis disable time Z High impedance en enable time X Unknown, changing, or don’t care level f fall time h hold time r rise time su setup time t transition time v valid time w pulse duration (width) general notes on timing parameters for ’C209 All output signals from the TMS320C2xx devices (including CLKOUT1) are derived from an internal clock such that all output transitions for a given half cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, refer to the appropriate cycle description section of this data sheet.

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approaching 0 Hz, but is tested at fx = 6.7 MHz to meet device test time requirements. approaching 0 Hz, but is tested at tc(CI) = 300 ns to meet device test time requirements. approaching 0 Hz, but is tested at a minimum tc(CI) = 150 ns to meet device test time requirements. Figure 24. CLKIN-to-CLKOUT1 Timing Without PLL (using ÷2 clock option) for TMS320C209

Figure 25. CLKIN-to-CLKOUT1 Timing With PLL (using ×2 clock option) for TMS320C209

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998

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MEMORY AND PERIPHERAL INTERFACE TIMING memory and parallel I/O interface read timing for TMS320C209 @ 5 V A15–A0, PS, DS, IS, R/W, and BR timings are all included in the timings referenced to A15–A0 except when in transition between read and write operations, where PS, DS, and IS pulse high [see tw(NSN) ]. switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 26) PARAMETER ALTERNATE ’320C209-57 UNITPARAMETER SYMBOLS MIN MAX UNIT tsu(A-RD) Setup time, address valid before RD low tsu(A)RD H – 5 ns th(RD-A) Hold time, address valid after RD high th(A)RD – 6 ns td(COL-A) Delay time, CLKOUT1 low to read address valid 8 ns th(COL-A)RD Hold time, read address valid after CLKOUT1 low th(A)COLRD – 2 ns td(CO-RD) Delay time, CLKOUT1 high/low to RD low/high 0 6 ns td(COL-S) Delay time, CLKOUT1 low to STRB low/high† 0 5 ns tw(RDL) Pulse duration, RD low (no wait states) H – 3 H + 2 ns tw(RDH) Pulse duration, RD high H – 4 H + 2 ns td(RD-W) Delay time, RD high to WE low td(RDW) 2H – 8 ns † Values derived from characterization data and not tested timing requirements over recommended operating conditions [H = 0.5tc(CO)] (see Figure 26) ALTERNATE ’320C209-57 UNITSYMBOLS MIN MAX UNIT ta(A) Access time, from address valid to read data 2H – 15 ns tsu(D-RD) Setup time, read data before RD high tsu(D)RD 13 ns th(RD-D) Hold time, read data after RD high th(D)RD – 2 ns th(AIV-D) Hold time, read data after address invalid th(D)A 0 ns tsu(D-COL)RD Setup time, read data before CLKOUT1 low tsu(DCOL)RD 9 ns th(COL-D)RD Hold time, read data after CLKOUT1 low th(DCOL)RD – 1 ns ta(RD) Access time, from RD low to read data H – 12 ns

Figure 26. Memory Interface Read Timing for TMS320C209

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998

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memory and parallel I/O interface write timing for TMS320C209 @ 5 V A15–A0, PS, DS, IS, R/W, and BR timings are all included in the timings referenced to A15–A0 except when in transition between read and write operations, where PS, DS, and IS pulse high [see tw(NSN) ]. switching characteristics over recommended operating conditions @ 5 V [H = 0.5tc(CO)] (see Figure 27) PARAMETER ALTERNATE ’320C209-57 UNITPARAMETER SYMBOLS MIN MAX UNIT tsu(A-W) Setup time, address valid before WE low tsu(A)W H – 7 ns th(W-A) Hold time, address valid after WE high th(A)W H – 10 ns tsu(A-COL) Setup time, write address valid before CLKOUT1 low tsu(A)CO H – 9 ns th(COL-A)W Hold time, write address valid after CLKOUT1 low th(A)COLW H – 3 ns tw(MS) Pulse duration, IS, DS, PS inactive high† tw(NSN) H – 9 ns tw(WL) Pulse duration, WE low (no wait states) 2H – 2 2H + 2 ns tw(WH) Pulse duration, WE high 2H – 2 ns td(COL-W) Delay time, CLKOUT1 low to WE low/high 0 6 ns td(RD-W) Delay time, RD high to WE low td(RDW) 2H – 8 ns td(W-RD) Delay time, WE high to RD low td(WRD) 3H – 8 ns tsu(D-W) Setup time, write data valid before WE high tsu(D)W 2H – 15 2H † ns th(W-D) Hold time, write data valid after WE high th(D)W H – 4 H + 7† ns tsu(D-COL)W Setup time, write data valid before CLKOUT1 low tsu(DCOL)W 2H – 20 2H † ns th(COL-D)W Hold time, write data valid after CLKOUT1 low th(DCOL)W H – 4 H + 11† ns ten(D-W) Enable time, data bus driven from WE† ten(D)W – 4 ns † Values derived from characterization data and not tested

Figure 27. Memory Interface Write Timing for TMS320C209

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Figure 28. READY Timing for TMS320C209

Figure 29. XF and TOUT Timing for TMS320C209

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† This parameter assumes the CLKOUT1 to be stable before RS goes active. Figure 30. Reset Timing for TMS320C209 Figure 31. Interrupts and BIO Timing for TMS320C209

NOTE A: IACK are not affected by wait states. Figure 32. IACK Timing for TMS320C209

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998

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PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 4040135/B10/94 0,17 0,27 0,13 NOM 0,25 0,45 0,75 0,05 MIN Seating Plane Gage Plane 4160 SQ SQ 13,80 14,20 12,20 9,50 TYP 11,80 1,45 1,35 1,60 MAX 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136

TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 81POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 4040149/B 10/94 26 0,13 NOM Gage Plane 0,25 0,45 0,75 0,05 MIN 0,27 12,00 TYP 0,17 100 SQ SQ15,80 16,20 13,80 1,35 1,45 1,60 MAX 14,20 0°–7° Seating Plane 0,08 0,50 M0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TMS320C203PZ ACTIVE LQFP PZ 100 90 None CU NIPDAU Level-1-220C-UNLIM TMS320C203PZ57 ACTIVE LQFP PZ 100 90 None CU NIPDAU Level-1-220C-UNLIM TMS320C203PZ80 ACTIVE LQFP PZ 100 90 None CU NIPDAU Level-1-220C-UNLIM TMS320C203PZA ACTIVE LQFP PZ 100 90 None CU NIPDAU Level-1-220C-UNLIM TMS320C203PZA57 ACTIVE LQFP PZ 100 90 None CU NIPDAU Level-1-220C-UNLIM TMS320C209PN57 ACTIVE LQFP PN 80 49 None CU NIPDAU Level-1-220C-UNLIM TMS320LC203PZ ACTIVE LQFP PZ 100 90 None CU NIPDAU Level-1-220C-UNLIM TMS320LC203PZA ACTIVE LQFP PZ 100 90 None CU NIPDAU Level-1-220C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 17-Dec-2004 Addendum-Page 1

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