TM2SR72EPN TI1 | Alldatasheet
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/C0084/C0077/C0050/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0084/C0077/C0052/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS698A − JUNE 1997 − REVISED FEBRUARY 1998 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Organization − TM2SR72EPN . . . 2097152 x 72 Bits − TM4SR72EPN . . . 4194304 x 72 Bits /C0068Single 3.3-V Power Supply (±10% Tolerance) /C0068Designed for 66-MHz 4-Clock Systems /C0068JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket /C0068TM2SR72EPN — Uses Nine 16M-Bit Synchronous Dynamic RAMs (SDRAMs) (2M × 8-Bit) in Plastic Thin Small-Outline Packages (TSOPs) /C0068TM4SR72EPN — Uses 18 16M-Bit SDRAMs (2M × 8-Bit) in Plastic TSOPs /C0068Performance Ranges: /C0068High-Speed, Low-Noise Low-Voltage TTL (LVTTL) Interface /C0068Byte-Read/Write Capability /C0068Read Latencies 2 and 3 Supported /C0068Support Burst-Interleave and Burst-Interrupt Operations /C0068Burst Length Programmable to 1, 2, 4, and 8 /C0068Two Banks for On-Chip Interleaving (Gapless Access) /C0068Ambient Temperature Range 0°C to 70°C /C0068Gold-Plated Contacts /C0068Pipeline Architecture /C0068Serial Presence Detect (SPD) Using EEPROM SYNCHRONOUS CLOCK CYCLE TIME ACCESS TIME (CLOCK TO OUTPUT) REFRESH INTERVAL tCK3 (CL = 3)† tCK2 (CL = 2) tAC3 (CL = 3) tAC2 (CL = 2) ’xSR72EPN-10 10 ns 15 ns 7.5 ns 7 ns 64 ms † CL = CAS latency
description
The TM2SR72EPN is a 16M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of nine TMS626812ADGE, 2097152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812A data sheet (literature number SMOS691). The TM4SR72EPN is a 32M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS626812ADGE, 2097152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling capacitors. See the TMS626812A data sheet (literature number SMOS691). operation The TM2SR72EPN operates as nine TMS626812ADGE devices that are connected as shown in the TM2SR72EPN functional block diagram. The TM4SR72EPN operates as eighteen TMS626812ADGE devices connected as shown in the TM4SR72EPN functional block diagram. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0084/C0077/C0050/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0084/C0077/C0052/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS698A − JUNE 1997 − REVISED FEBRUARY 1998
2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DUAL-IN-LINE MEMORY MODULE (TOP VIEW) TM4SR72EPN (SIDE VIEW) PIN NOMENCLATURE A[0:10] Row-Address Inputs A[0:8] Column-Address Inputs A11/BA0 Bank-Select Zero CAS Column-Address Strobe CB[0:7] Data In/Data Out CKE[0:1] Clock Enable CK[0:3] System Clock DQ[0:63] Data In/Data Out DQMB[0:7] Data-In/Data-Out Mask Enable NC No Connect RAS Row-Address Strobe S[0:3] Chip-Select SA[0:2] Serial Presence Detect (SPD) Device Address Input SCL SPD Clock SDA SPD Address/Data VDD 3.3-V Supply VSS Ground WE Write Enable TM2SR72EPN (SIDE VIEW)
/C0084/C0077/C0050/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0084/C0077/C0052/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS698A − JUNE 1997 − REVISED FEBRUARY 1998 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Pin Assignments PIN PIN PIN PIN NO. NAME NO. NAME NO. NAME NO. NAME
1 VSS 43 VSS 85 VSS 127 VSS
2 DQ0 44 NC 86 DQ32 128 CKE0
3 DQ1 45 S2 87 DQ33 129 S3
4 DQ2 46 DQMB2 88 DQ34 130 DQMB6
5 DQ3 47 DQMB3 89 DQ35 131 DQMB7
6 VDD 48 NC 90 VDD 132 NC
7 DQ4 49 VDD 91 DQ36 133 VDD
8 DQ5 50 NC 92 DQ37 134 NC
9 DQ6 51 NC 93 DQ38 135 NC
10 DQ7 52 CB2 94 DQ39 136 CB6
11 DQ8 53 CB3 95 DQ40 137 CB7
12 VSS 54 VSS 96 VSS 138 VSS
13 DQ9 55 DQ16 97 DQ41 139 DQ48
14 DQ10 56 DQ17 98 DQ42 140 DQ49
15 DQ11 57 DQ18 99 DQ43 141 DQ50
16 DQ12 58 DQ19 100 DQ44 142 DQ51
17 DQ13 59 VDD 101 DQ45 143 VDD
18 VDD 60 DQ20 102 VDD 144 DQ52
19 DQ14 61 NC 103 DQ46 145 NC
20 DQ15 62 NC 104 DQ47 146 NC
21 CB0 63 CKE1 105 CB4 147 NC
22 CB1 64 VSS 106 CB5 148 VSS
23 VSS 65 DQ21 107 VSS 149 DQ53
24 NC 66 DQ22 108 NC 150 DQ54
25 NC 67 DQ23 109 NC 151 DQ55
26 VDD 68 VSS 110 VDD 152 VSS
27 WE 69 DQ24 111 CAS 153 DQ56
28 DQMB0 70 DQ25 112 DQMB4 154 DQ57
29 DQMB1 71 DQ26 113 DQMB5 155 DQ58
30 S0 72 DQ27 114 S1 156 DQ59
31 NC 73 VDD 115 RAS 157 VDD
32 VSS 74 DQ28 116 VSS 158 DQ60
33 A0 75 DQ29 117 A1 159 DQ61
34 A2 76 DQ30 118 A3 160 DQ62
35 A4 77 DQ31 119 A5 161 DQ63
36 A6 78 VSS 120 A7 162 VSS
37 A8 79 CK2 121 A9 163 CK3
38 A10 80 NC 122 A11/BA0 164 NC
39 NC 81 NC 123 NC 165 SA0
40 VDD 82 SDA 124 VDD 166 SA1
41 VDD 83 SCL 125 CK1 167 SA2
42 CK0 84 VDD 126 NC 168 VDD
/C0084/C0077/C0050/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0084/C0077/C0052/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS698A − JUNE 1997 − REVISED FEBRUARY 1998
4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
dual-in-line memory module and components The dual-in-line memory module and components include: /C0068PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage /C0068Bypass capacitors: Multilayer ceramic /C0068Contact area: Nickel plate and gold plate over copper functional block diagram for the TM2SR72EPN
8 DQ[0:7]8
DQ[0:7] DQMB4 DQ[32:39] DQM DQ[0:7] DQM RAS RAS : SDRAM U[0:8] CK0 U0, U4 U1, U5, U8 CK2 C SPD EEPROM SA0 SA1 SA2 A0 A1 A2 SCL SDA DQ[8:15] DQMB5 DQ[40:47] DQM DQ[0:7] DQM R = 10 Ω R B = 5 Ω R C = 10Ω C = 10 pF DQ[16:23] DQMB6 DQ[48:55] DQM DQ[0:7] DQM DQ[24:31] DQMB7 DQ[56:63] DQM DQ[0:7] DQM CAS CAS : SDRAM U[0:8] WE WE : SDRAM U[0:8] CKE0 CKE: SDRAM U[0:8] A[0:11] A[0:11]: SDRAM U[0:8] R C R B R B VDD VSS U[0:8] U[0:8] CK1 U2, U6 U3, U7 CK3 C R C R C R C CS R DQMB1 CB[0:7] DQM DQ[0:7] Two 0.33 µF per SDRAM LEGEND: CS = Chip Select SPD = Serial Presence Detect
/C0084/C0077/C0050/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0084/C0077/C0052/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS698A − JUNE 1997 − REVISED FEBRUARY 1998 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block diagram for the TM4SR72EPN DQ[0:7] DQ[0:7] DQ[0:7] CS CS R DQMB0 DQMB4 DQ[32:39] DQM DQM RAS RAS : U[0:8], UB[0:8] CK0 CK: U0, U4 CK: U1, U5, U8 SPD EEPROM SA0 SA1 SA2 A0 A1 A2 SCL SDA DQ[0:7] CS CS RR DQMB1 DQ[8:15] DQMB5 DQ[40:47] DQM DQ[0:7] DQM R = 10 Ω R C = 10Ω R B = 5Ω DQ[0:7] CS CS RR DQMB2 DQ[16:23] DQMB6 DQ[48:55] DQM DQ[0:7] DQM DQ[0:7] CS CS RR DQMB3 DQ[24:31] DQMB7 DQ[56:63] DQM DQ[0:7] DQM CAS CAS : U[0:8], UB[0:8] CKE0 CKE: U[0:8] WE WE: U[0:8], UB[0:8] R B R B VDD VSS U[0:8], UB[0:8] U[0:8], UB[0:8] CK1 CK: UB0, UB4 CK: UB1, UB5, UB8 R B R B DQ[0:7] CS UB0 DQM CS UB1 DQM DQ[0:7] DQ[0:7] CS UB2 DQM CS UB3 DQM DQ[0:7] DQ[0:7] CS UB4 DQM CS UB5 DQM DQ[0:7] DQ[0:7] CS UB6 DQM CS UB7 DQM DQ[0:7] CKE1 CKE: UB[0:8]
10 K Ω
CK: U2, U6 CK: U3, U7 R C R C CK3 CK: UB2, UB6 CK: UB3, UB7 R C R C CS R DQMB1 CB[0:7] DQM DQ[0:7] CS UB8 DQM DQ[0:7] Two 0.33 µF per SDRAM
/C0084/C0077/C0050/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0084/C0077/C0052/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS698A − JUNE 1997 − REVISED FEBRUARY 1998
6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
absolute maximum ratings over ambient temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VDD Supply voltage 3 3.3 3.6 V VSS Supply voltage 0 V VIH High-level input voltage 2 VDD + 0.3 V VIH-SPD High-level input voltage for SPD device 2 5.5 V VIL Low-level input voltage ‡ −0.3 0.8 V TA Ambient temperature 0 70 °C ‡ VIL MIN = −1.5 V ac (pulse width /C0118 5 ns) capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)§ PARAMETERS TMxSR72EPN UNITPARAMETERS MIN MAX UNIT C i(CK) Input capacitance, CK input 4 pF C i(AC) Input capacitance, address and control inputs: A0−A11, RAS, CAS, WE 5 pF C i(CKE) Input capacitance, CKE input 5 pF C o Output capacitance 6.5 pF C i(DQMBx ) Input capacitance, DQMBx input 5 pF C i(Sx) Input capacitance, Sx input 5 pF C i/o(SDA) Input/output capacitor, SDA input 9 pF C i(SPD) Input capacitor, SA0, SA1, SA2, SCL inputs 7 pF § Specifications in this table represent a single SDRAM device. NOTE 2: V DD = 3.3 V ± 0.3 V. Bias on pins under test is 0 V.
/C0084/C0077/C0050/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0084/C0077/C0052/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS698A − JUNE 1997 − REVISED FEBRUARY 1998 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3)† PARAMETER TEST CONDITIONS ’xSR72EPN-10 UNITPARAMETER TEST CONDITIONS MIN MAX UNIT VOH High-level output voltage IOH = − 2 mA 2.4 V VOL Low-level output voltage IOL = 2 mA 0.4 V II Input current (leakage) 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD /C003410 µA IO Output current (leakage) 0 V < VO < VDD +0.3 V, Output disabled /C003410 µA ICC1 Operating current Burst length = 1, tRC ≥ tRC MIN CAS latency = 2 95 mA ICC1 Operating current tRC ≥ tRC MIN IOH /IOL = 0 mA, one bank activated (see Note 4) CAS latency = 3 105 mA ICC2P CKE ≤ VIL MAX, tCK = 15 ns (see Note 5) 2 mA ICC2PS Precharge standby current in power-down mode CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 6) 2 mA ICC2N Precharge standby current in non-power-down CKE ≥ VIH MIN, tCK = 15 ns (see Note 5) 25 mA ICC2NS Precharge standby current in non-power-down mode CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞ (see Note 6) 2 mA ICC3P CKE ≤ VIL MAX, tCK = 15 ns (see Note 5) 3 mA ICC3PS Active standby current in power-down modeCKE and CK ≤ VIL MAX, tCK = ∞ (see Note 6) 3 mA ICC3N CKE ≥ VIH MIN, tCK = 15 ns (see Note 5) 30 mA ICC3NS Active standby current in non-power-down modeCKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞ (see Note 6) 10 mA ICC4 Burst current Page burst, IOH /IOL = 0 mA All banks activated, CAS latency = 2 100 mA ICC4 Burst current All banks activated, nCCD = one cycle (see Note 7) CAS latency = 3 130 mA ICC5 Auto-refresh current tRC ≤ tRC MIN CAS latency = 2 85 mA ICC5 Auto-refresh current t RC ≤ tRC MIN CAS latency = 3 95 mA ICC6 Self-refresh current CKE ≤ VIL MAX 2 mA † Specifications in this table represent a single SDRAM device. NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Control, DQ, and address inputs change state only twice during tRC . 5. Control, DQ, and address inputs change state only once every 30 ns. 6. Control, DQ, and address inputs do not change (stable). 7. Control, DQ, and address inputs change only once every cycle.
/C0084/C0077/C0050/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0084/C0077/C0052/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS698A − JUNE 1997 − REVISED FEBRUARY 1998
8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ac timing requirements†‡ ’xSR72EPN-10 UNITMIN MAX UNIT tCK2 Cycle time, CLK, CAS latency = 2 15 ns tCK3 Cycle time, CLK, CAS latency = 3 10 ns tCH Pulse duration, CLK high 3 ns tCL Pulse duration, CLK low 3 ns tAC2 Access time, CLK high to data out, CAS latency = 2 (see Note 8) 7 ns tAC3 Access time, CLK high to data out, CAS latency = 3 (see Note 8) 7.5 ns tOH Hold time, CLK high to data out 3 ns tLZ Delay time, CLK high to DQ in low-impedance state (see Note 9) 2 ns tHZ Delay time, CLK high to DQ in high-impedance state (see Note 10) 8 ns tIS Setup time, address, control, and data input 3 ns tIH Hold time, address, control, and data input 1 ns tCESP Power-down/self-refresh exit time 10 ns tRAS Delay time, ACTV command to DEAC or DCAB command 50 100000 ns tRC Delay time, ACTV, REFR, or SLFR exit to ACTV, MRS, REFR, or SLFR command 80 ns tRCD Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 11) 30 ns tRP Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command 30 ns tRRD Delay time, ACTV command in one bank to ACTV command in the other bank 20 ns tRSA Delay time, MRS command to ACTV, MRS, REFR, or SLFR command 20 ns tAPR Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command tRP − (CL −1) * tCK ns tAPW Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command tRP + tCK ns tWR Delay time, final data in of WRT operation to DEAC or DCAB command 10 ns tT Transition time (see Note 12) 1 5 ns tREF Refresh interval 64 ms nCCD Delay time, READ or WRT command to an interrupting command 1 cycle nCDD Delay time, CS low or high to input enabled or inhibited 0 0 cycle nCLE Delay time, CKE high or low to CLK enabled or disabled 1 1 cycle nCWL Delay time, final data in of WRT operation to READ, READ-P, WRT, WRT-P 1 cycle nDID Delay time, ENBL or MASK command to enabled or masked data in 0 0 cycle nDOD Delay time, ENBL or MASK command to enabled or masked data out 2 2 cycle nHZP2 Delay time, DEAC or DCAB command to DQ in high-impedance state, CAS latency = 2 2 cycle nHZP3 Delay time, DEAC or DCAB command to DQ in high-impedance state, CAS latency = 3 3 cycle nWCD Delay time, WRT command to first data in 0 0 cycle † All references are made to the rising transition of CKx, unless otherwise noted. ‡ Specifications in this table represent a single SDRAM device. NOTES: 8. t AC is referenced from the rising transition of CK that is previous to the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CKx that is CAS latency − one cycle after the READ command. Access time is measured at output reference level 1.4 V. 9. tLZ is measured from the rising transition of CKx that is CAS latency − one cycle after the READ command. 10. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 11. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS . 12. Transition time, tT, is measured between VIH and VIL.
(SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. Table 1. Serial Presence Detect Data for the TM2SR72EPN
0 Defines number of bytes written into serial memory during module manufacturing 128 bytes 80h
1 Total number of bytes of SPD memory device 256 bytes 08h
3 Number of row addresses on this assembly 11 0Bh
4 Number of column addresses on this assembly 9 09h
5 Number of module rows on this assembly 1 bank 01h
6 Data width of this assembly 72 bits 48h
7 Data width continuation 00h
8 Voltage interface standard of this assembly LVTTL 01h
9 SDRAM cycle time at maximum supported CAS latency (CL), CL = X tCK = 10 ns A0h
11 DIMM configuration type (non-parity, parity, error correcting code [ECC]) ECC 02h
13 SDRAM width, primary DRAM x8 08h
14 Error-checking SDRAM data width x8 08h
15 Minimum clock delay, back-to-back random column addresses 1 CK cycle 01h
16 Burst lengths supported 1, 2, 4, 8 0Fh
17 Number of banks on each SDRAM device 2 banks 02h
18 CAS latencies supported 2, 3 06h
19 CS latency 0 01h
20 Write latency 0 01h
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 1. Serial Presence Detect Data for the TM2SR72EPN (Continued)
21 SDRAM module attributes Non-buffered/
22 SDRAM device attributes: general
23 Minimum clock cycle time at CL = X − 1 tCK = 15 ns F0h
24 Maximum data-access time from clock at CL = X − 1 tAC = 7 ns 70h
25 Minimum clock cycle time at CL = X − 2 N/A 00h
26 Maximum data-access time from clock at CL = X − 2 N/A 00h
27 Minimum row precharge time tRP = 30 ns 1Eh
28 Minimum row-active to row-active delay tRRD = 20 ns 14h
29 Minimum RAS -to-CAS delay tRCD = 30 ns 1Eh
30 Minimum RAS pulse width tRAS = 50 ns 32h
31 Density of each bank on module 16M Bytes 04h
32 Command and address signal input setup time tIS = 3 ns 30h
33 Command and address signal input hold time tIH = 1 ns 10h
34 Data signal input setup time tIS = 3 ns 30h
35 Data signal input hold time tIH = 1 ns 10h
63 Checksum for byte 0−62 33 21h
72 Manufacturing location† TBD
91 Die revision code† TBD
92 PCB revision code† TBD
† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).
Table 2. Serial Presence Detect Data for the TM4SR72EPN
5 Number of module banks on this assembly 2 banks 02h
12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 2. Serial Presence Detect data for the TM4SR72EPN (Continued)
63 Checksum for byte 0−62 34 22h
† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).
/C0084/C0077/C0050/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0084/C0077/C0052/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS698A − JUNE 1997 − REVISED FEBRUARY 1998 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device symbolization (TM2SR72EPN) TM2SR72EPN -SS YYMMT YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE A: Location of symbolization may vary. Unbuffered Key Position 3.3-V Voltage Key Position
/C0084/C0077/C0050/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0084/C0077/C0052/C0083/C0082/C0055/C0050/C0069/C0080/C0078 /C0052/C0257/C0049/C0057/C0052/C0257/C0051/C0048/C0052 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS698A − JUNE 1997 − REVISED FEBRUARY 1998
14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
BU (R-PDIM-N168) DUAL IN-LINE MEMORY MODULE 0.118 (3,00) TYP 1.255 (31,88) 1.245 (31,62) 0.700 (17,78) TYP 0.014 (0,35) MAX 0.106 (2,70) MAX 0.054 (1,37) 0.046 (1,17) 4088183/A 06/97 0.157 (4,00) MAX (For Double Sided DIMM Only) (Note D) 5.255 (133,48) 5.245 (133,22) 0.118 (3,00) DIA
2 Places
0.125 (3,18) 0.039 (1,00) TYP Notch 0.157 (4,00) x 0.122 (3,10) Deep Notch 0.079 (2,00) x 0.122 (3,10) Deep 0.125 (3,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-161 D. Dimension includes de-panelization variations; applies between notch and tab edge. E. Outline may vary above notches to allow router/panelization irregularities.
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