TM2EJ64DPN TI1 | Alldatasheet
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/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Organization − TM2xJ64xPN-xx...2 0 9 7152 × 64 Bits /C0068Single 3.3-V Power Supply (±10% Tolerance) /C0068JEDEC 144-Pin Small Outline Dual-In-Line Memory Module (SODIMM) Without Buffer for Use With Socket /C0068TM2xJ64xPN-xx — Utilizes Eight 16M-Bit (2M ×8-Bit) Dynamic RAMs in TSOPs /C0068Performance ranges ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE tRAC tCAC tAA tHPC MAX MAX MAX MIN ’2xJ64xPN-50 50 ns 13 ns 25 ns 20 ns ’2xJ64xPN-60 60 ns 15 ns 30 ns 25 ns ’2xJ64xPN-70 70 ns 18 ns 35 ns 30 ns /C0068High-Speed, Low-Noise LVTTL Interface /C0068Long Refresh Period: − TM2EJ64DPN: 32 ms (2048 cycles) − TM2EJ64EPN: 64 ms (4096 cycles) /C0068Low-Power, Battery-Backup Refresh Available: − TM2FJ64DPN: 128 ms (2048 cycles) − TM2FJ64EPN: 128 ms (4096 cycles) /C00683-State Output /C0068Extended-Data-Out (EDO) Operation With CAS -Before-RAS (CBR), RAS-Only, and Hidden Refresh /C0068Serial Presence-Detect (SPD) Using EEPROM /C0068Ambient Temperature Range 0°C to 70°C /C0068Gold-Plated Contacts
description
The TM2EJ64DPN is a 16M-byte, 144-pin, small outline dual-in-line memory module (SODIMM). The SODIMM is composed of eight TMS427809A, 2097152 × 8-bit 2K-refresh EDO dynamic random-access memories (DRAMs), each in a 400-mil, 28-pin plastic thin small-outline package (TSOP) (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS894). The TM2EJ64EPN is an 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS426809A, 2097152 × 8-bit 4K-refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS426809A data sheet (literature number SMKS894). The TM2FJ64DPN is a 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS427809AP, 2097152 × 8-bit 2K low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809AP data sheet (literature number SMKS894). The TM2FJ64EPN is a 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS426809AP, 2097152 × 8-bit 4K low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS426809AP data sheet (literature number SMKS894). operation The TM2xJ64xPN operates as eight TMS42x809A/Ps, connected as shown in the functional block diagram. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW Copyright 1997, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084 /C0080/C0082/C0069/C0086/C0073/C0069/C0087 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0099/C0111/C0110/C0099/C0101/C0114/C0110/C0115 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0105/C0110 /C0116/C0104/C0101 /C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0118/C0101 /C0111/C0114 /C0100/C0101/C0115/C0105/C0103/C0110 /C0112/C0104/C0097/C0115/C0101 /C0111/C0102 /C0100/C0101/C0118/C0101/C0108/C0111/C0112/C0109/C0101/C0110/C0116/C0046 /C0067/C0104/C0097/C0114/C0097/C0099/C0116/C0101/C0114/C0105/C0115/C0116/C0105/C0099 /C0100/C0097/C0116/C0097 /C0097/C0110/C0100 /C0111/C0116/C0104/C0101/C0114 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0097/C0114/C0101 /C0100/C0101/C0115/C0105/C0103/C0110 /C0103/C0111/C0097/C0108/C0115/C0046 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0114/C0101/C0115/C0101/C0114/C0118/C0101/C0115 /C0116/C0104/C0101 /C0114/C0105/C0103/C0104/C0116 /C0116/C0111 /C0099/C0104/C0097/C0110/C0103/C0101 /C0111/C0114 /C0100/C0105/C0115/C0099/C0111/C0110/C0116/C0105/C0110/C0117/C0101 /C0116/C0104/C0101/C0115/C0101 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0119/C0105/C0116/C0104/C0111/C0117/C0116 /C0110/C0111/C0116/C0105/C0099/C0101/C0046
/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997
2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DUAL-IN-LINE MEMORY MODULE (TOP VIEW) TM2xJ64xPN (SIDE VIEW) PIN NOMENCLATURE A[0:11]† Row Address Inputs A[0:9] Column Address Inputs DQ[0:63] Data In/Data Out CAS[0:7] Column-Address Strobe RAS0 Row-Address Strobe WE0 Write Enable OE0 Output Enable SDA Serial PD Address/Data SCL Serial PD Clock NC No-Connect Pin VDD 3.3-V Supply VSS Ground 143 † A11 is NC for TM2xJ64DPN PRODUCT PREVIEW
/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Pin Assignments ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ PIN ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ PIN ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ PIN ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ PIN ÁÁÁ NO. ÁÁÁÁÁ NAME ÁÁÁÁ NO. ÁÁÁÁÁ NAME ÁÁÁÁ NO. ÁÁÁÁÁ NAME ÁÁÁ NO. ÁÁÁÁÁÁ NAME ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ8 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ OE ÁÁÁ ÁÁÁ 109 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ40 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 110 ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ9 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 111 ÁÁÁÁÁÁ ÁÁÁÁÁÁ A10 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ32 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ41 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 112 ÁÁÁÁÁÁ ÁÁÁÁÁÁ NC ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ1 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ10 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 113 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ33 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ42 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 114 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁÁÁ DQ2 ÁÁÁÁ ÁÁÁÁÁ DQ11 ÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ 115 ÁÁÁÁÁÁ CAS2 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ34 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ43 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁ ÁÁÁ 116 ÁÁÁÁÁÁ ÁÁÁÁÁÁ CAS6 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ3 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ 117 ÁÁÁÁÁÁ ÁÁÁÁÁÁ CAS3 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ35 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ 118 ÁÁÁÁÁÁ ÁÁÁÁÁÁ CAS7 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ12 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ16 ÁÁÁ ÁÁÁ 119 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ44 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ48 ÁÁÁ ÁÁÁ 120 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ4 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ13 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ17 ÁÁÁ ÁÁÁ 121 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ24 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ36 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ45 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ49 ÁÁÁ ÁÁÁ 122 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ56 ÁÁÁ ÁÁÁÁÁ DQ5 ÁÁÁÁ ÁÁÁÁÁ DQ14 ÁÁÁÁ ÁÁÁÁÁ DQ18 ÁÁÁ 123 ÁÁÁÁÁÁ DQ25 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ37 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ46 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ50 ÁÁÁ ÁÁÁ 124 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ57 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ6 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ15 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ19 ÁÁÁ ÁÁÁ 125 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ26 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ38 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ47 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ51 ÁÁÁ ÁÁÁ 126 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ58 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ7 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 127 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ27 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ39 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 128 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ59 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ20 ÁÁÁ ÁÁÁ 129 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ52 ÁÁÁ ÁÁÁ 130 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CAS0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ21 ÁÁÁ ÁÁÁ 131 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ28 ÁÁÁ ÁÁÁÁÁ CAS4 ÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁÁ DQ53 ÁÁÁ 132 ÁÁÁÁÁÁ DQ60 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CAS1 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ22 ÁÁÁ ÁÁÁ 133 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ29 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ CAS5 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ54 ÁÁÁ ÁÁÁ 134 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ61 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DQ23 ÁÁÁ ÁÁÁ 135 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ30 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁÁ ÁÁÁÁ 100 ÁÁÁÁÁ ÁÁÁÁÁ DQ55 ÁÁÁ ÁÁÁ 136 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ62 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 101 ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ 137 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ31 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 102 ÁÁÁÁÁ ÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ 138 ÁÁÁÁÁÁ ÁÁÁÁÁÁ DQ63 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ WE0 ÁÁÁÁ ÁÁÁÁ 103 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ 139 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ 104 ÁÁÁÁÁ ÁÁÁ 140 ÁÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ RAS0 ÁÁÁÁ ÁÁÁÁ 105 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ 141 ÁÁÁÁÁÁ ÁÁÁÁÁÁ SDA ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 106 ÁÁÁÁÁ ÁÁÁÁÁ A11 ÁÁÁ ÁÁÁ 142 ÁÁÁÁÁÁ ÁÁÁÁÁÁ SCL ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 107 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 143 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ NC ÁÁÁÁ ÁÁÁÁ 108 ÁÁÁÁÁ ÁÁÁÁÁ VSS ÁÁÁ ÁÁÁ 144 ÁÁÁÁÁÁ ÁÁÁÁÁÁ VDD PRODUCT PREVIEW
/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997
4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
small outline dual-in-line memory module and components The small−outline dual-in-line memory module and components include: /C0068PC substrate: 1,10 /C0034 0,1 mm (0.04 inch) nominal thickness /C0068Bypass capacitors: Multilayer ceramic /C0068Contact area: Nickel plate and gold plate over copper functional block diagram for the TM2xJ64xPN CAS OE W RAS RAS0 WE0 OE0 CAS0 DQ[0:7] CAS OE W RAS CAS1 DQ[8:15] CAS OE W RAS CAS2 DQ[16:23] CAS OE W RAS UB0 RAS0 WE0 OE0 CAS4 DQ[32:39] CAS OE W RAS UB1 CAS5 DQ[40:47] CAS OE W RAS UB2 CAS6 DQ[48:55] CAS OE W RAS UB3 CAS7 DQ[56:63] A0 A1SCL VSS SPD EEPROM CAS OE W RAS CAS3 DQ[24:31] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] DQ[0:7] A2 SDA TM2xJ64DPN: TM2xJ64EPN: VDD VSS Two 0.1 µF (minimum) per DRAM U[0:3], UB[0:3] U[0:3], UB[0:3] PRODUCT PREVIEW
/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over ambient temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ MIN ÁÁÁ ÁÁÁ NOM ÁÁÁÁ ÁÁÁÁ MAX ÁÁÁ ÁÁÁ UNIT ÁÁÁÁ ÁÁÁÁ VDD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 3.3 ÁÁÁÁ ÁÁÁÁ 3.6 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VSS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VIH ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ High-level input voltage ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ VDD + 0.3 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VIH-SPD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ High-level input voltage for the SPD device ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 5.5 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ VIL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Low-level input voltage ÁÁÁ ÁÁÁ −0.3 ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ 0.8 ÁÁÁ ÁÁÁ V ÁÁÁÁ ÁÁÁÁ TA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Ambient temperature ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2) PARAMETER ’2xJ64xPN UNITPARAMETER MIN MAX UNIT C i(A) Input capacitance, A0−A10 42 pF C i(OE) Input capacitance, OE0 58 pF C i(CAS) Input capacitance, CASx 9 pF C i(RAS) Input capacitance, RAS0 58 pF C i(W) Input capacitance, WE0 58 pF C o Output capacitance 9 pF C i/o(SDA) Input/output capacitance, SDA input 9 pF C i(SPD) Input capacitance, SA0, SA1, SA2, SCL inputs 7 pF NOTE 2: V DD = NOM supply voltage ±10%, and the bias on pins under test is 0 V. PRODUCT PREVIEW
/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997
6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) TM2EJ64DPN PARAMETER TEST CONDITIONS † ’2EJ64DPN-50 ’2EJ64DPN-60 ’2EJ64DPN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level outputIOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH High-level output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL Low-level output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 10 ± 10 ± 10 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 10 ± 10 ± 10 µA ICC1 ‡§ Read- or write-cycle current VDD = 3.6 V, Minimum cycle 960 800 720 mA ICC2 Standby current VIH = 2 V (LVTTL), After one memory cycle, RAS0 and CASx high 16 16 16 mA ICC2 Standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RAS0 and CASx high 8 8 8 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VDD = 3.6 V, Minimum cycle, RAS0 cycling, CASx high (RAS-only refresh), RAS0 low after CASx low (CBR) 960 800 720 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RAS0 low, CASx cycling 880 720 640 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS0 = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC PRODUCT PREVIEW
/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) TM2EJ64EPN PARAMETER TEST CONDITIONS † ’2EJ64EPN-50 ’2EJ64EPN-60 ’2EJ64EPN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level outputIOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH High-level output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL Low-level output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 10 ± 10 ± 10 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 10 ± 10 ± 10 µA ICC1 ‡§ Read- or write-cycle current VDD = 3.6 V, Minimum cycle 720 560 480 mA ICC2 Standby current VIH = 2 V (LVTTL), After one memory cycle, RAS0 and CASx high 16 16 16 mA ICC2 Standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RAS0 and CASx high 8 8 8 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RAS0 low after CASx low (CBR) 720 560 480 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RAS0 low, CASx cycling 800 720 640 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS0 = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC PRODUCT PREVIEW
/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997
8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended ranges of supply voltage and ambient temperture (unless otherwise noted) (continued) TM2FJ64DPN PARAMETER TEST CONDITIONS † ’2FJ64DPN-50 ’2FJ64DPN-60 ’2FJ64DPN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level outputIOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH High-level output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL Low-level output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 10 ± 10 ± 10 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 10 ± 10 ± 10 µA ICC1 ‡§ Read- or write-cycle current VDD = 3.6 V, Minimum cycle 960 800 720 mA ICC2 Standby current VIH = 2 V (LVTTL), After one memory cycle, RAS0 and CASx high 8 8 8 mA ICC2 Standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RAS0 and CASx high 1.2 1.2 1.2 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VDD = 3.6 V, Minimum cycle, RAS0 cycling, CASx high (RAS-only refresh), RAS0 low after CASx low (CBR) 960 800 720 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RAS0 low, CASx cycling 880 720 640 mA ICC6 Average self-refresh current CASx < 0.2 V, RAS0 < 0.2 V, Measured after tRASS min 1.6 1.6 1.6 mA ICC10 Average battery back-up operating current (equivalent refresh time is 128 ms), CBR only tRC = 31.25 µs, tRAS ≤ 300 ns VDD − 0.2 V ≤ VIH ≤ 3.9 V, 0 V ≤ VIL ≤ 0.2 V, WE0 and OE0 = VIH, Address and data stable 2.8 2.8 2.8 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS0 = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC PRODUCT PREVIEW
/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM2FJ64EPN PARAMETER TEST CONDITIONS † ’2FJ64EPN-50 ’2FJ64EPN-60 ’2FJ64EPN-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level outputIOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH High-level output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL Low-level output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 10 ± 10 ± 10 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 10 ± 10 ± 10 µA ICC1 ‡§ Read- or write-cycle current VDD = 3.6 V, Minimum cycle 720 560 480 mA ICC2 Standby current VIH = 2 V (LVTTL), After one memory cycle, RAS0 and CASx high 8 8 8 mA ICC2 Standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RAS0 and CASx high 1.2 1.2 1.2 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VDD = 3.6 V, Minimum cycle, RAS0 cycling, CASx high (RAS-only refresh), RAS0 low after CASx low (CBR) 720 560 480 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RAS0 low, CASx cycling 800 720 640 mA ICC6 Average self-refresh current CASx < 0.2 V, RAS0 < 0.2 V, Measured after tRASS min 2 2 2 mA ICC10 Average battery back-up operating current (equivalent refresh time is 128 ms), CBR only tRC = 31.25 µs, tRAS ≤ 300 ns VDD − 0.2 V ≤ VIH ≤ 3.9 V, 0 V ≤ VIL ≤ 0.2 V, WE0 and OE0 = VIH, Address and data stable 2.8 2.8 2.8 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RAS0 = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC PRODUCT PREVIEW
/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 3) PARAMETER ’2XJ64xPN-50 ’2XJ64xPN-60 ’2XJ64xPN-70 UNITPARAMETER MIN MAX MIN MAX MIN MAX UNIT tAA Access time from column address (see Note 4) 25 30 35 ns tCAC Access time from CASx (see Note 4) 13 15 18 ns tCPA Access time from CASx precharge (see Note 4) 28 35 40 ns tRAC Access time from RAS0 (see Note 4) 50 60 70 ns tOEA Access time from OE0 (see Note 4) 13 15 18 ns tCLZ Delay time, CASx to output in low impedance 0 0 0 ns tREZ Output buffer turn off delay from RAS0 (see Note 5) 3 13 3 15 3 18 ns tCEZ Output buffer turn off delay from CASx (see Note 5) 3 13 3 15 3 18 ns tOEZ Output buffer turn off delay from OE0 (see Note 5) 3 13 3 15 3 18 ns tWEZ Output buffer turn off delay from WE0 (see Note 5) 3 13 3 15 3 18 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 4. Access times are measured with output reference levels of VOH =2 V and VOL =0.8 V. 5. The maximum values of tREZ , tCEZ , tOEZ , and tWEZ are specified when the outputs are no longer driven. Data-in should not be driven until one of the applicable maximum values is satisfied. EDO timing requirements (see Note 3) ’2XJ64xPN-50 ’2XJ64xPN-60 ’2XJ64xPN-70 UNITMIN MAX MIN MAX MIN MAX UNIT tHPC Cycle time, EDO page mode, read-write 20 25 30 ns tPRWC Cycle time, EDO read-write 57 68 78 ns tCSH Delay time, RAS0 active to CASx precharge 40 48 58 ns tCHO Hold time, OE0 from CASx 7 10 10 ns tDOH Hold time, output from CASx 5 5 5 ns tCAS Pulse duration, CASx active 8 10000 10 10000 12 10000 ns tWPE Pulse duration, WE0 active (output disable only) 7 7 7 ns tCP Pulse duration, CASx precharge 8 10 10 ns tOCH Setup time, OE0 before CASx 8 10 10 ns tOEP Precharge time, OE0 5 5 5 ns NOTE 3: With ac parameters, it is assumed that tT = 2 ns. PRODUCT PREVIEW
/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ac timing requirements (see Note 3) ’2xJ64xPN-50 ’2xJ64xPN-60 ’2xJ64xPN-70 UNITMIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, random read or write 84 104 124 ns tRWC Cycle time, read-write 111 135 160 ns tRASP Pulse duration, RAS0 active, fast page mode (see Note 6)50 100 000 60 100 000 70 100 000 ns tRAS Pulse duration, RAS0 active, non-page mode (see Note 6) 50 10 000 60 10 000 70 10 000 ns tRP Pulse duration, RAS0 precharge 30 40 50 ns tWP Pulse duration, write command 8 10 10 ns tRASS Pulse duration, RAS0 active, self refresh (see Note 7) 100 100 100 /C0109s tRPS Pulse duration, RAS0 precharge after self refresh 90 110 130 ns tASC Setup time, column address 0 0 0 ns tASR Setup time, row address 0 0 0 ns tDS Setup time, data in (see Note 8) 0 0 0 ns tRCS Setup time, read command 0 0 0 ns tCWL Setup time, write command before CASx precharge 8 10 12 ns tRWL Setup time, write command before RAS0 precharge 8 10 12 ns tWCS Setup time, write command before CASx active (early-write only) 0 0 0 ns tWRP Setup time, WE0 high before RAS0 low (CBR refresh only) 10 10 10 ns tCSR Setup time, CASx referenced to RAS0 (CBR refresh only) 5 5 5 ns tCAH Hold time, column address 8 10 12 ns tDH Hold time, data in (see Note 8) 8 10 12 ns tRAH Hold time, row address 8 10 10 ns tRCH Hold time, read command referenced to CASx (see Note 9) 0 0 0 ns tRRH Hold time, read command referenced to RAS0 (see Note 9) 0 0 0 ns tWCH Hold time, write command during CASx active (early-write only) 8 10 12 ns tROH Hold time, RAS0 referenced to OE0 8 10 10 ns tWRH Hold time, WE0 high after RAS0 low (CBR refresh only) 10 10 10 ns tCHR Hold time, CASx referenced to RAS0 (CBR refresh only) 10 10 10 ns tOEH Hold time, OE0 command 13 15 18 ns tRHCP Hold time, RAS0 active from CASx precharge 28 35 40 ns tCHS Hold time, CASx referenced to RAS0 (self refresh only) − 50 − 50 − 50 ns tAWD Delay time, column address to write command (read-write only) 42 49 57 ns tCRP Delay time, CASx precharge to RAS0 5 5 5 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 6. In a read-write cycle, tRWD and tRWL must be observed. 7. During the period of 10 µs ≤ tRASS ≤100 µs, the device is in a transition state from normal-operation mode to self-refresh mode. 8. Referenced to the later of CASx or WE0 in write operations 9. Either tRRH or tRCH must be satisfied for a read cycle. PRODUCT PREVIEW
/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997
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ac timing requirements (see Note 3) (continued) ’2xJ64xPN-50 ’2xJ64xPN-60 ’2xJ64xPN-70 UNITMIN MAX MIN MAX MIN MAX UNIT tCWD Delay time, CASx to write command (read-write only) 0 0 0 ns tOED Delay time, OE0 to data in 0 0 0 ns tRAD Delay time, RAS0 to column address (see Note 10) 8 10 12 ns tRAL Delay time, column address to RAS0 precharge 8 10 12 ns tCAL Delay time, column address to CASx precharge 0 0 0 ns tRCD Delay time, RAS0 to CASx (see Note 10) 5 5 5 ns tRPC Delay time, RAS0 precharge to CASx 5 5 5 ns tRSH Delay time, CASx active to RAS0 precharge 8 10 12 ns tRWD Delay time, RAS0 to write command (read−write only) 67 79 92 ns tCPW Delay time, CASx precharge to write command (read-write only) 45 54 62 ns ’2EJ64DPN 32 32 32 ms tREF Refresh time interval ’2EJ64EPN 64 64 64 ms tREF Refresh time interval ’2FJ64xPN 128 128 128 tT Transition time 2 30 2 30 2 30 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 10. The maximum value is specified only to ensure access time. PRODUCT PREVIEW
/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 serial presence detect The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Tables in this section list the SPD contents as follows: Table 1−TM2EJ64DPN Table 2−TM2EJ64EPN Table 3−TM2FJ64DPN Table 4−TM2FJ64EPN PRODUCT PREVIEW
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Table 1. Serial Presence-Detect Data for the TM2EJ64DPN
1 Total number of bytes of SPD
2 Fundamental memory type (FPM,
3 Number of row addresses on this
4 Number of column addresses on
5 Number of module banks on this
6 Data width of this assembly 64 bits 40h 64 bits 40h 64 bits 40h
7 Data width continuation 00h 00h 00h
8 Voltage interface standard of this
9 RAS0 access time of module tRAC = 50 ns 32h tRAC = 60 ns 3Ch tRAC = 70 ns 46h
10 CASx access time of module tCAC = 13 ns 0Dh tCAC = 15 ns 0Fh tCAC = 18 ns 12h
11 SODIMM configuration type
13 DRAM width, primary DRAM x8 08h x8 08h x8 08h
14 Error-checking SDRAM data width N/A 00h N/A 00h N/A 00h
63 Checksum for bytes 0−62 41 29h 53 35h 66 42h
72 Manufacturing location† TBD TBD TBD
91 Die revision code† TBD TBD TBD
92 PCB revision code† TBD TBD TBD
† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).
Table 2. Serial Presence-Detect Data for the TM2EJ64EPN
13 DRAM width, primary DRAM x8 08h x8 08h 08h 08h
† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).
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Table 3. Serial Presence-Detect Data for the TM2FJ64DPN
63 Checksum for bytes 0−62 169 A9h 181 B5h 194 C2h
† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).
Table 4. Serial Presence-Detect Data for the TM2FJ64EPN † TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).
/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997
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device symbolization (TM2EJ64DPN illustrated) -SS YYMMT YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE A: Location of symbolization may vary. TM2EJ64DPN PRODUCT PREVIEW
/C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0068/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0068/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0050/C0069/C0074/C0054/C0052/C0069/C0080/C0078/C0044 /C0084/C0077/C0050/C0070/C0074/C0054/C0052/C0069/C0080/C0078 /C0050/C0257/C0048/C0057/C0055/C0257/C0049/C0053/C0050 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 /C0266 /C0083/C0079/C0068/C0073/C0077/C0077 SMMS685 − AUGUST 1997 19POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MECHANICAL DATA BDM (R-SODIMM-N144) SMALL OUTLINE DUAL IN-LINE MEMORY MODULE 1.005 (25,53) 0.010 (0,25) MAX 0.788 (20,00) TYP 0.044 (1,12) 0.036 (0,91) 0.157 (4,00) 4088187/A 07/97 0.150 (3,81) MAX (For Double Sided Module Only) 0.095 (2,41) MAX 0.126 (3,20) 0.995 (25,27) 2.655 (67,44) 0.024 (0,61) TYP 0.098 (2,49) 0.196 (4,98) 2.665 (67,69) Notch 0.157 (4,00) x 0.079 (2,00) Deep (2 Places) Notch 0.060 (1,52) x 0.158 (4,01) Deep 0.031 (0,79) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-190 PRODUCT PREVIEW
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