TM248NBK36F-60

TM124MBK36F TI1 | Alldatasheet

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TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization TM124MBK36F ...10 4 85 7 6 × 36 TM248NBK36F ...20 9 7152 × 36 /C0068Single 5-V Power Supply (±10% Tolerance) /C006872-Pin Single-In-Line Memory Module (SIMM) for Use With Socket /C0068TM124MBK36F – Utilizes Two 16-Megabit and One 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages /C0068TM248NBK36F – Utilizes Four 16-Megabit and Two 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages /C0068Long Refresh Period...1 6 m s (1024 Cycles) /C0068All Inputs, Outputs, Clocks Fully TTL Compatible /C00683-State Output /C0068Common CAS Control for Nine Common Data-In and Data-Out Lines in Four Blocks /C0068Enhanced Page-Mode Operation With CAS -Before-RAS (CBR), RAS-Only, and Hidden Refresh /C0068Presence Detect /C0068Performance Ranges: ACCESS ACCESS ACCESS READ TIME TIME TIME OR tRAC tAA tCAC WRITE CYCLE (MAX) (MAX) (MAX) (MIN) ’124MBK36F-60 60 ns 30 ns 15 ns 110 ns ’124MBK36F-70 70 ns 35 ns 18 ns 130 ns ’124MBK36F-80 80 ns 40 ns 20 ns 150 ns ’248NBK36F-60 60 ns 30 ns 15 ns 110 ns ’248NBK36F-70 70 ns 35 ns 18 ns 130 ns ’248NBK36F-80 80 ns 40 ns 20 ns 150 ns /C0068Low Power Dissipation /C0068Operating Free-Air Temperature Range: 0°C to 70°C /C0068Gold-Tabbed Versions Available:† – TM124MBK36F – TM248NBK36F /C0068Tin-Lead (Solder) Tabbed Versions Available: – TM124MBK36U – TM248NBK36U

description

The TM124MBK36F is a 4-MByte dynamic random-access memory (DRAM) organized as four times 1048576 × 9 in a 72-pin single-in-line memory module (SIMM). The SIMM is composed of two TMS418160DZ, 1 048 576 × 16-bit dynamic RAMs, each in a 42-lead plastic small-outline J-lead (SOJ) package and one TMS44460DJ, 1048576 × 4-bit DRAM in a 24/26-lead plastic small-outline J-lead (SOJ) package mounted on a substrate with decoupling capacitors. The TMS418160DZ and TMS44460DJ are described in the TMS418160 and TMS44460 data sheets, respectively. The TM124MBK36F SIMM is available in the single-sided BK leadless module for use with sockets. TM248NBK36F The TM248NBK36F is an 8-MByte DRAM organized as four times 2097152 × 9 in a 72-pin single-in-line memory module (SIMM). The SIMM is composed of four TMS418160DZ, 1 048 576 × 16-bit dynamic RAMs, each in a 42-lead plastic small-outline J-lead (SOJ) package and two TMS44460DJ, 1048576 × 4-bit DRAMs, each in a 24/26-lead plastic small-outline (SOJ) package mounted on a substrate with decoupling capacitors. The TMS418160DZ and TMS44460DJ are described in the TMS418160 and TMS44460 data sheets, respectively. The TM248NBK36F SIMM is available in the double-sided BK leadless module for use with sockets. operation The TM124MBK36F operates as two TMS418160DZs and one TMS44460DJ connected as shown in the functional block diagram and NO TAG. The TM248NBK36F operates as four TMS418160DZs and two TMS44460DJs connected as shown in the functional block diagram and NO TAG. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1995, Texas Instruments Incorporated

TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995

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(PIN) PD1 (67) PD2 (68) PD3 (69) PD4 (70) 80 ns VSS VSS NC VSS TM124MBK36F 70 ns VSS VSS VSS NC 60 ns VSS VSS NC NC 80 ns NC NC NC VSS TM248NBK36F 70 ns NC NC VSS NC 60 ns NC NC NC NC BK SINGLE-IN-LINE MEMORY MODULE (TOP VIEW) TM124MBK36F (SIDE VIEW) PIN NOMENCLATURE A0–A9 Address Inputs CAS0 –CAS3 Column-Address Strobe DQ0–DQ35 Data In/Data Out NC No Connection PD1– PD4 Presence Detects RAS0 –RAS3 Row-Address Strobe VCC 5-V Supply VSS Ground W Write Enable TM248NBK36F (SIDE VIEW) DQ17 DQ35 CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 VCC DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC VSS VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 VCC NC NC DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 NC VCC RAS3 RAS2 DQ26 DQ8 VSS (TM248NBK36 only)

Table 1. Connection Table † Side 2 applies to the TM248NBK36F only.

TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995

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functional block diagram [TM124MBK36F and TM248NBK36F, side 1] 1M × 16 A0–A9 DQ0– RAS DQ7 W LCAS DQ8– UCAS DQ15 A0–A9 D9– D16 D27– D34 W RAS0 CAS0 CAS1 RAS2 10 10 D0– D18– D25 1M × 16 A0–A9 DQ0– RAS DQ7 W LCAS DQ8– UCAS DQ15 CAS2 CAS3 10 1M × 4 A0–A9 DQ1 RAS DQ2 W DQ3 CAS1 DQ4 CAS2 CAS3 CAS4 DQ8 DQ17 DQ26 DQ35 CAS0 CAS1 CAS2 CAS3 functional block diagram [TM248NBK36F, side 2] 1M × 16 A0–A9 DQ0– RAS DQ7 W LCAS DQ8– UCAS DQ15 A0–A9 W RAS1 CAS1 CAS0 RAS3 10 10 1M × 16 A0–A9 DQ0– RAS DQ7 W LCAS DQ8– UCAS DQ15 CAS3 CAS2 10 1M × 4 A0–A9 DQ1 RAS DQ2 W DQ3 CAS1 DQ4 CAS2 CAS3 CAS4 DQ8 DQ17 DQ26 DQ35 CAS0 CAS1 CAS2 CAS3 D0– D18– D25 D9– D16 D27– D35

TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) – 1 0.8 V TA Operating free-air temperature 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS ’124MBK36F-60 ’124MBK36F-70 ’124MBK36F-80 UNITPARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltageIOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 Read- or write-cycle current VCC = 5.5 V, Minimum cycle 285 250 220 mA ICC2 Standby current VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 6 6 6 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high 3 3 3 mA ICC3 Average refresh current (RAS only or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 285 250 220 mA ICC4 Average page current VCC = 5.5 V, tPC = MIN, RAS low, CAS cycling 250 220 190 mA

TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995

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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)† PARAMETER TEST CONDITIONS ’248NBK36F-60 ’248NBK36F-70 ’248NBK36F-80 UNITPARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, V I = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC , CAS high ± 20 ± 20 ± 20 µA ICC1 Read- or write-cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 391 256 226 mA ICC2 Standby current VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 12 12 12 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high 6 6 6 mA ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 570 500 440 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, t PC = MIN, RAS low, CAS cycling 256 226 196 mA † For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5) PARAMETER ’124MBK36F ’248NBK36F UNITPARAMETER MIN MAX MIN MAX UNIT C i(A) Input capacitance, address inputs 15 30 pF C i(R) Input capacitance RAS inputs RAS2 , RAS3 14 14 pFC i(R) Input capacitance, RAS inputs RAS0 , RAS1 7 7 pF C i(C) Input capacitance, CAS inputs 14 28 pF C i(W) Input capacitance, write-enable input 21 42 pF C o(DQ) Output capacitance on DQ pins 7 14 pF NOTE 5: Bias on pins under test is 0 V.

TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’124MBK36F-60 ’248NBK36F-60 ’124MBK36F-70 ’248NBK36F-70 ’124MBK36F-80 ’248NBK36F-80 UNIT MIN MAX MIN MAX MIN MAX tAA Access time from column address 30 35 40 ns tCAC Access time from CAS low 15 18 20 ns tRAC Access time from RAS low 60 70 80 ns tCPA Access time from column precharge 35 40 45 ns tCLZ CAS to output in low-impedance state 0 0 0 ns tOH Output disable time from start of CAS high 3 3 3 ns tOFF Output disable time after CAS high (see Note 6) 0 15 0 18 0 20 ns NOTE 6: tOFF is specified when the output is no longer driven. timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124MBK36F-60 ’248NBK36F-60 ’124MBK36F-70 ’248NBK36F-70 ’124MBK36F-80 ’248NBK36F-80 UNIT MIN MAX MIN MAX MIN MAX tRC Cycle time, random read or write (see Note 7) 110 130 150 ns tPC Cycle time, page-mode read or write (see Notes 7 and 8)40 45 50 ns tRASP Pulse duration, page mode, RAS low 60 100 000 70 100 000 80 100 000 ns tRAS Pulse duration, nonpage mode, RAS low 60 10 000 70 10 000 80 10 000 ns tCAS Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns tCP Pulse duration, CAS high (precharge) 10 10 10 ns tRP Pulse duration, RAS high (precharge) 40 50 60 ns tWP Pulse duration, W low 10 10 10 ns tASC Setup time, column address before CAS low 0 0 0 ns tASR Setup time, row address before RAS low 0 0 0 ns tDS Setup time, data before CAS low 0 0 0 ns tRCS Setup time, W high before CAS low 0 0 0 ns tCWL Setup time, W low before CAS high 15 18 20 ns tRWL Setup time, W low before RAS high 15 18 20 ns tWCS Setup time, W low before CAS low 0 0 0 ns tWRP Setup time, W high before RAS low (CBR refresh only) 10 10 10 ns tCAH Hold time, column address after CAS low 10 15 15 ns tRHCP Hold time, RAS high from CAS precharge 35 40 45 ns tDH Hold time, data after CAS low 10 15 15 ns tRAH Hold time, row address after RAS low 10 10 10 ns tRCH Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 9) 0 0 0 ns tWCH Hold time, W low after CAS low 10 15 15 ns tWRH Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be ≥ tCP . 9. Either tRRH or tRCH must be satisfied for a read cycle.

TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995

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timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) ’124MBK36F-60 ’248NBK36F-60 ’124MBK36F-70 ’248NBK36F-70 ’124MBK36F-80 ’248NBK36F-80 UNIT MIN MAX MIN MAX MIN MAX tCHR Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns tCRP Delay time, CAS high to RAS low 5 5 5 ns tCSH Delay time, RAS low to CAS high 60 70 80 ns tCSR Delay time, CAS low to RAS low (CBR refresh only) 5 5 5 ns tRAD Delay time, RAS low to column address (see Note 10) 15 30 15 35 15 40 ns tRAL Delay time, column address to RAS high 30 35 40 ns tCAL Delay time, column address to CAS high 30 35 40 ns tRCD Delay time, RAS low to CAS low (see Note 10) 20 45 20 52 20 60 ns tRPC Delay time, RAS high to CAS low (CBR only) 0 0 0 ns tRSH Delay time, CAS low to RAS high 15 18 20 ns tREF Refresh time interval 16 16 16 ms tT Transition time 3 30 3 30 3 30 ns NOTE 10: The maximum value is specified only to assure access time. device symbolization (TM124MBK36F illustrated) TM124MBK36F -SS YYMMT YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE: Location of symbolization may vary.

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