TM248GBK32H

TM124FBK32H TI1 | Alldatasheet

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TM124FBK32H, TM124FBK32I 1048576 BY 32-BIT TM248GBK32H, TM248GBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS678 – APRIL 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068 Organization TM124FBK32H/ I...10 4 85 7 6 × 32 TM248GBK32H/ I...20 9 7152 × 32 /C0068 Single 5-V Power Supply (±10% Tolerance) /C0068 72-Pin Single In-Line Memory Module (SIMM) for Use With Socket /C0068 TM124FBK32H/I – Uses Two 16M-Bit Dynamic Random-Access Memories (DRAMs) in Plastic Small-Outline J-Lead (SOJ) Package /C0068 TM248GBK32H/I – Uses Four 16M-Bit DRAMs in Plastic SOJ Package /C0068 Long Refresh Period 16 ms (1024 Cycles) /C0068 All Inputs, Outputs, Clocks Fully TTL-Compatible /C0068 3-State Output /C0068 Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks /C0068 Extended Data Out (EDO) Operation With CAS -Before-RAS (CBR), RAS-Only, Hidden Refresh, and Self Refresh /C0068 Presence Detect /C0068 JEDEC First Generation 72-Pin SIMM Pinout /C0068 Performance Ranges: ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE tRAC tAA tCAC tHPC (MAX) (MAX) (MAX) (MIN) ’124FBK32H/I-50 50 ns 25 ns 13 ns 20 ns ’124FBK32H/I-60 60 ns 30 ns 15 ns 25 ns ’124FBK32H/I-70 70 ns 35 ns 18 ns 30 ns ’248GBK32H/I-50 50 ns 25 ns 13 ns 20 ns ’248GBK32H/I-60 60 ns 30 ns 15 ns 25 ns ’248GBK32H/I-70 70 ns 35 ns 18 ns 30 ns /C0068 Low Power Dissipation /C0068 Operating Free-Air Temperature Range 0°C to 70°C /C0068 Gold-Tabbed Versions Available:† TM124FBK32H TM248GBK32H /C0068 Tin-Lead Solder-Tabbed Versions Available: TM124FBK32I TM248GBK32I

description

The TM124FBK32H/I is a 4M-byte DRAM organized as four times 1048576 × 8 in a 72-pin SIMM. The SIMM is composed of two TMS418169ADZ 1 048 576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418169ADZ is described in the TMS418169A data sheet (literature number SMKS892). The TM124FBK32H/I SIMM is available in the single-sided BK-leadless module for use with sockets. TM248GBK32H/I The TM248GBK32H/I is an 8M-byte DRAM organized as four times 2 097 152× 8 in a 72-pin SIMM. The SIMM is composed of four TMS418169ADZ 1 048 576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418169ADZ is described in the TMS418169A data sheet (literature number SMKS892). The TM248GBK32H/I SIMM is available in the double-sided BK-leadless module for use with sockets. operation The TM124FBK32H/I operates as two TMS418169ADZs connected as shown in the functional block diagram and in Table 1. The TM248GBK32H/I operates as four TMS418169ADZs connected as shown in the functional block diagram and in Table 1. The common I/O feature dictates the use of early-write cycles to prevent contention on D and Q. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1997, Texas Instruments Incorporated

TM124FBK32H, TM124FBK32I 1048576 BY 32-BIT TM248GBK32H, TM248GBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS678 – APRIL 1997

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(PIN) PD1 (67) PD2 (68) PD3 (69) PD4 (70) 50 ns VSS VSS VSS VSS TM124FBK32H/I 60 ns VSS VSS NC NC 70 ns VSS VSS VSS NC 50 ns NC NC VSS VSS TM248GBK32H/I 60 ns NC NC NC NC 70 ns NC NC VSS NC NC NC CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS BK SINGLE IN-LINE MEMORY MODULE (TOP VIEW) TM124FBK32H/I (SIDE VIEW) PIN NOMENCLATURE A0 –A9 Address Inputs CAS0 –CAS3 Column-Address Strobe DQ0 –DQ31 Data In/Data Out NC No Connection PD1 – PD4 Presence Detect RAS0 –RAS3 Row-Address Strobe VCC 5-V Supply VSS Ground W Write Enable TM248GBK32H/I (SIDE VIEW) VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC NC DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 NC VCC RAS3 RAS2 NC NC VSS

Table 1. Connection Table † Side 2 applies to the TM248GBK32H and the TM248GBK32I.

TM124FBK32H, TM124FBK32I 1048576 BY 32-BIT TM248GBK32H, TM248GBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS678 – APRIL 1997

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) – 1 0.8 V TA Operating free-air temperature 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ ’124FBK32H/I-50 ’124FBK32H/I-60 ’124FBK32H/I-70 UNITPARAMETER TEST CONDITIONS ‡ MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 Read- or write-cycle current (see Note 3)VCC = 5.5 V, Minimum cycle 360 320 300 mA ICC2 Standby current VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high 4 4 4 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and CAS high 2 2 2 mA ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 360 320 300 mA ICC4 Average EDO current (see Note 4) VCC = 5.5 V, tHPC = MIN, RAS low, CAS cycling 280 220 200 mA ‡ For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH

TM124FBK32H, TM124FBK32I 1048576 BY 32-BIT TM248GBK32H, TM248GBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS678 – APRIL 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS † ’248GBK32H/I-50 ’248GBK32H/I-60 ’248GBK32H/I-70 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, V I = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC , CAS high ± 20 ± 20 ± 20 µA ICC1 Read- or write-cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 362 322 302 mA ICC2 Standby current VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high 8 8 8 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After one memory cycle, RAS and CAS high 4 4 4 mA ICC3 Average refresh current (RAS only or CBR) (see Notes 3 and 5) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 720 640 600 mA ICC4 Average EDO current (see Note 4) VCC = 5.5 V, t PC = MIN, RAS low, CAS cycling 560 440 400 mA † For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH 5. Measured with both sides in CBR cycle capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 6) PARAMETER ’124FBK32H/I ’248GBK32FH/I UNITPARAMETER MIN MAX MIN MAX UNIT C i(A) Input capacitance, A0–A9 12 22 pF C i(R) Input capacitance, RAS inputs 8 8 pF C i(C) Input capacitance, CAS inputs 8 15 pF C i(W) Input capacitance, W 16 30 pF C o(DQ) Output capacitance on DQ0–DQ31 8 15 pF NOTE 6: V CC = 5 V ± 0.5 V, and the bias on pins under test is 0 V.

TM124FBK32H, TM124FBK32I 1048576 BY 32-BIT TM248GBK32H, TM248GBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS678 – APRIL 1997

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switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’124FBK32H/I-50 ’248GBK32H/I-50 ’124FBK32H/I-60 ’248GBK32H/I-60 ’124FBK32H/I-70 ’248GBK32H/I-70 UNIT MIN MAX MIN MAX MIN MAX tAA Access time from column address 25 30 35 ns tCAC Access time from CAS low 13 15 18 ns tRAC Access time from RAS low 50 60 70 ns tCPA Access time from column precharge 28 35 40 ns tCLZ CAS to output in low-impedance state 0 0 0 ns tREZ Output disable time after RAS high (see Note 7) 3 13 3 15 3 18 ns tWEZ Output disable time after W low (see Note 7) 3 13 3 15 3 18 ns NOTE 7: tREZ and tWEZ are specified when the output is no longer driven. EDO timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124FBK32H/I-50 ’248GBK32H/I-50 ’124FBK32H/I-60 ’248GBK32H/I-60 ’124FBK32H/I-70 ’248GBK32H/I-70 UNIT MIN MAX MIN MAX MIN MAX tHPC Cycle time, EDO page-mode read or write 20 25 30 ns tPRWC Cycle time, EDO read-write 57 68 78 ns tCSH Hold time, CAS from RAS 40 48 58 ns tDOH Hold time, output from CAS 5 5 5 ns tCAS Pulse duration, CAS 8 10000 10 10000 12 10000 ns tWPE Pulse duration, W (output disable only) 7 7 7 ns tCP Precharge time, CAS 8 10 10 ns timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124FBK32H/I-50 ’248GBK32H/I-50 ’124FBK32H/I-60 ’248GBK32H/I-60 ’124FBK32H/I-70 ’248GBK32H/I-70 UNIT MIN MAX MIN MAX MIN MAX tRC Cycle time, random read or write (see Note 8) 84 104 124 ns tRWC Cycle time, read-write 111 135 160 ns tRASP Pulse duration, page mode, RAS low 50 100 000 60 100 000 70 100 000 ns tRAS Pulse duration, nonpage mode, RAS low 50 10 000 60 10 000 70 10 000 ns tRP Pulse duration, RAS high (precharge) 30 40 50 ns tWP Pulse duration, W low 8 10 10 ns tASC Setup time, column address before CAS low 0 0 0 ns tASR Setup time, row address before RAS low 0 0 0 ns tDS Setup time, data before CAS low 0 0 0 ns tRCS Setup time, W high before CAS low 0 0 0 ns tCWL Setup time, W low before CAS high 8 10 12 ns NOTE 8: The ac parameter assumes tT = 2 ns.

TM124FBK32H, TM124FBK32I 1048576 BY 32-BIT TM248GBK32H, TM248GBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS678 – APRIL 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251 –1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) ’124FBK32H/I-50 ’248GBK32H/I-50 ’124FBK32H/I-60 ’248GBK32H/I-60 ’124FBK32H/I-70 ’248GBK32H/I-70 UNIT MIN MAX MIN MAX MIN MAX tRWL Setup time, W low before RAS high 8 10 12 ns tWCS Setup time, W low before CAS low 0 0 0 ns tCAH Hold time, column address after CAS low 8 10 15 ns tDH Hold time, data after CAS low 8 10 15 ns tRAH Hold time, row address after RAS low 8 10 10 ns tRCH Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 9) 0 0 0 ns tWCH Hold time, W low after CAS low 8 10 12 ns tRHCP Hold time, RAS high from CAS precharge 28 35 40 ns tCHR Delay time, RAS low to CAS high (CBR refresh only) 8 10 10 ns tCRP Delay time, CAS high to RAS low 5 5 5 ns tCSR Delay time, CAS low to RAS low (CBR refresh only) 5 5 5 ns tRAD Delay time, RAS low to column address (see Note 10) 12 25 15 30 15 35 ns tRAL Delay time, column address to RAS high 25 30 35 ns tCAL Delay time, column address to CAS high 18 20 25 ns tRCD Delay time, RAS low to CAS low (see Note 10) 17 37 20 45 20 52 ns tRPC Delay time, RAS high to CAS low (CBR only) 5 5 5 ns tRSH Delay time, CAS low to RAS high 8 10 12 ns tREF Refresh time interval 16 16 16 ms tT Transition time 2 30 2 30 2 30 ns NOTES: 9. Either tRRH or tRCH must be satisfied for a read cycle. 10. The maximum value is specified only to assure access time. device symbolization (TM124FBK32H illustrated) TM124FBK32H -SS YYMMT YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE A: Location of symbolization may vary.

TM124FBK32H, TM124FBK32I 1048576 BY 32-BIT TM248GBK32H, TM248GBK32I 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS678 – APRIL 1997

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BK (R-PSIM-N72) SINGLE-IN-LINE MEMORY MODULE 4040197/C 4/95 0.208 (5,28) MAX 0.400 (10,16) TYP 0.010 (0,25) MAX 0.054 (1,37) 1.005 (25,53) 0.995 (25,27) 0.047 (1,19) 0.360 (9,14) MAX (For Double-Sided SIMM) 4.255 (108,08) 4.245 (107,82) 0.125 (3,18) TYP 0.040 (1,02) TYP 0.120 (3,05) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.

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