TM16LR64JFN TI1 | Alldatasheet
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/C0084/C0077/C0056/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0056 /C0051/C0056/C0056 /C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0049/C0054 /C0055/C0055/C0055 /C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS710 − MAY 1998 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Organization: − T M 8 L R 6 4 J F N...8 3 8 8608 × 64 Bits − TM16LR64JFN ...1 6 7 7 7216 × 64 Bits /C0068Designed for 100-MHz 4-Clock Systems /C0068JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket /C0068TM8LR64JFN — Uses Eight 64M-Bit Synchronous Dynamic RAMs (SDRAMs) (8M × 8-Bit) in Plastic Thin Small-Outline Packages (TSOPs) /C0068TM16LR64JFN — Uses Sixteen 64M-Bit SDRAMs (8M × 8-Bit) in Plastic TSOPs /C0068Performance Ranges: /C0068Single 3.3-V Power Supply (±10% Tolerance) /C0068Byte-Read/Write Capability /C0068High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface /C0068Read Latencies 2 and 3 Supported /C0068Supports Burst-Interleave and Burst-Interrupt Operations /C0068Burst Length Programmable to 1, 2, 4, and 8 /C0068Four Banks for On-Chip Interleaving (Gapless Access) /C0068Ambient Temperature Range 0°C to 70°C /C0068Electroless Gold-Finished Contacts /C0068Pipeline Architecture /C0068Serial Presence-Detect (SPD) Using EEPROM SYNCHRONOUS CLOCK CYCLE TIME ACCESS TIME CLOCK TO OUTPUT REFRESH INTERVAL tCK3 tCK2 tAC3 tAC2 tREF ’xLR64JFN-8 8 ns 10 ns 6 ns 6 ns 64 ms ’xLR64JFN-8A 8 ns 10 ns 6 ns 7.5 ns 64 ms
description
The TM8LR64JFN is a 64M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of eight TMS664814DGE 8388608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695). The TM16LR64JFN is a 128M-byte, 168-pin DIMM. The DIMM is composed of sixteen TMS664814DGE 8388608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic TSOP mounted on a substrate with decoupling capacitors. operation The TM8LR64JFN operates as eight TMS664814DGE devices that are connected as shown in the TM8LR64JFN functional block diagram. The TM16LR64JFN operates as 16 TMS664814DGE devices connected as shown in the TM16LR64JFN functional block diagram. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW Copyright 1998, Texas Instruments Incorporated /C0080/C0082/C0079/C0068/C0085/C0067/C0084 /C0080/C0082/C0069/C0086/C0073/C0069/C0087 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0099/C0111/C0110/C0099/C0101/C0114/C0110/C0115 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0105/C0110 /C0116/C0104/C0101 /C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0118/C0101 /C0111/C0114 /C0100/C0101/C0115/C0105/C0103/C0110 /C0112/C0104/C0097/C0115/C0101 /C0111/C0102 /C0100/C0101/C0118/C0101/C0108/C0111/C0112/C0109/C0101/C0110/C0116/C0046 /C0067/C0104/C0097/C0114/C0097/C0099/C0116/C0101/C0114/C0105/C0115/C0116/C0105/C0099 /C0100/C0097/C0116/C0097 /C0097/C0110/C0100 /C0111/C0116/C0104/C0101/C0114 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0097/C0114/C0101 /C0100/C0101/C0115/C0105/C0103/C0110 /C0103/C0111/C0097/C0108/C0115/C0046 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0114/C0101/C0115/C0101/C0114/C0118/C0101/C0115 /C0116/C0104/C0101 /C0114/C0105/C0103/C0104/C0116 /C0116/C0111 /C0099/C0104/C0097/C0110/C0103/C0101 /C0111/C0114 /C0100/C0105/C0115/C0099/C0111/C0110/C0116/C0105/C0110/C0117/C0101 /C0116/C0104/C0101/C0115/C0101 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0119/C0105/C0116/C0104/C0111/C0117/C0116 /C0110/C0111/C0116/C0105/C0099/C0101/C0046
/C0084/C0077/C0056/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0056 /C0051/C0056/C0056 /C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0049/C0054 /C0055/C0055/C0055 /C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS710 − MAY 1998
2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DUAL-IN-LINE MEMORY MODULE (TOP VIEW) TM16LR64JFN (SIDE VIEW) PIN NOMENCLATURE A[0:11] Row-Address Inputs A[0:8] Column-Address Inputs A13/BA0 Bank-Select Zero A12/BA1 Bank-Select One CAS Column-Address Strobe CB[0:7] Check Bit In/Check Bit Out CKE[0:1] Clock Enable CK[0:3] System Clock DQ[0:63] Data-In/Data-Out DQMB[0:7] Data-In/Data-Out Mask Enable NC No Connect RAS Row-Address Strobe S[0:3] Chip-Select SA[0:2] Serial Presence Detect (SPD) Device Address Input SCL SPD Clock SDA SPD Address/Data VDD 3.3-V Supply VSS Ground WE Write Enable WP Write Protect TM8LR64JFN (SIDE VIEW) PRODUCT PREVIEW
/C0084/C0077/C0056/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0056 /C0051/C0056/C0056 /C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0049/C0054 /C0055/C0055/C0055 /C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS710 − MAY 1998 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Pin Assignments PIN PIN PIN PIN NO. NAME NO. NAME NO. NAME NO. NAME
1 VSS 43 VSS 85 VSS 127 VSS
2 DQ0 44 NC 86 DQ32 128 CKE0
3 DQ1 45 S2 87 DQ33 129 S3
4 DQ2 46 DQMB2 88 DQ34 130 DQMB6
5 DQ3 47 DQMB3 89 DQ35 131 DQMB7
6 VDD 48 NC 90 VDD 132 NC
7 DQ4 49 VDD 91 DQ36 133 VDD
8 DQ5 50 NC 92 DQ37 134 NC
9 DQ6 51 NC 93 DQ38 135 NC
10 DQ7 52 CB2 94 DQ39 136 CB6
11 DQ8 53 CB3 95 DQ40 137 CB7
12 VSS 54 VSS 96 VSS 138 VSS
13 DQ9 55 DQ16 97 DQ41 139 DQ48
14 DQ10 56 DQ17 98 DQ42 140 DQ49
15 DQ11 57 DQ18 99 DQ43 141 DQ50
16 DQ12 58 DQ19 100 DQ44 142 DQ51
17 DQ13 59 VDD 101 DQ45 143 VDD
18 VDD 60 DQ20 102 VDD 144 DQ52
19 DQ14 61 NC 103 DQ46 145 NC
20 DQ15 62 NC 104 DQ47 146 NC
21 CB0 63 CKE1 105 CB4 147 NC
22 CB1 64 VSS 106 CB5 148 VSS
23 VSS 65 DQ21 107 VSS 149 DQ53
24 NC 66 DQ22 108 NC 150 DQ54
25 NC 67 DQ23 109 NC 151 DQ55
26 VDD 68 VSS 110 VDD 152 VSS
27 WE 69 DQ24 111 CAS 153 DQ56
28 DQMB0 70 DQ25 112 DQMB4 154 DQ57
29 DQMB1 71 DQ26 113 DQMB5 155 DQ58
30 S0 72 DQ27 114 S1 156 DQ59
31 NC 73 VDD 115 RAS 157 VDD
32 VSS 74 DQ28 116 VSS 158 DQ60
33 A0 75 DQ29 117 A1 159 DQ61
34 A2 76 DQ30 118 A3 160 DQ62
35 A4 77 DQ31 119 A5 161 DQ63
36 A6 78 VSS 120 A7 162 VSS
37 A8 79 CK2 121 A9 163 CK3
38 A10 80 NC 122 A13/BA0 164 NC
39 A12/BA1 81 WP 123 A11 165 SA0
40 VDD 82 SDA 124 VDD 166 SA1
41 VDD 83 SCL 125 CK1 167 SA2
42 CK0 84 VDD 126 NC 168 VDD
/C0084/C0077/C0056/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0056 /C0051/C0056/C0056 /C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0049/C0054 /C0055/C0055/C0055 /C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS710 − MAY 1998
4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
dual-in-line memory module and components The dual-in-line memory module and components include: /C0068PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage /C0068Bypass capacitors: Multilayer ceramic /C0068Contact area: Nickel plate and electroless gold-finished contacts over copper functional block diagram for the TM8LR64JFN
8 DQ[0:7]8
DQ[0:7] DQMB4 DQ[32:39] DQM DQ[0:7] DQM RAS RAS : SDRAM U[0:7] CK0 † CK: U1, U5 CK1 C SPD EEPROM SA0 SA1 SA2 A0 A1 A2 SDA DQ[8:15] DQMB5 DQ[40:47] DQM DQ[0:7] DQM R = 10 Ω R C = 10 Ω C = 10 pF DQ[16:23] DQMB6 DQ[48:55] DQM DQ[0:7] DQM DQ[24:31] DQMB7 DQ[56:63] DQM DQ[0:7] DQM CAS CAS : SDRAM U[0:7] WE WE : SDRAM U[0:7] CKE0 CKE: SDRAM U[0:7] A[0:13] A[0:13]: SDRAM U[0:7] R C R C R C VDD VSS One 0.1 µF and One 0.01 µF U[0:7] U[0:7] CK2 † CK: U2, U6 CK: U3, U7 CK3 C R C R C R C CK: U0, U4 SCL WP 47 kΩ LEGEND: CS = Chip select SPD = Serial Presence Detect † Additional 3.3 pF capacity is used to balance loads among clocks. PRODUCT PREVIEW
/C0084/C0077/C0056/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0056 /C0051/C0056/C0056 /C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0049/C0054 /C0055/C0055/C0055 /C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS710 − MAY 1998 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block diagram for the TM16LR64JFN CS CS R DQMB0 DQMB4 DQ[32:39] DQM DQM RAS RAS : U[0:7], UB[0:7] CK0 † CK: U0, U4 CK: U1, U5 SPD EEPROM SA0 SA1 SA2 A0 A1 A2 SDA DQ[8:15] DQMB5 DQ[40:47] DQM DQ[0:7] DQM R = 10 Ω R C = 10 Ω DQ[16:23] DQMB6 DQ[48:55] DQM DQ[0:7] DQM DQ[24:31] DQMB7 DQ[56:63] DQM DQ[0:7] DQM CAS CAS : U[0:7], UB[0:7] CKE0 CKE: U[0:7] WE WE: U[0:7], UB[0:7] R C R C VDD VSS U[0:7] U[0:7] CK1 † CK: UB0, UB4 CK: UB1, UB5 R C R C DQ[0:7] CS UB0 DQM CS UB1 DQM DQ[0:7] DQ[0:7] CS UB2 DQM CS UB3 DQM DQ[0:7] DQ[0:7] CS UB4 DQM CS UB5 DQM DQ[0:7] DQ[0:7] CS UB6 DQM CS UB7 DQM DQ[0:7] CKE1 CKE: UB[0:7] 10 kΩ VDD CK2 † CK: U2, U6 CK: U3, U7 R C R C CK3 † CK: UB2, UB6 CK: UB3, UB7 R C R C SCL WP 47 kΩ One 0.1 µF and One 0.01 µF † Additional 3.3 pF capacity is used to balance loads among clocks. PRODUCT PREVIEW
/C0084/C0077/C0056/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0056 /C0051/C0056/C0056 /C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0049/C0054 /C0055/C0055/C0055 /C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS710 − MAY 1998
6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
absolute maximum ratings over ambient temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VDD Supply voltage 3 3.3 3.6 V VSS Supply voltage 0 V VIH High-level input voltage 2 VDD + 0.3 V VIH-SPD High-level input voltage for SPD device 2 5.5 V VIL Low-level input voltage −0.3 0.8 V TA Ambient temperature 0 70 °C capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)‡ PARAMETER ’xLR64JFN UNITPARAMETER MIN MAX UNIT C i(CK) Input capacitance, CK input 2.5 4 pF C i(AC) Input capacitance, address and control inputs: A0−A13, RAS, CAS, WE 2.5 5 pF C i(CKE) Input capacitance, CKE input 5 pF C o Output capacitance 4 6.5 pF C i(DQMBx) Input capacitance, DQMBx input 2.5 5 pF C i(Sx) Input capacitance, Sx input 2.5 5 pF C i/o(SDA) SDA input/output capacitance 9 pF C i(SPD) Input capacitance, SA0, SA1, SA2, SCL inputs 7 pF ‡ Specifications in this table represent a single SDRAM device. NOTE 2: V DD = 3.3 V ± 0.3 V. Bias on pins under test is 0 V. PRODUCT PREVIEW
/C0084/C0077/C0056/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0056 /C0051/C0056/C0056 /C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0049/C0054 /C0055/C0055/C0055 /C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS710 − MAY 1998 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3)† PARAMETER TEST CONDITIONS ’xLR64JFN-8 ’xLR64JFN-8A UNITPARAMETER TEST CONDITIONS MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = − 2 mA 2.4 2.4 V VOL Low-level output voltage IOL = 2 mA 0.4 0.4 V II Input current (leakage) 0 V ≤ VI ≤ VDD + 0.3 V, All other pins = 0 V to VDD /C003410 /C003410 µA IO Output current (leakage) 0 V ≤ VO ≤ VDD + 0.3 V, Output disabled /C003410 /C003410 µA ICC1 Operating current Burst length = 1, tRC ≥ tRC MIN, CAS latency = 2 115 95 mAICC1 Operating current tRC ≥ tRC MIN, IOH /IOL = 0 mA (See Notes 4, 5, and 6)CAS latency = 3 125 95 mA ICC2P Precharge standby current in CKE ≤ VIL MAX, tCK = 15 ns (see Note 7) 1 1 ICC2PS Precharge standby current in power-down mode CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 8) 1 1 mA ICC2N Active standby current in CKE ≥ VIH MIN, tCK = 15 ns (see Note 7) 40 40 mAICC2NS Active standby current in non-power-down mode tCK = ∞ (see Note 8) 5 5 mA ICC3P Active standby current in CKE ≤ VIL MAX, tCK = 15 ns (see Notes 4 and 7) 5 5 mA ICC3PS Active standby current in power-down mode CKE and CK ≤ VIL MAX, tCK = ∞ (see Notes 4 and 8) 5 5 mA ICC3N Precharge standby current in CKE ≥ VIH MIN, tCK = 15 ns (see Notes 4 and 7) 50 50 ICC3NS Precharge standby current in non-power-down mode CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞ (see Notes 4 and 8) 10 10 mA ICC4 Burst current Page burst, IOH /IOL = 0 mA All banks activated, CAS latency = 2 165 120 mAICC4 Burst current OH OL All banks activated, nCCD = one cycle (see Notes 9 and 10) CAS latency = 3 225 165 mA ICC5 Auto-refresh current tRC ≤ tRC MIN CAS latency = 2 150 150 mAICC5 Auto-refresh current tRC ≤ tRC MIN (see Notes 5 and 8) CAS latency = 3 150 150 mA ICC6 Self-refresh current CKE ≤ VIL MAX 1 1 mA † Specifications in this table represent a single SDRAM device. NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Only one bank is activated. 5. tRC ≥ tRC MIN 6. Control and address inputs change state twice during tRC . 7. Control and address inputs change state once every 30 ns. 8. Control and address inputs do not change state (stable). 9. Control and address inputs change state once every cycle. 10. Continuous burst access, nCCD = 1 cycle PRODUCT PREVIEW
/C0084/C0077/C0056/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0056 /C0051/C0056/C0056 /C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0049/C0054 /C0055/C0055/C0055 /C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS710 − MAY 1998
8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ac timing requirements†‡ ’xLR64JFN-8 ’xLR64JFN-8A UNITMIN MAX MIN MAX UNIT tCK2 Cycle time, CK CAS latency = 2 10 15 ns tCK3 Cycle time, CK CAS latency = 3 8 8 ns tCH Pulse duration, CK high 3 3 ns tCL Pulse duraction, CK low 3 3 ns tAC2 Access time, CK high to data out (see Note 11) CAS latency = 2 6 7.5 ns tAC3 Access time, CK high to data out (see Note 11) CAS latency = 3 6 6 ns tOH Hold time, CK high to data out with 50-pF load 3 3 ns tLZ Delay time, CK high to DQ in low-impedance state (see Note 12) 1 1 ns tHZ Delay time, CK high to DQ in high-impedance state (see Note 13) 8 8 ns tIS Setup time, address, control, and data input 2 2 ns tIH Hold time, address, control, and data input 1 1 nstIH Hold time, address, control, and data input 1 1 ns tCESP Power down/self-refresh exit time 8 8 ns tRAS Delay time, ACTV command to DEAC or DCAB command 48 100000 48 100000 ns tRC Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR command 68 68 ns tRCD Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 14) 20 20 ns tRP Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command 20 20 ns tRRD Delay time, ACTV command in one bank to ACTV command in the other bank 16 16 ns tRSA Delay time, MRS command to ACTV, MRS, REFR, or SLFR command 16 16 ns tAPR Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command tRP −(CL−1) * tCK tRP − (CL−1) * tCK ns tAPW Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR commandtRP + 1 tCK tRP + 1 tCK ns tT Transition time 1 5 1 5 ms tREF Refresh interval 64 64 mstREF Refresh interval 64 64 ms nCCD Delay time, READ or WRT command to an interrupting command 1 1 cyclesnCCD Delay time, READ or WRT command to an interrupting command 1 1 cycles nCDD Delay time, CS low or high to input enabled or inhibited 0 0 0 0 cycles nCLE Delay time, CKE high or low to CLK enabled or disabled 1 1 1 1 cycles nCWL Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P1 1 cycles nDID Delay time, ENBL or MASK command to enabled or masked data in 0 0 0 0 cycles nDOD Delay time, ENBL or MASK command to enabled or masked data out 2 2 2 2 cycles nHZP2 Delay time, DEAC or DCAB command to DQ in high-impedance state CAS latency = 2 2 2 cycles † All references are made to the rising transition of CK unless otherwise noted. ‡ Specifications in this table represent a single SDRAM device. NOTES: 11. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CK that is read latency (one cycle after the READ command). Access time is measured at output reference level 1.4 V. 12. tLZ is measured from the rising transition of CK that is read latency (one cycle after the READ command). 13. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 14. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS . PRODUCT PREVIEW
/C0084/C0077/C0056/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0056 /C0051/C0056/C0056 /C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0049/C0054 /C0055/C0055/C0055 /C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS710 − MAY 1998 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ac timing requirements†‡ (continued) ’xLR64JFN-8 ’xLR64JFN-8A UNITMIN MAX MIN MAX UNIT nHZP3 Delay time, DEAC or DCAB command to DQ in high-impedance state CAS latency = 3 3 3 cycles nWCD Delay time, WRT command to first data in 0 0 0 0 cycles nWR Delay time, final data in of WRT operation to DEAC or DCAB command 1 1 cycles † All references are made to the rising transition of CK unless otherwise noted. ‡ Specifications in this table represent a single SDRAM device. PRODUCT PREVIEW
/C0084/C0077/C0056/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0056 /C0051/C0056/C0056 /C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0049/C0054 /C0055/C0055/C0055 /C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS710 − MAY 1998
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
The serial presence detect (SPD) is contained in a 256-byte serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing parameters (see Table 1 and Table 2). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. SPD contents of each TMxLR64JFN device are listed in the following tables: Table 1 −TM8LR64JFN Table 2 −TM16LR64JFN PRODUCT PREVIEW
Table 1. Serial Presence-Detect Data for the TM8LR64JFN
0 Defines number of bytes written into serial memory during module
1 Total number of bytes of SPD memory device 256 bytes 08h 256 bytes 08h
3 Number of row addresses on this assembly 12 0Ch 12 0Ch
4 Number of column addresses on this assembly 9 09h 9 09h
5 Number of module rows on this assembly 1 bank 01h 1 bank 01h
6 Data width of this assembly 64 bits 40h 64 bits 40h
7 Data width continuation 00h 00h
8 Voltage interface standard of this assembly LVTTL 01h LVTTL 01h
9 SDRAM cycle time at maximum supported CAS latency (CL), CL = XtCK = 8 ns 80h tCK = 8 ns 80h
10 SDRAM access from clock at CL = X tAC = 6 ns 60h tAC = 6 ns 60h
11 DIMM configuration type (non-parity, parity, error correcting code
13 SDRAM width, primary DRAM x8 08h x8 08h
14 Error-checking SDRAM data width N/A 00h N/A 00h
15 Minimum clock delay, back-to-back random column addresses 1 CK cycle 01h 1 CK cycle 01h
16 Burst lengths supported 1, 2, 4, 8 0Fh 1, 2, 4, 8 0Fh
17 Number of banks on each SDRAM device 4 banks 04h 4 banks 04h
18 CAS latencies supported 2, 3 06h 2, 3 06h
19 CS latency 0 01h 0 01h
20 Write latency 0 01h 0 01h
21 SDRAM module attributes Non-buffered/
22 SDRAM device attributes: general
23 Minimum clock cycle time at CL = X − 1 tCK = 10 ns A0h tCK = 15 ns F0h
25 Minimum clock cycle time at CL = X − 2 N/A 00h N/A 00h
26 Maximum data-access time from clock at CL = X − 2 N/A 00h N/A 00h
27 Minimum row-precharge time tRP = 20 ns 14h tRP = 20 ns 14h
12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 1. Serial Presence-Detect Data for the TM8LR64JFN (Continued)
28 Minimum row-active to row-active delay tRRD = 16 ns 10h tRRD = 16 ns 10h
29 Minimum RAS -to-CAS delay tRCD = 20 ns 14h tRCD = 20 ns 14h
30 Minimum RAS pulse width tRAS = 48 ns 30h tRAS = 48 ns 30h
31 Density of each bank on module 64M Bytes 10h 64M Bytes 10h
32 Command and address signal input setup time tIS = 2 ns 20h tIS = 2 ns 20h
33 Command and address signal input hold time tIH = 1 ns 10h tIH = 1 ns 10h
34 Data signal input setup time tIS = 2 ns 20h tIS = 2 ns 20h
35 Data signal input setup time tIH = 1 ns 10h tIH = 1 ns 10h
63 Checksum for byte 0−62 95 5Fh 196 C4h
64−71 Manufacturer’s JEDEC ID code per JEP−106E 97h 9700...
72 Manufacturing location† TBD TBD
73 Manufacturer’s part number T 54h T 54h
74 Manufacturer’s part number M 4Dh M 4Dh
75 Manufacturer’s part number 8 38h 8 38h
76 Manufacturer’s part number L 4Ch L 4Ch
77 Manufacturer’s part number R 52h R 52h
78 Manufacturer’s part number 6 36h 6 36h
79 Manufacturer’s part number 4 34h 4 34h
80 Manufacturer’s part number J 4Ah J 4Ah
81 Manufacturer’s part number F 46h F 46h
82 Manufacturer’s part number N 4Eh N 4Eh
83 Manufacturer’s part number — 2Dh — 2Dh
84 Manufacturer’s part number 8 38h 8 38h
85 Manufacturer’s part number SPACE 20h A 41h
91 Die revision code† TBD TBD
92 PCB revision code† TBD TBD
126 Clock frequency 100 MHz 64h 100 MHz 64h
127 SDRAM component and clock interconnection details 199 C7h 199 C7h
† TBD indicates values are determined at manufacturing time and are module-dependent. ‡ These TBD values are determined and programmed by the customer (optional).
Table 2. Serial Presence-Detect Data for the TM16LR64JFN
5 Number of module rows on this assembly 2 banks 02h 2 banks 02h
30 Minimum RAS pulse width tRAS = 48 ns 30h tRAS = 48 ns 32h
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Table 2. Serial Presence-Detect Data for the TM16LR64JFN (Continued)
35 Data signal input hold time tIH = 1 ns 10h tIH = 1 ns 10h
63 Checksum for byte 0−62 96 60h 197 C5h
64−71 Manufacturer’s JEDEC ID code per JEP−106E 97h 9700...
75 Manufacturer’s part number 1 31h 1 31h
76 Manufacturer’s part number 6 36h 6 36h
77 Manufacturer’s part number L 4Ch L 4Ch
78 Manufacturer’s part number R 52h R 52h
79 Manufacturer’s part number 6 36h 6 36h
80 Manufacturer’s part number 4 34h 4 34h
81 Manufacturer’s part number J 4Ah J 4Ah
82 Manufacturer’s part number F 46h F 46h
83 Manufacturer’s part number N 4Eh N 4Eh
84 Manufacturer’s part number — 2Dh — 2Dh
85 Manufacturer’s part number 8 38h 8 38h
86 Manufacturer’s part number SPACE 20h A 41h
127 SDRAM component and clock interconnection details 247 F7h 247 F7h
† TBD indicates values are determined at manufacturing time and are module-dependent. ‡ These TBD values are determined and programmed by the customer (optional).
/C0084/C0077/C0056/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0056 /C0051/C0056/C0056 /C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0049/C0054 /C0055/C0055/C0055 /C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS710 − MAY 1998 15POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device symbolization (TM8LR64JFN) TM8LR64JFN YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE A: Location of symbolization may vary. Unbuffered Key Position 3.3-V Voltage Key Position PRODUCT PREVIEW
/C0084/C0077/C0056/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0056 /C0051/C0056/C0056 /C0054/C0048/C0056 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0076/C0082/C0054/C0052/C0074/C0070/C0078 /C0049/C0054 /C0055/C0055/C0055 /C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS710 − MAY 1998
16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
BVC (R-PDIM-N168) DUAL-IN-LINE MEMORY MODULE 0.118 (3,00) TYP 1.550 (39,37) 1.450 (36,83) 0.700 (17,78) TYP 0.014 (0,35) MAX 0.046 (1,17) 0.054 (1,37) 4088193/A 05/98 0.157 (4,00) MAX (For Double-Sided DIMM Only) 0.106 (2,70) MAX (Note D) 5.245 (133,22) 0.118 (3,00) DIA
2 Places
0.125 (3,18) 0.039 (1,00) TYP 5.255 (133,48) Notch 0.157 (4,00) x 0.122 (3,10) Deep Notch 0.079 (2,00) x 0.122 (3,10) Deep 0.125 (3,18) 0.050 (1,27) NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-161 D. Dimension includes depanelization variations; applies between notch and tab edge. E. Outline may vary above notches to allow router/panelization irregularities. PRODUCT PREVIEW
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