TM16EN64HPU TI1 | Alldatasheet
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Technical content
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Organization − TM16EN64xPU-xx ...1 6 7 7 7216 × 64 Bits − TM16EN72xPU-xx ...1 6 7 7 7216 × 72 Bits /C0068Single 3.3-V Power Supply (±10% Tolerance) /C0068JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket /C0068TM16EN64HPUxx — Utilizes Sixteen 64M-Bit High-Speed (16M×4-Bit) Dynamic RAMs /C0068TM16EN72HPUxx — Utilizes Eighteen 64M-Bit High-Speed (16M×4-Bit) Dynamic RAMs /C0068High-Speed, Low-Noise LVTTL Interface /C0068High-Reliability 32-Lead 300-Mil-Wide Surface-Mount Thin Small-Outline Package (TSOP) (DGC Suffix) /C0068Long Refresh Periods: − TM16ENxxHPU: 64 ms (4096 Cycles) − TM16ENxxLPU: 64 ms (8192 Cycles) /C00683-State Output /C0068Extended-Data-Out (EDO) Operation With CAS -Before-RAS (CBR), RAS-Only, and Hidden Refresh /C0068Serial Presence-Detect (SPD) Using EEPROM /C0068Ambient Temperature Range 0°C to 70°C /C0068Gold-Plated Contacts /C0068Performance Ranges ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE tRAC tCAC tAA tHPC (MAX) (MAX) (MAX) (MIN) ’16ENxxxPU-40 40 ns 11 ns 20 ns 16 ns ’16ENxxxPU-50 50 ns 13 ns 25 ns 20 ns ’16ENxxxPU-60 60 ns 15 ns 30 ns 25 ns
description
The TM16EN64HPU is a 128M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of sixteen TMS465409, 16777216 × 4-bit 4K-refresh EDO dynamic random-access memories (DRAMs), each in a 400-mil, 32-pin plastic thin small-outline package (TSOP) (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895). The TM16EN64LPU is a 128M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS464409, 16777216 × 4-bit 8K-refresh EDO dynamic random-access memories (DRAMs), each in a 400-mil, 32-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895). The TM16EN72HPU is a 128M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS465409, 16777216 × 4-bit 4K-refresh EDO dynamic random-access memories (DRAMs), each in a 400-mil, 32-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895). The TM16EN72LPU is a 128M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS464409, 4194309 × 4-bit 8K-refresh EDO dynamic random-access memories (DRAMs), each in a 400-mil, 32-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895). operation The TM16EN64xPU operates as sixteen TMS46x409s that are connected as shown in the TM16EN64xPU functional block diagram. The TM16EN72xPU operates as eighteen TMS46x409s that are connected as shown in the TM16EN72xPU functional block diagram. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW Copyright 1997, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084 /C0080/C0082/C0069/C0086/C0073/C0069/C0087 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0099/C0111/C0110/C0099/C0101/C0114/C0110/C0115 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0105/C0110 /C0116/C0104/C0101 /C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0118/C0101 /C0111/C0114 /C0100/C0101/C0115/C0105/C0103/C0110 /C0112/C0104/C0097/C0115/C0101 /C0111/C0102 /C0100/C0101/C0118/C0101/C0108/C0111/C0112/C0109/C0101/C0110/C0116/C0046 /C0067/C0104/C0097/C0114/C0097/C0099/C0116/C0101/C0114/C0105/C0115/C0116/C0105/C0099 /C0100/C0097/C0116/C0097 /C0097/C0110/C0100 /C0111/C0116/C0104/C0101/C0114 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0097/C0114/C0101 /C0100/C0101/C0115/C0105/C0103/C0110 /C0103/C0111/C0097/C0108/C0115/C0046 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0114/C0101/C0115/C0101/C0114/C0118/C0101/C0115 /C0116/C0104/C0101 /C0114/C0105/C0103/C0104/C0116 /C0116/C0111 /C0099/C0104/C0097/C0110/C0103/C0101 /C0111/C0114 /C0100/C0105/C0115/C0099/C0111/C0110/C0116/C0105/C0110/C0117/C0101 /C0116/C0104/C0101/C0115/C0101 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0119/C0105/C0116/C0104/C0111/C0117/C0116 /C0110/C0111/C0116/C0105/C0099/C0101/C0046
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997
2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DUAL-IN-LINE MEMORY MODULE (TOP VIEW) TM16EN72HPU (SIDE VIEW) PIN NOMENCLATURE − TM16ENxxHPU A[0:11] Row Address Inputs A[0:11] Column Address Inputs DQ[0:63] Data In/Data Out CB[0:7] Check Bit In/Check Bit Out CAS[0:7] Column-Address Strobe RAS0 and RAS2 Row-Address Strobe WE0 and WE2 Write Enable OE0 and OE2 Output Enable SA[0:2] Serial Presence-Detect (SPD) Device Add Input SDA SPD Address/Data SCL SPD Clock NC No-Connect Pin VDD 3.3-V Supply VSS Ground TM16EN64HPU (SIDE VIEW) PIN NOMENCLATURE − TM16ENxxLPU A[0:12] Row Address Inputs A[0:10] Column Address Inputs DQ[0:63] Data In/Data Out CB[0:7] Check Bit In/Check Bit Out CAS[0:7] Column-Address Strobe RAS0 and RAS2 Row-Address Strobe WE0 and WE2 Write Enable OE0 and OE2 Output Enable SA[0:2] Serial Presence-Detect (SPD) Device Add Input SDA SPD Address/Data SCL SPD Clock NC No-Connect Pin VDD 3.3-V Supply VSS Ground PRODUCT PREVIEW
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Pin Assignments PIN PIN PIN PIN NO. NAME NO. NAME NO. NAME NO. NAME
1 VSS 43 VSS 85 VSS 127 VSS
2 DQ0 44 OE2 86 DQ32 128 NC
3 DQ1 45 RAS2 87 DQ33 129 NC
4 DQ2 46 CAS2 88 DQ34 130 CAS6
5 DQ3 47 CAS3 89 DQ35 131 CAS7
6 VDD 48 WE2 90 VDD 132 NC
7 DQ4 49 VDD 91 DQ36 133 VDD
8 DQ5 50 NC 92 DQ37 134 NC
9 DQ6 51 NC 93 DQ38 135 NC
10 DQ7 52 CB2 94 DQ39 136 CB6
11 DQ8 53 CB3 95 DQ40 137 CB7
12 VSS 54 VSS 96 VSS 138 VSS
13 DQ9 55 DQ16 97 DQ41 139 DQ48
14 DQ10 56 DQ17 98 DQ42 140 DQ49
15 DQ11 57 DQ18 99 DQ43 141 DQ50
16 DQ12 58 DQ19 100 DQ44 142 DQ51
17 DQ13 59 VDD 101 DQ45 143 VDD
18 VDD 60 DQ20 102 VDD 144 DQ52
19 DQ14 61 NC 103 DQ46 145 NC
20 DQ15 62 NC 104 DQ47 146 NC
21 CB0 63 NC 105 CB4 147 NC
22 CB1 64 VSS 106 CB5 148 VSS
23 VSS 65 DQ21 107 VSS 149 DQ53
24 NC 66 DQ22 108 NC 150 DQ54
25 NC 67 DQ23 109 NC 151 DQ55
26 VDD 68 VSS 110 VDD 152 VSS
27 WE0 69 DQ24 111 NC 153 DQ56
28 CAS0 70 DQ25 112 CAS4 154 DQ57
29 CAS1 71 DQ26 113 CAS5 155 DQ58
30 RAS0 72 DQ27 114 NC 156 DQ59
31 OE0 73 VDD 115 NC 157 VDD
32 VSS 74 DQ28 116 VSS 158 DQ60
33 A0 75 DQ29 117 A1 159 DQ61
34 A2 76 DQ30 118 A3 160 DQ62
35 A4 77 DQ31 119 A5 161 DQ63
36 A6 78 VSS 120 A7 162 VSS
37 A8 79 NC 121 A9 163 NC
38 A10 80 NC 122 A11 164 NC
39 A12 81 NC 123 NC 165 SA0
40 VDD 82 SDA 124 VDD 166 SA1
41 NC 83 SCL 125 NC 167 SA2
42 NC 84 VDD 126 NC 168 VDD
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997
4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
dual-in-line memory module and components The dual-in-line memory module and components include: /C0068PC substrate: 1,27 /C0034 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage /C0068Bypass capacitors: Multilayer ceramic /C0068Contact area: Nickel plate and gold plate over copper functional block diagram for the TM16EN64xPU CAS OE W RAS RAS0 WE0 OE0 CAS0 DQ[0:3] CAS OE W RAS UB0 RAS2 WE2 OE2 CAS4 DQ[32:35] A0 A1 A2 SCL SDA SA0 SA1 SA2 SPD EEPROM DQ[0:3] DQ[0:3] CAS OE W RAS U1DQ[4:7] CAS OE W RAS UB1DQ[36:39]DQ[0:3] DQ[0:3] CAS OE W RAS CAS1 DQ[8:11] CAS OE W RAS UB2 CAS5 DQ[40:43]DQ[0:3] DQ[0:3] CAS OE W RAS U3DQ[12:15] CAS OE W RAS UB3DQ[44:47]DQ[0:3] DQ[0:3] CAS OE W RAS CAS2 DQ[16:19] CAS OE W RAS UB4 CAS6 DQ[48:51]DQ[0:3] DQ[0:3] CAS OE W RAS U5DQ[20:23] CAS OE W RAS UB5DQ[52:55]DQ[0:3] DQ[0:3] CAS OE W RAS CAS3 DQ[24:27] CAS OE W RAS UB6 CAS7 DQ[56:59]DQ[0:3] DQ[0:3] CAS OE W RAS U7DQ[28:31] CAS OE W RAS UB7DQ[60:63]DQ[0:3] DQ[0:3] TM16EN64HPU TM16EN64LPU LEGEND: CS = Chip select SPD = Serial Presence Detect PRODUCT PREVIEW
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block diagram for the TM16EN72xPU CAS OE W RAS RAS0 WE0 OE0 CAS0 DQ[0:3] CAS OE W RAS UB0 RAS2 WE2 OE2 CAS4 DQ[32:35] A0 A1 A2 SCL SDA SA0 SA1 SA2 SPD EEPROM DQ[0:3] DQ[0:3] CAS OE W RAS U1DQ[4:7] CAS OE W RAS UB1DQ[36:39]DQ[0:3] DQ[0:3] CAS OE W RAS CAS1 DQ[8:11] CAS OE W RAS UB2 CAS5 DQ[40:43]DQ[0:3] DQ[0:3] CAS OE W RAS U3DQ[12:15] CAS OE W RAS UB3DQ[44:47]DQ[0:3] DQ[0:3] CAS OE W RAS CAS2 DQ[16:19] CAS OE W RAS UB4 CAS6 DQ[48:51]DQ[0:3] DQ[0:3] CAS OE W RAS U5DQ[20:23] CAS OE W RAS UB5DQ[52:55]DQ[0:3] DQ[0:3] CAS OE W RAS CAS3 DQ[24:27] CAS OE W RAS UB6 CAS7 DQ[56:59]DQ[0:3] DQ[0:3] CAS OE W RAS U7DQ[28:31] CAS OE W RAS UB7DQ[60:63]DQ[0:3] DQ[0:3] CAS OE W RAS CAS1 CB[0:3] CAS OE W RAS UB8 CAS5 CB[4:7]DQ[0:3] DQ[0:3] TM16EN72HPU TM16EN72LPU PRODUCT PREVIEW
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997
6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
absolute maximum ratings over ambient temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VDD Supply voltage 3 3.3 3.6 V VSS Supply voltage 0 V VIH High-level input voltage 2 VDD + 0.3 V VIH−SPD High-level input voltage for the SPD device 2 5.5 V VIL Low-level input voltage −0.3 0.8 V TA Ambient temperature 0 70 °C PRODUCT PREVIEW
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) TM16EN64HPU PARAMETER TEST CONDITIONS † ’16EN64HPU-40 ’16EN64HPU-50 ’16EN64HPU-60 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 20 ± 20 ± 20 µA ICC1 ‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 2560 2080 1760 mA Average VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 16 16 16 mA ICC2 Average standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 8 8 8 mA ICC3 ‡§ Average refresh current (RASx-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) 2560 2080 1760 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 2400 1920 1600 mA ICC5 ‡¶ Average CBR refresh current VDD = 3.6 V, Minimum cycle, RASx low after CASx low 2560 2080 1760 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC PRODUCT PREVIEW
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997
8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM16EN64LPU PARAMETER TEST CONDITIONS † ’16EN64LPU-40 ’16EN64LPU-50 ’16EN64LPU-60 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 20 ± 20 ± 20 µA ICC1 ‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 2000 1600 1440 mA Average VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 16 16 16 mA ICC2 Average standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 8 8 8 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) 2000 1600 1440 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 2240 1760 1440 mA ICC5 ‡§ Average CBR refresh current VDD = 3.6 V, Minimum cycle, RASx low after CASx low 2560 2080 1760 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC PRODUCT PREVIEW
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM16EN72HPU PARAMETER TEST CONDITIONS † ’16EN72HPU-40 ’16EN72HPU-50 ’16EN72HPU-60 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 20 ± 20 ± 20 µA ICC1 ‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 2880 2340 1980 mA Average VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 18 18 36 mA ICC2 Average standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 9 9 9 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) 2880 2340 1980 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 2700 2160 1800 mA ICC5 ‡§ Average CBR refresh current VDD = 3.6 V, Minimum cycle, RASx low after CASx low 2880 2340 1980 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC PRODUCT PREVIEW
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM16EN72LPU PARAMETER TEST CONDITIONS † ’16EN72LPU-40 ’16EN72LPU-50 ’16EN72LPU-60 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 VVOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 VVOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, V I = 0 V to 3.9 V, All others = 0 V to VDD ± 20 ± 20 ± 20 µA IO Output current (leakage) VDD = 3.6 V, V O = 0 V to VDD , CASx high ± 20 ± 20 ± 20 µA ICC1 ‡§ Average read- or write-cycle current VDD = 3.6 V, Minimum cycle 2250 1800 1620 mA Average VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 18 18 18 mA ICC2 Average standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 9 9 9 mA ICC3 ‡§ Average refresh current (RAS -only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RASx-only refresh), RASx low after CASx low (CBR) 2250 1800 1620 mA ICC4 ‡¶ Average EDO current VDD = 3.6 V, t HPC = MIN, RASx low, CASx cycling 2520 1980 1620 mA ICC5 ‡§ Average CBR refresh current VDD = 3.6 V, Minimum cycle, RASx low after CASx low 2880 2340 1980 mA † For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL¶ Measured with a maximum of one address change during each EDO cycle, tHPC PRODUCT PREVIEW
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2) PARAMETER ’16EN64xPU ’16EN72xPU UNITPARAMETER MIN MAX MIN MAX UNIT C i(A) Input capacitance, A0−A12 82 92 pF C i(OE) Input capacitance, OEx 58 65 pF C i(CAS) Input capacitance, CASx 16 23 pF C i(RAS) Input capacitance, RASx 58 65 pF C i(W) Input capacitance, WEx 58 65 pF C o Output capacitance 8 8 pF NOTE 2: V DD = NOM supply voltage ±10%, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 3) PARAMETER ’16ENxxxPU-40 ’16ENxxxPU-50 ’16ENxxxPU-60 UNITPARAMETER MIN MAX MIN MAX MIN MAX UNIT tAA Access time from column address (see Note 4) 20 25 30 ns tCAC Access time from CASx (see Note 4) 11 13 15 ns tCPA Access time from CASx precharge (see Note 4) 22 28 35 ns tRAC Access time from RASx (see Note 4) 40 50 60 ns tOEA Access time from OEx (see Note 4) 11 13 15 ns tCLZ Delay time, CASx to output in low impedance 0 0 0 ns tREZ Output buffer turn off delay from RASx (see Note 5) 3 11 3 13 3 15 ns tCEZ Output buffer turn off delay from CASx (see Note 5) 3 11 3 13 3 15 ns tOEZ Output buffer turn off delay from OEx (see Note 5) 3 11 3 13 3 15 ns tWEZ Output buffer turn off delay from WEx (see Note 5) 3 11 3 13 3 15 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 5. The maximum values of tREZ , tCEZ , tOEZ , and tWEZ are specified when the output is no longer driven. Data in should not be driven until one of the applicable maximum specs is satisfied. EDO timing requirements ’16ENxxxPU-40 ’16ENxxxPU-50 ’16ENxxxPU-60 UNITMIN MAX MIN MAX MIN MAX UNIT tHPC Cycle time, EDO page mode, read-write 16 20 25 ns tPRWC Cycle time, EDO read-write 47 57 68 ns tCSH Delay time, RASx active to CASx precharge 32 40 48 ns tCHO Hold time, OEx from CASx 5 5 5 ns tDOH Hold time, output from CASx 5 5 5 ns tCAS Pulse duration, CASx active (see Note 6) 6 10000 8 10000 10 10000 ns tWPE Pulse duration, WEx active (output disable only) 5 5 5 ns tOCH Setup time, OEx before CASx 5 5 5 ns tCP Pulse duration, CASx precharge 6 8 10 ns tOEP Precharge time, OEx 5 5 5 ns NOTE 6: In a read-write cycle, tCWD and tCWL must be observed. PRODUCT PREVIEW
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997
12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
’16ENxxxPU-40 ’16ENxxxPU-50 ’16ENxxxPU-60 UNITMIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, random read or write 69 84 104 ns tRWC Cycle time, read-write 92 111 135 ns tRASP Pulse duration, RASx active, fast page mode (see Note 7) 40 100 000 50 100 000 60 100 000 ns tRAS Pulse duration, RASx active, non-page mode (see Note 7) 40 10 000 50 10 000 60 10 000 ns tRP Pulse duration, RASx precharge 25 30 40 ns tWP Pulse duration, write command 6 8 10 ns tRASS Pulse duration, RASx active, self refresh (see Note 8) 100 100 100 /C0109s tRPS Pulse duration, RASx precharge after self refresh 70 90 110 ns tASC Setup time, column address 0 0 0 ns tASR Setup time, row address 0 0 0 ns tDS Setup time, data in (see Note 9) 0 0 0 ns tRCS Setup time, read command 0 0 0 ns tCWL Setup time, write command before CASx precharge 6 8 10 ns tRWL Setup time, write command before RASx precharge 6 8 10 ns tWCS Setup time, write command before CASx active (early-write only) 0 0 0 ns tWRP Setup time, WEx high before RASx low (CBR refresh only) 5 5 5 ns tWTS Setup time, WEx low before RASx low (test mode only) 5 5 5 ns tCSR Setup time, CASx referenced to RASx (CBR refresh only) 5 5 5 ns tCAH Hold time, column address 6 8 10 ns tDH Hold time, data in (see Note 9) 6 8 10 ns tRAH Hold time, row address 6 8 10 ns tRCH Hold time, read command referenced to CASx (see Note 10) 0 0 0 ns tRRH Hold time, read command referenced to RASx (see Note 10) 0 0 0 ns tWCH Hold time, write command during CASx active (early-write only) 6 8 10 ns tROH Hold time, RASx referenced to OEx 6 8 10 ns tWRH Hold time, WEx high after RASx low (CBR refresh) 6 8 10 ns tWTH Hold time, WEx low after RASx low (test mode only) 6 8 10 ns tCHR Hold time, CASx referenced to RASx (CBR refresh only) 6 8 10 ns tOEH Hold time, OEx command 11 13 15 ns tCHS Hold time, CASx active after RASx precharge (self-refresh)−50 −50 −50 ns tRHCP Hold time, RASx active from CASx precharge 22 28 35 ns NOTES: 7. In a read-write cycle, tRWD and tRWL must be observed. 8. During the period of 10 /C0109s /C0020 tRASS /C0020 100 /C0109s, the device is in transition state from normal operation mode to self-refresh mode. 9. Referenced to the later of CASx or WEx in write operations 10. Either tRRH or tRCH must be satisfied for a read cycle. PRODUCT PREVIEW
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997 13POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 ac timing requirements (continued) ’16ENxxxPU-40 ’16ENxxxPU-50 ’16ENxxxPU-60 UNITMIN MAX MIN MAX MIN MAX UNIT tAWD Delay time, column address to write command (read-write only) 35 42 49 ns tCPW Delay time, WEx low after CASx precharge (read-write only)37 45 54 ns tCRP Delay time, CASx precharge to RASx 5 5 5 ns tCWD Delay time, CASx to write command (read-write only) 26 30 34 ns tOED Delay time, OEx to data in 11 13 15 ns tRAD Delay time, RASx to column address (see Note 11) 8 20 10 25 12 30 ns tRAL Delay time, column address to RASx precharge 20 25 30 ns tCAL Delay time, column address to CASx precharge 12 15 18 ns tRCD Delay time, RASx to CASx (see Note 11) 10 29 12 37 14 45 ns tRPC Delay time, RASx precharge to CASx 5 5 5 ns tRSH Delay time, CASx active to RASx precharge 6 8 10 ns tRWD Delay time, RASx to write command (read-write only) 55 67 79 ns tTAA Access time from address (test mode) 25 30 35 ns tTCPA Access time, from column precharge (test mode) 30 35 40 ns tTRAC Access time, from RASx (test mode) 45 55 65 ns tT Transition time 1 50 1 50 1 50 ns tREF Refresh time interval 64 64 64 ms NOTE 11: The maximum value is specified only to ensure access time. PRODUCT PREVIEW
14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
(SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. Table 1. Serial-Presence-Detect Data for the TM16EN64HPU
1 Total number of bytes of SPD memory
2 Fundamental memory type (FPM, EDO,
3 Number of row addresses on this
4 Number of column addresses on this
5 Number of module banks on this
6 Data width of this assembly 64 bits 40h 64 bits 40h 64 bits 40h
7 Data width continuation 00h 00h 00h
8 Voltage interface standard of this
9 RASx access time of module tRAC =40 ns 28h tRAC =50 ns 32h tRAC =60 ns 3Ch
10 CASx access time of module tCAC =11ns 0Bh tCAC =13ns 0Dh tCAC =15ns 0Fh
11 DIMM configuration type (non-parity,
13 DRAM width, primary DRAM x4 04h x4 04h x4 04h
14 Error-checking SDRAM data width N/A 00h N/A 00h N/A 00h
63 Checksum for bytes 0−62 26 1Ah 38 26h 50 32h
72 Manufacturing location† TBD TBD TBD
91 Die revision code† TBD TBD TBD
† TBD indicates values are determined at manufacturing time and are module dependent.
Table 1. Serial Presence-Detect Data for the TM16EN64HPU (Continued)
92 PCB revision code† TBD TBD TBD
† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).
16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 2. Serial-Presence-Detect Data for the TM16EN64LPU
10 CASx access time of module tCAC =11 ns 0Bh tCAC =13 ns 0Dh tCAC =15 ns 0Fh
63 Checksum for bytes 0−62 36 1Ah 38 26h 50 32h
† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).
Table 3. Serial-Presence-Detect Data for the TM16EN72HPU
6 Data width of this assembly 72 bits 48h 72 bits 48h 72 bits 48h
14 Error-checking SDRAM data width x4 04h x4 04h x4 04h
63 Checksum for bytes 0−62 40 28h 52 34h 64 40h
† TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).
18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 4. Serial-Presence-Detect Data for the TM16EN72LPU † TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional).
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997 19POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device symbolization (TM16EN64HPU illustrated) -SS YYMMT YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE A: Location of symbolization may vary. Unbuffered Key Position 3.3-V Voltage Key Position TM16EN64HPU PRODUCT PREVIEW
/C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0054/C0052/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0054/C0052/C0262/C0066/C0073/C0084 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0072/C0080/C0085/C0044 /C0084/C0077/C0049/C0054/C0069/C0078/C0055/C0050/C0076/C0080/C0085 /C0049/C0054/C0257/C0055/C0055/C0055/C0257/C0050/C0049/C0054 /C0066/C0089 /C0055/C0050/C0262/C0066/C0073/C0084 /C0069/C0088/C0084/C0069/C0078/C0068/C0069/C0068/C0262/C0068/C0065/C0084/C0065/C0262/C0079/C0085/C0084 /C0068/C0089/C0078/C0065/C0077/C0073/C0067 /C0082/C0065/C0077 /C0077/C0079/C0068/C0085/C0076/C0069/C0083 SMMS695A − AUGUST 1997 − REVISED NOVEMBER 1997
20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
BS (R-PDIM-N168) DUAL IN-LINE MEMORY MODULE 0.118 (3,00) TYP 1.130 (28,70) 1.120 (28,45) 0.700 (17,78) TYP 0.014 (0,35) MAX 0.106 (2,70) MAX 0.054 (1,37) 0.046 (1,17) 4088181/A 06/97 0.157 (4,00) MAX (For Double Sided DIMM Only) (Note D) 5.255 (133,48) 5.245 (133,22) 0.118 (3,00) DIA
2 Places
0.125 (3,18) 0.039 (1,00) TYP Notch 0.157 (4,00) x 0.122 (3,10) Deep Notch 0.079 (2,00) x 0.122 (3,10) Deep 0.125 (3,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-161 D. Dimension includes De−panelization variations; applies between notch and tab edge. E. Outline may vary above notches to allow router/panelization irregularities. PRODUCT PREVIEW
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