TM124FBK32S-60

TM124FBK32 TI | Alldatasheet

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TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C0068Organization TM124FBK32 ...10 4 85 7 6 × 32 TM248GBK32 ...2 097 152 × 32 /C0068Single 5-V Power Supply /C006872-pin Single In-Line Memory Module (SIMM) for Use With Sockets /C0068TM124FBK32 Utilizes Eight 4M-Bit Dynamic RAMs (DRAMs) in Plastic Small-Outline J-Lead (SOJ) Packages /C0068TM248GBK32 Utilizes Sixteen 4M-Bit DRAMs in Plastic SOJ Packages /C0068Long Refresh Period 16 ms (1024 Cycles) /C0068All Inputs, Outputs, Clocks Fully TTL Compatible /C00683-State Output /C0068Common CAS Control for Eight Common Data-In and Data-Out Lines, In Four Blocks /C0068Extended Data-Out (EDO) Operation With CAS -Before-RAS (CBR), RAS-Only, and Hidden Refresh /C0068JEDEC First Generation 72-Pin SIMM Pinout /C0068Presence Detect /C0068Performance Ranges: ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE tRAC tAA tCAC tHPC (MAX) (MAX) (MIN) (MIN) ’124FBK32-60 60 ns 30 ns 15 ns 25 ns ’124FBK32-70 70 ns 35 ns 18 ns 30 ns ’124FBK32-80 80 ns 40 ns 20 ns 35 ns ’248GBK32-60 60 ns 30 ns 15 ns 25 ns ’248GBK32-70 70 ns 35 ns 18 ns 30 ns ’248GBK32-80 80 ns 40 ns 20 ns 35 ns /C0068Low Power Dissipation /C0068Operating Free-Air Temperature Rang e...0 °C to 70°C /C0068Gold-Tabbed Versions Available:† – TM124FBK32 – TM248GBK32 /C0068Tin-Lead- (Solder-) Tabbed Versions Available: – TM124FBK32S – TM248GBK32S

description

The TM124FBK32 is a 4M-byte DRAM organized as four times 1 048 576 × 8 in a 72-pin leadless SIMM. The SIMM is composed of eight TMS44409, 1 048 576 × 4-bit DRAMs, each in a 20/26-lead plastic SOJ package, mounted on a substrate together with decoupling capacitors. Each TMS44409 is described in the TMS44409 data sheet. The TM124FBK32 is available in the single-sided BK leadless module for use with sockets. TM248GBK32 The TM248GBK32 is a 8M-byte DRAM organized as four times 2 097 152 × 8 in a 72-pin leadless SIMM. The SIMM is composed of sixteen TMS44409, 1 048 576 × 4-bit DRAMs, each in a 20/26-lead plastic SOJ package, mounted on a substrate together with decoupling capacitors. Each TMS44409 is described in the TMS44409 data sheet. The TM248GBK32 is available in the double-sided BK leadless module for use with sockets. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1996, Texas Instruments Incorporated † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996

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The TM124FBK32 operates as eight TMS44409DJs connected as shown in the functional block diagram. Refer to the TMS44409 data sheet for details of operation. The common I/O feature of the TM124FBK32 dictates the use of early write cycles to prevent contention on D and Q. TM248GBK32 The TM248GBK32 operates as sixteen TMS44409DJs connected as shown in the functional block diagram. Refer to the TMS44409 data sheet for details of operation. The common I/O feature of the TM248GBK32 dictates the use of early write cycles to prevent contention on D and Q. specifications Refresh period is extended to 16 ms and, during this period, each of the 1024 rows must be strobed with RAS in order to retain data. A0–A9 address lines must be refreshed every 16 ms as required by the TMS44409 DRAM. CAS can remain high during the refresh sequence to conserve power. single in-line memory module and components PC substrate: 1,27± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM124FBK32 and TM248GBK32: Nickel plate and gold plate over copper Contact area for TM124FBK32S and TM248GBK32S: Nickel plate and tin-lead over copper

W NC RAS1 RAS0 CAS1 CAS3 CAS2 CAS0 VSS NC NC NC NC RAS2 RAS3 VCC NC DQ23 DQ7 DQ22 DQ6 DQ21 DQ5 DQ20 DQ4 NC NC VCC DQ19 DQ3 DQ18 DQ2 DQ17 DQ1 DQ16 DQ0 VSS † The packages shown here are for pinout reference only and are not drawn to scale. PIN NOMENCLATURE A0–A9 Address Inputs CAS0 , CAS3 Column-Address Strobe DQ0–DQ31 Data In/Data Out NC No Connection PD1– PD4 Presence Detects RAS0 –RAS3 Row-Address Strobe VCC 5-V Supply VSS Ground W Write Enable TM248GBK32 † (SIDE VIEW) TM124FBK32 † (SIDE VIEW) BK SINGLE IN-LINE PACKAGE † (TOP VIEW) TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 3POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PRESENCE DETECT SIGNAL (PIN) PD1 (67) PD2 (68) PD3 (69) PD4 (70) 80 ns VSS VSS NC VSS TM124FBK32 70 ns VSS VSS VSS NC 60 ns VSS VSS NC NC 80 ns NC NC NC VSS TM248GBK32 70 ns NC NC VSS NC 60 ns NC NC NC NC

TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 Temp late R elease D ate: 7–11–94

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functional block diagram (for TM124FBK32 and TM248GBK32, Side 1) 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 A0–A9 DQ0– DQ3 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 DQ8– DQ11 DQ16– DQ19 DQ24– DQ27 DQ4– DQ7 DQ12– DQ15 DQ20– DQ23 DQ28– DQ31 W RAS0 CAS0 CAS1 CAS2 CAS3 RAS2 10 10 10 10 10 10 10 10

TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443• 5 functional block diagram (for TM248GBK32, Side 2) 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 A0–A9 DQ0– DQ3 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 DQ8– DQ11 DQ16– DQ19 DQ24– DQ27 DQ4– DQ7 DQ12– DQ15 DQ20– DQ23 DQ28– DQ31 W RAS1 CAS0 CAS1 CAS2 CAS3 RAS3 10 10 10 10 10 10 10 10

TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) – 1 0.8 V TA Operating free-air temperature 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic voltage levels only. electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS ’124FBK32-60 ’124FBK32-70 ’124FBK32-80 UNITPARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VI = 0 to 6.5 V, VCC = 5 V, All other pins = 0 to VCC ±10 ±10 ±10 µA IO Output current (leakage) VO = 0 to VCC ,V CC = 5.5 V, CAS high ±10 ±10 ±10 µA ICC1 Read- or write-cycle current (see Note 3) Minimum cycle, V CC = 5.5 V 840 720 640 mA ICC1 Standby current After one memory cycle, RAS and CAShigh, VIH=2.4 V (TTL) 16 16 16 mAICC1 Standby current After one memory cycle, RAS and CAShigh, VIH = VCC – 0.2 V (CMOS) 8 8 8 mA ICC3 Average refresh current (RAS -only or CBR) (see Note 3) Minimum cycle, V CC = 5.5 V, RAS cycling, CAS high (RAS-only), RAS low after CAS low (CBR) 840 720 640 mA ICC4 Average page current (see Note 4) tPC = minimum, V CC = 5.5 V, RAS low, CAS cycling 720 640 560 mA NOTES: 3. Measured with a maximum of one address change while RAS = VIL. 4. Measured with a maximum of one address change while CAS = VIH.

TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS ’248GBK32-60 ’248GBK32-70 ’248GBK32-80 UNITPARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VI = 0 to 6.5 V, VCC = 5 V, All other pins = 0 to VCC ±20 ±20 ±20 µA IO Output current (leakage) VO = 0 to VCC ,V CC = 5.5 V, CAS high ±20 ±20 ±20 µA ICC1 Read- or write-cycle current (see Note 3) Minimum cycle, V CC = 5.5 V 856 736 656 mA ICC1 Standby current After one memory cycle, RAS and CAShigh, VIH=2.4 V (TTL) 32 32 32 mAICC1 Standby current After one memory cycle, RAS and CAShigh, VIH = VCC – 0.2 V (CMOS) 16 16 16 mA ICC3 Average refresh current (RAS -only or CBR) (see Note 3) Minimum cycle, V CC = 5.5 V, RAS cycling, CAS high (RAS-only), RAS low after CAS low (CBR) 1680 1440 1280 mA ICC4 Average EDO current (see Note 4) tPC = minimum, V CC = 5.5 V, RAS low, CAS cycling 736 656 576 mA NOTES: 3. Measured with a maximum of one address change while RAS = VIL. 4. Measured with a maximum of one address change while CAS = VIH. capacitance over recommended ranges of supply voltage and operating free-air temperature f = 1 MHz (see Note 5) ’124FBK32 ’248GBK32 UNIT MIN MAX MIN MAX UNIT C i(A) Input capacitance, address inputs 40 80 pF C i(R) Input capacitance, RAS 28 28 pF C i(C) Input capacitance, CAS 14 28 pF C i(W) Input capacitance, write-enable input 56 112 pF C o(DQ) Output capacitance on DQ pins 7 14 pF NOTE 5: V CC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.

TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996

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switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’124FBK32-60 ’248GBK32-60 ’124FBK32-70 ’248GBK32-70 ’124FBK32-80 ’248GBK32-80 UNIT MIN MAX MIN MAX MIN MAX tAA Access time from column address 30 35 40 ns tCAC Access time from CAS low 15 18 20 ns tRAC Access time from RAS low 60 70 80 ns tCPA Access time from column precharge 35 40 45 ns tCLZ CAS to output in the low-impedance state 0 0 0 ns tREZ Output disable time after RAS high (see Note 6) 3 15 3 18 3 20 ns tWEZ Output disable time after W low (see Note 6) 3 15 3 18 3 20 ns NOTE 6: tREZ and tWEZ are specified when the output is no longer driven. EDO timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124FBK32-60 ’248GBK32-60 ’124FBK32-70 ’248GBK32-70 ’124FBK32-80 ’248GBK32-80 UNIT MIN MAX MIN MAX MIN MAX tHPC Cycle time, EDO page-mode read or write 25 30 35 ns tPRWC Cycle time, EDO read-write 80 90 100 ns tCSH Hold time, CAS from RAS 50 55 60 ns tDOH Hold time, output from CAS 3 3 3 ns tCAS Pulse duration, CAS 10 10000 12 10000 15 10000 ns tWPE Pulse duration, W (output disable only) 5 5 5 ns tCP Precharge time, CAS 5 5 5 ns

TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 9POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended range of supply voltage and operating free-air temperature ’124FBK32-60 ’248GBK32-60 ’124FBK32-70 ’248GBK32-70 ’124FBK32-80 ’248GBK32-80 UNIT MIN MAX MIN MAX MIN MAX tRC Cycle time, random read or write (see Note 7) 110 130 150 ns tRWC Cycle time, read-write 150 175 200 ns tRASP Pulse duration, page-mode, RAS low 60 100 000 70 100 000 80 100 000 ns tRAS Pulse duration, non-page-mode, RAS low 60 10 000 70 10 000 80 10 000 ns tRP Pulse duration, RAS high (precharge) 40 50 60 ns tWP Pulse duration, W low 10 10 10 ns tRASS Pulse duration, self-refresh entry from RAS low 100 100 100 µs tRPS Pulse duration, RAS precharge after self-refresh 110 130 150 ns tASC Setup time, column address before CAS low 0 0 0 ns tASR Setup time, row address before RAS low 0 0 0 ns tDS Setup time, data before CAS low 0 0 0 ns tRCS Setup time, W high before CAS low 0 0 0 ns tCWL Setup time, W low before CAS high 10 12 15 ns tRWL Setup time, W low before RAS high 10 12 15 ns tWCS Setup time, W low before CAS low 0 0 0 ns tWRP Setup time, W high before RAS low (see Note 8) 10 10 10 ns tCAH Hold time, column address after CAS low 10 15 15 ns tDH Hold time, data after CAS low 10 15 15 ns tRAH Hold time, row address after RAS low 10 10 10 ns tRCH Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 9) 0 0 0 ns tWCH Hold time, W low after CAS low 10 15 15 ns tWRH Hold time, W high after RAS low (see Note 8) 10 10 10 ns tRHCP Hold time, RAS high from CAS precharge 35 40 45 ns tCHS Hold time, CAS low after RAS high (self-refresh) – 50 – 50 – 50 ns tCHR Delay time, RAS low to CAS high (see Note 8) 10 10 10 ns tCRP Delay time, CAS high to RAS low 5 5 5 ns tCSR Delay time, CAS low to RAS low (see Note 8) 5 5 5 ns tRAD Delay time, RAS low to column address (see Note 10) 15 30 15 35 15 40 ns tRAL Delay time, column address to RAS high 30 35 40 ns tCAL Delay time, column address to CAS high 20 25 30 ns tRCD Delay time, RAS low to CAS low (see Note 10) 20 45 20 52 20 60 ns tRPC Delay time, RAS high to CAS low (CBR only) 0 0 0 ns tRSH Delay time, CAS low to RAS high 10 12 15 ns tREF Refresh time interval 16 16 16 ms tT Transition time 2 30 2 30 2 30 ns NOTES: 7. All cycled times assume tT = 5 ns. 8. CBR refresh only 9. Either tRRH or tRCH must be satisfied for a read cycle. 10. Maximum value specified only to assure access time.

TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996

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BK (R-PSIM-N72) SINGLE-IN-LINE MEMORY MODULE 4040197/C 4/95 0.208 (5,28) MAX 0.400 (10,16) TYP 0.010 (0,25) MAX 0.054 (1,37) 1.005 (25,53) 0.995 (25,27) 0.047 (1,19) 0.360 (9,14) MAX (For Double-Sided SIMM) 4.255 (108,08) 4.245 (107,82) 0.125 (3,18) TYP 0.040 (1,02) TYP 0.120 (3,05) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. device symbolization (TM124FBK32 illustrated) –SSL YYMMTTM124FBK32 YY = Year Code MM = Month Code T = Assembly Site Code –SS = Speed Code L = Temperature Range NOTE: Location of symbolization may vary.

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