TM124BBJ32F

TM124BBJ32F TI | Alldatasheet

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TM124BBJ32F, TM124BBJ32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBJ32F, TM248CBJ32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS661 – JANUARY 1996 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

• Organization TM124BBJ32F ...10 4 85 7 6 × 32 TM248CBJ32F ...20 9 7152 × 32
• Single 5-V Power Supply (±10% Tolerance)
• 72-Pin Single In-Line Memory Module (SIMM) for Use With Socket
• TM124BBJ32F – Utilizes Two 16-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages
• TM248CBJ32F – Utilizes Four 16-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages
• Long Refresh Period 16 ms (1024 Cycles)
• All Inputs, Outputs, Clocks Fully TTL-Compatible
• 3-State Output
• Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks
• Enhanced Page-Mode Operation With CAS -Before-RAS (CBR), RAS-Only, and Hidden Refresh
• Presence Detect
• Performance Ranges: ACCESS ACCESS ACCESS READ TIME TIME TIME OR tRAC tAA tCAC WRITE CYCLE (MAX) (MAX) (MAX) (MIN) ’124BBJ32F-60 60 ns 30 ns 15 ns 110 ns ’124BBJ32F-70 70 ns 35 ns 18 ns 130 ns ’124BBJ32F-80 80 ns 40 ns 20 ns 150 ns ’248CBJ32F-60 60 ns 30 ns 15 ns 110 ns ’248CBJ32F-70 70 ns 35 ns 18 ns 130 ns ’248CBJ32F-80 80 ns 40 ns 20 ns 150 ns
• Low Power Dissipation
• Operating Free-Air Temperature Range 0°C to 70°C
• Gold-Tabbed Versions Available:† TM124BBJ32F TM248CBJ32F
• Tin-Lead (Solder) Tabbed Versions Available: TM124BBJ32U TM248CBJ32U

description

The TM124BBJ32F is a 4-MByte dynamic random-access memory (DRAM) organized as four times 1048576 × 8 in a 72-pin SIMM. The SIMM is composed of two TMS418160DZ, 1 048 576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418160DZ is described in the TMS418160 data sheet. The TM124BBJ32F SIMM is available in the single-sided BJ-leadless module for use with sockets. TM248CBJ32F The TM248CBJ32F is an 8-MByte DRAM organized as four times 2 097 152× 8 in a 72-pin SIMM. The SIMM is composed of four TMS418160DZ, 1048576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418160DZ is described in the TMS418160 data sheet. The TM248CBJ32F SIMM is available in the double-sided BJ-leadless module for use with sockets. operation The TM124BBJ32F operates as two TMS418160DZs connected as shown in the functional block diagram and Table 1. The TM248CBJ32F operates as four TMS418160DZs connected as shown in the functional block Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. PRODUCTION DATA information is current as of publication date.

TM124BBJ32F, TM124BBJ32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBJ32F, TM248CBJ32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS661 – JANUARY 1996

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(PIN) PD1 (67) PD2 (68) PD3 (69) PD4 (70) 80 ns VSS VSS NC VSS TM124BBJ32F 70 ns VSS VSS VSS NC 60 ns VSS VSS NC NC 80 ns NC NC NC VSS TM248CBJ32F 70 ns NC NC VSS NC 60 ns NC NC NC NC NC NC CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS BJ SINGLE IN-LINE MEMORY MODULE (TOP VIEW) TM124BBJ32F (SIDE VIEW) PIN NOMENCLATURE A0–A9 Address Inputs CAS0 –CAS3 Column-Address Strobe DQ0–DQ31 Data In/Data Out NC No Connection PD1– PD4 Presence Detects RAS0 –RAS3 Row-Address Strobe VCC 5-V Supply VSS Ground W Write Enable TM248CBJ32F (SIDE VIEW) VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC NC DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 NC VCC RAS3 RAS2 NC NC VSS

Table 1. Connection Table † Side 2 applies to the TM248CBJ32F only.

TM124BBJ32F, TM124BBJ32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBJ32F, TM248CBJ32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS661 – JANUARY 1996

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS . recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2.4 6.5 V VIL Low-level input voltage (see Note 2) – 1 0.8 V TA Operating free-air temperature 0 70 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS ‡ ’124BBJ32F-60 ’124BBJ32F-70 ’124BBJ32F-80 UNITPARAMETER TEST CONDITIONS ‡ MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltageIOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltageIOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage)VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC , CAS high ± 10 ± 10 ± 10 µA ICC1 Read- or write-cycle current VCC = 5.5 V, Minimum cycle 380 360 340 mA ICC2 Standby current VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 4 4 4 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high 2 2 2 mA ICC3 Average refresh current (RAS only or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 380 360 340 mA ICC4 Average page current VCC = 5.5 V, tPC = MIN, RAS low, CAS cycling 200 180 160 mA ‡ For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions.

TM124BBJ32F, TM124BBJ32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBJ32F, TM248CBJ32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS661 – JANUARY 1996 5POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS † ’248CBJ32F-60 ’248CBJ32F-70 ’248CBJ32F-80 UNITPARAMETER TEST CONDITIONS † MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5 V, V I = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC , CAS high ± 20 ± 20 ± 20 µA ICC1 Read- or write-cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 384 364 344 mA ICC2 Standby current VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 8 8 8 mA ICC2 Standby current VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high 4 4 4 mA ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 760 720 680 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, t PC = MIN, RAS low, CAS cycling 204 184 164 mA † For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5) PARAMETER ’124BBJ32F ’248CBJ32F UNITPARAMETER MIN MAX MIN MAX UNIT C i(A) Input capacitance, A0–A9 17 27 pF C i(R) Input capacitance, RAS inputs 10 10 pF C i(C) Input capacitance, CAS inputs 12 19 pF C i(W) Input capacitance, W 21 35 pF C o(DQ) Output capacitance on DQ0–DQ31 10 17 pF NOTE 5: V CC = 5 V ± 0.5 V, and the bias on pins under test is 0 V.

TM124BBJ32F, TM124BBJ32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBJ32F, TM248CBJ32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS661 – JANUARY 1996

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switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’124BBJ32F-60 ’248CBJ32F-60 ’124BBJ32F-70 ’248CBJ32F-70 ’124BBJ32F-80 ’248CBJ32F-80 UNIT MIN MAX MIN MAX MIN MAX tAA Access time from column address 30 35 40 ns tCAC Access time from CAS low 15 18 20 ns tRAC Access time from RAS low 60 70 80 ns tCPA Access time from column precharge 35 40 45 ns tCLZ CAS to output in the low-impedance state 0 0 0 ns tOH Output disable time from start of CAS high 3 3 3 ns tOFF Output disable time after CAS high (see Note 6) 0 15 0 18 0 20 ns NOTE 6: tOFF is specified when the output is no longer driven. timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124BBJ32F-60 ’248CBJ32F-60 ’124BBJ32F-70 ’248CBJ32F-70 ’124BBJ32F-80 ’248CBJ32F-80 UNIT MIN MAX MIN MAX MIN MAX tRC Cycle time, random read or write (see Note 7) 110 130 150 ns tRWC Cycle time, read-write 155 181 205 ns tPC Cycle time, page-mode read or write (see Notes 7 and 8)40 45 50 ns tRASP Pulse duration, page mode, RAS low 60 100 000 70 100 000 80 100 000 ns tRAS Pulse duration, nonpage mode, RAS low 60 10 000 70 10 000 80 10 000 ns tCAS Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns tCP Pulse duration, CAS high 10 10 10 ns tRP Pulse duration, RAS high (precharge) 40 50 60 ns tWP Pulse duration, W low 10 10 10 ns tASC Setup time, column address before CAS low 0 0 0 ns tASR Setup time, row address before RAS low 0 0 0 ns tDS Setup time, data before CAS low 0 0 0 ns tRCS Setup time, W high before CAS low 0 0 0 ns tCWL Setup time, W low before CAS high 15 18 20 ns tRWL Setup time, W low before RAS high 15 18 20 ns tWCS Setup time, W low before CAS low 0 0 0 ns tCAH Hold time, column address after CAS low 10 15 15 ns tRHCP Hold time, RAS high from CAS precharge 35 40 45 ns tDH Hold time, data after CAS low 10 15 15 ns tRAH Hold time, row address after RAS low 10 10 10 ns tRCH Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 9) 0 0 0 ns NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be ≥ tCP . 9. Either tRRH or tRCH must be satisfied for a read cycle.

TM124BBJ32F, TM124BBJ32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBJ32F, TM248CBJ32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS661 – JANUARY 1996 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124BBJ32F-60 ’248CBJ32F-60 ’124BBJ32F-70 ’248CBJ32F-70 ’124BBJ32F-80 ’248CBJ32F-80 UNIT MIN MAX MIN MAX MIN MAX tWCH Hold time, W low after CAS low 10 15 15 ns tCHR Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns tCRP Delay time, CAS high to RAS low 5 5 5 ns tCSH Delay time, RAS low to CAS high 60 70 80 ns tCSR Delay time, CAS low to RAS low (CBR refresh only) 5 5 5 ns tRAD Delay time, RAS low to column address (see Note 10) 15 30 15 35 15 40 ns tRAL Delay time, column address to RAS high 30 35 40 ns tCAL Delay time, column address to CAS high 30 35 40 ns tRCD Delay time, RAS low to CAS low (see Note 10) 20 45 20 52 20 60 ns tRPC Delay time, RAS high to CAS low (CBR only) 0 0 0 ns tRSH Delay time, CAS low to RAS high 15 18 20 ns tREF Refresh time interval 16 16 16 ms tT Transition time 3 30 3 30 3 30 ns NOTE 10: The maximum value is specified only to assure access time.

TM124BBJ32F, TM124BBJ32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBJ32F, TM248CBJ32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS661 – JANUARY 1996

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BJ (R-PSIM-N72) SINGLE-IN-LINE MEMORY MODULE 0.047 (1,19) 0.054 (1,37) 0.208 (5,28) MAX 0.695 (17,65) 0.705 (17,91) 0.010 (0,25) MAX 0.400 (10,16) TYP 4088178/A 01/96 0.360 (9,14) MAX (For Double-Sided SIMM) 4.245 (107,82) 4.255 (108,08) 0.125 (3,18) TYP 0.128 (3,25) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. device symbolization (TM124BBJ32F illustrated) TM124BBJ32F -SS YYMMT YY = Year Code MM = Month Code T = Assembly Site Code -SS = Speed Code NOTE: Location of symbolization may vary.

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