TLV9001SIDBVRG4

TLV9001 TI | Alldatasheet

Document overview

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Technical content

TLV900x Low-Power, RRIO, 1-MHz Operational Amplifier for Cost-Sensitive Systems

1 Features

• Scalable CMOS amplifier for low-cost applications
• Rail-to-rail input and output
• Low input offset voltage: ±0.4 mV
• Unity-gain bandwidth: 1 MHz
• Low broadband noise: 27 nV/√Hz
• Low input bias current: 5 pA
• Low quiescent current: 60 µA/Ch
• Unity-gain stable
• Internal RFI and EMI filter
• Operational at supply voltages as low as 1.8 V
• Easier to stabilize with higher capacitive load due to resistive open-loop output impedance
• Extended temperature range: –40°C to 125°C

2 Applications

• Sensor signal conditioning
• Power modules
• Active filters
• Low-side current sensing
• Smoke detectors
• Motion detectors
• Wearable devices
• Large and small appliances
• EPOS
• Barcode scanners
• Personal electronics
• HVAC: heating, ventilating, and air conditioning
• Motor control: AC induction

3 Description

The TLV900x family includes single (TLV9001), dual (TLV9002), and quad-channel (TLV9004) low-voltage (1.8 V to 5.5 V) operational amplifiers (op amps) with rail-to-rail input and output swing capabilities. These op amps provide a cost-effective solution for space-constrained applications such as smoke detectors, wearable electronics, and small appliances where low-voltage operation and high capacitive-load drive are required. The capacitive-load drive of the TLV900x family is 500 pF, and the resistive open- loop output impedance makes stabilization easier with much higher capacitive loads. These op amps are designed specifically for low-voltage operation (1.8 V to 5.5 V) with performance specifications similar to the TLV600x devices. The robust design of the TLV900x family simplifies circuit design. The op amps feature unity-gain stability, an integrated RFI and EMI rejection filter, and no-phase reversal in overdrive conditions. The TLV900x devices include a shutdown mode (TLV9001S, TLV9002S, and TLV9004S) that allow the amplifiers to switch off into standby mode with typical current consumption less than 1 µA. Micro-size packages, such as SOT-553 and WSON, are offered for all channel variants (single, dual, and quad), along with industry-standard packages such as SOIC, MSOP, SOT-23, and TSSOP packages. Device Information PART NUMBER(1) PACKAGE BODY SIZE (NOM) TLV9001 SOT-23 (5) 1.60 mm × 2.90 mm SC70 (5) 1.25 mm × 2.00 mm SOT-553 (5)(2) 1.65 mm × 1.20 mm X2SON (5) 0.80 mm × 0.80 mm TLV9001S SOT-23 (6) 1.60 mm × 2.90 mm SC70 (6) 1.25 mm × 2.00 mm TLV9002 SOIC (8) 3.91 mm × 4.90 mm WSON (8) 2.00 mm × 2.00 mm VSSOP (8) 3.00 mm × 3.00 mm SOT-23 (8) 1.60 mm × 2.90 mm TSSOP (8) 3.00 mm × 4.40 mm TLV9002S VSSOP (10) 3.00 mm × 3.00 mm X2QFN (10) 1.50 mm × 2.00 mm DSBGA (9) 1.00 mm × 1.00 mm TLV9004 SOIC (14) 8.65 mm × 3.91 mm SOT-23 (14) 4.20 mm × 2.00 mm TSSOP (14) 4.40 mm × 5.00 mm WQFN (16) 3.00 mm × 3.00 mm X2QFN (14) 2.00 mm × 2.00 mm TLV9004S WQFN (16) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Package is for preview only. Single-Pole, Low-Pass Filter TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

12.2 Receiving Notification of Documentation Updates..36

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision Q (June 2021) to Revision R (November 2021) Page Changes from Revision P (April 2021) to Revision Q (June 2021) Page Changes from Revision O (April 2020) to Revision P (April 2021) Page Changes from Revision N (January 2020) to Revision O (April 2020) Page TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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Changes from Revision M (September 2019) to Revision N (January 2020) Page Changes from Revision L (May 2019) to Revision M (September 2019) Page Changes from Revision K (March 2019) to Revision L (May 2019) Page Changes from Revision J (January 2019) to Revision K (March 2019) Page Changes from Revision I (November 2018) to Revision J (January 2019) Page Changes from Revision H (October 2018) to Revision I (November 2018) Page www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TLV9001 TLV9002 TLV9004

Changes from Revision G (September 2018) to Revision H (October 2018) Page Changes from Revision F (August 2018) to Revision G (September 2018) Page Changes from Revision E (July 2018) to Revision F (August 2018) Page Changes from Revision D (June 2018) to Revision E (July 2018) Page Changes from Revision C (May 2018) to Revision D (June 2018) Page

• Added shutdown section to Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V Changes from Revision B (March 2018) to Revision C (May 2018) Page TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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Changes from Revision A (December 2017) to Revision B (March 2018) Page

• Added package preview notes to TLV9001 packages, TLV9004 packages, and TLV9002 8-pin VSSOP
• Added package preview notes to TLV9001, TLV9004 and TLV9002 VSSOP package pinout drawings in Pin
• Deleted package preview note from TLV9002 DSG (WSON) pinout drawing in Pin Configurations and
• Deleted package preview note from TLV9002 RUG (X2QFN) pinout drawing in Pin Configurations and Changes from Revision * (October 2017) to Revision A (December 2017) Page www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TLV9001 TLV9002 TLV9004

5 Device Comparison Table

NO. OF CH. PACKAGE LEADS SC70 DCK SOIC D SOT-23 DBV SOT-23 DYY SOT-553 DRL TSSOP PW VSSOP DGK SOT-23 DDF WQFN RTE WSON DSG X2QFN RUC X2SON DPW X2QFN RUG VSSOP DGS DSBGA YCK TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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6 Pin Configuration and Functions

2V± 3IN+ 4 IN ± 5 V+ Not to scale Figure 6-1. TLV9001 DBV, TLV9001T DCK Package 5-Pin SOT-23, SC70 Top View 1IN+ 2V± 3IN± 4 OUT 5 V+ Not to scale Figure 6-2. TLV9001 DCK Package, TLV9001 DRL 5-Pin SC70, SOT-553, SOT-23 Top View 1OUT 2IN±

4 IN+

Figure 6-3. TLV9001 DPW Package 5-Pin X2SON Top View Table 6-1. Pin Functions: TLV9001 PIN I/O DESCRIPTION NAME SOT-23, SC70(T) SC70, SOT-23(U), SOT-553 X2SON IN– 4 3 2 I Inverting input IN+ 3 1 4 I Noninverting input OUT 1 4 1 O Output V– 2 2 3 I or — Negative (low) supply or ground (for single-supply operation) V+ 5 5 5 I Positive (high) supply www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TLV9001 TLV9002 TLV9004

2V± 5 SHDN 3IN+ 4 IN ± Not to scale Figure 6-4. TLV9001S DBV Package 6-Pin SOT-23 Top View 1IN+ 6 V+ 2V± 5 SHDN 3IN± 4 OUT Not to scale Figure 6-5. TLV9001S DCK Package 6-Pin SC70 Top View Table 6-2. Pin Functions: TLV9001S PIN I/O DESCRIPTION NAME SOT-23 SC70 IN– 4 3 I Inverting input IN+ 3 1 I Noninverting input OUT 1 4 O Output SHDN 5 5 I Shutdown: low = amp disabled, high = amp enabled. See Section 8.5 for more information. V– 2 2 I or — Negative (low) supply or ground (for single-supply operation) V+ 6 6 I Positive (high) supply 1OUT1 8 V+ 2IN1± 7 OUT2 3IN1+ 6 IN2 ± 4V± 5 IN2+ Not to scale Figure 6-6. TLV9002 D, DGK, PW, DDF Package 8-Pin SOIC, VSSOP, TSSOP, SOT-23 Top View 1OUT1 8 V+ 2IN1± 7 OUT2 3IN1+ 6 IN2 ± 4V± 5 IN2+ Not to scale Thermal Pad A. Connect thermal pad to V–. Figure 6-7. TLV9002 DSG Package 8-Pin WSON With Exposed Thermal Pad Top View Table 6-3. Pin Functions: TLV9002 PIN I/O DESCRIPTION NAME NO. IN1– 2 I Inverting input, channel 1 IN1+ 3 I Noninverting input, channel 1 IN2– 6 I Inverting input, channel 2 IN2+ 5 I Noninverting input, channel 2 OUT1 1 O Output, channel 1 OUT2 7 O Output, channel 2 V– 4 I or — Negative (low) supply or ground (for single-supply operation) V+ 8 I Positive (high) supply TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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2IN1± 9 OUT2 3IN1+ 8 IN2 ± 4V± 7 IN2+ 5SHDN1 6 SHDN2 Not to scale Figure 6-8. TLV9002S DGS Package 10-Pin VSSOP Top View 1V± 2SHDN1 3SHDN2 4IN2+ 5IN2±

6 OUT2

8 OUT1

9 IN1 ±

10 IN1+

Figure 6-9. TLV9002S RUG Package 10-Pin X2QFN Top View 1 2 3 C B A Not to scale OUT1 V+ OUT2 IN1– SHDN IN2– IN1+ V– IN2+ Figure 6-10. TLV9002S YCK Package 9-Pin DSBGA (WCSP) Bottom View Table 6-4. Pin Functions: TLV9002S PIN I/O DESCRIPTION NAME VSSOP X2QFN DSBGA (WCSP) IN1– 2 9 B1 I Inverting input, channel 1 IN1+ 3 10 A1 I Noninverting input, channel 1 IN2– 8 5 B3 I Inverting input, channel 2 IN2+ 7 4 A3 I Noninverting input, channel 2 OUT1 1 8 C1 O Output, channel 1 OUT2 9 6 C3 O Output, channel 2 SHDN1 5 2 — I Shutdown: low = amp disabled, high = amp enabled, channel 1. See Section 8.5 for more information. www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TLV9001 TLV9002 TLV9004

Table 6-4. Pin Functions: TLV9002S (continued) PIN I/O DESCRIPTION NAME VSSOP X2QFN DSBGA (WCSP) SHDN2 6 3 — I Shutdown: low = amp disabled, high = amp enabled, channel 1. See Section 8.5 for more information. SHDN — — B2 Shutdown: low = both amplifiers disabled, high = both amplifiers enabled V– 4 1 A2 I or — Negative (low) supply or ground (for single-supply operation) V+ 10 7 C2 I Positive (high) supply TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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2IN1± 13 IN4 ± 3IN1+ 12 IN4+ 4V+ 11 V ± 5IN2+ 10 IN3+ 6IN2± 9 IN3 ± 7OUT2 8 OUT3 Not to scale Figure 6-11. TLV9004 D, DYY, PW Package 14-Pin SOIC, SOT-23 (14), TSSOP Top View 1IN1± 2IN1+ 3V+ 4IN2+ 5IN2± 6OUT2 7OUT3

8 IN3 ±

9 IN3+

10 V ±

11 IN4+

12 IN4 ±

13 OUT4

14 OUT1

Figure 6-12. TLV9004 RUC Package 14-Pin X2QFN Top View

16 IN1 ±5OUT2

15 OUT16NC

2V+ 11 V ±

14 OUT47NC

13 IN4 ±8OUT3

4IN2± 9 IN3 ± Not to scale Thermal Pad A. Connect thermal pad to V–. Figure 6-13. TLV9004 RTE Package 16-Pin WQFN With Exposed Thermal Pad Top View Table 6-5. Pin Functions: TLV9004 PIN I/O DESCRIPTION NAME SOIC, SOT-23 (14), TSSOP WQFN X2QFN IN1– 2 16 1 I Inverting input, channel 1 IN1+ 3 1 2 I Noninverting input, channel 1 IN2– 6 4 5 I Inverting input, channel 2 IN2+ 5 3 4 I Noninverting input, channel 2 www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TLV9001 TLV9002 TLV9004

Table 6-5. Pin Functions: TLV9004 (continued) PIN I/O DESCRIPTION NAME SOIC, SOT-23 (14), TSSOP WQFN X2QFN IN3– 9 9 8 I Inverting input, channel 3 IN3+ 10 10 9 I Noninverting input, channel 3 IN4– 13 13 12 I Inverting input, channel 4 IN4+ 12 12 11 I Noninverting input, channel 4 NC — 6, 7 — — No internal connection OUT1 1 15 14 O Output, channel 1 OUT2 7 5 6 O Output, channel 2 OUT3 8 8 7 O Output, channel 3 OUT4 14 14 13 O Output, channel 4 V– 11 11 10 I or — Negative (low) supply or ground (for single-supply operation) V+ 4 2 3 I Positive (high) supply TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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15 OUT16SHDN12

2V+ 11 V ±

14 OUT47SHDN34

4IN2± 9 IN3 ± Not to scale Thermal Pad A. Connect thermal pad to V–. Figure 6-14. TLV9004S RTE Package 16-Pin WQFN With Exposed Thermal Pad Top View Table 6-6. Pin Functions: TLV9004S PIN I/O DESCRIPTION NAME NO. IN1+ 1 I Noninverting input IN1– 16 I Inverting input IN2+ 3 I Noninverting input IN2– 4 I Inverting input IN3+ 10 I Noninverting input IN3– 9 I Inverting input IN4+ 12 I Noninverting input IN4– 13 I Inverting input SHDN12 6 I Shutdown: low = amp disabled, high = amp enabled, channel 1 and 2. See Section 8.5 for more information. SHDN34 7 I Shutdown: low = amp disabled, high = amp enabled, channel 3 and 4. See Section 8.5 for more information. OUT1 15 O Output OUT2 5 O Output OUT3 8 O Output OUT4 14 O Output V– 11 I or — Negative (low) supply or ground (for single-supply operation) V+ 2 I Positive (high) supply www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TLV9001 TLV9002 TLV9004

7 Specifications

7.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage (V+) – (V–) 7 V Signal input pins Voltage(2) Common-mode (V–) – 0.5 (V+) + 0.5 V Differential (V+) – (V–) + 0.2 V Current(2) –10 10 mA Output short-circuit(3) Continuous Operating, TA –55 150 °C Junction, TJ 150 °C Storage, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less. (3) Short-circuit to ground, one amplifier per package.

7.2 ESD Ratings

TLV9002S PACKAGE VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 ALL OTHER PACKAGES V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating temperature range (unless otherwise noted) MIN MAX UNIT VS Supply voltage 1.8 5.5 V TA Specified temperature –40 125 °C TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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7.4 Thermal Information: TLV9001

THERMAL METRIC(1) TLV9001 UNITDBV (SOT-23) DCK (SC70) DPW (X2SON) DRL (SOT-553)(2)

5 PINS 5 PINS 5 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance 232.9 239.6 470.0 TBD °C/W RθJC(top) Junction-to-case (top) thermal resistance 153.8 148.5 211.9 TBD °C/W RθJB Junction-to-board thermal resistance 100.9 82.3 334.8 TBD °C/W ψJT Junction-to-top characterization parameter 77.2 54.5 29.8 TBD °C/W ψJB Junction-to-board characterization parameter 100.4 81.8 333.2 TBD °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics . (2) This package option for TLV9001 is preview only.

7.5 Thermal Information: TLV9001S

THERMAL METRIC(1) TLV9001S UNITDBV (SOT-23) DCK (SC70)

6 PINS 6 PINS

RθJA Junction-to-ambient thermal resistance 232.9 215.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 153.8 146.4 °C/W RθJB Junction-to-board thermal resistance 100.9 72.0 °C/W ψJT Junction-to-top characterization parameter 77.2 55.0 °C/W ψJB Junction-to-board characterization parameter 100.4 71.7 °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics .

7.6 Thermal Information: TLV9002

THERMAL METRIC(1) TLV9002 UNITD (SOIC) DGK (VSSOP) DGS (VSSOP) DSG (WSON) PW (TSSOP) DDF (SOT-23)

8 PINS 8 PINS 10 PINS 8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient RθJC(top) Junction-to-case (top) RθJB Junction-to-board thermal ψJT Junction-to-top ψJB Junction-to-board (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics . www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TLV9001 TLV9002 TLV9004

7.7 Thermal Information: TLV9002S

THERMAL METRIC(1) TLV9002S UNITDGS (VSSOP) RUG (X2QFN) YCK (DSBGA)

10 PINS 10 PINS 9 PINS

RθJA Junction-to-ambient thermal resistance 169.5 194.2 101.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 84.1 90.3 0.9 °C/W RθJB Junction-to-board thermal resistance 113 122.2 33.8 °C/W ψJT Junction-to-top characterization parameter 15.8 3.5 0.5 °C/W ψJB Junction-to-board characterization parameter 111.6 118.8 33.8 °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics .

7.8 Thermal Information: TLV9004

THERMAL METRIC(1) TLV9004 UNITD (SOIC) DYY (SOT-23) PW (TSSOP) RTE (WQFN) RUC (X2QFN)

14 PINS 14 PINS 14 PINS 16 PINS 14 PINS

RθJA Junction-to-ambient thermal RθJC(top) Junction-to-case (top) thermal RθJB Junction-to-board thermal ψJT Junction-to-top characterization ψJB Junction-to-board (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics .

7.9 Thermal Information: TLV9004S

THERMAL METRIC(1) TLV9004S UNITRTE (WQFN)

16 PINS

RθJA Junction-to-ambient thermal resistance 66.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 69.3 °C/W RθJB Junction-to-board thermal resistance 41.7 °C/W ψJT Junction-to-top characterization parameter 5.7 °C/W ψJB Junction-to-board characterization parameter 41.5 °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics . TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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7.10 Electrical Characteristics

For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage VS = 5 V ±0.4 ±1.6 mV VS = 5 V, TA = –40°C to 125°C ±2 dVOS/dT VOS vs temperature TA = –40°C to 125°C ±0.6 µV/°C PSRR Power-supply rejection ratio VS = 1.8 to 5.5 V, VCM = (V–) 80 105 dB INPUT VOLTAGE RANGE VCM Common-mode voltage range No phase reversal, rail-to-rail input (V–) – 0.1 (V+) + 0.1 V CMRR Common-mode rejection ratio TA = –40°C to 125°C 86 dB TA = –40°C to 125°C 95 TA = –40°C to 125°C 63 77 TA = –40°C to 125°C 68 INPUT BIAS CURRENT IB Input bias current VS = 5 V ±5 pA IOS Input offset current ±2 pA NOISE En Input voltage noise (peak-to- peak) ƒ = 0.1 Hz to 10 Hz, VS = 5 V 4.7 µVPP en Input voltage noise density ƒ = 1 kHz, VS = 5 V 30 nV/√ Hz ƒ = 10 kHz, VS = 5 V 27 in Input current noise density ƒ = 1 kHz, VS = 5 V 23 fA/√ Hz INPUT CAPACITANCE CID Differential 1.5 pF CIC Common-mode 5 pF OPEN-LOOP GAIN AOL Open-loop voltage gain RL = 10 kΩ 104 117 dB RL = 10 kΩ 100 RL = 2 kΩ 115 RL = 2 kΩ 130 FREQUENCY RESPONSE GBW Gain-bandwidth product VS = 5 V 1 MHz φm Phase margin VS = 5.5 V, G = 1 78 ° SR Slew rate VS = 5 V 2 V/µs tS Settling time To 0.1%, VS = 5 V, 2-V step, G = +1, CL = 100 pF 2.5 µs To 0.01%, VS = 5 V, 2-V step, G = +1, CL = 100 pF 3 tOR Overload recovery time VS = 5 V, VIN × gain > VS 0.85 µs THD+N Total harmonic distortion + noise VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1, ƒ = 1 kHz, 80-kHz measurement BW 0.004% OUTPUT VO Voltage output swing from supply rails VS = 5.5 V, RL = 10 kΩ 10 20 mV VS = 5.5 V, RL = 2 kΩ 35 55 ISC Short-circuit current VS = 5.5 V ±40 mA ZO Open-loop output impedance VS = 5 V, ƒ = 1 MHz 1200 Ω www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TLV9001 TLV9002 TLV9004

7.10 Electrical Characteristics (continued)

For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VS Specified voltage range 1.8 (±0.9) 5.5 (±2.75) V IQ Quiescent current per amplifier TLV9002, TLV9002S TLV9004, TLV9004S IO = 0 mA, VS = 5.5 V 60 75 µATLV9001, TLV9001S IO = 0 mA, VS = 5.5 V 60 77 IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C 85 SHUTDOWN(1) IQSD Quiescent current per amplifier VS = 1.8 V to 5.5 V, all amplifiers disabled, SHDN = VS– 0.5 1.5 µA ZSHDN Output impedance during shutdown VS = 1.8 V to 5.5 V, amplifier disabled 10 || 2 GΩ || pF High level voltage shutdown threshold (amplifier enabled) VS = 1.8 V to 5.5 V (V–) + 0.9 (V–) + 1.1 V Low level voltage shutdown threshold (amplifier disabled) VS = 1.8 V to 5.5 V (V–) + 0.2 V (V–) + 0.7 V V tON Amplifier enable time (full shutdown) VS = 1.8 V to 5.5 V, full shutdown; G = 1, VOUT = 0.9 × VS / 2, RL connected to V– 70 µs Amplifier enable time (partial shutdown) VS = 1.8 V to 5.5 V, partial shutdown; G = 1, VOUT = 0.9 × VS / 2, RL connected to V– 50 tOFF Amplifier disable time VS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS / 2, RL connected to V– 4 µs SHDN pin input bias current (per pin) VS = 1.8 V to 5.5 V, V+ ≥ SHDN ≥ (V+) – 0.8 V 40 nA VS = 1.8 V to 5.5 V, V– ≤ SHDN ≤ V– + 0.8 V 150 (1) Specified by design and characterization; not production tested. TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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7.11 Typical Characteristics

at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) Offset Voltage ( V) μ Population (%) -1200 -900 -600 -300 0 300 600 900 1200 1500 D001 1800 VS = 5 V Figure 7-1. Offset Voltage Distribution Histogram Offset Voltage Drift ( V/°C)μ Population (%) D002 VS = 5 V, TA = –40°C to 125°C Figure 7-2. Offset Voltage Drift Distribution Histogram Temperature (°C) Input Offset Voltage ( V) µ -40 -20 0 20 40 60 80 100 120 140 -1000 -800 -600 -400 -200 200 400 600 800 1000 D003 Figure 7-3. Input Offset Voltage vs Temperature Common-Mode Voltage (V) Offset Voltage ( V) μ -4 -3 -2 -1 0 1 2 3 4 -2000 -1500 -1000 -500 500 1000 1500 2000 D004 Figure 7-4. Offset Voltage vs Common-Mode Supply Voltage (V) Offset Voltage (PV) -1000 -800 -600 -400 -200 200 400 600 800 1000 D005 Figure 7-5. Offset Voltage vs Supply Voltage Temperature (qC) IB and IOS (pA) -40 -20 0 20 40 60 80 100 120 140 -10 D006 IB IB+ IOS Figure 7-6. IB and IOS vs Temperature www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TLV9001 TLV9002 TLV9004

7.11 Typical Characteristics (continued)

at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) Common-Mode Voltage (V) IB and IOS (pA) -3 -2 -1 0 1 2 3 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 D007 IB IB+ IOS Figure 7-7. IB and IOS vs Common-Mode Voltage Temperature (qC) Gain (dB) -40 -20 0 20 40 60 80 100 120 140 100 120 140 160 D008 VS = 5.5 V VS = 1.8 V Figure 7-8. Open-Loop Gain vs Temperature Frequency (Hz) Gain (dB) Phase (q) -20 0 0 20 20 40 40 60 60 80 80 100 100 120 1k 10k 100k 1M D009 Gain Phase CL = 10 pF Figure 7-9. Open-Loop Gain and Phase vs Frequency Output Voltage (V) Open-Loop Voltage Gain (dB) -3 -2 -1 0 1 2 3 100 120 140 160 D010 Figure 7-10. Open-Loop Gain vs Output Voltage Frequency (Hz) Gain (dB) -20 -10 100 1k 10k 100k 1M D011 Gain = 1 Gain = 1 Gain = 100 Gain = 1000 Gain = 10 CL = 10 pF Figure 7-11. Closed-Loop Gain vs Frequency Output Current (mA) Output Voltage (V) 0 5 10 15 20 25 30 35 40 45 50 -2.5 -1.5 -0.5 0.5 1.5 2.5 -40°C -40°C25°C 85°C 85°C 125°C 125°C D012 25°C Figure 7-12. Output Voltage vs Output Current (Claw) TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) Frequency (Hz) Power Supply Rejection Ratio (dB) 100 120 100 1k 10k 100k 1M D013 PSRR+ PSRR Figure 7-13. PSRR vs Frequency Temperature (qC) Power Supply Rejection Ratio (dB) -40 -20 0 20 40 60 80 100 120 140 100 120 D014 VS = 1.8 V to 5.5 V Figure 7-14. DC PSRR vs Temperature Frequency (Hz) Common-Mode Rejection Ratio (dB) 100 120 100 1k 10k 100k 1M D015 Figure 7-15. CMRR vs Frequency Temperature (qC) Common-Mode Rejection Ratio (dB) -40 -20 0 20 40 60 80 100 120 140 100 120 140 160 D016 VS = 1.8 V VS = 5.5 V VCM = (V–) – 0.1 V to (V+) – 1.4 V Figure 7-16. DC CMRR vs Temperature Time (1 s/div) Amplitude (1 PV/div) D017 Figure 7-17. 0.1-Hz to 10-Hz Integrated Voltage Noise Frequency (Hz) Input Voltage Noise Spectral Density (nV/—Hz) 100 120 10 100 1k 10k 100k D018 Figure 7-18. Input Voltage Noise Spectral Density www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TLV9001 TLV9002 TLV9004

at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) Frequency (Hz) THD + N (dB) -100 -90 -80 -70 -60 -50 100 1k 10k D019 RL = 2K RL = 10K VS = 5.5 V VCM = 2.5 V G = 1 BW = 80 kHz VOUT = 0.5 VRMS Figure 7-19. THD + N vs Frequency Amplitude (VRMS) THD + N (dB) 0.001 0.01 0.1 1 2 -100 -80 -60 -40 -20 D020 G = +1, RL = 2 k: G = +1, RL = 10 k: G = 1, RL = 2 k: G = 1, RL = 10 k: VS = 5.5 V VCM = 2.5 V ƒ = 1 kHz G = 1 BW = 80 kHz Figure 7-20. THD + N vs Amplitude Voltage Supply (V) Quiescent Current (PA) D021 Figure 7-21. Quiescent Current vs Supply Voltage Temperature (qC) Quiescent Current (PA) -40 -20 0 20 40 60 80 100 120 140 D022 Figure 7-22. Quiescent Current vs Temperature Frequency (Hz) Open-Loop Output Impedance (:) 200 400 600 800 1000 1200 1400 1600 1800 2000 1k 10k 100k 1M 10M D023 Figure 7-23. Open-Loop Output Impedance vs Frequency Capacitance Load (pF) Overshoot (%) 0 200 400 600 800 1000 D024 Overshoot (+) Overshoot (–) G = 1 VIN = 100 mVpp Figure 7-24. Small Signal Overshoot vs Capacitive Load TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) Capacitance Load (pF) Overshoot (%) 0 200 400 600 800 1000 D025 Overshoot (+) Overshoot (–) G = –1 VIN = 100 mVpp Figure 7-25. Small Signal Overshoot vs Capacitive Load Capacitance Load (pF) Phase Margin (q) 0 200 400 600 800 1000 D026 Figure 7-26. Phase Margin vs Capacitive Load Time (100 Ps/div) Amplitude (1 V/div) D027 VOUT VIN G = 1 VIN = 6.5 VPP Figure 7-27. No Phase Reversal Time (20 Ps/div) Amplitude (1 V/div) D028 VOUT VIN G = –10 VIN = 600 mVPP Figure 7-28. Overload Recovery Time (10 Ps/div) Voltage (20 mV/div) D029 VOUT VIN G = 1 VIN = 100 mVPP CL = 10 pF Figure 7-29. Small-Signal Step Response Time (10 Ps/div) Voltage (1 V/div) D030 VOUT VIN G = 1 VIN = 4 VPP CL = 10 pF Figure 7-30. Large-Signal Step Response www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TLV9001 TLV9002 TLV9004

at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) Time (1 s/div)μ Output Voltage (1 mV/div) D031 G = 1 CL = 100 pF 2-V step Figure 7-31. Large-Signal Settling Time (Negative) Time (1 Ps/div) Output Voltage (1 mV/div) D032 G = 1 CL = 100 pF 2-V step Figure 7-32. Large-Signal Settling Time (Positive) Temperature (qC) Short Circuit Current (mA) -40 -20 0 20 40 60 80 100 120 -80 -60 -40 -20 D033 Sinking Sourcing Figure 7-33. Short-Circuit Current vs Temperature Frequency (Hz) Maximum Output Voltage (V) 1 10 100 1k 10k 100k 1M 10M 100M D034 VS = 5.5 V VS = 1.8 V Figure 7-34. Maximum Output Voltage vs Frequency Frequency (Hz) EMIRR (dB) 100 120 140 10M 100M 1G 10G D035 Figure 7-35. Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency Frequency (Hz) Channel Separation (dB) -140 -120 -100 -80 -60 -40 -20 1k 10k 100k 1M 10M D036 Figure 7-36. Channel Separation TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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8 Detailed Description

8.1 Overview

The TLV900x is a family of low-power, rail-to-rail input and output op amps. These devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The input common-mode voltage range includes both rails and allows the TLV900x family to be used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply applications, and makes them suitable for driving sampling analog-to-digital converters (ADCs).

8.2 Functional Block Diagram

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8.3 Feature Description

8.3.1 Operating Voltage

The TLV900x family of op amps are for operation from 1.8 V to 5.5 V. In addition, many specifications such as input offset voltage, quiescent current, offset current, and short circuit current apply from –40°C to 125°C. Parameters that vary significantly with operating voltages or temperature are shown in Section 7.11.

8.3.2 Rail-to-Rail Input

The input common-mode voltage range of the TLV900x family extends 100 mV beyond the supply rails for the full supply voltage range of 1.8 V to 5.5 V. This performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a P-channel differential pair, as shown in Section 8.2. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100 mV above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in which both pairs are on. This 100-mV transition region can vary up to 100 mV with process variation. Thus, the transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to (V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can degrade compared to device operation outside this region.

8.3.3 Rail-to-Rail Output

Designed as a low-power, low-voltage operational amplifier, the TLV900x family delivers a robust output drive capability. A class-AB output stage with common-source transistors achieves full rail-to-rail output swing capability. For resistive loads of 10 k Ω, the output swings to within 20 mV of either supply rail, regardless of the applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the rails.

8.3.4 EMI Rejection

The TLV900x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the TLV900x benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 8-1 shows the results of this testing on the TLV900x. Table 8-1 shows the EMIRR IN+ values for the TLV900x at particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op amps and is available for download from www.ti.com. Frequency (Hz) EMIRR (dB) 100 120 140 10M 100M 1G 10G D035 Figure 8-1. EMIRR Testing TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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Table 8-1. TLV900x EMIRR IN+ For Frequencies of Interest FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+

400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)

applications 59.5 dB

900 MHz Global system for mobile communications (GSM) applications, radio communication, navigation,

GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications 68.9 dB 1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 77.8 dB 2.4 GHz 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) 78.0 dB 3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.8 dB

8.4 Overload Recovery

Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated state to a linear state. The output devices of the operational amplifier enter a saturation region when the output voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return to the linear state. After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew time. The overload recovery time for the TLV900x family is approximately 850 ns.

8.5 Shutdown

The TLV9001S, TLV9002S, and TLV9004S devices feature SHDN pins that disable the op amp, placing it into a low-power standby mode. In this mode, the op amp typically consumes less than 1 µA. The SHDN pins are active low, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic low. The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown feature lies around 620 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.2 V and V+. The shutdown pin circuitry includes a pull-up resistor, which will inherently pull the voltage of the pin to the positive supply rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or driven to a valid logic high. To disable the amplifier, the SHDN pins must be driven to a valid logic low. While we highly recommend that the shutdown pin be connected to a valid high or a low voltage or driven, we have included a pull-up resistor connected to VCC. The maximum voltage allowed at the SHDN pins is (V+) + 0.5 V. Exceeding this voltage level will damage the device. The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be used to greatly reduce the average current and extend battery life. The enable time is 70 µs for full shutdown of all channels; disable time is 4 µs. When disabled, the output assumes a high-impedance state. This architecture allows the TLV9002S and TLV9004S to operate as a gated amplifier (or to have the device output multiplexed onto a common analog output bus). Shutdown time (t OFF) depends on loading conditions and increases as load resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-k Ω load to midsupply (V S / 2) is required. If using the TLV9001S, TLV9002S, or TLV9004S without a load, the resulting turnoff time significantly increases.

8.6 Device Functional Modes

The TLV900x family has a single functional mode. The devices are powered on as long as the power-supply www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TLV9001 TLV9002 TLV9004

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TLV900x family of low-power, rail-to-rail input and output operational amplifiers is specifically designed for portable applications. The devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose applications. The class AB output stage is capable of driving less than or equal to 10‑kΩ loads connected to any point between V+ and V–. The input common-mode voltage range includes both rails, and allows the TLV900x devices to be used in any single-supply application.

9.2 Typical Application

9.2.1 TLV900x Low-Side, Current Sensing Application

Figure 9-1 shows the TLV900x configured in a low-side current sensing application. ILOAD ZLOAD VBUS VSHUNT RSHUNT 0.1 Ÿ RF 57.6 NŸ RG 1.2 NŸ VOUT 5 V í TLV9002 í Figure 9-1. TLV900x in a Low-Side, Current-Sensing Application TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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9.2.1.1 Design Requirements

The design requirements for this design are:

• Load current: 0 A to 1 A
• Output voltage: 4.9 V
• Maximum shunt voltage: 100 mV

9.2.1.2 Detailed Design Procedure

The transfer function of the circuit in Figure 9-1 is given in Equation 1. OUT LOAD SHUNTV I R Gain u u (1) The load current (I LOAD) produces a voltage drop across the shunt resistor (R SHUNT). The load current is set from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is shown using Equation 2. SHUNT MAX SHUNT LOAD MAX V 100mVR 100m I 1 A : (2) Using Equation 2 , R SHUNT is calculated to be 100 m Ω. The voltage drop produced by I LOAD and R SHUNT is amplified by the TLV900x to produce an output voltage of approximately 0 V to 4.9 V. The gain needed by the TLV900x to produce the necessary output voltage is calculated using Equation 3. _ _ _ _ OUT MAX OUT MIN IN MAX IN MIN V V Gain V V (3) Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors R F and RG. Equation 4 sizes the resistors RF and RG, to set the gain of the TLV900x to 49 V/V. F G RGain 1 R (4) Selecting RF as 57.6 k Ω and R G as 1.2 k Ω provides a combination that equals 49 V/V. Figure 9-2 shows the measured transfer function of the circuit shown in Figure 9-1 . Notice that the gain is only a function of the feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors values are determined by the impedance levels that the designer wants to establish. The impedance level determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no optimal impedance selection that works for every system, you must choose an impedance that is ideal for your system parameters. www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TLV9001 TLV9002 TLV9004

9.2.1.3 Application Curve

0 0.2 0.4 0.6 0.8 1 Output (V) ILOAD (A) C219 Figure 9-2. Low-Side, Current-Sense Transfer Function TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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9.2.2 Single-Supply Photodiode Amplifier

Photodiodes are used in many applications to convert light signals to electrical signals. The current through the photodiode is proportional to the photon energy absorbed, and is commonly in the range of a few hundred picoamps to a few tens of microamps. An amplifier in a transimpedance configuration is typically used to convert the low-level photodiode current to a voltage signal for processing in an MCU. The circuit shown in Figure 9-3 is an example of a single-supply photodiode amplifier circuit using the TLV9002. CPD 47 pF IIN 0-10 µA VREF VOUT 3.3 V RF 309 NŸ CF 10 pF 357 Ÿ 11.5 NŸ +3.3V VREF RL 10 k TLV9002 Figure 9-3. Single-Supply Photodiode Amplifier Circuit www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TLV9001 TLV9002 TLV9004

9.2.2.1 Design Requirements

The design requirements for this design are:

• Supply voltage: 3.3 V
• Input: 0 µA to 10 µA
• Output: 0.1 V to 3.2 V
• Bandwidth: 50 kHz

9.2.2.2 Detailed Design Procedure

The transfer function between the output voltage (V OUT), the input current, (IIN) and the reference voltage (V REF) is defined in Equation 5. OUT IN F REFV I R V u (5) Where: 1 2 REF 1 2 R R V V R R (6) Set VREF to 100 mV to meet the minimum output voltage level by setting R1 and R2 to meet the required ratio calculated in Equation 7. REFV 0.1 V 0.0303V 3.3 V (7) The closest resistor ratio to meet this ratio sets R1 to 11.5 kΩ and R2 to 357 Ω. The required feedback resistance can be calculated based on the input current and desired output voltage. OUT REF F IN V V 3.2 V 0.1 V kVR 310 309 kI 10 A A | : P (8) Calculate the value for the feedback capacitor based on R F and the desired –3-dB bandwidth, (f –3dB) using Equation 9. F F 3dB 1 1 C 10.3 pF 10 pF2 R f 2 309 k 50 kHz |uSu u uSu :u (9) The minimum op amp bandwidth required for this application is based on the value of R F, C F, and the capacitance on the INx– pin of the TLV9002 which is equal to the sum of the photodiode shunt capacitance, (CPD) the common-mode input capacitance, (CCM) and the differential input capacitance (CD) as Equation 10 shows. IN PD CM DC C C C 47 pF 5 pF 1 pF 53 pF (10) The minimum op amp bandwidth is calculated in Equation 11. IN F BGW 2 F F C C f 324 kHz

2 R C

(11) The 1-MHz bandwidth of the TLV900x meets the minimum bandwidth requirement and remains stable in this application configuration. TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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9.2.2.3 Application Curves

The measured current-to-voltage transfer function for the photodiode amplifier circuit is shown in Figure 9-4. The measured performance of the photodiode amplifier circuit is shown in Figure 9-5. Frequency (Hz) Gain (dB) 100 120 10 100 1k 10k 100k 1M D001 D001 D001 Figure 9-4. Photodiode Amplifier Circuit AC Gain Results Input Current (A) Output Voltage (V) 0 2E-6 4E-6 6E-6 8E-6 1E-5 0.5 1.5 2.5 D002 Figure 9-5. Photodiode Amplifier Circuit DC Results www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TLV9001 TLV9002 TLV9004

10 Power Supply Recommendations

The TLV900x family is specified for operation from 1.8 V to 5.5 V (± 0.9 V to ±2.75 V); many specifications apply from –40°C to 125°C. Section 7.11 presents parameters that may exhibit significant variance with regard to operating voltage or temperature. CAUTION Supply voltages larger than 6 V may permanently damage the device; see Section 7.1. Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or high- impedance power supplies. For more detailed information on bypass capacitor placement, see Section 11.1.

10.1 Input and ESD Protection

The TLV900x family incorporates internal ESD protection circuits on all pins. For input and output pins, this protection primarily consists of current-steering diodes connected between the input and power-supply pins. These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10 mA. Figure 10-1 shows how a series input resistor can be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the value must be kept to a minimum in noise-sensitive applications. 5 k/c87 10-mA maximum VIN VOUT IOVERLOAD Device Figure 10-1. Input Current Protection TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

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11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

• Noise can propagate into analog circuitry through the power connections of the board and propagate to the power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a low-impedance path to ground. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care to physically separate digital and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as opposed to running the traces in parallel with the noisy trace.
• Place the external components as close to the device as possible, as shown in Figure 11-2. Keeping RF and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

11.2 Layout Example

+VIN 2 VOUT 2RG RF +VIN 1 VOUT 1RG RF Figure 11-1. Schematic Representation OUT1 IN1± IN1+ OUT2 IN2± IN2+ VS± GND Ground (GND) plane on another layer Keep input traces short and run the input traces as far away from the supply lines as possible . Place components close to device and to each other to reduce parasitic errors . Use low-ESR, ceramic bypass capacitor . Place as close to the device as possible . VIN 1 GND RF RG VIN 2 GND RF RG VS+ GND OUT 1 OUT 2 Use low-ESR, ceramic bypass capacitor . Place as close to the device as possible . Figure 11-2. Layout Example www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TLV9001 TLV9002 TLV9004

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. Bluetooth® is a registered trademark of Bluetooth SIG, Inc. All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most- current data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane. TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

36 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TLV9001 TLV9002 TLV9004

www.ti.com PACKAGE OUTLINE C

0.33 MAX

0.125 0.075

0.7 TYP

0.35 TYP

0.35 TYP9X 0.195 0.155 B E A D 4226891/A 06/2021 D: Max = 1.01 mm, Min = 0.97 mm DSBGA - 0.33 mm max heightYCK0009-C01 DIE SIZE BALL GRID ARRAY E: Max = 1.01 mm, Min = 0.97 mm NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER SEATING PLANE BALL TYP 0.05 C A 2 3

0.015 C A B

B C SCALE 12.000 www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TLV9001 TLV9002 TLV9004

www.ti.com EXAMPLE BOARD LAYOUT 0.0375 MIN0.0375 MAX 9X ( 0.18) (0.35) TYP (0.35) TYP ( 0.18) SOLDER MASK OPENING ( 0.18) METAL 4226891/A 06/2021 DSBGA - 0.33 mm max heightYCK0009-C01 DIE SIZE BALL GRID ARRAY NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). SOLDER MASK DETAILS NOT TO SCALE SYMM SYMM C 1 2 3 A B EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE: 50X NON-SOLDER MASK DEFINED EXPOSED METAL SOLDER MASK OPENING SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK EXPOSED METAL TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 www.ti.com

38 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TLV9001 TLV9002 TLV9004

www.ti.com EXAMPLE STENCIL DESIGN (0.35) TYP (0.35) TYP 4226891/A 06/2021 DSBGA - 0.33 mm max heightYCK0009-C01 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.075 mm THICK STENCIL SCALE: 50X METAL TYP C 1 2 3 A B www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TLV9001 TLV9002 TLV9004

www.ti.com 9-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLV9001IDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1OGF TLV9001IDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1OGF TLV9001IDCKR Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 1BZ TLV9001IDCKR.A Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 1BZ TLV9001IDPWR Active Production X2SON (DPW) | 5 3000 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 DF TLV9001IDPWR.A Active Production X2SON (DPW) | 5 3000 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 DF TLV9001SIDBVR Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1OJF TLV9001SIDBVR.A Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1OJF TLV9001SIDBVRG4 Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1OJF TLV9001SIDBVRG4.A Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1OJF TLV9001SIDCKR Active Production SC70 (DCK) | 6 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 1F8 TLV9001SIDCKR.A Active Production SC70 (DCK) | 6 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 1F8 TLV9001TIDCKR Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 1D6 TLV9001TIDCKR.A Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 1D6 TLV9001UIDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1ODF TLV9001UIDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1ODF TLV9001ZIDPWR Active Production X2SON (DPW) | 5 3000 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 (D, DF) TLV9001ZIDPWR.A Active Production X2SON (DPW) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (D, DF) TLV9002IDDFR Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T902 TLV9002IDDFR.A Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T902 TLV9002IDDFRG4 Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T902 TLV9002IDDFRG4.A Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T902 TLV9002IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU | SN | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 (1GNX, OBBI) TLV9002IDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 (1GNX, OBBI) TLV9002IDGKRG4 Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 1GNX TLV9002IDGKRG4.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 1GNX TLV9002IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU | SN | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 (1GNX, OBBI) TLV9002IDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 (1GNX, OBBI) Addendum-Page 1

www.ti.com 9-Nov-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLV9002IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL9002 TLV9002IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL9002 TLV9002IDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL9002 TLV9002IDRG4.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL9002 TLV9002IDSGR Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1GMH TLV9002IDSGR.A Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1GMH TLV9002IDSGRG4 Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1GMH TLV9002IDSGRG4.A Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1GMH TLV9002IDSGT Active Production WSON (DSG) | 8 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1GMH TLV9002IDSGT.A Active Production WSON (DSG) | 8 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1GMH TLV9002IPWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 9002 TLV9002IPWR.A Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 9002 TLV9002SIDGSR Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1GDX TLV9002SIDGSR.A Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1GDX TLV9002SIRUGR Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 ENF TLV9002SIRUGR.A Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 ENF TLV9002SIYCKR Active Production DSBGA (YCK) | 9 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 JK TLV9002SIYCKR.A Active Production DSBGA (YCK) | 9 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 JK TLV9004IDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV9004 TLV9004IDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV9004 TLV9004IDRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TLV9004 TLV9004IDRG4.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TLV9004 TLV9004IDYYR Active Production SOT-23-THIN (DYY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TLV9004I TLV9004IDYYR.A Active Production SOT-23-THIN (DYY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TLV9004I TLV9004IPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 TLV9004 TLV9004IPWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 TLV9004 TLV9004IPWR.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R - Call TI Call TI -40 to 125 TLV9004IRTER Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T9004 TLV9004IRTER.A Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T9004 Addendum-Page 2

www.ti.com 9-Nov-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLV9004IRUCR Active Production QFN (RUC) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 1DC TLV9004IRUCR.A Active Production QFN (RUC) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 1DC TLV9004IRUCRG4 Active Production QFN (RUC) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 1DC TLV9004IRUCRG4.A Active Production QFN (RUC) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 1DC TLV9004SIRTER Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T9004S TLV9004SIRTER.A Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T9004S (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV9001, TLV9002, TLV9004 : Addendum-Page 3

www.ti.com 9-Nov-2025

• Automotive : TLV9001-Q1 , TLV9002-Q1 , TLV9004-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 24-Oct-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TLV9002IDDFR SOT-23- THIN TLV9002IDDFRG4 SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Oct-2025 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TLV9004IDYYR SOT-23- THIN Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Oct-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV9001IDBVR SOT-23 DBV 5 3000 208.0 191.0 35.0 TLV9001IDCKR SC70 DCK 5 3000 210.0 185.0 35.0 TLV9001IDCKR SC70 DCK 5 3000 210.0 185.0 35.0 TLV9001IDPWR X2SON DPW 5 3000 205.0 200.0 33.0 TLV9001SIDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0 TLV9001SIDBVRG4 SOT-23 DBV 6 3000 210.0 185.0 35.0 TLV9001SIDCKR SC70 DCK 6 3000 208.0 191.0 35.0 TLV9001SIDCKR SC70 DCK 6 3000 210.0 185.0 35.0 TLV9001TIDCKR SC70 DCK 5 3000 210.0 185.0 35.0 TLV9001UIDBVR SOT-23 DBV 5 3000 208.0 191.0 35.0 TLV9001ZIDPWR X2SON DPW 5 3000 205.0 200.0 33.0 TLV9002IDDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 TLV9002IDDFRG4 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 TLV9002IDGKR VSSOP DGK 8 2500 356.0 356.0 36.0 TLV9002IDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 TLV9002IDGKRG4 VSSOP DGK 8 2500 353.0 353.0 32.0 TLV9002IDGKT VSSOP DGK 8 250 353.0 353.0 32.0 TLV9002IDR SOIC D 8 2500 353.0 353.0 32.0 Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 24-Oct-2025 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV9002IDRG4 SOIC D 8 2500 353.0 353.0 32.0 TLV9002IDSGR WSON DSG 8 3000 210.0 185.0 35.0 TLV9002IDSGRG4 WSON DSG 8 3000 210.0 185.0 35.0 TLV9002IDSGT WSON DSG 8 250 210.0 185.0 35.0 TLV9002IPWR TSSOP PW 8 2000 353.0 353.0 32.0 TLV9002SIDGSR VSSOP DGS 10 2500 366.0 364.0 50.0 TLV9002SIRUGR X2QFN RUG 10 3000 205.0 200.0 33.0 TLV9002SIYCKR DSBGA YCK 9 3000 182.0 182.0 20.0 TLV9004IDR SOIC D 14 2500 353.0 353.0 32.0 TLV9004IDRG4 SOIC D 14 2500 353.0 353.0 32.0 TLV9004IDYYR SOT-23-THIN DYY 14 3000 336.6 336.6 31.8 TLV9004IPWR TSSOP PW 14 2000 356.0 356.0 35.0 TLV9004IPWR TSSOP PW 14 2000 353.0 353.0 32.0 TLV9004IRTER WQFN RTE 16 3000 367.0 367.0 35.0 TLV9004IRUCR QFN RUC 14 3000 205.0 200.0 30.0 TLV9004IRUCRG4 QFN RUC 14 3000 205.0 200.0 30.0 TLV9004SIRTER WQFN RTE 16 3000 367.0 367.0 35.0 Pack Materials-Page 4

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05

4.75 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.1 MAX

0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023

0.13 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM

www.ti.com PACKAGE OUTLINE C 0.22 0.15 2.4 1.8 4X 0.65 1.1 0.8 0.1

0.0 TYP

6X 0.30 0.15 NOTE 5 0.46

0.26 TYP

1.3 4X 0 -12 4X 4 -15 A 2.15 1.85 B1.4 1.1 SOT - 1.1 max heightDCK0006A SMALL OUTLINE TRANSISTOR 4214835/D 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Falls within JEDEC MO-203 variation AB. INDEX AREA PIN 1 NOTE 5

0.1 C A B

0.1 C SCALE 5.600

www.ti.com EXAMPLE BOARD LAYOUT 6X (0.9) 6X (0.4) (2.2) 4X (0.65) (R0.05) TYP 4214835/D 11/2024 SOT - 1.1 max heightDCK0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.2) 4X(0.65) 6X (0.9) 6X (0.4) (R0.05) TYP SOT - 1.1 max heightDCK0006A SMALL OUTLINE TRANSISTOR 4214835/D 11/2024 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG 3 4

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightRTE 16 PLASTIC QUAD FLATPACK - NO LEAD3 x 3, 0.5 mm pitch 4225944/A

www.ti.com PACKAGE OUTLINE C 16X 0.30 0.18 1.68 0.07 16X 0.5 0.3

0.8 MAX

(DIM A) TYP 0.05 0.00 12X 0.5 1.5 A 3.1 2.9 B 3.1 2.9 WQFN - 0.8 mm max heightRTE0016C PLASTIC QUAD FLATPACK - NO LEAD 4219117/B 04/2022 SIDE WALL METAL THICKNESS DIM A OPTION 1 OPTION 2 0.1 0.2 PIN 1 INDEX AREA 0.08 SEATING PLANE 4 9 5 8 16 13 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD

17 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.600

www.ti.com EXAMPLE BOARD LAYOUT 16X (0.24) 16X (0.6) ( 0.2) TYP VIA 12X (0.5) (2.8) (2.8) (0.58) TYP ( 1.68) (R0.05) ALL PAD CORNERS (0.58) TYP WQFN - 0.8 mm max heightRTE0016C PLASTIC QUAD FLATPACK - NO LEAD 4219117/B 04/2022 SYMM 5 8 1316 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 16X (0.6) 16X (0.24) 12X (0.5) (2.8) (2.8) ( 1.55) (R0.05) TYP WQFN - 0.8 mm max heightRTE0016C PLASTIC QUAD FLATPACK - NO LEAD 4219117/B 04/2022 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM ALL AROUND METAL SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 17: 85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X SYMM 5 8 1316

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AB PACKAGE OUTLINE 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0014A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.3 0.11 C SEATING PLANE 0.2 0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP 12X 0.5 4X 4° - 15° 4X 0° - 15°

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8 METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4) 14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

www.ti.com PACKAGE OUTLINE 1.6 1.4 2.1 1.9 0.40 0.34 0.05 0.00 2X 1.5 6X 0.5 10X 0.45 0.35 4X 0.25 0.15 2X 0.35 0.25 4X 0.3 0.2

0.1 MIN

(0.127) TYP X2QFN - 0.4 mm max heightRUG0010B PLASTIC QUAD FLATPACK - NO LEAD 4220582/B 05/2025 0.05 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Minimum 0.1 mm solder wetting on pin side wall. Available for wettable flank version only. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID (45 X 0.1) SYMM SYMM 0.05 C 0.05 C 0.05 C SCALE 7.500 50.000 OPTIONAL: SIDE WALL PIN DETAIL NOTE 3 AB C

www.ti.com EXAMPLE BOARD LAYOUT 6X (0.5) (R0.05) TYP 10X (0.6) 4X (0.25) (1.8) (1.3) 4X (0.2) 2X (0.3) X2QFN - 0.4 mm max heightRUG0010B PLASTIC QUAD FLATPACK - NO LEAD 4220582/B 05/2025 NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 35X SEE SOLDER MASK DETAIL METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 10X (0.6) 4X (0.25) 6X (0.5) (R0.05) TYP (1.8) (1.3) 4X (0.2) 2X (0.3) X2QFN - 0.4 mm max heightRUG0010B PLASTIC QUAD FLATPACK - NO LEAD 4220582/B 05/2025 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 35X SYMM SYMM

www.ti.com PACKAGE OUTLINE C TYP5.05 4.75 8X 0.5 10X 0.27 0.17 0.15 0.05 TYP0.23 0.13 0 - 8 0.25 GAGE PLANE 0.7 0.4 A NOTE 3 3.1 2.9 B NOTE 4 3.1 2.9 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA. 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 3.200

www.ti.com EXAMPLE BOARD LAYOUT (4.4) 10X (1.45) 10X (0.3) 8X (0.5) (R ) TYP 0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 5 6 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (4.4) 8X (0.5) 10X (0.3) 10X (1.45) (R ) TYP0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 5 6 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

www.ti.com PACKAGE OUTLINE C 4X 0.27 0.17 3X 0.288 0.188

0.4 MAX

0.05 0.00 0.48 0.239 0.139 0.25 0.1 B 0.85 0.75 A 0.85 0.75 (0.1) 4X (0.05) (0.324) 2X (0.26) X2SON - 0.4 mm max heightDPW0005A PLASTIC SMALL OUTLINE - NO LEAD 4223102/D 03/2022 PIN 1 INDEX AREA SEATING PLANE NOTE 3 0.05 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The size and shape of this feature may vary. NOTE 3 SCALE 12.000

www.ti.com EXAMPLE BOARD LAYOUT (0.21) TYP EXPOSED METAL CLEARANCE (0.48) (0.78) 4X (0.42) 4X (0.22) ( 0.25) 4X (0.26) 4X (0.06) ( 0.1) VIA (R0.05) TYP X2SON - 0.4 mm max heightDPW0005A PLASTIC SMALL OUTLINE - NO LEAD 4223102/D 03/2022 SYMM SYMM LAND PATTERN EXAMPLE SOLDER MASK DEFINED SCALE:60X SOLDER MASK OPENING, TYP METAL UNDER SOLDER MASK TYP NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com EXAMPLE STENCIL DESIGN (0.48) (0.78) 4X (0.42) 4X (0.22) 4X (0.26) 4X (0.06) ( 0.24) (0.21) TYP (R0.05) TYP X2SON - 0.4 mm max heightDPW0005A PLASTIC SMALL OUTLINE - NO LEAD 4223102/D 03/2022 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 3 92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:100X SYMM SYMM EDGE SOLDER MASK

www.ti.com PACKAGE OUTLINE C 2X (0.36) 4X 0.27 0.17 0.35 0.15 4X 0.27 0.17 2X (0.26) 0.05 0.00 (0.1) TYP 2X 0.48 B 0.85 0.75 A 0.85 0.75 X2SON - 0.4 mm max heightDPW0005B PLASTIC SMALL OUTLINE - NO LEAD 4228233/D 09/2023 PIN 1 INDEX AREA SEATING PLANE NOTE 3 0.05 C PIN 1 ID NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The size and shape of this feature may vary. NOTE 3 SCALE 12.000

www.ti.com EXAMPLE BOARD LAYOUT (0.21) TYP EXPOSED METAL CLEARANCE (R0.05) TYP 4X (0.42) 4X (0.22) 4X (0.26) ( 0.25) ( 0.1) VIA (0.78) (0.48) 4X (0.06) X2SON - 0.4 mm max heightDPW0005B PLASTIC SMALL OUTLINE - NO LEAD 4228233/D 09/2023 SYMM SYMM LAND PATTERN EXAMPLE SOLDER MASK DEFINED SCALE:60X SOLDER MASK OPENING, TYP METAL UNDER SOLDER MASK, TYP NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com EXAMPLE STENCIL DESIGN 4X (0.22) 4X (0.42) 4X (0.06) (R0.05) TYP ( 0.24) (0.21) TYP (0.78) (0.48) X2SON - 0.4 mm max heightDPW0005B PLASTIC SMALL OUTLINE - NO LEAD 4228233/D 09/2023 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 5 92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:60X SYMM SYMM SOLDER MASK EDGE

www.ti.com PACKAGE OUTLINE C 0.22 0.15 2.4 1.8 2X 0.65 1.3 0.1 5X 0.33 0.15 NOTE 5 0.46 1.3 4X 0 -12 4X 4 -15 A 2.15 1.85 B1.4 1.1 (0.9) (0.15) (0.1) SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/G 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-203. 4. Support pin may differ or may not be present. 5. Lead width does not comply with JEDEC. 6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side 0.1 C SCALE 5.600

www.ti.com EXAMPLE BOARD LAYOUT 5X (0.95) 5X (0.4) (2.2) (1.3) 2X (0.65) (R0.05) TYP 4214834/G 11/2024 SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 7. Publication IPC-7351 may have alternate designs. 8. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.2) (1.3) 2X(0.65) 5X (0.95) 5X (0.4) (R0.05) TYP SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/G 11/2024 NOTES: (continued) 9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 10. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C 2.95

2.65 TYP

1.1 MAX 6X 0.65 8X 0.38 0.22 1.95 0.20 0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 4X 0 -15 4X 4 -15 A 2.95 2.85 NOTE 3 B 1.65 1.55 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT (2.6) ALL AROUND 0.05 MIN ALL AROUND 8X (1.05) 8X (0.45) 6X (0.65) (R0.05) TYP 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R0.05) TYP 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C 0.125 0.075 0.35 TYP9X 0.195 0.155 B E A D 4225837/A 04/2020 DSBGA - 0.33 mm max heightYCK0009 DIE SIZE BALL GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER SEATING PLANE BALL TYP 0.05 C A 2 3 B C SCALE 12.000

www.ti.com EXAMPLE BOARD LAYOUT 0.0325 MIN0.0325 MAX 9X ( 0.18) (0.35) TYP (0.35) TYP ( 0.18) SOLDER MASK OPENING ( 0.18) METAL 4225837/A 04/2020 DSBGA - 0.33 mm max heightYCK0009 DIE SIZE BALL GRID ARRAY NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). SOLDER MASK DETAILS NOT TO SCALE SYMM SYMM C 1 2 3 A B LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 50X NON-SOLDER MASK DEFINED EXPOSED METALSOLDER MASK OPENING SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (0.35) TYP (0.35) TYP 4225837/A 04/2020 DSBGA - 0.33 mm max heightYCK0009 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.075 mm THICK STENCIL SCALE: 50X METAL TYP C 1 2 3 A B

www.ti.com PACKAGE OUTLINE C 0.22 0.25 3.0 2.6 2X 0.95 1.45 0.90 0.15 6X 0.50 0.25 0.6 1.9 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/G 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178. 0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT 6X (1.1) 6X (0.6) (2.6) 2X (0.95) (R0.05) TYP 4214840/G 08/2024 SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 2X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/G 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WSON - 0.8 mm max heightDSG 8 PLASTIC SMALL OUTLINE - NO LEAD2 x 2, 0.5 mm pitch 4224783/A

www.ti.com PACKAGE OUTLINE C 8X 0.32 0.18 1.6 0.1 1.5 0.9 0.1 6X 0.5 8X 0.4 0.2 0.05 0.00 0.8 0.7 A 2.1 1.9 B 2.1 1.9 0.32 0.18 0.4 0.2 (DIM A) TYP WSON - 0.8 mm max heightDSG0008A PLASTIC SMALL OUTLINE - NO LEAD 4218900/E 08/2022 SIDE WALL METAL THICKNESS DIM A OPTION 1 OPTION 2 0.1 0.2 PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 X 0.25)(45 PIN 1 ID 0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 5.500 ALTERNATIVE TERMINAL SHAPE TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT 8X (0.25) (1.6) (1.9) 6X (0.5) (0.9) ( 0.2) VIA TYP (0.55) 8X (0.5) (R0.05) TYP WSON - 0.8 mm max heightDSG0008A PLASTIC SMALL OUTLINE - NO LEAD 4218900/E 08/2022 SYMM 4 5 LAND PATTERN EXAMPLE SCALE:20X SYMM 9 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 8X (0.25) 8X (0.5) (0.9) (0.7) (1.9) (0.45) 6X (0.5) WSON - 0.8 mm max heightDSG0008A PLASTIC SMALL OUTLINE - NO LEAD 4218900/E 08/2022 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X SYMM METAL SYMM

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2 6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8) 8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. X2QFN - 0.4 mm max heightRUC 14 PLASTIC QUAD FLATPACK - NO LEAD2 x 2, 0.4 mm pitch 4229871/A

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PACKAGE OUTLINE 4220584/A 05/2019 www.ti.com X2QFN - 0.4 mm max height PLASTIC QUAD FLAT PACK- NO LEAD RUC0014A A 0.08 C 0.05 C B SYMM SYMM PIN 1 INDEX AREA 2.1 1.9 2.1 1.9 0.05 0.00 SEATING PLANE C PIN 1 ID (45oX0.1) 2X 0.4 8X 0.4 1.6 14X 0.25 0.15 14X 0.5 0.3 6 7 1314 (0.15) TYP

NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . EXAMPLE BOARD LAYOUT 4220584/A 05/2019 www.ti.com X2QFN - 0.4 mm max heightRUC0014A PLASTIC QUAD FLAT PACK- NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 23X (PREFERRED) SOLDER MASK DEFINED METAL EXPOSED METAL SOLDER MASK OPENING 14X (0.2) 14X (0.6) (1.6) (1.8) (R0.05) 8X (0.4) 2X (0.4) (1.8)

NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4220584/A 05/2019 www.ti.com X2QFN - 0.4 mm max heightRUC0014A PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.100mm THICK STENCIL SCALE: 23X SYMM SYMM 14X (0.2) 14X (0.6) (1.6) (1.8) (R0.05) 8X (0.4) 2X (0.4) (1.8)

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